Display device

Abstract

A display device includes: a light emitting element; and a driving thin film transistor (TFT) including a first electrode, a second electrode connected to the light emitting element, and a gate electrode, in which a voltage level of the gate electrode is determined according to a data voltage input to the first electrode when the gate electrode is connected with the second electrode in a non-emission period, a driving thin film transistor configured to receive the first high voltage through the first electrode to control a current applied to the light emitting element according to a voltage difference between the gate electrode and the first electrode when the gate electrode is disconnected from the second electrode in an emission period; and a voltage compensation unit configured to reflect, in the gate electrode, a difference between the first high voltage in the emission period and the first high voltage in the non-emission period.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2024-0013472, filed on Jan. 29, 2024, which is incorporated herein by reference in its entirety as if fully set forth herein. Technical Field

[0002] The present disclosure relates to a display device. Background Art

[0003] An organic light emitting display device, which has recently attracted much attention, emits light by using an organic light emitting diode (OLED), and has advantages such as a fast response speed, a high contrast ratio, a high luminous efficiency, a high brightness, and a wide viewing angle.

[0004] The organic light emitting display device includes sub-pixels and can display an image by controlling the brightness of each sub-pixel according to the gray scale of image data. The sub-pixels have OLEDs and driving transistors for driving the OLEDs and are arranged in a matrix form. The brightness of each sub-pixel can be controlled by controlling the amount of current flowing through the OLED by using the driving transistor.

[0005] Since the image quality of such an organic light emitting display device is greatly affected by the current driving ability of the sub-pixels, efforts are needed to improve the accuracy and stability of the operation of the driving transistors. Summary of the Invention

[0006] Accordingly, the present disclosure relates to a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of the related art.

[0007] An object of the present disclosure is to provide a display device capable of improving the accuracy and stability of the operation of the driving transistors of sub-pixels.

[0008] Other advantages, objects, and features of the present disclosure will be partly set forth in the description below, and partly will become apparent to those of ordinary skill in the art upon examination of the following, or may be learned by practice of the present disclosure. The objects and other advantages of the present disclosure may be realized and obtained by the structure particularly pointed out in this specification, its claims, and the drawings.

[0009] To achieve these objects and other advantages and in accordance with the purpose of the present disclosure, as embodied and broadly described herein, a display device includes: a light-emitting element; a first high-voltage source that supplies a first high voltage; a driving thin-film transistor (TFT) including a first electrode, a second electrode connected to the light-emitting element, and a gate electrode, wherein a voltage level of the gate electrode is determined based on a data voltage input to the first electrode in a state where the gate electrode is connected to the second electrode during a non-emission period, and the driving thin-film transistor is configured to receive the first high voltage through the first electrode to control a current applied to the light-emitting element based on a voltage difference between the gate electrode and the first electrode in a state where the gate electrode is disconnected from the second electrode during an emission period; and a voltage compensation unit configured to reflect a difference between the first high voltage during the emission period and the first high voltage during the non-emission period in the gate electrode.

[0010] The display device may further include a first emission control TFT and a second emission control TFT, the first emission control TFT being configured to be turned on during the emission period to connect the first electrode and the first high-voltage source, and the second emission control TFT being configured to be turned on during the emission period to connect the second electrode and the light-emitting element.

[0011] The display device may further include: a first switch TFT configured to be turned on during the emission period to connect the gate electrode and the second electrode; a second switch TFT configured to be turned on during the non-emission period to connect an input line through which the data voltage is supplied to the first electrode; a third switch TFT configured to be turned on during the non-emission period to apply an initialization voltage to the gate electrode; and a fourth switch TFT configured to apply a reset voltage to a current input terminal of the light-emitting element.

[0012] The display device may further include a first capacitor connected between the first high-voltage source and the gate electrode.

[0013] The voltage compensation unit may include: a second high-voltage source that supplies a second high voltage having the same level as the first high voltage; a second capacitor connected to the gate electrode; a fifth switch TFT configured to connect the second capacitor and the first high-voltage source during the emission period; and a sixth switch TFT configured to connect the second capacitor and the second high-voltage source during the non-emission period.

[0014] The display device may further include a first capacitor connected between the first high voltage source and the gate electrode, wherein the second capacitor connected to the second high voltage source and the first capacitor connected to the first high voltage source are connected in parallel during the non-emission period, and the second capacitor connected to the first high voltage source and the first capacitor connected to the first high voltage source are connected in parallel during the emission period.

[0015] The second capacitor may reflect, in the gate electrode, a difference between the voltage of the second high voltage source connected to the second capacitor during the non-emission period and the voltage of the first high voltage source connected to the second capacitor during the emission period.

[0016] The display device may further include a first emission control TFT and a second emission control TFT. The first emission control TFT is configured to be turned on during the emission period to connect the first electrode and the first high voltage source, and the second emission control TFT is configured to be turned on during the light emission period to connect the second electrode and the light emitting element. Wherein, the fifth switch TFT connects the second capacitor and the first high voltage source by receiving a conduction level emission signal input to the first emission control TFT and the second emission control TFT, and the sixth switch TFT connects the second capacitor and the second high voltage source by receiving a cut-off level emission signal input to the first emission control TFT and the second emission control TFT.

[0017] The display device may further include a seventh switch TFT configured to be turned on during the non-emission period to apply a conduction bias stress (OBS) voltage to the first electrode.

[0018] In another aspect of the present disclosure, a display device includes: a light-emitting element; a first high-voltage source supplying a first high voltage; a second high-voltage source supplying a second high voltage; a driving TFT including a first electrode connected to a first node, a second electrode connected to a third node, and a gate electrode connected to a second node; a first emission control TFT configured to be turned on by a conduction-level emission signal to connect the first high-voltage source and the first node; a second emission control TFT configured to be turned on by the conduction-level emission signal to connect the third node and the light-emitting element; a first switching TFT configured to be turned on by a conduction-level first scan signal to connect the gate electrode and the second electrode; a second switching TFT configured to be turned on by a conduction-level second scan signal to connect an input line through which a data voltage is supplied to the first node; a fifth switching TFT configured to be turned on by the conduction-level emission signal to connect the first high-voltage source and the second node; a sixth switching TFT configured to be turned on by a cut-off-level emission signal to connect the second high-voltage source and the second node; and a second capacitor having a first electrode connected to the second node and a second electrode connected to the fifth switching TFT or the sixth switching TFT.

[0019] The display device may further include a first capacitor having a first electrode connected to the second node and a second electrode connected to the first high-voltage source.

[0020] The display device may further include a third switching TFT and a fourth switching TFT. The third switching TFT is configured to be turned on by a conduction-level third scan signal to apply an initialization voltage to the second node, and the fourth switching TFT is configured to be turned on by a conduction-level fourth scan signal to apply a reset voltage to a current input terminal of the light-emitting element.

[0021] The display device may further include a seventh switching TFT configured to be turned on by the conduction-level fourth scan signal to apply a conduction bias stress (OBS) voltage to the first electrode.

[0022] It should be understood that the foregoing general description and the following detailed description of the present disclosure are both exemplary and explanatory and are intended to provide further explanation of the claimed present disclosure. Description of the Drawings

[0023] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate one or more aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0024] Figure 1 is a schematic block diagram of a display device;

[0025] Figure 2 is included in Figure 1 an equivalent circuit diagram of a sub-pixel in a light-emitting display device;

[0026] Figure 3 is a diagram showing Figure 2 the driving waveform of the sub-pixel;

[0027] Figure 4 and Figure 5 are diagrams for describing the change in the gate-source voltage Vgs that may occur in the sub-pixel of Figure 2 ;

[0028] Figure 6 is a circuit diagram of a sub-pixel according to a first aspect of the disclosure;

[0029] Figure 7 is Figure 6 the driving waveform diagram of the sub-pixel;

[0030] Figure 8 and Figure 9 are diagrams for describing the method of driving the sub-pixel of Figure 6 ;

[0031] Figure 10 is for describing Figure 6 the characteristics of the capacitor of the sub-pixel;

[0032] Figure 11 and Figure 12 are graphs showing the results of simulating the change in the gate-source voltage Vgs of the sub-pixel according to the comparative example and the first aspect;

[0033] Figure 13 is a circuit diagram of a sub-pixel according to a second aspect of the disclosure;

[0034] Figure 14 is Figure 13 the driving waveform diagram of the sub-pixel; and

[0035] Figure 15 and Figure 16 are graphs showing the results of simulating the change in the gate-source voltage Vgs of the sub-pixel according to the comparative example and the second aspect. Detailed Description

[0036] Advantages and features of the present disclosure, and ways of obtaining the advantages and features, will become apparent by referring to the various aspects described in detail below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the various aspects disclosed below and can be embodied in many different forms. On the contrary, these exemplary aspects are provided so that the present disclosure will be complete and full, and will fully convey the scope to those skilled in the art.

[0037] To describe the various aspects of the present disclosure, the shapes, sizes, ratios, angles, numbers, etc. shown in the drawings are given only by way of example, and thus, the present disclosure is not limited to the illustrations in the drawings. In the present disclosure, when using terms such as "comprising", "including", etc., other elements can be added unless the term "only" is used. Unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0038] When interpreting components, unless otherwise clearly described, the components are interpreted as including an error range.

[0039] When describing the positional relationship, for example, when using "on", "above", "below", "next to", etc. to describe the positional relationship between two parts, unless the terms "directly" or "closely" are used, one or more other parts can be located between the two parts.

[0040] In the description of the various aspects of the present disclosure, although terms such as "first" and "second" can be used to describe various elements, these terms are only used to distinguish the same or similar elements from each other. Therefore, in the present disclosure, unless otherwise stated, the element modified by "first" can be the same as the element modified by "second" within the technical scope of the present disclosure.

[0041] In addition, the pixel circuit of the display device to be described below can include a plurality of transistors. The transistors can be implemented as oxide thin film transistors (TFTs) containing an oxide semiconductor, low-temperature polysilicon (LTPS) TFTs containing LTPS, etc. Each transistor can be implemented as a p-channel TFT or an n-channel TFT.

[0042] A transistor is a three - electrode device including a gate, a source, and a drain. The source is the electrode that supplies carriers to the transistor. Inside the transistor, carriers flow from the source. The drain is the electrode through which carriers leave the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n - channel transistor, the carriers are electrons, and thus the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain. In an n - channel transistor, current flows from the drain to the source. In the case of a p - channel transistor (PMOS), the carriers are holes, and thus the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p - channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can change according to the applied voltage. Therefore, the present disclosure is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as the first electrode and the second electrode.

[0043] The gate signal swings between a gate - on voltage and a gate - off voltage. The gate - on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate - off voltage is set to a voltage lower than the threshold voltage of the transistor. The transistor conducts in response to the gate - on voltage and cuts off in response to the gate - off voltage. For an n - channel transistor, the gate - on voltage can be the gate - high voltage VGH, and the gate - off voltage can be the gate - low voltage VGL. For a p - channel transistor, the gate - on voltage can be the gate - low voltage VGL, and the gate - off voltage can be the gate - high voltage VGH.

[0044] Each pixel of an electroluminescent display device includes a light - emitting element and a driving element. The driving element generates a pixel current according to the voltage between the gate and the source to drive the light - emitting element. The light - emitting element includes an anode, a cathode, and an organic compound layer formed between the anode and the cathode. The organic compound layer may include a hole - injection layer (HIL), a hole - transport layer (HTL), an emission layer (EML), an electron - transport layer (ETL), an electron - injection layer (EIL), etc., but is not limited thereto. When the pixel current flows through the light - emitting element, holes that have passed through the hole - transport layer (HTL) and electrons that have passed through the electron - transport layer (ETL) move to the emission layer (EML), form excitons, and thus the emission layer (EML) emits visible light.

[0045] Recently, there have been more and more attempts to implement some of the transistors included in the pixel circuit of an electroluminescent display device as oxide transistors. For oxide transistors, an oxide (i.e., IGZO, which is a compound of indium (In), gallium (Ga), zinc (Zn), and oxygen (O)) is used as the semiconductor material instead of polysilicon.

[0046] Since oxide transistors have low off-state current, they have the advantages of high driving stability and reliability during low-speed operation, where the transistor off-state period is relatively long. Therefore, oxide transistors can be used in large liquid crystal displays that require high resolution and low power operation, or in OLED TVs whose screen sizes cannot be achieved using low-temperature polysilicon processes.

[0047] The display device according to various aspects of the present disclosure may be implemented as a television, a video player, a personal computer (PC), a home theater, an automotive electric device, a smart phone, etc., but is not limited thereto. The display device according to various aspects of the present disclosure may be implemented as a light emitting display (LED) device, a quantum dot display (QDD) device, a liquid crystal display (LCD) device, etc. However, for the convenience of description, an example of a display device based on direct light emission of an inorganic light emitting diode or an organic light emitting diode will be described below.

[0048] The same reference numerals refer to substantially the same elements throughout the specification. Hereinafter, various aspects of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, when it is determined that the detailed description of known functions or configurations related to the present disclosure may unnecessarily obscure the subject matter of the present disclosure, their detailed description will be omitted.

[0049] Figure 1 is a block diagram schematically showing the configuration of a display device.

[0050] refer to Figure 1 , the display device may include an image provider 110 , a timing controller 120 , a scan driver 130 , a data driver 140 , a display panel 150 , and a power supply 180 .

[0051] The image provider 110 may output various driving signals in addition to an image data signal supplied from the outside or an image data signal stored in an internal memory. The image provider 110 may supply the timing controller 120 with a data signal and various driving signals.

[0052] The timing controller 120 may output a gate timing control signal GDC for controlling the operation timing of the scan driver 130, a data timing control signal DDC for controlling the operation timing of the data driver 140, and various synchronization signals including a vertical synchronization signal and a horizontal synchronization signal. The timing controller 120 may supply the data signal DATA supplied from the image provider 110 together with the data timing control signal DDC to the data driver 140. The timing controller 120 may be formed in the form of an integrated circuit (IC) and mounted on a printed circuit board, but is not limited thereto.

[0053] The data driver 140 may convert a data signal DATA in digital form into an analog data voltage in response to a data timing control signal DDC supplied from the timing controller 120, and output the analog data voltage. The data driver 140 may supply the data voltage to sub-pixels included in the display panel 150 through data lines DL1 to DLn. The data driver 140 may be formed in the form of an IC and mounted on the display panel 150 or a printed circuit board, but is not limited thereto.

[0054] The scan driver 130 may output a scan signal and an emission signal in response to a gate timing control signal GDC supplied from the timing controller 120. The scan driver 130 may supply at least one scan signal and an emission signal to sub-pixels included in the display panel 150 through gate lines GL1 to GLm. The scan driver 130 may be formed in the form of an IC, or directly formed on the display panel 150 in a gate structure in the panel.

[0055] The power supply 180 may convert power supplied from the outside into power required to drive the display device under the control of the timing controller 120, and output the converted power. For example, the power supply 180 may convert power supplied from the outside into a high voltage EVDD and a low voltage EVSS, output the voltages, generate and output a voltage required to drive the scan driver 130 or a voltage required to drive the data driver 140.

[0056] In the display panel 150, a plurality of data lines DL1 to DLn extending in the column direction (or vertical direction) and a plurality of gate lines GL1 to GLm extending in the row direction (or horizontal direction) intersect, and sub-pixels SP are arranged in a matrix form at the intersections, thereby forming a pixel array. Each sub-pixel SP includes a light-emitting element and a pixel circuit that controls the amount of current applied to the anode of the light-emitting element. The pixel circuit may include a driving TFT DT that controls the amount of current so that a constant current flows through the light-emitting element. The light-emitting element emits light during an emission period, and does not emit light during a period other than the emission period. During a period other than the emission period, initialization of the pixel circuit, programming of the light-emitting element, and resetting may be performed.

[0057] Figure 2 is included in Figure 1 of the display device, and Figure 3 is a schematic configuration diagram of the sub-pixel SP Figure 2 and is a diagram showing the driving waveform of the sub-pixel SP

[0058] A sub-pixel SP can be supplied with a high voltage EVDD, a low voltage EVSS, an initialization voltage Vini, and an anode reset voltage VAR, and receive a first scan signal Scan1 to a fourth scan signal Scan4, an emission signal EM, and a data voltage signal Vdata.

[0059] A sub-pixel SP includes an organic light-emitting diode (OLED), a driving TFT DT, a capacitor C1, a first emission control TFT ET1, a second emission control TFT ET2, and a first switch TFT T1 to a fourth switch TFT T4. Each TFT of the sub-pixel SP can be configured as a p-type MOSFET (PMOS) or an n-type MOSFET (NMOS). For example, the driving TFT DT, the first emission control TFT ET1, the second emission control TFT ET2, the second switch TFT T2, and the fourth switch TFT T4 can be implemented as p-type MOSFETs, and the first switch TFT T1 and the third switch TFT T3 can be implemented as n-type MOSFETs, but not limited thereto.

[0060] The OLED emits light by a driving current supplied from the driving TFT DT. An anode of the OLED is connected to a fourth node N4, and a cathode of the OLED is connected to a line through which the low voltage EVSS is supplied.

[0061] A gate electrode of the driving TFT DT can be connected to a second node N2, a first electrode thereof can be connected to a first node N1, and a second electrode thereof can be connected to a third node N3. The driving TFT DT can generate a driving current in response to the data voltage signal Vdata. The driving TFT DT can be a p-type MOSFET (PMOS) and can be implemented as a low-temperature polycrystalline silicon (LTPS) thin-film transistor.

[0062] The first emission control TFT ET1 and the second emission control TFT ET2 control the light emission of the OLED. The first emission control TFT ET1 and the second emission control TFT ET2 are turned on / off simultaneously by an emission signal EM input to their gate electrodes at the same time. The first emission control TFT ET1 may have a first electrode to which a high voltage EVDD is applied and a second electrode connected to a first node N1. The first emission control TFT ET1 may be used to send the high voltage EVDD to the first electrode of the driving TFT DT in response to the emission signal EM. The second emission control TFT ET2 may have a first electrode connected to a third node N3 and a second electrode connected to a fourth node N4. The second emission control TFT ET2 may be used to send a driving current to the anode of the OLED. The first emission control TFT ET1 and the second emission control TFT ET2 may be p-type MOSFETs (PMOSs), and may be implemented as low temperature polycrystalline silicon (LTPS) thin film transistors.

[0063] The storage capacitor C1 maintains the data voltage Vdata stored in the sub-pixel SP for one frame. One electrode of the storage capacitor C1 is connected to a second node N2 to which the gate electrode of the driving TFT DT is connected, and the other electrode of the storage capacitor C1 is supplied with the high voltage EVDD.

[0064] The first switching TFT T1 connects the gate electrode of the driving TFT DT and the drain electrode as the second electrode to diode-connect the driving TFT DT. The first switching TFT T1 may include a gate electrode connected to an input line to which a first scan signal Scan1 is applied, a first electrode connected to the third node N3, and a second electrode connected to the second node N2. The first switching TFT T1 may be an n-type MOSFET (NMOS), and may be implemented as an oxide thin film transistor so as to minimize the leakage current during the cut-off period. Accordingly, the first switching TFT T1 diode-connects the gate electrode and the drain electrode of the driving TFT DT in response to a high-level first scan signal Scan1 (i.e., a turn-on voltage).

[0065] The second switching TFT T2 applies a data voltage signal Vdata to a first node N1 that serves as a first electrode of a driving TFT DT. The second switching TFT T2 may include a gate electrode connected to an input line to which a second scan signal Scan2 is applied, a first electrode connected to a data line that supplies the data voltage signal Vdata, and a second electrode connected to the first node N1. The second switching TFT T2 may be a p-type MOSFET (PMOS) and may be implemented as a low-temperature polycrystalline silicon (LTPS) thin-film transistor. Accordingly, the second switching TFT T2 applies the data voltage signal Vdata supplied from the data line to the first node N1 corresponding to the first electrode of the driving TFT DT in response to a low-level second scan signal Scan2 (i.e., a turn-on voltage).

[0066] The third switching TFT T3 applies an initialization voltage Vini to a second node N2 that serves as a gate electrode of a driving TFT DT. The third switching TFT T3 may include a gate electrode connected to an input line to which a third scan signal Scan3 is applied, a first electrode to which the initialization voltage Vini is applied, and a second electrode connected to the second node N2. The third switching TFT T3 may be an n-type MOSFET (NMOS) and may be implemented as an oxide thin-film transistor to minimize leakage current. Accordingly, the third switching TFT T3 applies the initialization voltage Vini to the second node N2 corresponding to the gate electrode of the driving TFT DT in response to a high-level third scan signal Scan3 (i.e., a turn-on voltage).

[0067] The fourth switching TFT T4 applies an anode reset voltage VAR to the anode of the OLED. The fourth switching TFT T4 may include a gate electrode connected to an input line to which a fourth scan signal Scan4 is applied, a first electrode to which the anode reset voltage VAR is applied, and a second electrode connected to a fourth node N4. The fourth switching TFT T4 may be a p-type MOSFET (PMOS) and may be implemented as a low-temperature polycrystalline silicon (LTPS) thin-film transistor. Thus, the fourth switching TFT T4 applies the anode reset voltage VAR to the anode of the OLED in response to a low-level fourth scan signal Scan4 (i.e., a turn-on voltage).

[0068] The driving period of the sub-pixel SP having this configuration may include an emission period EM_ON and a non-emission period EM_OFF. During the emission period EM_ON, an emission signal EM of a conductive level is applied, and during the non-emission period EM_OFF, an emission signal EM of a cut-off level is applied. Here, the non-emission period EM_OFF includes an initial period Pi and a sampling period Ps, and the data voltage Vdata may be written into the sub-pixel SP during the non-emission period EM_OFF.

[0069] When the non-emission time period EM_OFF starts, the fourth switch TFT T4 applies the anode reset voltage VAR to the anode of the OLED until immediately before the emission time period EM_ON starts in response to the low-level fourth scan signal Scan4 which is the turn-on voltage.

[0070] During the initial time period Pi and the sampling time period Ps, a high-level first scan signal Scan1 (i.e., the turn-on voltage) is applied. During the initial time period Pi and the sampling time period Ps, the first switch TFT T1 connects the second node N2 and the third node N3 in response to the high-level first scan signal Scan1 (i.e., the turn-on voltage). Accordingly, the driving TFT DT enters the diode-connected state, in which the gate electrode and the drain electrode are short-circuited and operate as a diode.

[0071] During the initial time period Pi, a high-level third scan signal Scan3 (i.e., the turn-on voltage) is applied. The third switch TFT T3 is turned on by the turn-on voltage of the third scan signal Scan3 to apply the initialization voltage Vini to the second node N2. Since the second node N2 and the third node N3 are connected to each other, the second node N2 corresponding to the gate electrode of the driving TFT DT and the third node N3 corresponding to the drain electrode of the driving TFT DT are initialized to the initialization voltage Vini. The initialization voltage Vini can be selected within a voltage range sufficiently lower than the operating voltage of the OLED and can be set to a voltage equal to or lower than the low voltage EVSS.

[0072] The sampling time period Ps is a time period during which the threshold voltage Vth of the driving TFT DT is sampled and the data voltage Vdata is programmed. Figure 4 is a diagram showing a method of operating the sub-pixel SP during the sampling time period Ps.

[0073] Reference Figure 3 and Figure 4, during the sampling period Ps, a second scan signal Scan2 of low level (i.e., conduction voltage) is applied. The second switch TFT T2 applies the data voltage signal Vdata applied from the data line to the first node N1 corresponding to the first electrode of the driving TFT DT in response to the second scan signal Scan2 of low level (i.e., conduction voltage). During the sampling period Ps, the driving TFT DT is turned on, and a current Ids flows between the source and drain of the driving TFT DT. Since the gate electrode and the drain electrode of the driving TFT DT are diode-connected, the voltage at the second node N2 rises until the gate-source voltage Vgs of the driving TFT DT reaches the threshold voltage Vth due to the current flowing from the source electrode to the drain electrode. During the sampling period Ps, the second node N2 is charged to a voltage Vdata - |Vth| corresponding to the difference between the data voltage Vdata and the threshold voltage Vth of the driving TFT DT. In this way, the voltage at the second node N2 is determined by the data voltage Vdata and the threshold voltage Vth of the driving TFT DT, regardless of the high voltage EVDD during the sampling period Ps.

[0074] Figure 5 is a diagram showing a method of operating the sub-pixel SP during the emission period Pe.

[0075] Reference Figure 3 and Figure 5 , when a low-level emission signal EM as a conduction voltage (EM_ON) is applied during the emission period Pe, the first emission control TFT ET1 and the second emission control TFT ET2 are turned on. When the first emission control TFT ET1 is turned on, the high voltage EVDD is applied to the first node N1, and as the second emission control TFT ET2 is turned on, a current path is formed between the third node N3 and the fourth node N4. Therefore, the driving current Ioled generated by the source and drain electrodes of the driving TFT DT can be applied to the OLED to emit light. In this way, during the emission period Pe, the high voltage EVDD is applied to the first node N1 corresponding to the source electrode of the driving TFT DT, so the OLED emits light according to the data voltage Vdata programmed during the sampling period Ps.

[0076] However, the high voltage EVDD may fluctuate due to various reasons such as IR drop. When the high voltage changes and is thus applied as EVDD’, the voltage DRS of the source electrode of the driving TFT DT also changes. As a result, the gate-source voltage Vgs of the driving TFT DT also changes to Vgs’. As a result, there is a problem that the emission luminance of the sub-pixel SP is different from the expected luminance. To solve the problem of luminance change caused by the change in the gate-source voltage Vgs of the driving TFT DT due to the change in the high voltage EVDD, the sub-pixel structure according to an aspect of the present disclosure is applicable.

[0077] The sub-pixel according to the first aspect of the present disclosure is different from Figure 2 the conventional sub-pixel shown in that the former further includes a voltage compensation circuit that reflects, in the gate electrode of the driving TFT DT, the difference between the first high voltage EVDD during the non-emission period when sampling the data voltage and the first high voltage EVDD during the period when the first high voltage EVDD is applied to the source electrode of the driving TFT DT to cause emission. That is, by using the voltage compensation circuit to reflect the change in the first high voltage EVDD applied to the source electrode of the driving TFT DT during the emission operation of the driving TFT DT in the gate electrode of the driving TFT DT, the change range of the gate-source voltage Vgs of the driving TFT DT can be reduced.

[0078] Figure 6 is a circuit diagram of the sub-pixel according to the first aspect of the present disclosure, and Figure 7 is Figure 6 the driving waveform diagram of the sub-pixel.

[0079] Referring to Figure 6 and Figure 7 , a sub-pixel SP can be provided with a first high voltage EVDD, a low voltage EVSS, an initialization voltage Vini, and an anode reset voltage VAR, can receive a first scan signal Scan1 to a fourth scan signal Scan4, an emission signal EM, and a data voltage signal Vdata, and can also receive a second high voltage ADD-VDD. The second high voltage ADD-VDD can be supplied independently of the first high voltage EVDD so that the second high voltage ADD-VDD is not affected by the change in the first high voltage EVDD. The second high voltage ADD-VDD can be supplied at the same level as the first high voltage EVDD.

[0080] A sub-pixel SP may include an OLED, a driving TFT DT, a first capacitor C1, a first emission control TFT ET1, a second emission control TFT ET2, and first to fourth switching TFTs T1 to T4, and the sub-pixel according to the first aspect of the present disclosure may further include a fifth switching TFT T5 and a sixth switching TFT T6 and a second capacitor C2 to compensate for the gate voltage of the driving TFT DT according to a change in a first high voltage EVDD. Each TFT of the sub-pixel SP may be configured as a p-type MOSFET (PMOS) or an n-type MOSFET (NMOS). For example, the driving TFT DT, the first emission control TFT ET1, the second emission control TFT ET2, the second switching TFT T2, the fourth switching TFT T4, and the fifth switching TFT T5 may be implemented as p-type MOSFETs, and the first switching TFT T1, the third switching TFT T3, and the sixth switching TFT T6 may be implemented as n-type MOSFETs, but it is not limited thereto.

[0081] Figure 6 The sub-pixel according to the first aspect of the present disclosure shown Figure 2 differs from the conventional sub-pixel shown in the circuit configuration of the region of the second node N2 connected to the gate electrode of the driving TFT DT.

[0082] The sub-pixel according to the first aspect of the present disclosure may further include a second capacitor C2 connected to the second node N2, a fifth switching TFT T5 that allows the first high voltage EVDD to be applied to the second capacitor C2 when an input conduction-level emission signal EM_ON is received, and a sixth switching TFT T6 that allows a second high voltage ADD-VDD to be applied to the second capacitor C2 when an input cut-off-level emission signal EM_OFF is received.

[0083] Although both the fifth switching TFT T5 and the sixth switching TFT T6 operate by receiving the emission signal EM, either the fifth switching TFT T5 or the sixth switching TFT T6 may be turned on according to the high / low level of the emission signal EM because the fifth switching TFT T5 and the sixth switching TFT T6 are different types of TFTs.

[0084] The gate electrode of the fifth switching TFT T5 receives the emission signal EM, its first electrode is provided with the first high voltage EVDD, and its second electrode is connected to the second capacitor C2. When an input conduction-level emission signal EM_ON is received, the fifth switching TFT T5 is turned on to allow the first high voltage EVDD to be applied to the second capacitor C2. Accordingly, the fifth switching TFT T5 may be implemented as the same p-type MOSFET (PMOS) as the first emission control TFT ET1 and the second emission control TFT ET2.

[0085] The gate electrode of the sixth switching TFT T6 receives the emission signal EM, the first electrode is supplied with the second high voltage ADD-VDD, and the second electrode is connected to the second capacitor C2. When the input cut-off level emission signal EM_OFF is received, the sixth switching TFT T6 is turned on to allow the second high voltage ADD-VDD to be applied to the second capacitor C2. Accordingly, the sixth switching TFT T6 can be implemented as an n-type MOSFET (NMOS).

[0086] The first electrode of the second capacitor C2 is connected to the second node N2 to which the gate electrode of the driving TFT DT is connected, and the second electrode of the second capacitor C2 is connected to the connection node between the fifth switching TFT T5 and the sixth switching TFT T6. Depending on the on / off operation of the fifth switching TFT T5 and the sixth switching TFT T6, the first high voltage EVDD or the second high voltage ADD-VDD can be applied to the second electrode of the second capacitor C2. As a result, the difference between the first high voltage EVDD and the second high voltage ADD-VDD can be reflected in the second node N2 to which the first electrode of the second capacitor C2 is connected. The node to which the second electrode of the second capacitor C2 is connected, i.e., the node to which the fifth switching TFT T5 or the sixth switching TFT T6 is connected, is referred to as an additional gate electrode node ADD-DRG.

[0087] During the non-emission period (EM_OFF period), the sixth switching TFT T6 is turned on, and accordingly, the second high voltage ADD-VDD can be applied to the second capacitor C2. Thus, the second high voltage ADD-VDD is reflected in the additional gate electrode node ADD-DRG. During the emission period (EM_ON period), the fifth switching TFT T5 is turned on, and accordingly, the first high voltage EVDD can be applied to the second capacitor C2. Thus, the first high voltage EVDD is reflected in the additional gate electrode node ADD-DRG. The first high voltage EVDD may change due to various reasons such as IR drop, but the second high voltage ADD-VDD is not affected by the change in the first high voltage EVDD. Accordingly, when the first high voltage EVDD is applied during the emission period (EM_ON period) after sampling the data voltage Vdata (applying the second high voltage ADD-VDD) during the non-emission period (EM_OFF period), the voltage difference between the first high voltage EVDD and the second high voltage ADD-VDD can be reflected in the second node N2 to which the second capacitor C2 is connected.

[0088] Reference Figure 8, during the non-emission time period (EM_OFF time period), the sixth switching TFT T6 is turned on and the fifth switching TFT T5 is turned off. Therefore, the second high voltage ADD-VDD is applied to the second capacitor C2, and thus the additional gate electrode node ADD-DRG can be maintained at the second high voltage ADD-VDD. Here, the non-emission time period EM_OFF includes the sampling time period Ps. Therefore, when the voltage of the additional gate electrode node ADD-DRG is maintained at the second high voltage ADD-VDD, the second node N2 is charged to a voltage Vdata - |Vth| corresponding to the difference between the data voltage Vdata and the threshold voltage Vth of the driving TFT DT.

[0089] Reference Figure 9 and Figure 7 , during the emission time period (EM_ON time period), the sixth switching TFT T6 is turned off and the fifth switching TFT T5 is turned on. Therefore, the first high voltage EVDD is applied to the second capacitor C2, and thus the additional gate electrode node ADD-DRG can be maintained at the first high voltage EVDD. The second high voltage ADD-VDD is an independent voltage and is not affected by the first high voltage EVDD. Therefore, when the first high voltage EVDD changes during the emission time period after the sampling time period, the changed first high voltage is sent to the second node N2 according to the capacitive coupling between the second capacitor C2 and the second node N2.

[0090] Therefore, as shown in Figure 7 showing the voltage changes in the node N1 (source node DRS of the driving TFT) and the node N2 (gate node DRG of the driving TFT), the voltage of the second node N2 (gate node DRG of the driving TFT) may also change due to the voltage change of the first node N1 (source node DRS of the driving TFT) caused by the change of the first high voltage EVDD. As a result, the change in the gate-source voltage Vgs can be reduced.

[0091] Figure 10 is a graph showing the result of simulating the voltage compensation effect of the second node N2 (gate node DRG of the driving TFT) according to the capacitance ratio of the first capacitor C1 and the second capacitor C2, and showing the measured voltages of the source node DRS and the gate node DRG of the driving TFT DT when the first high voltage EVDD is 2.8V during the sampling period and changes to 2.5V during the emission period.

[0092] Theoretically, the compensation value of the gate node DRG of the driving TFT DT can satisfy the following expression:

[0093] <Expression 1>

[0094]

[0095] As a result of the simulation, it can be determined that the Vgs for driving the TFT DT has changed from 3.91 V to 3.90 V, and thus a voltage difference of 10 mV has occurred when the Cst of the first capacitor C1 is 0 [fF] and the Cst2 of the second capacitor C2 is 110 [fF], as shown in the graph of Figure 10 .

[0096] It can be determined that the Vgs for driving the TFT DT has changed from 3.89 V to 3.74 V, and thus a voltage difference of 150 mV has occurred when the Cst of the first capacitor C1 is 55 [fF] and the Cst2 of the second capacitor C2 is 55 [fF].

[0097] Therefore, it can be determined that the greater the capacitance value of the second capacitor C2 is than that of the first capacitor C1, the more the compensation effect of the Vgs for driving the TFT DT is improved.

[0098] Meanwhile, when the second capacitor C2 is used as a storage capacitor instead of a voltage compensation capacitor, the first capacitor C1 can be eliminated. That is, the first capacitor C1 fixed to the first high voltage EVDD is eliminated, and the second capacitor C2 to which the second high voltage ADD-VDD is applied during the non-emission period (EM_OFF period) and the first high voltage EVDD is applied during the emission period (EM_ON period) can be used as a storage capacitor for sampling the data voltage Vdata.

[0099] In the case of operating with only the second capacitor C2 without the first capacitor C1, the data voltage Vdata of the second node N2 can be stored in the second capacitor C2 to which the second high voltage ADD-VDD is applied during the non-emission period (EM_OFF period). Thereafter, during the emission period (EM_ON period), the first high voltage EVDD is applied to the second capacitor C2, and thus the difference between the second high voltage ADD-VDD and the first high voltage EVDD can be reflected in the second node N2. Therefore, the difference between the first high voltage EVDD and the second high voltage ADD-VDD can be reflected in the second node N2, while the voltage at the source node DRS changes due to the change in the first high voltage EVDD during the emission period (EM_ON period). That is, as the first high voltage EVDD changes, the voltages at the gate node DRG and the source node DRS of the driving TFT DT also change, and as a result, the gate-source voltage Vgs can be maintained.

[0100] Figure 11 and Figure 12It is a graph showing the results of simulating the change in the gate-source voltage Vgs in a comparative example applying a conventional sub-pixel structure and in an aspect of a sub-pixel structure applying the first aspect of the present disclosure under the same conditions where the first high voltage EVDD changes. Figure 11 is a simulation diagram of the comparative example and Figure 12 is a simulation diagram of the said aspect.

[0101] Reference Figure 11 to the simulation diagram of the comparative example shown in, it can be determined that even if the first high voltage EVDD changes from 2.8V to 2.5V, the voltages at the source node DRS and the gate node DRG of the driving TFT DT do not change during the sampling period. It can be determined that the voltage at the source node DRS changes according to the change in the first high voltage EVDD, while the voltage at the gate node DRG is not affected by the change in the first high voltage EVDD during the emission period. Therefore, it can be determined that the brightness will change because there is a difference between the gate-source voltage Vgs in the sampling period and the gate-source voltage Vgs in the emission period.

[0102] Reference Figure 12 to the simulation diagram of the said aspect shown in, it can be determined that even if the first high voltage EVDD changes from 2.8V to 2.5V, the voltages at the source node DRS and the gate node DRG of the driving TFT DT do not change during the sampling period. It can be determined that during the emission period, the voltage at the source node DRS changes according to the change in the first high voltage EVDD and the voltage at the gate node DRG also changes according to the change in the first high voltage EVDD. That is to say, as the first high voltage EVDD changes, the voltage at the source node DRS and the voltage at the gate node DRG of the driving TFT DT change together, and as a result, the gate-source voltage Vgs can be maintained. Therefore, it can be determined that the brightness will be maintained even if the first high voltage EVDD changes.

[0103] Figure 13 is a circuit diagram of a sub-pixel according to the second aspect of the present disclosure, and Figure 14 is Figure 13 the driving waveform diagram of the sub-pixel. The sub-pixel according to the second aspect of the present disclosure is different from the sub-pixel according to the first aspect in that the former includes a configuration for supplying a conduction bias stress (OBS) voltage Vobs to the source node of the driving TFT DT.

[0104] Reference Figure 13 and Figure 14, a sub-pixel SP may be provided with a first high voltage EVDD, a low voltage EVSS, an initialization voltage Vini, an anode reset voltage VAR, an OBS voltage Vobs, and a second high voltage Add-VDD, and may receive a first scan signal Scan1 to a fourth scan signal Scan4, an emission signal EM, and a data voltage signal Vdata. The second high voltage Add-VDD may be independent of the first high voltage EVDD, although it has the same voltage level as the first high voltage EVDD. Therefore, the second high voltage Add-VDD may not be affected by the change of the first high voltage EVDD.

[0105] A sub-pixel SP may include an OLED, a driving TFT DT, a first capacitor C1, a second capacitor C2, a first emission control TFT ET1, a second emission control TFT ET2, and a first switch TFT T1 to a seventh switch TFT T7. Each TFT of the sub-pixel SP may be configured as a p-type MOSFET (PMOS) or an n-type MOSFET (NMOS). For example, the driving TFT DT, the first emission control TFT ET1, the second emission control TFT ET2, the first switch TFT T1, the fourth switch TFT T4, the fifth switch TFT T5, and the seventh switch TFT T7 may be implemented as p-type MOSFETs, and the second switch TFT T2, the third switch TFT T3, and the sixth switch TFT T6 may be implemented as n-type MOSFETs, but not limited thereto.

[0106] Figure 13 The sub-pixel according to the second aspect of the present disclosure shown in Figure 6 differs from the sub-pixel according to the first aspect shown in the circuit configuration of the region of the first node N1 connected to the source electrode of the driving TFT DT.

[0107] The sub-pixel according to the second aspect of the present disclosure may further include a seventh switch TFT T7 for supplying the OBS voltage Vobs to the first node N1 connected to the source electrode of the driving TFT DT.

[0108] The seventh switch TFT T7 may apply the OBS voltage Vobs to the first node N1 connected to the source electrode of the driving TFT DT when receiving the fourth scan signal Scan4, and the fourth switch TFT T4 applies the anode reset voltage VAR to the anode of the OLED.

[0109] The seventh switching TFT T7 may include a gate electrode connected to an input line through which a fourth scan signal scan4 is applied, a first electrode to which an OBS voltage Vobs is applied, and a second electrode connected to a first node N1. The seventh switching TFT T7 may be a p-type MOSFET (PMOS) and may be implemented as a low temperature polycrystalline silicon (LTPS) thin film transistor. Accordingly, the seventh switching TFT T7 may apply the OBS voltage Vobs to the first electrode of the driving TFT DT in response to a low level third scan signal Scan3 (i.e., a turn-on voltage).

[0110] Except for the seventh switching TFT T7, the first emission control TFT ET1, the second emission control TFT ET2, and the first switching TFT T1 - the sixth switching TFT T6 operate in the same manner as those in the sub-pixel according to the first aspect.

[0111] Reference Figure 13 and Figure 14 According to the second aspect of the present disclosure, the driving period of the sub-pixel includes an emission period EM_ON and a non-emission period EM_OFF. During the emission period EM_ON, an emission signal EM of a conductive level is applied, and during the non-emission period EM_OFF, an emission signal EM of a cut-off level is applied. The non-emission period EM_OFF may include an initial period Pi, a sampling period Ps, and a plurality of OBS periods.

[0112] When the non-emission period EM_OFF starts, a first OBS operation OBS1 may be performed. During the first OBS operation OBS1, a low level fourth scan signal Scan4 (i.e., a turn-on voltage) is applied. In response to the conductive level fourth scan signal Scan4, the seventh switching TFT T7 that applies the OBS voltage Vobs to the first node N1 of the driving TFT DT and the fourth switching TFT T4 that applies an anode reset voltage VAR to a fourth node N4 corresponding to the anode of the OLED are turned on. When the fourth switching TFT T4 is turned on, the anode of the OLED is reset by the anode reset voltage VAR, and thus the emission characteristics of the OLED may be maintained. When the seventh switching TFT T7 is turned on, the OBS voltage Vobs is applied to the driving TFT DT, and thus the hysteresis phenomenon of the driving TFT DT may be alleviated.

[0113] During the initial period Pi and the sampling period Ps, a first scan signal Scan1 at a high level (i.e., a conduction voltage) is applied. During the initial period Pi and the sampling period Ps, the first switching TFT T1 connects the second node N2 and the third node N3 in response to the first scan signal Scan1 at a high level (i.e., a conduction voltage). As a result, the driving TFT DT enters a diode-connected state, in which the gate electrode and the drain electrode are short-circuited and thus operates as a diode.

[0114] During the initial period Pi, a third scan signal Scan3 at a high level (i.e., a conduction voltage) is applied. The third switching TFT T3 is turned on by the conduction voltage of the third scan signal Scan3 to apply an initialization voltage Vini to the second node N2. Since the second node N2 and the third node N3 are connected to each other, the second node N2 corresponding to the gate electrode of the driving TFT DT and the third node N3 corresponding to the drain electrode are initialized to the initialization voltage Vini. The initialization voltage Vini can be selected within a voltage range sufficiently lower than the operating voltage of the OLED and can be set to a voltage equal to or lower than the low voltage EVSS.

[0115] During the sampling period Ps, a second scan signal Scan2 at a low level (i.e., a conduction voltage) is applied. The second switching TFT T2 applies a data voltage signal Vdata supplied from the data line to the first node N1 corresponding to the first electrode of the driving TFT DT in response to the second scan signal Scan2 at a low level (i.e., a conduction voltage). During the sampling period Ps, the driving TFT DT is turned on, and thus a current Ids flows between the source and the drain. Since the gate electrode and the drain electrode of the driving TFT DT are diode-connected, the voltage at the second node N2 rises until the gate-source voltage Vgs of the driving TFT DT reaches the threshold voltage Vth due to the current flowing from the source electrode to the drain electrode. During the sampling period Ps, the second node N2 is charged to a voltage Vdata - |Vth| corresponding to the difference between the data voltage Vdata and the threshold voltage Vth of the driving TFT DT. In this way, the voltage at the second node N2 can be determined by the data voltage Vdata and the threshold voltage Vth of the driving TFT DT, regardless of the high voltage EVDD during the sampling period Ps.

[0116] Thereafter, a second OBS operation OBS2 can be performed. During the second OBS operation OBS2, a low-level fourth scan signal Scan4 (i.e., the turn-on voltage) is applied, and thus an OBS voltage Vobs is applied to turn on the seventh switching TFT T7 of the first node N1 of the driving TFT DT and the fourth switching TFT T4 that applies an anode reset voltage VAR to the fourth node N4 corresponding to the anode of the OLED. Therefore, the anode of the OLED is reset by the anode reset voltage VAR, so that the emission characteristics of the OLED can be maintained. When the seventh switching TFT T7 is turned on, the OBS voltage Vobs is applied to the driving TFT DT, thereby alleviating the hysteresis phenomenon of the driving TFT DT.

[0117] As described above, during the non-emission time period (EM_OFF time period) when the data voltage Vdata is sampled, the sixth switching TFT T6 is turned on and the fifth switching TFT T5 is turned off. Therefore, the second high voltage ADD-VDD is applied to the second capacitor C2, and thus the additional gate electrode node ADD-DRG can be maintained at the second high voltage ADD-VDD.

[0118] When a low-level emission signal EM (i.e., the turn-on voltage (EM_ON)) is applied, during the emission time period Pe, the first emission control TFT ET1 and the second emission control TFT ET2 are turned on. When the first emission control TFT ET1 is turned on, the high voltage EVDD is applied to the first node N1, and as the second emission control TFT ET2 is turned on, a current path is formed between the third node N3 and the fourth node N4. Therefore, the driving current Ioled generated by the source electrode and the drain electrode of the driving TFT DT can be applied to the OLED to emit light. In this way, during the emission time period Pe, the high voltage EVDD can be applied to the first node N1 corresponding to the source electrode of the driving TFT DT, so that the OLED emits light according to the data voltage Vdata programmed during the sampling time period Ps.

[0119] Here, during the emission time period (EM_ON time period), the sixth switching TFT T6 is turned off and the fifth switching TFT T5 is turned on. Therefore, the first high voltage EVDD is applied to the second capacitor C2, and thus the additional gate electrode node ADD-DRG can be maintained at the first high voltage EVDD. The second high voltage ADD-VDD is an independent voltage and is not affected by the first high voltage EVDD. Therefore, when the first high voltage EVDD changes during the emission time period after the sampling time period, the changed first high voltage is transmitted to the second node N2 according to the capacitive coupling between the second capacitor C2 and the second node N2.

[0120] Therefore, as shown in the voltage variations of node N1 (source node DRS of driving TFT DT) and node N2 (gate node DRG of driving TFT DT), Figure 14 as shown in Figure 14 , as the voltage at the first node N1 (source node DRS of driving TFT DT) changes due to the change in the high voltage EVDD, the voltage at the second node N2 (gate node DRG of driving TFT DT) can also change. As a result, the variation in the gate-source voltage Vgs can be reduced.

[0121] Figure 15 and Figure 16 are graphs showing the results of simulating the variation of the gate-source voltage Vgs in a comparative example applying a conventional sub-pixel structure and in an aspect of the sub-pixel structure applying the second aspect of the present disclosure under the same conditions where the first high voltage EVDD changes. Figure 15 is the simulation diagram of the comparative example and Figure 16 is the simulation diagram of the second aspect.

[0122] Referring to Figure 15 the simulation diagram of the comparative example shown in Figure 15 , it can be determined that even if the first high voltage EVDD changes from 2.8V to 2.5V, the voltages at the source node DRS and the gate node DRG of the driving TFT DT do not change during the non-emission period EM_OFF.

[0123] It can be determined that the voltage at the source node DRS changes according to the change in the first high voltage EVDD, while the voltage at the gate node DRG is not affected by the change in the first high voltage EVDD during the emission period EM_ON. Therefore, it is confirmed that when the first high voltage EVDD changes from 2.8V to 2.5V during the emission period EM_ON, a difference of 272 mV is generated in the gate-source voltage Vgs.

[0124] Referring to Figure 16 the simulation diagram of this aspect shown in Figure 16 , it can be determined that even if the high voltage EVDD changes from 2.8V to 2.5V, the voltages at the source node DRS and the gate node DRG of the driving TFT DT do not change during the non-emission period EM_OFF.

[0125] It can be determined that the voltage at the source node DRS changes according to the change in the first high voltage EVDD, and the voltage at the gate node DRG also changes according to the change in the first high voltage EVDD during the emission period EM_ON. That is, it is confirmed that the voltages of the source node DRS and the gate node DRG of the driving TFT DT change together with the change in the first high voltage EVDD. As a result, it is confirmed that when the first high voltage EVDD changes from 2.8V to 2.5V during the emission period EM_ON, a difference of 14mV is generated in the gate-source voltage Vgs.

[0126] As described above, under the same condition that the first high voltage EVDD changes from 2.8V to 2.5V, in Figure 15 the comparative example shown, the difference in the gate-source voltage Vgs during the emission period EM_ON is 272mV, while in the case of the present aspect, the difference in the gate-source voltage Vgs is only 14mV. Therefore, it can be confirmed that the difference in the gate-source voltage Vgs can be significantly reduced compared with the comparative example.

[0127] Each aspect of the present disclosure has the following effects.

[0128] Each aspect of the present disclosure can provide a display device capable of improving the accuracy and stability of the operation of sub-pixel driving transistors.

[0129] Each aspect of the present disclosure can provide a display device that can minimize the change in the brightness of the display device by minimizing the change in the gate-source voltage Vgs of the driving transistor even when the high voltage EVDD changes due to various reasons such as IR drop.

[0130] The effects according to the present disclosure are not limited to the above effects, and various other effects are also within the scope of the present disclosure.

[0131] Although each aspect of the present disclosure has been described in detail with reference to the accompanying drawings, the present disclosure is not necessarily limited to these aspects, and various modifications can be made without departing from the technical spirit of the present disclosure. Therefore, each aspect disclosed in the present disclosure is not intended to limit the technical concept of the present disclosure, but to explain the technical concept, and the scope of the technical concept of the present disclosure is not limited by these aspects. Therefore, the above aspects should be understood as illustrative rather than restrictive in all aspects. The scope of the present disclosure should be interpreted according to the claims, and all technical concepts within the equivalent scope should be interpreted as being within the scope of the present disclosure.

Claims

1. A display device, comprising: a light-emitting element; a first high-voltage source that supplies a first high voltage; a driving thin-film transistor including a first electrode, a second electrode connected to the light-emitting element, and a gate electrode, wherein a voltage level of the gate electrode is determined according to a data voltage input to the first electrode in a state where the gate electrode is connected to the second electrode during a non-emission period, and the driving thin-film transistor is configured to receive the first high voltage through the first electrode to control a current applied to the light-emitting element according to a voltage difference between the gate electrode and the first electrode in a state where the gate electrode is disconnected from the second electrode during an emission period; and a voltage compensation unit configured to reflect a difference between the first high voltage during the emission period and the first high voltage during the non-emission period in the gate electrode.

2. The display device according to claim 1, further comprising: a first emission control thin-film transistor configured to be turned on during the emission period to connect the first electrode and the first high-voltage source; and a second emission control thin-film transistor configured to be turned on during the emission period to connect the second electrode and the light-emitting element.

3. The display device according to claim 1, further comprising: a first switching thin-film transistor configured to be turned on during the emission period to connect the gate electrode and the second electrode; a second switching thin-film transistor configured to be turned on during the non-emission period to connect an input line through which the data voltage is supplied to the first electrode; a third switching thin-film transistor configured to be turned on during the non-emission period to apply an initialization voltage to the gate electrode; and a fourth switching thin-film transistor configured to apply a reset voltage to a current input terminal of the light-emitting element.

4. The display device according to claim 1, further comprising a first capacitor connected between the first high-voltage source and the gate electrode.

5. The display device according to claim 1, wherein, The voltage compensation unit includes: a second high-voltage source that supplies a second high voltage having the same level as the first high voltage; a second capacitor connected to the gate electrode; a fifth switching thin-film transistor configured to connect the second capacitor and the first high-voltage source during the emission period; and a sixth switching thin-film transistor configured to connect the second capacitor and the second high-voltage source during the non-emission period.

6. The display device according to claim 5, further comprising a first capacitor connected between the first high-voltage source and the gate electrode, Among them, During the non-emission time period, the second capacitor connected to the second high voltage source and the first capacitor connected to the first high voltage source are connected in parallel, and during the emission time period, the second capacitor connected to the first high voltage source and the first capacitor connected to the first high voltage source are connected in parallel.

7. The display device according to claim 5, wherein, The second capacitor reflects, in the gate electrode, a difference between the voltage of the second high voltage source connected to the second capacitor during the non-emission time period and the voltage of the first high voltage source connected to the second capacitor during the emission time period.

8. The display device according to claim 5, further comprising: A first emission control thin film transistor configured to be turned on during the emission time period to connect the first electrode and the first high voltage source; And A second emission control thin film transistor configured to be turned on during the light emission time period to connect the second electrode and the light emitting element, wherein the fifth switching thin film transistor connects the second capacitor and the first high voltage source by receiving a turn-on level emission signal input to the first emission control thin film transistor and the second emission control thin film transistor, and the sixth switching thin film transistor connects the second capacitor and the second high voltage source by receiving a turn-off level emission signal input to the first emission control thin film transistor and the second emission control thin film transistor.

9. The display device according to claim 5, further comprising a seventh switching thin film transistor configured to be turned on during the non-emission time period to apply a turn-on bias stress (OBS) voltage to the first electrode.

10. A display device, comprising: A light emitting element; A first high voltage source that supplies a first high voltage; A second high voltage source that supplies a second high voltage; A driving thin film transistor including a first electrode connected to a first node, a second electrode connected to a third node, and a gate electrode connected to a second node; A first emission control thin film transistor configured to be turned on by a turn-on level emission signal to connect the first high voltage source and the first node; A second emission control thin film transistor configured to be turned on by the turn-on level emission signal to connect the third node and the light emitting element; A first switching thin film transistor configured to be turned on by a turn-on level first scan signal to connect the gate electrode and the second electrode; A second switching thin film transistor configured to be turned on by a turn-on level second scan signal to connect an input line through which a data voltage is supplied to the first node; A fifth switching thin film transistor configured to be turned on by an emission signal at the conductive level to connect the first high voltage source and the second node; A sixth switching thin film transistor configured to be turned on by an emission signal at the cut-off level to connect the second high voltage source and the second node; and A second capacitor having a first electrode connected to the second node and a second electrode connected to the fifth switching thin film transistor or the sixth switching thin film transistor.

11. The display device according to claim 10, further comprising a first capacitor having a first electrode connected to the second node and a second electrode connected to the first high voltage source.

12. The display device according to claim 10, further comprising: A third switching thin film transistor configured to be turned on by a third scan signal at the conductive level to apply an initialization voltage to the second node; and A fourth switching thin film transistor configured to be turned on by a fourth scan signal at the conductive level to apply a reset voltage to the current input terminal of the light emitting element.

13. The display device according to claim 12, further comprising a seventh switching thin film transistor configured to be turned on by the fourth scan signal at the conductive level to apply a conductive bias stress (OBS) voltage to the first electrode.

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