Display device

Abstract

The invention relates to a display device. The display device includes: a substrate including a display area and a bending area on one side of the display area, a lower surface of the substrate defining a plurality of openings; a shielding layer disposed along a profile of the lower surface of the substrate and continuously extending within the plurality of openings; and a first organic layer disposed under the shielding layer and planarizing a lower surface of the shielding layer.

Description

Technical Field

[0001] The present disclosure generally relates to a display device. More specifically, the present disclosure relates to a display device that provides visual information. Background Art

[0002] With the development of information technology, the importance of display devices as a connection medium between users and information has become increasingly prominent. For example, the use of display devices such as liquid crystal display (LCD) devices, organic light-emitting display (OLED) devices, plasma display panel (PDP) devices, quantum dot display devices, etc. is increasing.

[0003] The display device may include a flexible display panel. The display panel may include a display area for displaying an image, a bending area located on one side of the display area, and a pad area spaced apart from the display area, wherein the bending area is between the display area and the pad area. A driving chip for driving pixels may be disposed in the pad area.

[0004] In order to reduce the heat transfer from the driving chip to the display panel, a heat dissipation member for dissipating the heat generated by the driving chip may be disposed on the rear surface of the display panel. In addition, in order to protect the display panel from external impacts, a buffer member may be disposed on the rear surface of the display panel. Summary of the Invention

[0005] Embodiments provide a display device including a shielding layer having improved heat dissipation characteristics.

[0006] Embodiments provide a display device including an organic layer having improved buffer characteristics.

[0007] A display device according to an embodiment of the present disclosure includes: a substrate including a display area and a bending area located on one side of the display area, a lower surface of the substrate defining a plurality of openings; a shielding layer disposed along the lower surface of the substrate and continuously extending within the plurality of openings; and a first organic layer disposed under the shielding layer and flattening the lower surface of the shielding layer.

[0008] In an embodiment, the shielding layer may define a plurality of grooves respectively overlapping the plurality of openings. The first organic layer may cover the plurality of grooves.

[0009] In an embodiment, the first organic layer may fill the plurality of grooves.

[0010] In an embodiment, each of the plurality of grooves may include pores.

[0011] In an embodiment, a first elastic modulus of the first organic layer may be less than a second elastic modulus of the substrate.

[0012] In an embodiment, the shielding layer may include at least one of copper, graphite, and carbon nanotubes.

[0013] In an embodiment, the first organic layer may include an organic material, and the organic material includes a light-blocking material having a black color.

[0014] In an embodiment, in a plan view, a plurality of openings may overlap with the display area and may be spaced apart from the bending area.

[0015] In an embodiment, in a plan view, each of the shielding layer and the first organic layer may overlap with the display area and may be spaced apart from the bending area.

[0016] In an embodiment, each of the plurality of openings may penetrate the substrate in the thickness direction of the substrate.

[0017] In an embodiment, the substrate may further include a pad area that is spaced apart from the display area in a plan view, and the bending area is between the pad area and the display area.

[0018] In an embodiment, the display device may further include a second organic layer disposed on the lower surface of the substrate and overlapping with the pad area in a plan view.

[0019] In an embodiment, the second organic layer and the first organic layer may include the same material.

[0020] In an embodiment, the second organic layer may include a material different from that of the first organic layer. A third elastic modulus of the second organic layer may be greater than a first elastic modulus of the first organic layer.

[0021] A display device according to an embodiment of the present disclosure includes: a substrate including a display area and a bending area located on one side of the display area, a lower surface of the substrate defining a plurality of openings; a first organic layer disposed under the substrate and covering the plurality of openings; and a shielding layer disposed under the first organic layer and covering a lower surface of the first organic layer.

[0022] In an embodiment, the first organic layer may fill the plurality of openings.

[0023] In an embodiment, the first organic layer may be disposed outside the plurality of openings, and each of the plurality of openings may include pores.

[0024] In an embodiment, the shielding layer may have a flat upper surface.

[0025] In an embodiment, a first elastic modulus of the first organic layer may be less than a second elastic modulus of the substrate.

[0026] In an embodiment, the shielding layer may include at least one of copper, graphite, and carbon nanotubes.

[0027] In an embodiment, the first organic layer may include an organic material, and the organic material includes a light-blocking material having a black color.

[0028] In an embodiment, in a plan view, a plurality of openings may overlap with the display area and may be spaced apart from the bending area.

[0029] In an embodiment, in a plan view, each of the shielding layer and the first organic layer may overlap with the display area and may be spaced apart from the bending area.

[0030] In an embodiment, each of the plurality of openings may penetrate the substrate in the thickness direction of the substrate.

[0031] In an embodiment, the substrate may further include a pad area, the pad area is spaced apart from the display area in a plan view, and the bending area is between the pad area and the display area.

[0032] In an embodiment, the display device may further include a second organic layer, the second organic layer is disposed on the lower surface of the substrate, and overlaps with the pad area in a plan view.

[0033] In an embodiment, the second organic layer and the first organic layer may include the same material.

[0034] In an embodiment, the second organic layer may include a material different from that of the first organic layer. A third elastic modulus of the second organic layer may be greater than a first elastic modulus of the first organic layer.

[0035] A display device according to an embodiment of the present disclosure may include a substrate having a plurality of openings defined on its lower surface, a shielding layer disposed along a contour of the lower surface of the substrate and continuously extending within the openings, and a first organic layer disposed below the shielding layer.

[0036] Since the openings are defined on the lower surface of the substrate and the shielding layer is disposed along the contour of the lower surface of the substrate, the shielding layer may respectively define a plurality of grooves overlapping with the openings. Therefore, the area of the shielding layer in contact with the substrate can be increased, and the surface area of the shielding layer can be increased. As a result, the shielding layer can effectively dissipate heat generated from the driving chip and can effectively shield electromagnetic interference noise.

[0037] A display device according to an embodiment of the present disclosure may include a substrate having a plurality of openings defined on its lower surface, a first organic layer disposed below the substrate and covering the openings, and a shielding layer disposed below the first organic layer. The first organic layer may be filled within the openings.

[0038] The first elastic modulus of the first organic layer may be less than the second elastic modulus of the substrate. When the first organic layer is filled in the opening, the substrate and the first organic layer may be arranged in the order of substrate, first organic layer, substrate, and first organic layer along one direction. That is, the substrate having a relatively large second elastic modulus and the first organic layer having a relatively small first elastic modulus may be alternately arranged along one direction. Therefore, the first organic layer can effectively protect the substrate from external impacts. Description of the Drawings

[0039] Exemplary, non-limiting embodiments will be understood more clearly from the following detailed description in conjunction with the accompanying drawings.

[0040] Figure 1 is a plan view showing a display device according to an embodiment of the present disclosure.

[0041] Figure 2 is showing Figure 1 a view of the bent shape of the display device of

[0042] Figure 3 is showing Figure 1 a cross-sectional view of the display device of

[0043] Figure 4 is a cross-sectional view taken along line I-I' of Figure 1 of

[0044] Figure 5A is showing Figure 3 a plan view of the substrate of

[0045] Figure 5B is Figure 3 an enlarged cross-sectional view of region “A” of

[0046] Figure 6 is a cross-sectional view showing a display device according to an embodiment of the present disclosure.

[0047] Figure 7 is Figure 6 an enlarged cross-sectional view of region “B” of

[0048] Figure 8 is a cross-sectional view showing a display device according to an embodiment of the present disclosure.

[0049] Figure 9 is Figure 8 an enlarged cross-sectional view of region “C” of

[0050] Figure 10 is a cross-sectional view showing a display device according to an embodiment of the present disclosure.

[0051] Figure 11 is Figure 10An enlarged cross-sectional view of the region "D". Detailed Description of the Invention

[0052] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components will be omitted.

[0053] Figure 1 is a plan view showing a display device DD according to an embodiment of the present disclosure. Figure 2 is showing Figure 1 a view of the curved shape of the display device DD.

[0054] In the present specification, a plane may be defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the first direction DR1 and the second direction DR2 may be perpendicular to each other. The direction perpendicular to the plane (i.e., the thickness direction of the display device DD) may be a third direction DR3. In other words, the third direction DR3 may be perpendicular to each of the first direction DR1 and the second direction DR2.

[0055] Referring to Figure 1 and Figure 2 , a display device DD according to an embodiment of the present disclosure may include a substrate SUB, a driving chip D-IC, a plurality of transmission lines TL, and a plurality of pads PDD.

[0056] The substrate SUB may include a display area DA and a non-display area NDA. The display area DA may be defined as an area for displaying an image by generating light or adjusting the transmittance of light provided from an external light source. A plurality of pixels PX may be provided in the display area DA. Each of the pixels PX may generate light in response to a driving signal. For example, the pixels PX may be arranged in a matrix form along the first direction DR1 and the second direction DR2.

[0057] The non-display area NDA may be defined as an area that does not display an image. The non-display area NDA may include a peripheral area PA, a bending area BA, and a pad area PDA.

[0058] The peripheral area PA may be located around the display area DA. The peripheral area PA may surround at least a part of the display area DA. For example, in a plan view, the peripheral area PA may completely surround the display area DA.

[0059] The bending area BA may be located on one side of the display area DA. Specifically, the bending area BA may extend from one side of the peripheral area PA and may be bent downward. In other words, as Figure 2As shown, the substrate SUB can be bent in the bending region BA around a reference axis parallel to the first direction DR1. In this case, the pad region PDA can be located on the lower surface of the display device DD. The pad region PDA can extend from the bending region BA and be located below the display region DA or the peripheral region PA. When the display device DD is unfolded, the bending region BA can be located between the display region DA and the pad region PDA. Specifically, when the display device DD is unfolded, the bending region BA can be located between the peripheral region PA and the pad region PDA.

[0060] The pad region PDA can be located on one side of the display region DA. For example, the pad region PDA and the display region DA can be spaced apart from each other in the second direction DR2. Specifically, in a plan view, the pad region PDA can be spaced apart from the display region DA, and the bending region BA is between the pad region PDA and the display region DA. The pad region PDA can extend in the first direction DR1. The pad PDD can be provided in the pad region PDA.

[0061] The transmission line TL can be provided on the substrate SUB. The transmission line TL can connect the display region DA and the pad region PDA. Each of the transmission lines TL can include a first end located in the pad region PDA and a second end adjacent to the display region DA. The first end of each of the transmission lines TL can be connected to the corresponding pad of the pad PDD. The second end of each of the transmission lines TL can be connected to a corresponding one of a plurality of lines (such as gate lines, data lines, driving voltage lines, etc.) provided in the display region DA. The pad PDD and the pixel PX can be electrically connected through the transmission line TL.

[0062] The driving chip D-IC can be provided in the pad region PDA on the substrate SUB. The driving chip D-IC can be connected to the pad PDD through an anisotropic conductive film (“ACF”). Specifically, the driving chip D-IC can include a plurality of bumps, and the plurality of bumps can be connected to the pad PDD through the anisotropic conductive film. The driving chip D-IC can provide a driving signal to the pixel PX. The driving signal can include various signals for driving the pixel PX, such as a driving voltage, a control signal, a data signal, etc. The driving signal can be transmitted to the pixel PX through the pad PDD and the transmission line TL.

[0063] Although not shown in Figure 1 and Figure 2 a printed circuit board (e.g., Figure 3 the flexible printed circuit board FPCB) can be provided in the pad region PDA on the substrate SUB. The printed circuit board can be coupled to the pad PDD through an anisotropic conductive film. For example, the printed circuit board can be a flexible printed circuit board.

[0064] Figure 3 is a cross-sectional view of a display device DD showing Figure 1 . Figure 4 is a cross-sectional view taken along line I-I' of Figure 1 . Figure 5A is a plan view of a substrate SUB showing Figure 3 . Figure 5B is an enlarged cross-sectional view of region “A” of Figure 3 .

[0065] Referring to Figure 3 , Figure 4 , Figure 5A and Figure 5B , a display device DD according to an embodiment of the present disclosure may include a cover window CW, an antireflection layer POL, a display panel DP, a shielding layer SHL, a first organic layer OGL1, a second organic layer OGL2, a first connection member CNM1, a second connection member CNM2, a reinforcement member BPL, a driving chip D-IC, a flexible printed circuit board FPCB, and a cover tape CT. The display panel DP may include a substrate SUB, a display element layer DPL, and a packaging layer TFE.

[0066] The substrate SUB may include a transparent material or an opaque material. The substrate SUB may be formed of a transparent resin substrate. In an embodiment, the substrate SUB may include polyimide. In this case, the substrate SUB may include a first organic layer, a first barrier layer, a second organic layer, and the like. In an embodiment, the substrate SUB may include a quartz substrate (such as a synthetic quartz substrate or a fluorine-doped quartz substrate), a calcium fluoride substrate, a soda-lime glass substrate, a non-alkali glass substrate, and the like. These may be used alone or in combination with each other.

[0067] The display element layer DPL may be disposed in a display area DA on the substrate SUB. Specifically, the display element layer DPL may be disposed on an upper surface of the substrate SUB. As Figure 4 shown, the display element layer DPL may include a thin film transistor TFT, a gate insulating layer GI, an interlayer insulating layer ILD, a via insulating layer VIA, a light emitting element LD, and a pixel defining layer PDL. The thin film transistor TFT may include an active pattern ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE. The light emitting element LD may include a pixel electrode PE, a light emitting layer EML, and a common electrode CE.

[0068] A buffer layer may be disposed between the substrate SUB and the display element layer DPL. The buffer layer can prevent metal atoms or impurities from diffusing from the substrate SUB into the upper structure (e.g., thin film transistor TFT, light emitting element LD, etc.). In addition, the buffer layer can obtain a substantially uniform active pattern ACT by controlling the heat transfer rate during the crystallization process for forming the active pattern ACT. In addition, when the surface of the substrate SUB is uneven, the buffer layer can be used to improve the flatness of the surface of the substrate SUB. That is, the buffer layer may include an inorganic insulating material. In an embodiment, the buffer layer may be omitted.

[0069] The active pattern ACT may be disposed on the substrate SUB. The active pattern ACT may include an oxide semiconductor, a silicon semiconductor, an organic semiconductor, etc. For example, the oxide semiconductor may include indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), zinc (Zn), etc. These may be used alone or in combination with each other. The silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. The active pattern ACT may include a source region, a drain region, and a channel region located between the source region and the drain region.

[0070] The gate insulating layer GI may be disposed on the active pattern ACT and the substrate SUB. The gate insulating layer GI may cover the active pattern ACT on the substrate SUB and may be disposed with a substantially uniform thickness along the contour of the active pattern ACT. In an embodiment, the gate insulating layer GI may sufficiently cover the active pattern ACT on the substrate SUB and may have a substantially flat upper surface without generating a step difference around the active pattern ACT. The gate insulating layer GI may include an inorganic insulating material. Examples of inorganic insulating materials that can be used as the gate insulating layer GI may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), etc. These may be used alone or in combination with each other. The gate insulating layer GI can electrically insulate the active pattern ACT from the gate electrode GE.

[0071] The gate electrode GE can be disposed on the gate insulating layer GI. The gate electrode GE can overlap with the channel region of the active pattern ACT. The gate electrode GE can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. Examples of materials that can be used as the gate electrode GE can include silver (Ag), an alloy including silver, molybdenum (Mo), an alloy including molybdenum, aluminum (Al), an alloy including aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc. These can be used alone or in combination with each other.

[0072] The interlayer insulating layer ILD can be disposed on the gate electrode GE and the gate insulating layer GI. The interlayer insulating layer ILD can cover the gate electrode GE on the gate insulating layer GI, and can be disposed with a substantially uniform thickness along the contour of the gate electrode GE. In an embodiment, the interlayer insulating layer ILD can sufficiently cover the gate electrode GE on the gate insulating layer GI, and can have a substantially flat upper surface without generating a step difference around the gate electrode GE. The interlayer insulating layer ILD can include an inorganic insulating material. Examples of inorganic insulating materials that can be used as the interlayer insulating layer ILD can include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), etc. These can be used alone or in combination with each other. The interlayer insulating layer ILD can electrically insulate the gate electrode GE from the source electrode SE. In addition, the interlayer insulating layer ILD can electrically insulate the gate electrode GE from the drain electrode DE.

[0073] The source electrode SE and the drain electrode DE can be disposed on the interlayer insulating layer ILD. The source electrode SE can be connected to the source region of the active pattern ACT through a contact hole formed by passing through the interlayer insulating layer ILD and the gate insulating layer GI. The drain electrode DE can be connected to the drain region of the active pattern ACT through a contact hole formed by passing through the interlayer insulating layer ILD and the gate insulating layer GI. Each of the source electrode SE and the drain electrode DE can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These can be used alone or in combination with each other.

[0074] Therefore, a thin film transistor TFT including the active pattern ACT, the gate electrode GE, the source electrode SE, and the drain electrode DE can be formed.

[0075] The via insulating layer VIA can be disposed on the interlayer insulating layer ILD. For example, the via insulating layer VIA can be disposed on the interlayer insulating layer ILD with a relatively thick thickness to sufficiently cover the source electrode SE and the drain electrode DE. The via insulating layer VIA can include an organic insulating material. Examples of the organic insulating material that can be used as the via insulating layer VIA can include photoresist, polyacrylic acid-based resin, polyimide-based resin, polyamide-based resin, silicone-based resin, acrylic acid-based resin, epoxy-based resin, etc. These can be used alone or in combination with each other.

[0076] The pixel electrode PE can be disposed on the via insulating layer VIA. The pixel electrode PE can be connected to the drain electrode DE through a contact hole formed through the via insulating layer VIA. Thus, the pixel electrode PE can be electrically connected to the thin film transistor TFT. For example, the pixel electrode PE can be a semi-transmissive electrode, a transmissive electrode, or a reflective electrode. The pixel electrode PE can include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. These can be used alone or in combination with each other. For example, the pixel electrode PE can be used as an anode electrode.

[0077] The pixel defining layer PDL can be disposed on the via insulating layer VIA. The pixel defining layer PDL can cover the edge of the pixel electrode PE and can expose a part of the upper surface of the pixel electrode PE. The pixel defining layer PDL can include an organic insulating material. Examples of the organic insulating material that can be used as the pixel defining layer PDL can include photoresist, polyacrylic acid-based resin, polyimide-based resin, polyamide-based resin, silicone-based resin, acrylic acid-based resin, epoxy-based resin, etc. These can be used alone or in combination with each other.

[0078] The light emitting layer EML can be disposed on the pixel electrode PE. Specifically, the light emitting layer EML can be disposed on the upper surface of the pixel electrode PE exposed by the pixel defining layer PDL. The light emitting layer EML can emit light having a specific color (e.g., red, green, and / or blue). In an embodiment, the light emitting layer EML can include one or both of an organic light emitting material and a quantum dot. For example, the light emitting layer EML can include an organic light emitting material including a fluorescent material or a phosphorescent material that emits red light, green light, blue light, or white light. The quantum dot can be a particle having a crystal structure with a size of several nanometers to dozens of nanometers and can include hundreds to thousands of atoms. The quantum dot can include a fluorescent material or a phosphorescent material and can produce monochromatic red light, green light, and blue light.

[0079] For example, the light emitting layer EML can have a single layer structure including one light emitting layer. In an embodiment, the light emitting layer EML can have a tandem structure in which a plurality of light emitting layers are stacked.

[0080] The common electrode CE can be disposed on the pixel defining layer PDL and the light emitting layer EML. The common electrode CE can be disposed along the contours of the pixel defining layer PDL and the light emitting layer EML with a substantially uniform thickness. In an embodiment, the common electrode CE can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These can be used alone or in combination with each other. For example, the common electrode CE can be used as a cathode electrode.

[0081] Thus, a light emitting element LD including a pixel electrode PE, a light emitting layer EML, and a common electrode CE can be formed.

[0082] The encapsulation layer TFE can be disposed on the common electrode CE. The encapsulation layer TFE can prevent impurities, moisture, etc. from infiltrating into the light emitting element LD from the outside. The encapsulation layer TFE can include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the inorganic encapsulation layer can include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), etc. These can be used alone or in combination with each other. That is, the organic encapsulation layer can include a cured polymer, such as polyacrylate.

[0083] The encapsulation layer TFE can have a structure in which the inorganic encapsulation layer and the organic encapsulation layer are alternately stacked. For example, the encapsulation layer TFE can have a three-layer structure in which two inorganic encapsulation layers and one organic encapsulation layer are alternately stacked. However, the present disclosure is not limited thereto, and the encapsulation layer TFE can have a five-layer structure in which three inorganic encapsulation layers and two organic encapsulation layers are alternately stacked, or the encapsulation layer TFE can have a seven-layer structure in which four inorganic encapsulation layers and three organic encapsulation layers are alternately stacked.

[0084] Although the display device DD of the present disclosure is described as an organic light emitting display (“OLED”) device, the configuration of the present disclosure is not limited thereto. In other embodiments, the display device DD can include a liquid crystal display (“LCD”) device, a field emission display (“FED”) device, a plasma display panel (“PDP”) device, an electrophoretic image display (“EPD”) device, an inorganic light emitting display (“ILED”) device, or a quantum dot display device.

[0085] As Figure 3As shown, the anti-reflection layer POL can be disposed in the display area DA on the display panel DP. Specifically, the anti-reflection layer POL can be disposed on the encapsulation layer TFE. The anti-reflection layer POL can reduce the external light reflection of the display device DD. With the reduction of the external light reflection, the visibility of the display device DD can be improved. The anti-reflection layer POL can include a polarizer and / or a phase retarder. For example, the anti-reflection layer POL can include a stretchable film type polarizer and / or phase retarder.

[0086] In an embodiment, the anti-reflection layer POL can include color filters and a black matrix disposed between the color filters. The color filters can have a predetermined arrangement. The color filters can be arranged according to the emission color of the light-emitting elements LD included in the display element layer DPL.

[0087] The cover window CW can be disposed on the anti-reflection layer POL. The cover window CW can be used to cover and protect the display panel DP. The cover window CW can be attached to the upper surface of the anti-reflection layer POL through an adhesive member. For example, the adhesive member can be a pressure-sensitive adhesive ("PSA") film, an optically clear adhesive ("OCA") film, an optically clear resin ("OCR"), etc.

[0088] The reinforcement member BPL can be disposed in the bending area BA on the substrate SUB. The reinforcement member BPL can cover the substrate SUB in the bending area BA. In addition, the reinforcement member BPL can extend to cover the substrate SUB in a part of the peripheral area PA and a part of the pad area PDA.

[0089] The reinforcement member BPL can protect the transmission line TL (see Figure 1 ) from the influence of external shocks. In addition, the reinforcement member BPL can supplement the rigidity of the substrate SUB in the bending area BA. The reinforcement member BPL can include an organic material. Examples of the organic material that can be used as the reinforcement member BPL can include polyacrylate-based resins, polyimide-based resins, polyamide-based resins, silicone-based resins, acrylic-based resins, epoxy-based resins, etc. These can be used alone or in combination with each other.

[0090] The driving chip D-IC can be disposed in the pad area PDA on the substrate SUB. For example, see Figure 1 , the driving chip D-IC can be connected to the pad PDD, and the pad PDD is disposed in the pad area PDA on the substrate SUB through an anisotropic conductive film. The driving chip D-IC can provide a driving signal to the display panel DP. The driving signal can include various signals for driving the display panel DP, such as a driving voltage, a control signal, a data signal, etc.

[0091] The printed circuit board FPCB can be disposed in the pad region PDA on the substrate SUB. The printed circuit board FPCB can be coupled to the Figure 1 pad PDD through an anisotropic conductive film. For example, the printed circuit board FPCB can be a flexible printed circuit board.

[0092] The cover tape CT can be disposed in the pad region PDA on the substrate SUB. The cover tape CT can cover the printed circuit board FPCB, the driving chip D-IC, and the reinforcing member BPL. The cover tape CT can protect the driving chip D-IC from external impacts. In addition, the cover tape CT can include a metal such that heat generated from the driving chip D-IC can dissipate. For example, the cover tape CT can include copper (Cu) or aluminum (Al).

[0093] A plurality of first openings OP1 can be defined on the lower surface of the substrate SUB. In other words, the first openings OP1 can be formed by removing a portion of the substrate SUB from its lower surface upward. In a plan view, the first openings OP1 can be within and overlap the display region DA, and are spaced apart from the bending region BA.

[0094] That is, the first openings OP1 can be formed on the lower surface of the substrate SUB in the display region DA, and can not be formed on the lower surface of the substrate SUB in the bending region BA and the pad region PDA. In an embodiment, the first openings OP1 can be formed on the lower surface of the substrate SUB in a part of the peripheral region PA.

[0095] In an embodiment, as Figure 3 shown, each of the first openings OP1 can penetrate and extend completely through the substrate SUB in the thickness direction (or the third direction DR3) of the substrate SUB. In this case, a part of the display element layer DPL can be exposed by the first openings OP1. However, the present disclosure is not limited thereto.

[0096] In other embodiments, each of the first openings OP1 may not completely penetrate the substrate SUB in the thickness direction of the substrate SUB. In this case, a plurality of grooves can be defined on the lower surface of the substrate SUB. Each of the grooves can represent a portion of the substrate SUB that is recessed from its lower surface toward the display element layer DPL.

[0097] In an embodiment, as Figure 5AAs shown, the first opening OP1 may be arranged in a zigzag shape in a plan view. However, the shape of the first opening OP1 arranged in the plan view is not limited thereto, and the first opening OP1 may be arranged in various shapes in the plan view. For example, the first opening OP1 may include a plurality of groups arranged in a line along a first direction DR1 in the plan view, and the plurality of groups may be arranged along a second direction DR2.

[0098] The shielding layer SHL may be provided under the substrate SUB. Specifically, the shielding layer SHL may be provided with a substantially uniform thickness along the contour of the lower surface of the substrate SUB. The shielding layer SHL may continuously extend within the first opening OP1.

[0099] The shielding layer SHL may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In an embodiment, the shielding layer SHL may include copper (Cu) or aluminum (Al). Thus, the shielding layer SHL may dissipate heat generated from the driving chip D-IC. As a result, the heat transferred from the driving chip D-IC to the display element layer DPL may be reduced. In addition, the shielding layer SHL may shield electromagnetic interference (“EMI”) noise. That is, the shielding layer SHL may function as a heat dissipation function and a shielding function.

[0100] In an embodiment, the shielding layer SHL may include graphite or carbon nanotubes. In this case, the shielding layer SHL may reduce the external light reflection of the display device DD and may improve the visibility of the display device DD. That is, the shielding layer SHL may function as a heat dissipation function, a shielding function, and a light blocking function.

[0101] Since the first opening OP1 is defined on the lower surface of the substrate SUB and the shielding layer SHL is provided along the contour of the lower surface of the substrate SUB, the shielding layer SHL may define a plurality of grooves GRV that respectively overlap with the first opening OP1. In other words, the shielding layer SHL may include an uneven pattern. When the shielding layer SHL includes an uneven pattern, the area of the shielding layer SHL in contact with the substrate SUB may be increased, and the surface area of the shielding layer SHL may be increased. Thus, the shielding layer SHL may effectively dissipate heat generated from the driving chip D-IC and may effectively shield electromagnetic interference noise. That is, the heat dissipation characteristics and shielding characteristics of the shielding layer SHL may be improved by increasing the surface area of the shielding layer SHL. Since the heat dissipation characteristics and shielding characteristics of the shielding layer SHL are improved, the shielding layer SHL may be formed with a relatively small thickness. For example, the shielding layer SHL may have a thickness of about 35 micrometers or less. However, the present disclosure is not limited thereto.

[0102] The first organic layer OGL1 may be disposed under the shielding layer SHL. The first organic layer OGL1 may planarize the lower surface of the shielding layer SHL. Specifically, the first organic layer OGL1 may sufficiently cover the lower surface of the shielding layer SHL and may have a substantially flat lower surface.

[0103] The first organic layer OGL1 may protect the substrate SUB from external impacts. In other words, the first organic layer OGL1 may supplement the rigidity of the substrate SUB by mitigating external impacts. The first organic layer OGL1 may keep the portion of the substrate SUB overlapping with the display area DA in a flat state. The first organic layer OGL1 may include an adhesive material having insulating properties. For example, the first organic layer OGL1 may include a thermoplastic resin and / or a thermosetting resin. Examples of the thermoplastic resin that can be used as the first organic layer OGL1 may include acrylic-based resins, vinyl-acid-based resins, polyolefin-based resins, polycarbonate-based resins, etc. They may be used alone or in combination with each other. Examples of the thermosetting resin that can be used as the first organic layer OGL1 may include epoxy-based resins, phenolic resins, melamine-based resins, etc. They may be used alone or in combination with each other.

[0104] The first organic layer OGL1 may cover the groove GRV defined by the shielding layer SHL. In an embodiment, the first organic layer OGL1 may fill the groove GRV. When the first organic layer OGL1 fills the groove GRV, the area of the first organic layer OGL1 in contact with the shielding layer SHL may increase, and the surface area of the first organic layer OGL1 may increase. Accordingly, the adhesion between the first organic layer OGL1 and the shielding layer SHL may be increased. As a result, when the substrate SUB is bent, the first organic layer OGL1 may be prevented from peeling off the shielding layer SHL.

[0105] In an embodiment, the first elastic modulus of the first organic layer OGL1 may be less than the second elastic modulus of the substrate SUB. For example, the first elastic modulus of the first organic layer OGL1 may be about 0.01 MPa to about 1 MPa. When the first organic layer OGL1 fills the groove GRV, as Figure 3 and Figure 5BAs shown, the substrate SUB and the first organic layer OGL1 may be arranged along the second direction DR2 in the order of substrate SUB, first organic layer OGL1, substrate SUB, and first organic layer OGL1. In other words, the substrate SUB and the first organic layer OGL1 may be alternately arranged along the second direction DR2. That is to say, the substrate SUB having a relatively large second elastic modulus and the first organic layer OGL1 having a relatively small first elastic modulus may be alternately arranged along the second direction DR2. Therefore, the first organic layer OGL1 can effectively protect the substrate SUB from external impacts. That is to say, the buffer characteristics of the first organic layer OGL1 and the characteristics of the first organic layer OGL1 for supplementing the rigidity of the substrate SUB can be improved.

[0106] In an embodiment, the first organic layer OGL1 may include an organic material including a light-blocking material having a black color. In this case, the first organic layer OGL1 can reduce the external light reflection of the display device DD and improve the visibility of the display device DD. That is to say, the first organic layer OGL1 can function as a light-blocking function. For example, the light-blocking material may include black pigments, black dyes, etc. They may be used alone or in combination with each other. In an embodiment, in addition to the organic material, the first organic layer OGL1 may further include an inorganic material such as carbon black.

[0107] In a plan view, the shielding layer SHL and the first organic layer OGL1 may overlap with the display area DA and may not overlap with the bending area BA. In other words, the shielding layer SHL and the first organic layer OGL1 may be disposed under the substrate SUB in the display area DA and may not be disposed under the substrate SUB in the bending area BA and the pad area PDA.

[0108] The second organic layer OGL2 may be disposed on the lower surface of the substrate SUB and may overlap with the pad area PDA in a plan view. The first opening OP1 may not be formed on the lower surface of the substrate SUB on which the second organic layer OGL2 is disposed. The second organic layer OGL2 can supplement the rigidity of the substrate SUB. The second organic layer OGL2 can keep the portion of the substrate SUB overlapping with the pad area PDA in a flat state. Examples of the organic material that can be used as the second organic layer OGL2 may include polyacrylic-based resins, polyimide-based resins, polyamide-based resins, silicone-based resins, acrylic-based resins, epoxy-based resins, etc. These may be used alone or in combination with each other.

[0109] In an embodiment, the second organic layer OGL2 may include the same material as the first organic layer OGL1. In this case, the third elastic modulus of the second organic layer OGL2 may be the same as the first elastic modulus of the first organic layer OGL1. For example, the third elastic modulus of the second organic layer OGL2 may be from about 0.01 MPa to about 1 MPa. However, the present disclosure is not limited thereto.

[0110] In other embodiments, the second organic layer OGL2 may include a material different from that of the first organic layer OGL1. For example, the second organic layer OGL2 may include polyethylene terephthalate (“PET”), polyimide (“PI”), polyethylene naphthalate (“PEN”), etc. They may be used alone or in combination with each other. In this case, the third elastic modulus of the second organic layer OGL2 may be greater than the first elastic modulus of the first organic layer OGL1. For example, the third elastic modulus of the second organic layer OGL2 may be about 4 GPa.

[0111] The first connection member CNM1 may be disposed under the first organic layer OGL1. Specifically, the first connection member CNM1 may be disposed between the first organic layer OGL1 and the printed circuit board FPCB. The first connection member CNM1 may directly contact the first organic layer OGL1 and the printed circuit board FPCB, and may fix the printed circuit board FPCB.

[0112] The second connection member CNM2 may be disposed under the first organic layer OGL1. Specifically, the second connection member CNM2 may be disposed between the first organic layer OGL1 and the second organic layer OGL2. The second connection member CNM2 may contact the first organic layer OGL1 and the second organic layer OGL2, and may hold the substrate SUB in a bent state. In other words, the second connection member CNM2 may hold the portion of the substrate SUB that overlaps with the bending region BA in a bent state.

[0113] In an embodiment, each of the first connection member CNM1 and the second connection member CNM2 may include a metal such that heat generated from the driving chip D-IC can be dissipated. In this case, each of the first connection member CNM1 and the second connection member CNM2 may include an upper adhesive layer, a lower adhesive layer, and a metal layer disposed between the upper adhesive layer and the lower adhesive layer. That is, the metal layer may include copper (Cu) or aluminum (Al).

[0114] Figure 6 is a cross-sectional view showing a display device DD2 according to an embodiment of the present disclosure. Figure 7 is Figure 6 an enlarged cross-sectional view of region “B” of

[0115] ReferenceFigure 6 and Figure 7 According to an embodiment of the present disclosure, the display device DD2 may include a cover window CW, an antireflection layer POL, a display panel DP, a shielding layer SHL, a first organic layer OGL1, a second organic layer OGL2, a first connection member CNM1, a second connection member CNM2, a reinforcement member BPL, a driving chip D-IC, a flexible printed circuit board FPCB, and a cover tape CT. The display panel DP may include a substrate SUB, a display element layer DPL, and a packaging layer TFE.

[0116] Except that the first organic layer OGL1 may not fill the grooves GRV of the shielding layer SHL, and each of the grooves GRV may include pores PRS, the display device DD2 may be substantially the same as the display device DD described above with reference to Figure 1 、 Figure 2 、 Figure 3 、 Figure 4 、 Figure 5A and Figure 5B In the following, the redundant descriptions of the display device DD given above with reference to Figure 1 、 Figure 2 、 Figure 3 、 Figure 4 、 Figure 5A and Figure 5B may not be repeated or may be simplified.

[0117] A plurality of second openings OP2 may be defined on the lower surface of the substrate SUB. In other words, the second openings OP2 may be formed by removing a part of the substrate SUB from the lower surface of the substrate SUB upward. In a plan view, the second openings OP2 may be within and overlap with the display area DA, and may be spaced apart from the bending area BA. That is, the second openings OP2 may be formed on the lower surface of the substrate SUB in the display area DA, and may not be formed on the lower surface of the substrate SUB in the bending area BA and the pad area PDA. In an embodiment, the size of each second opening OP2 may be smaller than Figure 3 the size of each first opening OP1. Here, the size of each opening may represent the length of each opening in the second direction DR2.

[0118] In an embodiment, as Figure 6 shown, each of the second openings OP2 may completely penetrate the substrate SUB in the thickness direction of the substrate SUB. In this case, a part of the display element layer DPL may be exposed by the second openings OP2. However, the present disclosure is not limited thereto.

[0119] In other embodiments, each of the second openings OP2 may not completely penetrate the substrate SUB in the thickness direction of the substrate SUB. In this case, a plurality of grooves may be defined on the lower surface of the substrate SUB. Each of the grooves may represent a portion of the substrate SUB that is recessed from its lower surface toward the display element layer DPL.

[0120] The shielding layer SHL may be disposed under the substrate SUB. Specifically, the shielding layer SHL may be disposed along the contour of the lower surface of the substrate SUB with a substantially uniform thickness. The shielding layer SHL may continuously extend within the second opening OP2. The shielding layer SHL may dissipate heat generated from the driving chip D-IC. In addition, the shielding layer SHL may shield electromagnetic interference noise.

[0121] Since the second opening OP2 is defined on the lower surface of the substrate SUB and the shielding layer SHL is disposed along the contour of the lower surface of the substrate SUB, the shielding layer SHL may define a plurality of grooves GRV that respectively overlap the second opening OP2. In other words, the shielding layer SHL may include an uneven pattern. When the shielding layer SHL includes an uneven pattern, the area of the shielding layer SHL in contact with the substrate SUB may be increased, and the surface area of the shielding layer SHL may be increased. Therefore, the shielding layer SHL may effectively dissipate heat generated from the driving chip D-IC and may effectively shield electromagnetic interference noise. That is, the heat dissipation characteristics and shielding characteristics of the shielding layer SHL may be improved by increasing the surface area of the shielding layer SHL. Since the heat dissipation characteristics and shielding characteristics of the shielding layer SHL are improved, the shielding layer SHL may be formed with a relatively small thickness.

[0122] The first organic layer OGL1 may be disposed under the shielding layer SHL. The first organic layer OGL1 may planarize the lower surface of the shielding layer SHL. Specifically, the first organic layer OGL1 may sufficiently cover the lower surface of the shielding layer SHL and may have a substantially flat lower surface.

[0123] The first organic layer OGL1 may protect the substrate SUB from external impacts. In other words, the first organic layer OGL1 may supplement the rigidity of the substrate SUB by mitigating external impacts. The first organic layer OGL1 may keep the portion of the substrate SUB overlapping the display area DA in a flat state.

[0124] The first organic layer OGL1 may cover the groove GRV defined by the shielding layer SHL. In an embodiment, the first organic layer OGL1 may not fill the groove GRV. In other words, the first organic layer OGL1 may not be disposed within the groove GRV, and each of the grooves GRV may include a pore PRS. Here, the pore PRS may represent an air-filled space located between the shielding layer SHL and the first organic layer OGL1. The pore PRS may have a square cross-sectional shape, but the present disclosure is not limited thereto.

[0125] When an impact is applied to the display device DD2 from the outside, the upper surface of the first organic layer OGL1 in contact with the pore PRS may elastically change its shape. That is, the first organic layer OGL1 and the pore PRS may effectively protect the substrate SUB from the influence of an external impact. In other words, when each of the grooves GRV includes a pore PRS, the buffering characteristics of the first organic layer OGL1 and the characteristic of the first organic layer OGL1 to supplement the rigidity of the substrate SUB may be improved.

[0126] Figure 8 is a cross-sectional view showing a display device DD3 according to an embodiment of the present disclosure. Figure 9 is Figure 8 an enlarged cross-sectional view of the region “C” of

[0127] Reference Figure 8 and Figure 9 , a display device DD3 according to an embodiment of the present disclosure may include a cover window CW, an antireflection layer POL, a display panel DP, a shielding layer SHL, a first organic layer OGL1, a second organic layer OGL2, a first connection member CNM1, a second connection member CNM2, a reinforcing member BPL, a driving chip D-IC, a printed circuit board FPCB, and a cover tape CT. The display panel DP may include a substrate SUB, a display element layer DPL, and a packaging layer TFE.

[0128] Except that the first organic layer OGL1 may be disposed on the lower surface of the substrate SUB and the shielding layer SHL may be disposed on the lower surface of the first organic layer OGL1, the display device DD3 may be substantially the same as the display device DD described above with reference to Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5A and Figure 5B . Hereinafter, the redundant description of the display device DD given above with reference to Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5A and Figure 5B may not be repeated or may be simplified.

[0129] A plurality of first openings OP1 may be defined on the lower surface of the substrate SUB. In other words, the first openings OP1 may be formed by removing a portion of the substrate SUB from its lower surface upward. In a plan view, the first openings OP1 may be within and overlap with the display area DA, and may be spaced apart from the bending area BA. That is, the first openings OP1 may be formed on the lower surface of the substrate SUB in the display area DA, and may not be formed on the lower surface of the substrate SUB in the bending area BA and the pad area PDA.

[0130] In an embodiment, as Figure 8 shown, each of the first openings OP1 may completely penetrate the substrate SUB in the thickness direction of the substrate SUB. In this case, a portion of the display element layer DPL may be exposed by the first openings OP1. However, the present disclosure is not limited thereto.

[0131] In other embodiments, each of the first openings OP1 may not completely penetrate the substrate SUB in the thickness direction of the substrate SUB. In this case, a plurality of grooves may be defined on the lower surface of the substrate SUB. Each of the grooves may represent a portion of the substrate SUB that is recessed from its lower surface toward the display element layer DPL.

[0132] The first organic layer OGL1 may be disposed under the substrate SUB. Specifically, the first organic layer OGL1 may be disposed on the lower surface of the substrate SUB, and may cover the first openings OP1. The first organic layer OGL1 may sufficiently cover the lower surface of the substrate SUB, and may have a substantially flat lower surface.

[0133] The first organic layer OGL1 may protect the substrate SUB from external impacts. In other words, the first organic layer OGL1 may supplement the rigidity of the substrate SUB by mitigating external impacts. The first organic layer OGL1 may keep the portion of the substrate SUB overlapping with the display area DA in a flat state.

[0134] In an embodiment, the first organic layer OGL1 may be filled within the first openings OP1. When the first organic layer OGL1 is filled within the first openings OP1, the area of the first organic layer OGL1 in contact with the substrate SUB may increase, and the surface area of the first organic layer OGL1 may increase. Accordingly, the adhesion between the first organic layer OGL1 and the substrate SUB may be increased. As a result, when the substrate SUB is bent, the first organic layer OGL1 may be prevented from peeling off from the substrate SUB.

[0135] In an embodiment, the first elastic modulus of the first organic layer OGL1 may be less than the second elastic modulus of the substrate SUB. For example, the first elastic modulus of the first organic layer OGL1 may be from about 0.01 MPa to about 1 MPa. When as Figure 8 and Figure 9 shown, when the first organic layer OGL1 is filled in the first opening OP1, the substrate SUB and the first organic layer OGL1 may be arranged in the order of the substrate SUB, the first organic layer OGL1, the substrate SUB, and the first organic layer OGL1 along the second direction DR2. In other words, the substrate SUB and the first organic layer OGL1 may be alternately arranged along the second direction DR2. That is to say, the substrate SUB having a relatively large second modulus and the first organic layer OGL1 having a relatively small first elastic modulus may be alternately arranged along the second direction DR2. Therefore, the first organic layer OGL1 can effectively protect the substrate SUB from the influence of external shocks. That is to say, the buffering characteristics of the first organic layer OGL1 and the characteristics of the first organic layer OGL1 for supplementing the rigidity of the substrate SUB can be improved.

[0136] The shielding layer SHL may be disposed under the first organic layer OGL1. Specifically, the shielding layer SHL may be disposed on the lower surface of the first organic layer OGL1 and may cover the lower surface of the first organic layer OGL1. The shielding layer SHL may dissipate heat generated from the driving chip D-IC. In addition, the shielding layer SHL may shield electromagnetic interference noise.

[0137] Since the first organic layer OGL1 has a flat lower surface, the shielding layer SHL disposed on the lower surface of the first organic layer OGL1 may have a flat upper surface. That is to say, compared with the display device DD according to the embodiment of the present disclosure (wherein the display device DD may include a shielding layer SHL defining a groove GRV), the display device DD3 according to the embodiment of the present disclosure may include a shielding layer SHL having a flat upper surface.

[0138] The first connection member CNM1 may be disposed under the shielding layer SHL. Specifically, the first connection member CNM1 may be disposed between the shielding layer SHL and the flexible printed circuit board FPCB. The first connection member CNM1 may contact the shielding layer SHL and the flexible printed circuit board FPCB and may fix the flexible printed circuit board FPCB.

[0139] The second connection member CNM2 may be disposed below the shielding layer SHL. Specifically, the second connection member CNM2 may be disposed between the shielding layer SHL and the second organic layer OGL2. The second connection member CNM2 may contact the shielding layer SHL and the second organic layer OGL2, and may hold the substrate SUB in a bent state. In other words, the second connection member CNM2 may hold the portion of the substrate SUB overlapping with the bending region BA in a bent state.

[0140] Figure 10 is a cross-sectional view showing a display device DD4 according to an embodiment of the present disclosure. Figure 11 is Figure 10 an enlarged cross-sectional view of region “D” of

[0141] Referring to Figure 10 and Figure 11 , a display device DD4 according to an embodiment of the present disclosure may include a cover window CW, an antireflection layer POL, a display panel DP, a shielding layer SHL, a first organic layer OGL1, a second organic layer OGL2, a first connection member CNM1, a second connection member CNM2, a reinforcing member BPL, a driving chip D-IC, a printed circuit board FPCB, and a cover tape CT. The display panel DP may include a substrate SUB, a display element layer DPL, and a packaging layer TFE.

[0142] Except that the first organic layer OGL1 may not be filled in the second opening OP2 and each of the second openings OP2 may include pores PRS, the display device DD4 may be substantially the same as the display device DD3 described above with reference to Figure 8 and Figure 9 . Hereinafter, the redundant descriptions of the display device DD3 given above with reference to Figure 8 and Figure 9 may not be repeated or may be simplified.

[0143] A plurality of second openings OP2 may be defined on the lower surface of the substrate SUB. In other words, the second openings OP2 may be formed by removing a part of the substrate SUB from the lower surface of the substrate SUB upward. In a plan view, the second openings OP2 may be within and overlap with the display area DA, and may be spaced apart from the bending region BA. That is, the second openings OP2 may be formed on the lower surface of the substrate SUB in the display area DA, and may not be formed on the lower surface of the substrate SUB in the bending region BA and the pad region PDA. In an embodiment, the size of each second opening OP2 may be smaller than Figure 8 the size of each first opening OP1 of

[0144] In an embodiment, asFigure 10 As shown, each of the second openings OP2 may completely penetrate the substrate SUB in the thickness direction of the substrate SUB. In this case, a part of the display element layer DPL may be exposed by the second opening OP2. However, the present disclosure is not limited thereto.

[0145] In other embodiments, each of the second openings OP2 may not completely penetrate the substrate SUB in the thickness direction of the substrate SUB. In this case, a plurality of grooves may be defined on the lower surface of the substrate SUB. Each of the grooves may represent a portion of the substrate SUB that is recessed from its lower surface toward the display element layer DPL.

[0146] The first organic layer OGL1 may be provided under the substrate SUB. Specifically, the first organic layer OGL1 may be provided on the lower surface of the substrate SUB and may cover the second opening OP2. The first organic layer OGL1 may sufficiently cover the lower surface of the substrate SUB and may have a substantially flat lower surface.

[0147] The first organic layer OGL1 may protect the substrate SUB from external impact. In other words, the first organic layer OGL1 may supplement the rigidity of the substrate SUB by mitigating external impact. The first organic layer OGL1 may keep the portion of the substrate SUB overlapping with the display area DA in a flat state.

[0148] In an embodiment, the first organic layer OGL1 may be provided outside the second opening OP2. In other words, the first organic layer OGL1 may not be provided within the second opening OP2, and each of the second openings OP2 may include a pore PRS. Here, the pore PRS may represent an air-filled space located between the substrate SUB and the first organic layer OGL1. The pore PRS may have a square cross-sectional shape, but the present disclosure is not limited thereto.

[0149] When an impact is applied to the display device DD4 from the outside, the upper surface of the first organic layer OGL1 in contact with the pore PRS may elastically change its shape. That is, the first organic layer OGL1 and the pore PRS may effectively protect the substrate SUB from external impact. In other words, when each of the second openings OP2 includes a pore PRS, the buffering characteristics of the first organic layer OGL1 and the characteristics of the first organic layer OGL1 for supplementing the rigidity of the substrate SUB may be improved.

[0150] The shielding layer SHL can be disposed below the first organic layer OGL1. Specifically, the shielding layer SHL can be disposed on the lower surface of the first organic layer OGL1 and can cover the lower surface of the first organic layer OGL1. The shielding layer SHL can dissipate heat generated from the driving chip D-IC. In addition, the shielding layer SHL can shield electromagnetic interference noise. Since the first organic layer OGL1 has a flat lower surface, the shielding layer SHL disposed on the lower surface of the first organic layer OGL1 can have a flat upper surface.

[0151] The present disclosure can be applied to various display devices. For example, the present disclosure can be applied to various display devices such as display devices for vehicles, ships, and airplanes, portable communication devices, display devices for exhibition or information transmission, medical display devices, and the like.

[0152] The above are examples of embodiments of the present disclosure and should not be construed as limitations thereof. Although multiple embodiments have been described with reference to the accompanying drawings, those skilled in the art will readily understand that many changes and modifications can be made therein without departing from the spirit and scope of the present disclosure as defined in the appended claims.

Claims

1. A display device, comprising: a substrate including a display area and a curved area located on one side of the display area, a lower surface of the substrate defining a plurality of openings; a shielding layer disposed along the lower surface of the substrate and continuously extending within the plurality of openings; and a first organic layer disposed below the shielding layer and planarizing a lower surface of the shielding layer.

2. The display device according to claim 1, wherein, The shielding layer defines a plurality of grooves respectively overlapping with the plurality of openings, and the first organic layer covers the plurality of grooves.

3. The display device according to claim 2, wherein, The first organic layer fills the plurality of grooves.

4. The display device according to claim 2, wherein, Each of the plurality of grooves includes pores.

5. The display device according to claim 1, wherein, A first elastic modulus of the first organic layer is less than a second elastic modulus of the substrate.

6. The display device according to claim 1, wherein, The shielding layer includes at least one of copper, graphite, and carbon nanotubes.

7. The display device according to claim 1, wherein, The first organic layer includes an organic material including a light-blocking material having a black color.

8. The display device according to claim 1, wherein, In a plan view, the plurality of openings overlap with the display area and are spaced apart from the curved area.

9. The display device according to claim 1, wherein, In a plan view, each of the shielding layer and the first organic layer overlaps with the display area and is spaced apart from the curved area.

10. The display device according to claim 1, wherein, Each of the plurality of openings penetrates the substrate in a thickness direction of the substrate.

11. The display device according to claim 1, wherein, The substrate further includes a pad area spaced apart from the display area in the plan view, and the curved area is between the pad area and the display area.

12. The display device according to claim 11, further comprising: a second organic layer disposed on the lower surface of the substrate and overlapping with the pad area in the plan view.

13. The display device according to claim 12, wherein, The second organic layer and the first organic layer include the same material.

14. The display device according to claim 12, wherein, The second organic layer includes a material different from that of the first organic layer, and a third elastic modulus of the second organic layer is greater than the first elastic modulus of the first organic layer.

15. A display device, comprising: a substrate including a display area and a curved area located on one side of the display area, a lower surface of the substrate defining a plurality of openings; a first organic layer disposed below the substrate and covering the plurality of openings; and a shielding layer disposed below the first organic layer and covering a lower surface of the first organic layer.

16. The display device according to claim 15, wherein, The first organic layer fills the plurality of openings.

17. The display device according to claim 15, wherein, The first organic layer is disposed outside the plurality of openings, and each of the plurality of openings includes pores.

18. The display device according to claim 15, wherein, The shielding layer has a flat upper surface.

19. The display device according to claim 15, wherein, A first elastic modulus of the first organic layer is less than a second elastic modulus of the substrate.

20. The display device according to claim 15, wherein, The shielding layer includes at least one of copper, graphite, and carbon nanotubes.

21. The display device according to claim 15, wherein, The first organic layer includes an organic material including a light-blocking material having a black color.

22. The display device according to claim 15, wherein, In a plan view, the plurality of openings overlap with the display area and are spaced apart from the curved area.

23. The display device according to claim 15, wherein, In a plan view, each of the shielding layer and the first organic layer overlaps with the display area and is spaced apart from the curved area.

24. The display device according to claim 15, wherein, Each of the plurality of openings penetrates the substrate in a thickness direction of the substrate.

25. The display device according to claim 15, wherein, The substrate further includes a pad region, the pad region being spaced apart from the display region in a plan view, and the bending region being between the pad region and the display region.

26. The display device according to claim 25, further comprising: A second organic layer disposed on the lower surface of the substrate and overlapping with the pad region in the plan view.

27. The display device according to claim 26, wherein, The second organic layer and the first organic layer include the same material.

28. The display device according to claim 26, wherein, The second organic layer includes a material different from that of the first organic layer, and A third elastic modulus of the second organic layer is greater than a first elastic modulus of the first organic layer.

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