A multi-level heat dissipation structure based on TSV heterogeneous integration and a preparation method thereof

Abstract

This invention relates to a multi-level heat dissipation structure based on TSV heterogeneous integration and its fabrication method, belonging to the field of integrated circuit packaging heat dissipation technology. It includes: a base, a manifold chipset, a stacked chipset, and a heat sink assembly. The base has internal liquid supply channels and liquid return channels, both extending through both sides of the base. The bottom end of the manifold chipset is bonded to the top end of the base and has multiple manifold microchannels inside. The bottom end of the stacked chipset is bonded to the top end of the manifold chipset and has multiple cooling microchannels inside. The bottom end of the heat sink assembly is bonded to the top end of the stacked chipset and has multiple heat dissipation microchannels extending through both sides. This invention utilizes the fact that the inlets and outlets of the manifold microchannels, the inlets and outlets of the cooling microchannels, and the inlets and outlets of the heat dissipation microchannels are connected to the outlets of the liquid supply channels and the inlets of the liquid return channels, respectively, which can significantly shorten the heat dissipation path and achieve independent and efficient heat dissipation.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit packaging heat dissipation technology, and in particular to a multi-level heat dissipation structure based on TSV heterogeneous integration and its fabrication method. Background Technology

[0002] As Moore's Law approaches its physical limits, traditional planar integrated circuits face a dual challenge in terms of performance improvement and power consumption control. The rapid development of fields such as artificial intelligence, 5G communication, and high-performance computing has placed near-exponential demands on chip computing density and energy efficiency, making it impractical to simply rely on process miniaturization to increase integration. The International Technology Roadmap for Semiconductors (ITRS) points out that three-dimensional heterogeneous integration technology is becoming the core path for continuing computing power growth in the post-Moore's Law era. This technology stacks chips vertically through through-silicon vias (TSVs), utilizing a third dimension to achieve three-dimensional integration, which can significantly reduce signal transmission latency and power consumption.

[0003] However, with the continuous increase in the number of stacked layers, the power density of the device has risen sharply, with the heat flux density exceeding 1 kW / cm² under typical operating conditions, and even exceeding 5 kW / cm² in local hot spots. This vertical stacking structure causes heat to accumulate continuously between chip layers, forming a significant thermal coupling effect. In particular, the intermediate functional layers, which are far from the heat sink, have significantly increased thermal resistance due to the complex and circuitous heat dissipation path, resulting in a sharp decline in heat dissipation efficiency. This far exceeds the handling range of traditional cooling methods, and thermal management has become a key bottleneck restricting the development of 3D packaging technology.

[0004] Embedded microfluidic liquid cooling technology eliminates the thermal resistance and interface thermal resistance of the package shell and TIM by directly integrating micron-level fluid channels inside the chip, shortening the heat transfer path from the chip's heat-generating area to the heat sink, and has extremely high heat dissipation efficiency.

[0005] However, in the three-dimensional stacked chip architecture, there is a contradiction between the spatial layout of TSV and embedded microchannel. There is an urgent need to develop a three-dimensional stacked chip heat dissipation structure that can achieve the co-integration of microchannel and TSV to meet the requirements of high-density interconnection and efficient heat dissipation. Summary of the Invention

[0006] The main objective of this application is to provide a dual-channel, multi-level heat dissipation structure for three-dimensional stacked chips based on TSV heterogeneous integration and its fabrication method, in order to solve the problem of insufficient heat dissipation efficiency caused by ultra-high density transistor integration in three-dimensional stacked chips. Through multi-level microchannel collaborative heat dissipation and three-dimensional thermal and electrical interconnect design, efficient heat dissipation and electrical signal transmission are achieved in the chip stacking structure.

[0007] The technical solution of this invention to solve the above-mentioned technical problems is as follows: a multi-level heat dissipation structure based on TSV heterogeneous integration, comprising: a base, a manifold chipset, a stacked chipset, and a heat sink assembly.

[0008] The base has a liquid supply channel and a liquid return channel inside, both of which extend through both sides of the base. The bottom end of the manifold chip assembly is bonded to the top end of the base, and it has multiple manifold microchannels extending through both sides inside. The bottom end of the stacked chip assembly is bonded to the top end of the manifold chip assembly, and it has multiple cooling microchannels extending through both sides inside. The bottom end of the heat sink assembly is bonded to the top end of the stacked chip assembly, and a TSV structure I is electrically connected between the heat sink assembly and the stacked chip assembly. The heat sink assembly has multiple heat dissipation microchannels extending through both sides inside. The inlet and outlet of the manifold microchannel, the inlet and outlet of the cooling microchannel, and the inlet and outlet of the heat dissipation microchannel are respectively connected to the outlet of the liquid supply channel and the inlet of the liquid return channel.

[0009] The beneficial effects of this invention are: it breaks through the limitations of traditional integrated circuit packaging heat dissipation efficiency, and by connecting the inlet and outlet of the manifold microchannel, the inlet and outlet of the manifold microchannel, the inlet and outlet of the cooling microchannel, and the inlet and outlet of the heat dissipation microchannel to the outlet of the liquid supply channel and the inlet of the liquid return channel respectively, the heat dissipation path can be significantly shortened, and the working heat of the manifold chipset and the stacked chipset can be reduced independently and efficiently.

[0010] Based on the above technical solution, the present invention can be further improved as follows.

[0011] Furthermore, the base includes a lower substrate and an upper substrate. The top of the lower substrate is provided with a liquid supply tank and a liquid return tank. The bottom of the liquid supply tank is provided with a liquid supply inlet hole that penetrates the side of the lower substrate, and the bottom of the liquid return tank is provided with a liquid return outlet hole that penetrates the side of the lower substrate. The bottom end of the upper substrate is bonded to the top end of the lower substrate, and it is provided with a liquid supply outlet hole communicating with the liquid supply tank and a liquid return inlet hole communicating with the liquid return tank. The liquid supply channel is composed of the liquid supply inlet hole, the liquid supply tank, and the liquid supply outlet hole. The liquid return channel is composed of the liquid return inlet hole, the liquid return tank, and the liquid return outlet hole. The bottom end of the manifold chip assembly is bonded to the top end of the upper substrate. The inlet and outlet of the manifold microchannel, the inlet and outlet of the manifold microchannel, the inlet and outlet of the cooling microchannel, and the inlet and outlet of the heat dissipation microchannel are respectively connected to the liquid supply outlet hole and the liquid return inlet hole.

[0012] Furthermore, the manifold chipset includes a manifold adapter board and a high-power chip. The bottom end of the manifold adapter board is bonded to the top end of the upper substrate, and its top end is provided with a heat dissipation groove. The bottom of the heat dissipation groove is provided with a liquid inlet and a liquid outlet. The bottom end of the high-power chip is bonded to the top end of the manifold adapter board, and its bottom end is fixed with a plurality of arrayed micro ribs A corresponding to the heat dissipation groove. The plurality of manifold microchannels are the gaps between the plurality of micro ribs A and the bottom of the heat dissipation groove. The liquid supply outlet is connected to the liquid inlet. The liquid return inlet is connected to the liquid outlet.

[0013] Furthermore, the manifold chip assembly also includes multiple conductive rods, and the manifold adapter plate is provided with multiple first penetrating holes; the high-power chip is provided with multiple second penetrating holes, and the multiple second penetrating holes are respectively arranged opposite to the multiple first penetrating holes; the two ends of the multiple conductive rods are respectively inserted into the oppositely arranged first penetrating holes and second penetrating holes.

[0014] Furthermore, the stacked chipset includes a heat sink and an IC chip. The bottom end of the heat sink is bonded to the top end of the high-power chip, and its top end has a fixing groove. The bottom of the fixing groove has a liquid inlet hole A and a liquid outlet hole A. Multiple arrayed micro ribs B are fixed to the bottom of the fixing groove, and each micro rib B has a TSV structure II fixed on it. The bottom end of the IC chip is bonded to the top end of the heat sink, and its top end is connected to the bottom end of the heat sink assembly. The TSV structure II is electrically connected to the TSV structure I. The cooling microchannel is the gap between the multiple micro ribs B, the bottom of the fixing groove, and the bottom end of the IC chip. The liquid supply outlet is connected to the liquid inlet hole A. The liquid return inlet is connected to the liquid outlet hole A.

[0015] The further beneficial effects of adopting the above are: due to the limited space of the IC chip substrate, the heat sink is manufactured separately from the IC chip layer, and the heat sink with integrated TSV is modularly designed. The shape, density and TSV arrangement strategy of the micro-needle ribs can be flexibly adjusted to adapt to different power consumption scenarios and signal transmission requirements.

[0016] Furthermore, the heat sink and the IC chip are arranged in multiple staggered configurations.

[0017] The further beneficial effects of adopting the above are: the multiple cooling microchannels formed by the staggered heat sinks and IC chips, and the bidirectional counterflow arrangement of the multiple vertically arranged cooling microchannels, utilize the vertical heat conduction of the IC chips to effectively suppress the decrease in heat dissipation efficiency caused by the temperature rise of the fluid, ensure uniform temperature distribution on the surface of the IC chips, and improve system reliability.

[0018] Furthermore, the cover plate is made of a transparent material.

[0019] Furthermore, the plurality of micro ribs A, the plurality of micro ribs B, and the plurality of micro ribs C are circular, airfoil-shaped, teardrop-shaped, rectangular, or triangular.

[0020] In addition, a method for fabricating a multi-level heat dissipation structure based on TSV heterogeneous integration is provided, including the multi-level heat dissipation structure based on TSV heterogeneous integration, and the specific steps are as follows:

[0021] S1. Heat dissipation microchannels are formed on the silicon substrate by deep reactive ion etching (DRIE), and inlet / outlet holes B and drain holes B are processed by laser drilling and then sealed by a cover plate.

[0022] S2. TSVs are fabricated on the IC chip and heat sink respectively using TSV process. Then, a micro rib B of a certain depth is etched in the bottom of the heat sink using DRIE, so that the TSV structure II is embedded in the micro rib B. The IC chip and heat sink are alternately stacked and bonded by low temperature eutectic bonding.

[0023] S3. The manifold microchannel and the second vertical hole are directly etched on the high-power chip substrate using DRIE. Similarly, heat dissipation grooves, liquid inlet holes, liquid outlet holes and the first vertical hole are etched on the first side of the manifold adapter plate. Then, the first side of the manifold adapter plate is bonded to the high-power chip substrate, the second vertical hole is aligned with the first vertical hole, and the second vertical hole and the first vertical hole are filled by using conductive rods or electroplating. A redistribution layer (RDL) is formed by electroplating on the second side of the manifold adapter plate.

[0024] S4. The manifold chipset and stacked chipset obtained above are bonded using bump technology and sealing rings to achieve signal interconnection and sealing of vertical flow path.

[0025] S5. Finally, the three-dimensional stacked structure and the base are encapsulated. Attached Figure Description

[0026] Figure 1 This is an exploded view of a multi-level heat dissipation structure based on TSV heterogeneous integration according to the present invention.

[0027] Figure 2 This is an exploded view of the heat sink assembly in a multi-level heat dissipation structure based on TSV heterogeneous integration according to the present invention.

[0028] Figure 3 This is an exploded view of the stacked chipset in a multi-level heat dissipation structure based on TSV heterogeneous integration according to the present invention.

[0029] Figure 4 This is a partial cross-sectional view of the manifold chip group in a multi-level heat dissipation structure based on TSV heterogeneous integration according to the present invention.

[0030] Figure 5 for Figure 4 A magnified structural diagram of point A;

[0031] Figure 6 A schematic diagram of the manifold adapter plate in a multi-level heat dissipation structure based on TSV heterogeneous integration according to the present invention.

[0032] Figure 7 A schematic diagram of a high-power chip in a multi-level heat dissipation structure based on TSV heterogeneous integration according to the present invention;

[0033] Figure 8 This is an exploded structural diagram of the base in a multi-level heat dissipation structure based on TSV heterogeneous integration according to the present invention.

[0034] The attached diagram lists the components represented by each number as follows:

[0035] 1. Base; 11. Lower substrate; 111. Liquid supply tank; 112. Liquid return tank; 12. Upper substrate; 121. Liquid supply outlet; 122. Liquid return inlet; 2. Manifold chipset; 21. Manifold adapter board; 211. Heat dissipation groove; 212. Liquid inlet hole; 213. Liquid outlet hole; 214. First vertical hole; 22. High-power chip; 221. Micro rib A; 222. Second vertical hole; 3. Stacked chipset; 31. Heat sink; 311. Fixing groove; 312. Liquid inlet hole A; 313. Liquid outlet hole A; 314. Micro rib B; 32. IC chip; 4. Heat sink assembly; 41. Heat sink; 411. Mounting groove; 412. Liquid inlet hole B; 413. Liquid outlet hole B; 414. Micro rib C; 42. Cover plate; 5. TSV structure I. Detailed Implementation

[0036] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0037] like Figure 1 As shown, a multi-level heat dissipation structure based on TSV heterogeneous integration includes: a base 1, a manifold chipset 2, a stacked chipset 3, and a heat sink assembly 4.

[0038] The base 1 has a liquid supply channel and a liquid return channel inside, both of which run through both sides of the base 1; the bottom end of the manifold chip group 2 is bonded to the top end of the base 1 and has multiple manifold microchannels running through both sides inside; the bottom end of the stacked chip group 3 is bonded to the top end of the manifold chip group 2 and has multiple cooling microchannels running through both sides inside; the bottom end of the heat sink group 4 is bonded to the top end of the stacked chip group 3 and a TSV structure I5 ​​is electrically connected between the heat sink group 4 and the stacked chip group 3, and the heat sink group 4 has multiple heat dissipation microchannels running through both sides inside; the inlet and outlet of the manifold microchannel, the inlet and outlet of the cooling microchannel, and the inlet and outlet of the heat dissipation microchannel are respectively connected to the outlet of the liquid supply channel and the inlet of the liquid return channel.

[0039] like Figure 8 As shown, in some specific embodiments, the base 1 may include a lower substrate 11 and an upper substrate 12. The top end of the lower substrate 11 is provided with a liquid supply groove 111 and a liquid return groove 112. The bottom of the liquid supply groove 111 is provided with a liquid supply inlet hole penetrating the side of the lower substrate 11, and the bottom of the liquid return groove 112 is provided with a liquid return outlet hole penetrating the side of the lower substrate 11. The bottom end of the upper substrate 12 is bonded to the top end of the lower substrate 11, and it is provided with a liquid supply outlet hole 121 communicating with the liquid supply groove 111, and a liquid return outlet hole 121 communicating with the liquid return groove 121. The return liquid inlet 122 is connected to the tank 112; the liquid supply channel is composed of the liquid supply inlet, the liquid supply tank 111 and the liquid supply outlet 121; the return liquid channel is composed of the return liquid inlet 122, the return liquid tank 112 and the return liquid outlet; the bottom end of the manifold chip group 2 is bonded to the top end of the upper substrate 12; the inlet and outlet of the manifold microchannel, the inlet and outlet of the manifold microchannel, the inlet and outlet of the cooling microchannel, and the inlet and outlet of the heat dissipation microchannel are respectively connected to the liquid supply outlet 121 and the return liquid inlet 122.

[0040] like Figures 4-7 As shown, in some specific embodiments, the manifold chipset 2 may include a manifold adapter plate 21 and a high-power chip 22. The bottom end of the manifold adapter plate 21 is bonded to the top end of the upper substrate 12, and its top end is provided with a heat dissipation groove 211. The bottom of the heat dissipation groove 211 is provided with a liquid inlet hole 212 and a liquid outlet hole 213. The bottom end of the high-power chip 22 is bonded to the top end of the manifold adapter plate 21, and its bottom end is fixed with a plurality of arrayed micro ribs A221 corresponding to the heat dissipation groove 211. The plurality of manifold microchannels are the gaps between the plurality of micro ribs A221 and the bottom of the heat dissipation groove 211. The liquid supply outlet hole 121 is connected to the liquid inlet hole 212. The liquid return inlet hole 122 is connected to the liquid outlet hole 213.

[0041] like Figure 5As shown, in some specific embodiments, the manifold chip group 2 may also include multiple conductive rods, and the manifold adapter plate 21 is provided with multiple first vertical holes 214; the high-power chip 22 is provided with multiple second vertical holes 222, and the multiple second vertical holes 222 are respectively arranged opposite to the multiple first vertical holes 214; the two ends of the multiple conductive rods are respectively inserted into the oppositely arranged first vertical holes 214 and second vertical holes 222.

[0042] like Figure 3 As shown, in some specific embodiments, the stacked chipset 3 may include a heat sink 31 and an IC chip 32. The bottom end of the heat sink 31 is bonded to the top end of the high-power chip 22, and its top end is provided with a fixing groove 311. The bottom of the fixing groove 311 is provided with a liquid inlet hole A312 and a liquid outlet hole A313. Multiple arrayed micro ribs B314 are fixed to the bottom of the fixing groove 311, and each micro rib B314 is fixed with a TSV structure II. The bottom end of the IC chip 32 is bonded to the top end of the heat sink 31, and its top end is connected to the bottom end of the heat sink assembly 4. The TSV structure II is electrically connected to the TSV structure I. The cooling microchannel is the gap between the multiple micro ribs B314, the bottom of the fixing groove 311, and the bottom end of the IC chip 32. The liquid supply outlet hole 121 is connected to the liquid inlet hole A312. The liquid return inlet hole 122 is connected to the liquid outlet hole A313.

[0043] like Figure 3 As shown, in some specific embodiments, the heat sink 31 and the IC chip 32 are multiple heat sinks 31 arranged in an alternating manner, with the higher heat sinks 31 bonded to the lower IC chip 32 for connection.

[0044] like Figure 2 As shown, in some specific embodiments, the heat sink assembly 4 may include a heat sink 41 and a cover plate 42. The bottom end of the heat sink 41 is bonded to the top end of the IC chip 32, and its top surface is provided with a mounting groove 411. The bottom of the mounting groove 411 is provided with a liquid inlet hole B412 and a liquid outlet hole B413, and a plurality of arrayed micro ribs C414 are fixed to the bottom of the groove. The bottom end of the cover plate 42 is bonded to the top end of the heat sink 41. The heat dissipation microchannel is the gap between the bottom of the mounting groove 411, the plurality of micro ribs C414 and the cover plate 42. The liquid supply outlet hole 121 is connected to the liquid inlet hole B412. The liquid return inlet hole 122 is connected to the liquid outlet hole B413.

[0045] Specifically, the cover plate 42 can be made of a transparent material.

[0046] Specifically, the multiple micro ribs A221, multiple micro ribs B314 and multiple micro ribs C414 are circular, airfoil-shaped, teardrop-shaped, rectangular or triangular.

[0047] In addition, a method for fabricating a multi-level heat dissipation structure based on TSV heterogeneous integration is provided, characterized by including a multi-level heat dissipation structure based on TSV heterogeneous integration, and the specific steps are as follows:

[0048] S1. Heat dissipation microchannels are formed on the silicon substrate by deep reactive ion etching (DRIE), and inlet / outlet holes B412 and outlet holes B413 are processed by laser drilling and then sealed by cover plate 42.

[0049] S2. TSVs are fabricated on IC chip 32 and heat sink 31 respectively using TSV process. Then, a micro rib B314 of a certain depth is etched in the bottom of heat sink 31 by DRIE, so that TSV structure II is embedded in the micro rib B314. IC chip 32 and heat sink 31 are alternately stacked and bonded by low temperature eutectic bonding.

[0050] S3. The manifold microchannel and the second vertical hole 222 are directly etched on the substrate of the high-power chip 22 using DRIE. Similarly, heat dissipation grooves 211, liquid inlet holes 212, liquid outlet holes 213 and the first vertical hole 214 are etched on the first side of the manifold adapter plate 21. Then, the first side of the manifold adapter plate 21 is bonded to the substrate of the high-power chip 22, the second vertical hole 222 is aligned with the first vertical hole 214, and the second vertical hole 222 and the first vertical hole 214 are filled by using conductive rods or electroplating. A redistribution layer RDL is formed by electroplating on the second side of the manifold adapter plate 21.

[0051] S4. The manifold chip set 2 and stacked chip set 3 obtained above are bonded together using bump technology and sealing ring to achieve signal interconnection and sealing of vertical flow path.

[0052] S5. Finally, the three-dimensional stacked structure is encapsulated with the base 1.

[0053] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A multi-level heat dissipation structure based on TSV heterogeneous integration, characterized in that, include: The base (1) has a liquid supply channel and a liquid return channel inside, and the liquid supply channel and the liquid return channel both pass through both sides of the base (1); Manifold chip group (2), the bottom end of the manifold chip group (2) is bonded to the top end of the base (1) and has multiple manifold microchannels that run through both sides inside. The stacked chipset (3) is bonded to the top of the manifold chipset (2) at its bottom end and has multiple cooling microchannels that run through both sides inside. The heat sink assembly (4) has its bottom end bonded to the top end of the stacked chip assembly (3) and is electrically connected to the heat sink assembly (4) and the stacked chip assembly (3) by a TSV structure I (5). The heat sink assembly (4) has multiple heat dissipation microchannels that run through both sides inside. The inlet and outlet of the manifold microchannel, the inlet and outlet of the manifold microchannel, the inlet and outlet of the cooling microchannel, and the inlet and outlet of the heat dissipation microchannel are respectively connected to the outlet of the liquid supply channel and the inlet of the liquid return channel. The base (1) includes a lower substrate (11) and an upper substrate (12). The top of the lower substrate (11) is provided with a liquid supply tank (111) and a liquid return tank (112). The bottom of the liquid supply tank (111) is provided with a liquid supply inlet hole that penetrates the side of the lower substrate (11), and the bottom of the liquid return tank (112) is provided with a liquid return outlet hole that penetrates the side of the lower substrate (11). The bottom end of the upper substrate (12) is bonded to the top of the lower substrate (11), and it is provided with a liquid supply outlet hole (121) that communicates with the liquid supply tank (111), and it is provided with a liquid return outlet hole (121) that communicates with the liquid return tank (112). Liquid return inlet (122); the liquid supply channel is composed of the liquid supply inlet, the liquid supply tank (111) and the liquid supply outlet (121); the liquid return channel is composed of the liquid return inlet (122), the liquid return tank (112) and the liquid return outlet; the bottom end of the manifold chip group (2) is bonded to the top end of the upper substrate (12); the inlet and outlet of the manifold microchannel, the inlet and outlet of the manifold microchannel, the inlet and outlet of the cooling microchannel, and the inlet and outlet of the heat dissipation microchannel are respectively connected to the liquid supply outlet (121) and the liquid return inlet (122).

2. The multi-level heat dissipation structure based on TSV heterogeneous integration according to claim 1, characterized in that, The manifold chip assembly (2) includes a manifold adapter plate (21) and a high-power chip (22). The bottom end of the manifold adapter plate (21) is bonded to the top end of the upper substrate (12), and a heat dissipation groove (211) is provided at its top end. The bottom of the heat dissipation groove (211) is provided with an inlet hole (212) and an outlet hole (213). The bottom end of the high-power chip (22) is bonded to the top end of the manifold adapter plate (21), and a plurality of arrayed micro ribs A (221) are fixed at its bottom end corresponding to the heat dissipation groove (211). The plurality of manifold microchannels are the gaps between the plurality of micro ribs A (221) and the bottom of the heat dissipation groove (211). The liquid supply outlet hole (121) is connected to the liquid inlet hole (212). The liquid return inlet hole (122) is connected to the liquid outlet hole (213).

3. The multi-level heat dissipation structure based on TSV heterogeneous integration according to claim 2, characterized in that, The manifold chip group (2) also includes multiple conductive rods. The manifold adapter plate (21) is provided with multiple first vertical holes (214). The high-power chip (22) is provided with multiple second vertical holes (222). The multiple second vertical holes (222) are respectively arranged opposite to the multiple first vertical holes (214). The two ends of the multiple conductive rods are respectively inserted into the oppositely arranged first vertical holes (214) and second vertical holes (222).

4. The multi-level heat dissipation structure based on TSV heterogeneous integration according to claim 2, characterized in that, The stacked chipset (3) includes a heat sink (31) and an IC chip (32). The bottom end of the heat sink (31) is bonded to the top end of the high-power chip (22), and a fixing groove (311) is provided at the top end of the heat sink (311). The bottom of the fixing groove (311) is provided with an inlet hole A (312) and a drain hole A (313). Multiple arrayed micro ribs B (314) are fixed at the bottom of the fixing groove (311), and each micro rib B (314) is fixed with a TSV structure II. The IC chip The bottom end of (32) is bonded to the top end of the heat sink (31) and its top end is connected to the bottom end of the heat sink assembly (4). The TSV structure II is electrically connected to the TSV structure I. The cooling microchannel is the gap between the multiple micro ribs B (314), the bottom of the fixing groove (311) and the bottom end of the IC chip (32). The liquid supply outlet (121) is connected to the liquid inlet A (312). The liquid return inlet (122) is connected to the liquid drain A (313).

5. A multi-level heat dissipation structure based on TSV heterogeneous integration according to claim 4, characterized in that, The heat sink (31) and the IC chip (32) are multiple staggered arrangements, and the heat sink (31) at the higher position is connected to the IC chip (32) at the lower position through the TSV structure I (5).

6. A multi-level heat dissipation structure based on TSV heterogeneous integration according to claim 4, characterized in that, The heat sink assembly (4) includes a heat sink (41) and a cover plate (42). The bottom end of the heat sink (41) is bonded to the top end of the IC chip (32), and its top surface is provided with a mounting groove (411). The bottom of the mounting groove (411) is provided with an inlet hole B (412) and a drain hole B (413), and a plurality of arrayed micro ribs C (414) are fixed at the bottom of the groove. The bottom end of the cover plate (42) is bonded to the top end of the heat sink (41). The heat dissipation microchannel is the gap between the bottom of the mounting groove (411), the plurality of micro ribs C (414), and the cover plate (42). The liquid supply outlet (121) is connected to the liquid inlet hole B (412). The liquid return inlet (122) is connected to the drain hole B (413).

7. A multi-level heat dissipation structure based on TSV heterogeneous integration according to claim 6, characterized in that, The cover plate (42) is made of transparent material.

8. A multi-level heat dissipation structure based on TSV heterogeneous integration according to claim 6, characterized in that, The plurality of micro ribs A (221), the plurality of micro ribs B (314) and the plurality of micro ribs C (414) are circular, airfoil-shaped, teardrop-shaped, rectangular or triangular.

9. A method for fabricating a multi-level heat dissipation structure based on TSV heterogeneous integration, characterized in that, Including the multi-level heat dissipation structure based on TSV heterogeneous integration as described in any one of claims 1-8, the specific steps are as follows: S1. Heat dissipation microchannels are formed on the silicon substrate by deep reactive ion etching (DRIE), and inlet / outlet holes B (412) and outlet holes B (413) are processed by laser drilling and then bonded and sealed by cover plate (42). S2. TSVs are fabricated on IC chip (32) and heat sink (31) respectively using TSV process. Then, a micro rib B (314) of a certain depth is etched in the bottom of heat sink (31) by DRIE, so that TSV structure II is embedded in the micro rib B (314). IC chip (32) and heat sink (31) are alternately stacked and bonded by low temperature eutectic bonding. S3. The manifold microchannel and the second vertical hole (222) are directly etched on the substrate of the high-power chip (22) by DRIE. Similarly, heat dissipation groove (211), liquid inlet hole (212), liquid outlet hole (213) and the first vertical hole (214) are etched on the first side of the manifold adapter plate (21). Then, the first side of the manifold adapter plate (21) is bonded to the substrate of the high-power chip (22), the second vertical hole (222) is aligned with the first vertical hole (214), the second vertical hole (222) and the first vertical hole (214) are filled by using conductive rods or electroplating, and a redistribution layer (RDL) is formed by electroplating on the second side of the manifold adapter plate (21). S4. The manifold chip group (2) and stacked chip group (3) obtained above are bonded by bumping process and sealing ring to realize signal interconnection and sealing of vertical flow path; S5. Finally, the three-dimensional stacked structure and the base (1) are encapsulated.

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