CPU load monitoring method based on dynamic compensation for satellite-borne network equipment

Abstract

An embodiment of the present invention discloses a method for monitoring CPU load of an onboard network device based on dynamic compensation, comprising: obtaining a first baseline and a second baseline at the start of a load calculation cycle; performing the following operations within each load calculation cycle: dynamically determining a baseline observation window based on the current CPU temperature, and extracting a packet-free period within the baseline observation window; dynamically updating the first baseline of the current cycle based on the first baseline at startup and the number of DPDK cycles within the packet-free period; preliminarily determining the CPU load rate of the current cycle based on the first baseline, the second baseline, and the number of DPDK cycles in the current cycle; and compensating the preliminarily determined CPU load rate based on the current temperature and space radiation to obtain the actual CPU load rate of the current cycle. This embodiment has low error, high reliability, and consumes few resources.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of satellite communication technology, and in particular to a CPU load monitoring method based on dynamic compensation of a satellite-borne network device. Background Art

[0002] Monitoring the actual CPU (Central Processing Unit) load of onboard network equipment can provide data support for satellite resource scheduling and fault warning. Currently, there are several CPU load monitoring technologies:

[0003] Technology 1: Interrupt-driven load monitoring method. This method uses a hardware interrupt trigger sampling mechanism to calculate CPU utilization by counting the number of interrupt triggers per unit time. After message processing is completed, an interrupt is triggered and the effective processing time segment is recorded.

[0004] However, this method has the following drawbacks: 1) Poor adaptability to radiation environments: The interrupt register is susceptible to single-particle upsets, resulting in interrupt loss or false triggering; 2) Distortion in high-load scenarios: In high-speed traffic scenarios above 10Gbps, the interrupt frequency exceeds the hardware processing capability, resulting in sampled data packet loss; 3) Incompatibility with the DPDK (Data Plane Development Kit) architecture: DPDK uses a polling mode to bypass the kernel protocol stack, and the interrupt mechanism cannot capture the actual load cycle.

[0005] Technique 2: Polling sampling in the DPDK environment. This method inserts timestamp sampling points into the DPDK packet receiving cycle, estimates CPU usage by comparing the time difference between adjacent cycles, and uses a fixed threshold to filter out invalid polling cycles.

[0006] However, this method has the following defects: 1) Baseline drift problem: It does not take into account the dynamic changes of CPU frequency affected by temperature in the space environment; 2) Lack of single-particle protection: The timestamp storage area is not protected by ECC, and continuous flipping will lead to cumulative error amplification; 3) Multi-core coordination failure: No cross-core data consistency mechanism is designed, and data contention occurs when multi-core loads are aggregated.

[0007] Patent application CN1664789A discloses a method for detecting the CPU occupancy rate of a real-time operating system, and patent application CN117827604A discloses a method and apparatus for determining a processor load rate and a readable storage medium, neither of which can solve the above-mentioned problem. Summary of the Invention

[0008] An embodiment of the present invention provides a CPU load monitoring method based on dynamic compensation for a satellite-borne network device to solve at least one of the above technical problems.

[0009] In a first aspect, an embodiment of the present invention provides a method for monitoring CPU load of a satellite-borne network device based on dynamic compensation, comprising:

[0010] Obtain a first baseline and a second baseline when a load calculation cycle of the onboard network device is started, wherein the first baseline is the number of DPDK cycles in which the CPU of the onboard network device remains in a no-data-packet state during one load calculation cycle, and the second baseline is the number of DPDK cycles in which the CPU of the onboard network device remains in a full-data-packet state during one load calculation cycle;

[0011] The following operations are performed in each load calculation cycle:

[0012] S1-1. Dynamically determine a baseline observation window based on the current CPU temperature, and extract a data packet-free period within the baseline observation window;

[0013] S1-2, dynamically updating the first baseline of the current load calculation cycle according to the first baseline at startup and the number of DPDK cycles in the data packet-free period;

[0014] S1-3. Preliminarily determine the CPU load rate of the current load calculation period based on the first baseline of the current load calculation period, the second baseline, and the number of DPDK cycles in the current load calculation period;

[0015] S1-4. Compensate the preliminarily determined CPU load rate according to the current temperature and space radiation to obtain the actual CPU load rate of the current load calculation period.

[0016] In a second aspect, an embodiment of the present invention provides an electronic device, comprising:

[0017] one or more processors;

[0018] a memory for storing one or more programs,

[0019] When the one or more programs are executed by the one or more processors, the one or more processors implement the CPU load monitoring method based on dynamic compensation of the onboard network device described in any embodiment.

[0020] In summary, this embodiment provides a CPU load monitoring method for satellite-borne network equipment based on dynamic compensation. It can accurately monitor the true load rate of the DPDK exclusive core in a space radiation environment with single-event upsets, solving the problems of error accumulation and insufficient anti-interference capability in traditional monitoring methods in extreme environments. It provides reliable data support for satellite resource scheduling and fault warning. The entire method has low error, high reliability, and low resource consumption. Specifically, the method:

[0021] 1. A non-intrusive timing anchor mechanism is introduced, embedding dual anchors in the DPDK main packet receiving loop. Cycle start and end timestamps are directly obtained through dedicated clock instructions, avoiding system call overhead. 4KB-aligned core-exclusive cache pages are used to isolate and store data, combined with memory barrier instructions to ensure timing measurement accuracy, with errors controlled to the 10 nanosecond level.

[0022] 2. A dynamic baseline calibration mode is proposed. Before the load calculation cycle starts, a baseline value is established by running in the no-packet state and the full-packet state. During operation, a sliding window algorithm with temperature compensation is used to dynamically update the baseline to improve environmental adaptability.

[0023] 3. A dynamic model for CPU load data environment compensation is proposed, and a temperature-clock drift linear compensation model and a radiation intensity sensitivity adjustment model are established to achieve real-time compensation calculation and further improve environmental adaptability. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 This is a flow chart of a method for monitoring CPU load of a satellite-borne network device based on dynamic compensation provided by an embodiment of the present invention;

[0026] Figure 2 This is a flowchart of anchor point counting provided by an embodiment of the present invention;

[0027] Figure 3 This is a flow chart of multi-core load aggregation provided by an embodiment of the present invention;

[0028] Figure 4 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0029] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention are described clearly and completely below. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort are also within the scope of protection of the present invention.

[0030] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0031] In the description of the present invention, it should also be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0032] Figure 1 This is a flow chart of a CPU load monitoring method based on dynamic compensation for a satellite network device provided by an embodiment of the present invention. This method is applicable to satellite network devices with a DPDK architecture and can be executed by a module deployed in the satellite network device or by other electronic devices. Figure 1 As shown, the method specifically includes:

[0033] S110 : Insert two counting anchor points into the DPDK loop of the onboard network device.

[0034] This embodiment introduces an anchor point insertion mechanism into the DPDK packet reception main loop of the onboard network device. Two non-blocking counting anchor points are inserted into each DPDK loop: one at the polling loop entry, used to record the number of DPDK loops; and one at the end of the data processing flow of the DPDK loop with a packet, used to record the number of DPDK loops with a packet. For ease of distinction and description, this embodiment refers to the counting anchor point at the polling loop entry as the first counting anchor point, and the counting anchor point at the end of the data processing flow as the second counting anchor point.

[0035] like Figure 2As shown in the figure, the working mechanism of the two timing anchor points is as follows: each time the CPU enters a DPDK cycle, the count of the first counting anchor point is increased by 1; then, the current DPDK cycle is checked to see if there is a data packet; if there is no data packet in the current DPDK cycle, the next DPDK cycle is entered directly; if there is a data packet in the current DPDK cycle, the count of the second counting anchor point is increased by 1, and the next DPDK cycle is entered after the data packet is processed.

[0036] Furthermore, this embodiment directly reads the clock counter via processor-specific instructions, avoiding system call overhead; memory barrier instructions are also used to ensure timing measurement accuracy. Furthermore, the CPU of the onboard network device can include multiple cores. This embodiment employs a cache isolation design, allocating each CPU core its own first and second counting anchor points, as well as independent cache pages to store each core's anchor count data. The memory area is aligned to 4KB, occupying exclusive L1 cache space, while a memory protection mechanism prevents cross-core data contamination.

[0037] S120. Before the load calculation cycle of the onboard network device is started, two time periods of equal length to the load calculation cycle are pre-run, and the following operations are performed in these two time periods: a no-data packet state is simulated in one of the time periods, and the number of DPDK cycles N1 in the time period is recorded using the first counting anchor point as a baseline when the load calculation cycle is started; a full-data packet state is simulated in the other time period, and the number of DPDK cycles N2 in the time period is recorded using the second counting anchor point as another baseline when the load calculation cycle is started.

[0038] The "no packet state" refers to a state in which no packets are pending for processing in each DPDK cycle within a time period; the "full packet state" refers to a state in which all packets are pending for processing in each DPDK cycle within a time period. This embodiment simulates these two typical states before performing periodic calculations on the CPU load rate. The number of DPDK cycles in these two states is recorded, respectively, as the initial baselines for subsequent load calculation cycles. The difference between these two initial baselines, N1-N2, corresponds to a 100% CPU load rate in the initial state (i.e., during the load calculation cycle of the onboard network device). For ease of distinction and description, this embodiment refers to the baseline in the "no packet state" as the first baseline, and the baseline in the "full packet state" as the second baseline.

[0039] S130: Start a load calculation cycle, receive service flow data from the onboard network device, and perform the following operations in each load calculation cycle:

[0040] S1-1. Dynamically determine the baseline observation window based on the current CPU temperature, and extract the data packet-free period within the baseline observation window. The baseline observation window here refers to a historical time window with the current moment as the end point, which is used to reflect the characteristics of the data packet-free period in the recent period. Specifically, the length of the baseline observation window is adaptively adjusted with the running time. Optionally, by introducing a temperature compensation factor, when the CPU chip temperature exceeds the threshold of ±5°C, the sliding window is automatically reduced to 1 / 3, and the data packet-free period within the window is extracted. Specifically, during the counting process of the second counting anchor point, if the count value of the second counting anchor point does not change within a period of time, this period is considered to be a data packet-free period. Multiple data packet-free periods can be covered within the baseline observation window with the current moment as the end point.

[0041] S1-2. Dynamically update the first baseline of the current load calculation cycle based on the first baseline N1 at startup and the number of DPDK cycles in the data packet-free period. Optionally, first convert the number of DPDK cycles in all data packet-free periods in the baseline observation window into the number of DPDK cycles current_cycles in the entire load calculation cycle. Exemplarily, the sum of the number of DPDK cycles in all data packet-free periods is summed, the sum is divided by the sum of the duration of all data packet-free periods, and then multiplied by the duration of a load calculation cycle to convert it into current_cycles. Then use the following formula to update the first baseline N11 of the current load calculation cycle:

[0042]

[0043] Among them, α is a dynamic weight coefficient, which can take a value between 0.75 and 0.9. The specific value is automatically adjusted according to environmental parameters.

[0044] S1-3. Preliminarily determine the CPU load rate of the current load calculation cycle based on the first baseline, the second baseline, and the number of DPDK cycles in the current load calculation cycle. Optionally, use the first counting anchor point to record the number of DPDK cycles in the current load calculation cycle to obtain the actual number of cycles N, then:

[0045]

[0046] in, Indicates the CPU load rate of the current load calculation cycle. Indicates the number of DPDK cycles in the current load calculation period. represents the second baseline, Represents the first baseline of the current load calculation cycle. This corresponds to a CPU load rate of 100% during the current load calculation period.

[0047] Furthermore, when the CPU of the onboard network device includes multiple cores, the operations from S1-1 to S1-2 can be performed separately for each CPU core, and the CPU load rate of each core can be collected in a lock-free data manner. Figure 3 As shown, each CPU core independently writes its data to local storage, and the aggregator then reads the data in batches. Data writes are atomic to avoid lock contention. After reading the data, the aggregator first normalizes the multi-core data to eliminate the impact of inter-core frequency differences. It then averages the CPU load rates of all cores to obtain the overall CPU load rate.

[0048] S1-4: Compensate the initially determined CPU load rate based on the current temperature and space radiation to obtain the actual CPU load rate for the current load calculation cycle. As mentioned above, the CPU load rate determined in S1-3 is based on baseline cycle data without message processing. In this non-message state, the CPU likely primarily executes basic instructions such as loop determination and branch jumps, which are relatively simple operations. However, when message processing is in progress, the CPU also involves packet copying, verification, memory access, and cache operations, which may result in more arithmetic, logical, and memory operations, thereby increasing the load on some hardware units (such as the floating-point unit and cache controller), and may be affected by temperature differences. Furthermore, radiation conditions in the satellite environment can also affect CPU status. Therefore, this module comprehensively considers the effects of temperature and radiation and proposes an environmental compensation model for CPU load data.

[0049] In one embodiment, the model includes temperature compensation and radiation compensation. Temperature compensation aims to establish a linear relationship model between chip temperature and clock drift, while radiation compensation aims to adjust the calculation sensitivity of the load factor based on the predicted spatial radiation intensity. With both compensations, the final load factor calculation formula is as follows:

[0050]

[0051] Where f(T) is the piecewise temperature compensation function, which is described as follows:

[0052] Low temperature area (<55℃): disable compensation to avoid overcorrection at low load;

[0053] Medium temperature range (55-75℃): linear compensation model is used, compensation coefficient f(T)=0.12×(T-55)+0.05×(dT / dt);

[0054] High temperature area (≥75°C): Enable the quadratic compensation model, compensation coefficient f(T) = 0.15 × (T-75)^2 + 0.18 × (dT / dt), where ^2 represents square.

[0055] RAD is the radiation intensity index. The above model introduces a temperature coupling factor in the radiation compensation, which enhances the radiation sensitivity when T>40℃;

[0056] λ is the calibration coefficient, t represents time, and dT / dt represents the partial derivative of temperature with respect to time.

[0057] Based on the above model, the preliminary load rate obtained in S1-3, as well as the current temperature and radiation lightness index, are substituted into the above formula to obtain the final actual load rate.

[0058] After the calculation is completed, this embodiment adopts a real-time output mechanism to output the load rate curve at a fixed time interval (100ms). The output data format is compatible with the telemetry interface of the onboard system and provides a load rate sudden change alarm function. The alarm threshold can be dynamically configured.

[0059] Furthermore, in this embodiment, the values ​​of the counting anchor points can be read in time slices. To ensure data accuracy, after obtaining the data of the two timing anchor points, they can also be verified and error-corrected to eliminate single-particle interference in the spatial environment and obtain accurate and effective DPDK cycle count values ​​(for example, the DPDK cycle count values ​​in S120 and S130 are all read in time slices and have been verified and error-corrected).

[0060] Specifically, this embodiment employs a three-level protection mechanism to detect errors in received data. First, hardware-level protection is performed: memory ECC (Error Checking and Correction) is enabled to correct single-bit flip errors in real time. Then, software-level verification is performed: hash values ​​of key data structures are periodically calculated to detect multi-bit errors. Finally, timing continuity verification is performed: the time difference distribution between adjacent cycles is statistically analyzed and compared with the time difference distribution between cycles in a baseline database to determine whether the count data is reasonable.

[0061] After the test is complete, the error recovery process begins. Optionally, if an error is detected in the count value data received in memory, a data rollback mechanism is automatically triggered, discarding the erroneous data and rolling back to the previous correct data. If the check fails three times in a row, the count value storage area is reinitialized. During this period, the error event is recorded in the radiation log for subsequent reliability analysis.

[0062] After three levels of error detection and error recovery, the CPU load rate is calculated based on the final retained count value.

[0063] In summary, this embodiment provides a CPU load monitoring method for satellite-borne network equipment based on dynamic compensation. It can accurately monitor the true load rate of the DPDK exclusive core in a space radiation environment with single-event upsets, solving the problems of error accumulation and insufficient anti-interference capability in traditional monitoring methods in extreme environments. It provides reliable data support for satellite resource scheduling and fault warning. The entire method has low error, high reliability, and low resource consumption. Specifically, the method:

[0064] 1. A non-intrusive timing anchor mechanism is introduced, embedding dual anchors in the DPDK main packet receiving loop. Cycle start and end timestamps are directly obtained through dedicated clock instructions, avoiding system call overhead. 4KB-aligned core-exclusive cache pages are used to isolate and store data, combined with memory barrier instructions to ensure timing measurement accuracy, with errors controlled to the 10 nanosecond level.

[0065] 2. A dynamic baseline calibration mode is proposed. Before the load calculation cycle starts, a baseline value is established by running in the no-packet and full-packet states. During operation, the baseline is dynamically updated using a temperature-compensated sliding window algorithm. By introducing a temperature weighting factor (adjustable from 0.75 to 0.9), the window is automatically narrowed to 1 / 3 when the chip temperature fluctuates by more than ±5°C, improving environmental adaptability.

[0066] 3. A three-level radiation-hardened verification system provides three levels of protection: hardware ECC (single-bit error correction), software hash check (critical data structure integrity), and timing continuity verification (analysis of time difference distribution between adjacent cycles). Triple-module redundancy is used to store timestamp data, and error recovery can complete baseline rollback within 2ms. This eliminates the cumulative error amplification caused by memory bit flips, ensuring continuous system operation and addressing the issue of monitoring data contamination caused by single-event upsets.

[0067] 4. A dynamic model for CPU load data environment compensation is proposed, and a temperature-clock drift linear compensation model and a radiation intensity sensitivity adjustment model (λ coefficient) are established to achieve real-time compensation calculation and further improve environmental adaptability.

[0068] Figure 4 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention is shown in FIG. Figure 4 As shown, the device includes a processor 60, a memory 61, an input device 62 and an output device 63; the number of processors 60 in the device can be one or more. Figure 4 In the embodiment, a processor 60 is used as an example; the processor 60, the memory 61, the input device 62 and the output device 63 in the device can be connected by a bus or other means. Figure 4 The bus connection is taken as an example.

[0069] Memory 61, as a computer-readable storage medium, can be used to store software programs, computer-executable programs, and modules, such as the program instructions / modules corresponding to the method for monitoring CPU load of an onboard network device based on dynamic compensation in the embodiments of the present invention. Processor 60 executes the software programs, instructions, and modules stored in memory 61 to execute various functional applications and data processing functions of the device, thereby implementing the aforementioned method for monitoring CPU load of an onboard network device based on dynamic compensation.

[0070] The memory 61 may primarily include a program storage area and a data storage area. The program storage area may store an operating system and at least one application required for a function; the data storage area may store data generated based on the use of the terminal. Furthermore, the memory 61 may include high-speed random access memory and non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state memory device. In some instances, the memory 61 may further include memory remotely located relative to the processor 60, and these remote memories may be connected to the device via a network. Examples of such networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0071] The input device 62 may be used to receive input digital or character information and generate key signal input related to user settings and function control of the device. The output device 63 may include a display device such as a display screen.

[0072] An embodiment of the present invention further provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the CPU load monitoring method based on dynamic compensation for a satellite-borne network device of any embodiment.

[0073] The computer storage medium of the embodiments of the present invention may adopt any combination of one or more computer-readable media. The computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device, or device.

[0074] A computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0075] Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0076] Computer program code for performing the operations of the present invention can be written in one or more programming languages, or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as C or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present invention.

Claims

1. A CPU load monitoring method based on dynamic compensation for a satellite-borne network device, characterized in that: include: Obtain a first baseline and a second baseline when a load calculation cycle of the onboard network device is started, wherein the first baseline is the number of Data Plane Development Kit (DPDK) cycles in which the CPU of the onboard network device remains in a no-data-packet state during one load calculation cycle, and the second baseline is the number of DPDK cycles in which the CPU of the onboard network device remains in a full-data-packet state during one load calculation cycle; The following operations are performed in each load calculation cycle: S1-1, dynamically determining a baseline observation window based on the current CPU temperature, and extracting a data packet-free period within the baseline observation window; S1-2, dynamically updating the first baseline of the current load calculation cycle according to the first baseline at startup and the number of DPDK cycles in the data packet-free period; S1-3. Preliminarily determine the CPU load rate of the current load calculation period based on the first baseline of the current load calculation period, the second baseline, and the number of DPDK cycles in the current load calculation period; S1-4. Compensate the preliminarily determined CPU load rate according to the current temperature and space radiation to obtain the actual CPU load rate of the current load calculation period.

2. The method according to claim 1, characterized in that The obtaining of the first baseline and the second baseline when the load calculation cycle of the onboard network device is started includes: Inserting a first counting anchor point and a second counting anchor point into a DPDK cycle of the onboard network device, wherein the first counting anchor point is used to record the number of DPDK cycles, and the second counting anchor point is used to record the number of DPDK cycles with data packets; Before the load calculation cycle of the onboard network equipment is started, the following operations are performed in two time periods of equal length to the load calculation cycle: Simulating a no-data-packet state within a period of time, and using the first counting anchor point to record the number of DPDK cycles within the period of time as a first baseline when the load calculation cycle starts; A full data packet state is simulated in another time period, and the second counting anchor point is used to record the number of DPDK cycles in the other time period as a second baseline when the load calculation cycle is started.

3. The method according to claim 1, characterized in that The dynamically determining the baseline observation window according to the current CPU temperature includes: When the CPU temperature fluctuation exceeds the set threshold, the baseline observation window length is reduced.

4. The method according to claim 1, wherein The dynamically updating the first baseline of the current load calculation cycle according to the first baseline at startup and the number of DPDK cycles in the data packet-free period includes: Convert the number of DPDK cycles in the no-data-packet period into the number of DPDK cycles in a load calculation cycle; A weighted average of the converted DPDK cycle number and the first baseline at startup is taken as the first baseline of the current load calculation cycle.

5. The method according to claim 1, wherein The preliminarily determining the CPU load rate of the current load calculation period according to the first baseline of the current load calculation period, the second baseline, and the number of DPDK cycles in the current load calculation period includes: in, Indicates the CPU load rate of the current load calculation cycle. Indicates the number of DPDK cycles in the current load calculation period. represents the second baseline, Indicates the first baseline for the current load calculation period.

6. The method according to claim 1, characterized in that The number of each DPDK cycle is recorded by a first counting anchor point and a second counting anchor point set in the DPDK cycle of the onboard network device, wherein the working mode of the two counting anchor points is: Each time the CPU enters the DPDK loop, the first counting anchor point is incremented by 1. If there is no data packet in the current DPDK cycle, it directly enters the next DPDK cycle; If there is a data packet in the current DPDK cycle, the second counting anchor point is increased by 1, and the next DPDK cycle is entered after the data packet is processed.

7. The method according to claim 1, characterized in that The number of each DPDK cycle is obtained by recording a first counting anchor point and a second counting anchor point set in the DPDK cycle of the onboard network device; The method further comprises: In response to the counting anchor point data from the onboard network device, performing memory error checking and correction (ECC) check, hash value check and statistical method verification on the data to detect single event disturbances; Perform error recovery on verified data; Use the recovered data for subsequent operations.

8. The method according to claim 1, characterized in that The CPU load rate initially determined is compensated according to the current temperature and space radiation to obtain the actual CPU load rate of the current load calculation period, including: Determine the actual load rate for the current load calculation period using the following formula: Actual load rate = preliminarily determined CPU load rate × [1 + f(T) + λ × RAD × (1 + A × (TB))] Where T is the current temperature, f(T) is the temperature compensation function, RAD is the radiation intensity index, and λ, A, and B are calibration coefficients.

9. The method according to claim 8, characterized in that f(T) is the segmented temperature compensation function, where Low temperature region, f(T)=0; In the medium temperature zone, f(T) is a linear temperature compensation function; In the high temperature area, f(T) is the quadratic temperature compensation function.

10. An electronic device, characterized in that: include: one or more processors; a memory for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the CPU load monitoring method based on dynamic compensation of the onboard network device as described in any one of claims 1-9.

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