Chip testing system and method based on ATE and package integration

Abstract

The application belongs to the technical field of chip testing, and discloses a chip detection system and method based on ATE and implementation integration. An electrical connection is established between a chip interface unit and a chip to be tested. The chip interface unit comprises an adaptive clamp and a connecting circuit board. A precise contact array is arranged in the adaptive clamp, which is used to reliably connect the chip to be tested and the connecting circuit board. A detection analysis unit executes various types of detection programs of the chip to be tested and collects detection data. A result processing unit receives, integrates and processes the detection data collected by the detection analysis unit, and generates a detection report. In the above manner, the shortcomings of single ATE testing and implementation testing are made up, and the test fault coverage is improved.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to a chip testing system and method based on ATE and physical integration. Background Technology

[0002] As a core chip for Dual-Tone Multi-Frequency (DTMF) codecs, the MT8880's performance directly impacts the signal resolution accuracy and anti-interference capabilities of communication equipment. Traditional testing methods primarily rely on discrete instruments such as signal generators and spectrum analyzers, manually verifying the chip's DTMF signal generation, receiving sensitivity, and decoding functions item by item. This approach suffers from long testing cycles and incomplete parameter coverage, particularly inadequate performance evaluation capabilities under complex conditions such as dynamic load changes and temperature drift. Although existing automated test equipment (ATE) has improved testing efficiency to some extent through script control, it still suffers from low fault test coverage.

[0003] The above content is only used to help understand the technical solution of the present invention and does not represent an admission that the above content is prior art. Summary of the Invention

[0004] The main objective of this invention is to provide a chip testing system and method based on ATE and physical integration, aiming to solve the technical problem of low fault test coverage.

[0005] To achieve the above objectives, the present invention provides a chip testing system based on ATE and physical integration. The chip testing system based on ATE and physical integration includes: a chip interface unit, a detection and analysis unit, and a result processing unit. The chip interface unit is electrically connected to the detection and analysis unit and the result processing unit.

[0006] The chip interface unit is used to establish an electrical connection with the chip under test. The chip interface unit includes an adapter fixture and a connecting circuit board. The adapter fixture is provided with a precision contact array to achieve reliable connection between the chip under test and the connecting circuit board.

[0007] The detection and analysis unit is used to execute various types of detection programs for the chip under test and collect detection data.

[0008] The result processing unit is used to receive, integrate and process the detection data collected by the detection and analysis unit, and generate a detection report. The result processing unit is built with a high-performance computer and equipped with dedicated data processing software to collect and parse the detection data in real time.

[0009] In some embodiments, the detection and analysis unit includes at least: an ATE automatic detection device, a spectrum analysis device, a bit error rate detector, a waveform observer, and a modulation signal generator. The ATE automatic detection device is used to run the chip test program and control the entire detection process. The spectrum analysis device is used to analyze the spectral characteristics of the chip. The bit error rate detector is used to detect the bit error rate of the chip during signal transmission. The waveform observer is used to observe the output waveform of the chip. The modulation signal generator is used to generate a modulation signal to test the modulation and demodulation capability of the chip.

[0010] In some embodiments, the ATE automatic testing device is used to perform a program start-up self-test during the system initialization phase to check the hardware and software status of the ATE device and ensure that the device operates normally, and during the chip testability design verification phase, including boundary scan testing and functional verification testing, to verify whether the internal structure and function of the chip are normal.

[0011] In some embodiments, the testing procedure includes connectivity testing, functional testing, performance testing, power supply voltage testing, interference immunity testing, and long-term reliability testing.

[0012] In some embodiments, the connectivity test involves establishing a hardware connection between the chip under test (DUT) and the test equipment via an adapter, procuring a matching test locking socket based on the DUT's packaging process, designing a PCB board, soldering the locking socket, and then performing a connectivity test to ensure reliable electrical connection between the chip and the test equipment. The functional test involves using a signal generator to generate a standard DTMF signal, connecting it to the input terminal of the DUT, introducing the DTMF signal, and using an oscilloscope to record the DUT's output to ensure correct decoding of each digit. The performance test involves performing basic performance tests at room temperature, recording decoding delay and accuracy, gradually changing the operating temperature from a first preset temperature to a second preset temperature, and then... Decoding tests are conducted at preset temperature intervals, and the stability and accuracy of decoding are recorded. The power supply voltage test involves increasing the voltage from a first preset voltage to a second preset voltage using an adjustable power supply, and recording the chip's decoding capability for DTMF signals at different voltage levels, while keeping the DTMF signal strength constant during the test. The anti-interference test involves applying noise while the signal generator outputs the DTMF signal, and recording the changes in the chip's decoding to test its stability under different interference levels, and recording the error rate of the decoded signal. The long-term reliability test involves placing the chip under test in a preset environment for a preset duration, and then determining whether the chip's function is normal and whether its decoding capability is affected.

[0013] Furthermore, to achieve the above objectives, this invention also proposes a chip testing method based on ATE and physical integration. This method is applied to the ATE and physical integration chip testing system described above, and includes:

[0014] The chip interface unit establishes an electrical connection with the chip under test. The chip interface unit includes an adapter fixture and a connecting circuit board. The adapter fixture is equipped with a precision contact array to achieve reliable connection between the chip under test and the connecting circuit board.

[0015] The detection and analysis unit executes various types of detection programs for the chip under test and collects detection data;

[0016] The result processing unit receives, integrates, and processes the detection data collected by the detection and analysis unit, and generates a detection report. The result processing unit is built using a high-performance computer and equipped with dedicated data processing software to collect and analyze the detection data in real time.

[0017] In some embodiments, the detection and analysis unit includes at least: an ATE automatic detection device, a spectrum analysis device, a bit error rate detector, a waveform observer, and a modulation signal generator. The ATE automatic detection device is used to run the chip test program and control the entire detection process. The spectrum analysis device is used to analyze the spectral characteristics of the chip. The bit error rate detector is used to detect the bit error rate of the chip during signal transmission. The waveform observer is used to observe the output waveform of the chip. The modulation signal generator is used to generate a modulation signal to test the modulation and demodulation capability of the chip.

[0018] In some embodiments, the method further includes:

[0019] During the system initialization phase, the ATE automatic testing equipment executes a program to start a self-test, checking the hardware and software status of the ATE equipment to ensure normal operation. During the chip testability design verification phase, including boundary scan testing and functional verification testing, it is used to verify whether the internal structure and function of the chip are normal.

[0020] In some embodiments, the testing procedure includes connectivity testing, functional testing, performance testing, power supply voltage testing, interference immunity testing, and long-term reliability testing.

[0021] In some embodiments, the connectivity test involves establishing a hardware connection between the chip under test (DUT) and the test equipment via an adapter, procuring a matching test locking socket based on the DUT's packaging process, designing a PCB board, soldering the locking socket, and then performing a connectivity test to ensure reliable electrical connection between the chip and the test equipment. The functional test involves using a signal generator to generate a standard DTMF signal, connecting it to the input terminal of the DUT, introducing the DTMF signal, and using an oscilloscope to record the DUT's output to ensure correct decoding of each digit. The performance test involves performing basic performance tests at room temperature, recording decoding delay and accuracy, gradually changing the operating temperature from a first preset temperature to a second preset temperature, and then... Decoding tests are conducted at preset temperature intervals, and the stability and accuracy of decoding are recorded. The power supply voltage test involves increasing the voltage from a first preset voltage to a second preset voltage using an adjustable power supply, and recording the chip's decoding capability for DTMF signals at different voltage levels, while keeping the DTMF signal strength constant during the test. The anti-interference test involves applying noise while the signal generator outputs the DTMF signal, and recording the changes in the chip's decoding to test its stability under different interference levels, and recording the error rate of the decoded signal. The long-term reliability test involves placing the chip under test in a preset environment for a preset duration, and then determining whether the chip's function is normal and whether its decoding capability is affected.

[0022] This invention establishes an electrical connection with the chip under test (DUT) through a chip interface unit. The chip interface unit includes an adapter fixture and a connecting circuit board. The adapter fixture contains a precision contact array to ensure reliable connection between the DUT and the connecting circuit board. A detection and analysis unit executes various types of detection programs for the DUT and collects detection data. A result processing unit receives, integrates, and processes the detection data collected by the detection and analysis unit and generates a test report. This approach overcomes the limitations of single ATE testing and physical assembly testing, improving test fault coverage. Attached Figure Description

[0023] Figure 1 This is a structural block diagram of the first embodiment of the chip testing system based on ATE and physical integration of the present invention;

[0024] Figure 2 This is a flowchart illustrating the first embodiment of the chip testing method based on ATE and physical integration of the present invention.

[0025] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0026] It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.

[0027] This invention provides a chip testing system based on ATE and physical integration, referring to... Figure 1 , Figure 1 This is a structural block diagram of a first embodiment of a chip testing system based on ATE and physical integration according to the present invention.

[0028] In this embodiment, the chip testing system based on ATE and physical integration includes a chip interface unit, a testing and analysis unit, and a result processing unit, wherein the chip interface unit is electrically connected to the testing and analysis unit and the result processing unit.

[0029] In its implementation, the chip interface unit establishes an electrical connection with the chip under test (DUT). The chip interface unit includes an adapter fixture and a connecting circuit board. The adapter fixture contains a precision contact array to ensure reliable connection between the DUT and the connecting circuit board. The detection and analysis unit executes various types of detection programs for the DUT and collects detection data. The result processing unit receives, integrates, and processes the detection data collected by the detection and analysis unit and generates a detection report. The result processing unit is built using a high-performance computer and equipped with dedicated data processing software to collect and analyze detection data in real time. The detection and analysis unit includes at least: an ATE (Automatic Test Equipment), a spectrum analyzer, a bit error rate detector, a waveform observer, and a modulation signal generator. The ATE runs the chip test program and controls the entire detection process. The spectrum analyzer analyzes the chip's spectral characteristics. The bit error rate detector detects bit errors during signal transmission. The waveform observer observes the chip's output waveform. The modulation signal generator generates a modulation signal to test the chip's modulation and demodulation capabilities.

[0030] It should be noted that the overall testing process of this technical solution involves assembling the chip under test into the interface unit; executing a complete testing procedure through the detection and analysis unit, simultaneously collecting DC operating parameters and AC characteristic parameters; and using a data processing terminal to synthesize the testing process data, DC parameters, and AC parameters to generate a standardized testing report. The circuit architecture in this technical solution integrates Automated Test Equipment (ATE) modules and System-in-Package (SiP) testing technology to construct a dual-dimensional verification system during chip testing: relying on the ATE platform to complete microsystem functional simulation and AC / DC parameter measurement, and combining this with the SiP implementation environment to achieve chip-level functional verification. This hybrid testing strategy effectively integrates the technical advantages of ATE modular testing and system-level implementation verification, forming a complementary testing architecture and significantly improving the defect detection rate (FDR) to an advanced level in the industry. Specifically, the circuit innovatively adopts an ATE programmable test interface, which can accurately acquire the electrical characteristic parameters of the microsystem I / O ports, covering key indicators such as connection integrity, static power consumption distribution, drive strength threshold, and dynamic timing response, while simultaneously supporting power spectrum analysis under multiple operating modes. Empirical studies have shown that this solution reduces the testing cycle by approximately 40% and the overall cost by up to 35% compared to traditional single-mode testing processes, demonstrating significant engineering application value. By integrating an ATE testing system with microsystem physical verification methods, system functionality and AC / DC parameter testing can be completed simultaneously during chip testing. This integrated solution effectively combines the advantages of ATE automated testing and prototype verification technologies, overcoming the limitations of single testing modes and significantly improving overall fault detection capabilities. Compared to existing technologies, the advantages and positive effects of this new testing method are: this solution achieves a shorter testing time and significantly higher testing accuracy than traditional step-by-step testing solutions.

[0031] In practical applications, the adapter is an external device under test (DUT) that connects to the DUT, converting various test channels, DPS, AGND, and control relays to the adapter, which then connects to the DUT via sockets. Taking the MT8880 chip as an example, the MT8880 chip's interface unit is connected to the test unit; the MT8880 chip's test unit establishes a signal transmission channel with the result output unit; the MT8880 chip's test unit consists of an automated test equipment (ATE), a spectrum analyzer, a bit error rate detector, a waveform acquisition unit, and a signal modulation source, all of which are electrically connected to the DUT through the interface unit; the ATE system runs the chip test program, while other devices simultaneously acquire the chip's AC and DC characteristic parameters during the test; the result output unit integrates the test program execution data and related parameter indicators; during testing, the MT8880 chip's interface pins are connected to the ATE equipment's digital system adapter.

[0032] The testing process corresponding to the aforementioned ATE automatic testing equipment is divided into two stages. Specifically, in the system initialization stage, the program is executed to start self-test, check the hardware and software status of the ATE equipment, and ensure that the equipment is operating normally. In the chip testability design verification stage, including boundary scan test and functional verification test, it is used to verify whether the internal structure and function of the chip are normal.

[0033] Furthermore, the detection and analysis unit executes various types of test procedures, including connectivity testing, functional testing, performance testing, power supply voltage testing, interference immunity testing, and long-term reliability testing. Specifically, connectivity testing involves establishing a hardware connection between the chip under test (DUT) and the test equipment via an adapter. A matching test locking socket is procured based on the DUT's packaging process. A PCB board is designed, and the locking socket is soldered before connectivity testing to ensure reliable electrical connection between the chip and the test equipment. Functional testing involves using a signal generator to generate a standard DTMF signal, connecting it to the input of the DUT, introducing the DTMF signal, and recording the DUT's output using an oscilloscope to ensure correct decoding of each digit. Performance testing involves performing basic performance tests at room temperature, recording decoding delay and accuracy, and gradually changing the operating temperature from a first preset temperature to a second preset temperature, and then following preset parameters. The decoding test is conducted at temperature intervals, and the stability and accuracy of the decoding are recorded. The power supply voltage test involves increasing the voltage from a first preset voltage to a second preset voltage using an adjustable power supply, and recording the chip's decoding capability for DTMF signals at different voltage levels, while keeping the DTMF signal strength constant during the test. The anti-interference test involves applying noise while the signal generator outputs the DTMF signal, and recording the changes in the decoding of the chip under test to test its stability under different interference levels, and recording the error rate of the decoded signal. The long-term reliability test involves placing the chip under test in a preset environment for a preset period of time, and then determining whether the chip's function is normal and whether its decoding capability is affected.

[0034] It should be noted that during connectivity testing, the hardware connection between the device under test (DUT) and the test equipment is established via an adapter. A matching test locking socket is procured based on the DUT's packaging process. The PCB is designed according to the test system interface board schematic, and finally, the locking socket is soldered in for connectivity testing. The standard DTMF signal used in functional testing is, for example, 1234567890*#. In performance testing, the first preset temperature can be set to -20℃, the second preset temperature to 70℃, and the preset temperature interval can be set to 10℃. That is, decoding is performed every 10℃ as the temperature rises from -20℃ to 70℃ to observe the stability and accuracy of decoding. In power supply voltage testing, the first preset voltage can be set to 4.5V, the second preset voltage to 5.5V, and the preset voltage range can be set to 0.5V. That is, the chip's decoding capability at different voltages is recorded in 0.5V intervals as it rises from 4.5V to 5.5V. The noise applied in the interference immunity test can be a 1kHz sine wave interference. In long-term reliability testing, the preset environment can be a high-temperature and high-humidity environment, such as an environment with a temperature of 60°C to 85°C and humidity above 85%, and the preset duration can be set to 72 hours. It should be understood that the above parameter settings are for illustrative purposes only and are not intended to limit this embodiment; adjustments can be made according to actual circumstances.

[0035] This embodiment establishes an electrical connection with the chip under test (DUT) through a chip interface unit. The chip interface unit includes an adapter fixture and a connecting circuit board. The adapter fixture contains a precision contact array to ensure reliable connection between the DUT and the connecting circuit board. A detection and analysis unit executes various types of detection programs for the DUT and collects detection data. A result processing unit receives, integrates, and processes the detection data collected by the detection and analysis unit and generates a test report. This approach overcomes the limitations of single ATE testing and physical assembly testing, improving test fault coverage.

[0036] Reference Figure 2 , Figure 2 This is a flowchart illustrating the first embodiment of the chip testing method based on ATE and physical integration of the present invention.

[0037] like Figure 2 As shown, the chip testing method based on ATE and physical integration proposed in this embodiment of the invention includes:

[0038] Step S10: The chip interface unit establishes an electrical connection with the chip under test.

[0039] Step S20: The detection and analysis unit executes various types of detection programs for the chip under test and collects detection data.

[0040] Step S30: The result processing unit receives, integrates and processes the detection data collected by the detection and analysis unit, and generates a detection report.

[0041] This embodiment establishes an electrical connection with the chip under test (DUT) through a chip interface unit. The chip interface unit includes an adapter fixture and a connecting circuit board. The adapter fixture contains a precision contact array to ensure reliable connection between the DUT and the connecting circuit board. A detection and analysis unit executes various types of detection programs for the DUT and collects detection data. A result processing unit receives, integrates, and processes the detection data collected by the detection and analysis unit and generates a test report. This approach overcomes the limitations of single ATE testing and physical assembly testing, improving test fault coverage.

[0042] In some embodiments, the detection and analysis unit includes at least: an ATE automatic detection device, a spectrum analysis device, a bit error rate detector, a waveform observer, and a modulation signal generator. The ATE automatic detection device is used to run the chip test program and control the entire detection process. The spectrum analysis device is used to analyze the spectral characteristics of the chip. The bit error rate detector is used to detect the bit error rate of the chip during signal transmission. The waveform observer is used to observe the output waveform of the chip. The modulation signal generator is used to generate a modulation signal to test the modulation and demodulation capability of the chip.

[0043] In some embodiments, the method further includes:

[0044] During the system initialization phase, the ATE automatic testing equipment executes a program to start a self-test, checking the hardware and software status of the ATE equipment to ensure normal operation. During the chip testability design verification phase, including boundary scan testing and functional verification testing, it is used to verify whether the internal structure and function of the chip are normal.

[0045] In some embodiments, the testing procedure includes connectivity testing, functional testing, performance testing, power supply voltage testing, interference immunity testing, and long-term reliability testing.

[0046] In some embodiments, the connectivity test involves establishing a hardware connection between the chip under test (DUT) and the test equipment via an adapter, procuring a matching test locking socket based on the DUT's packaging process, designing a PCB board, soldering the locking socket, and then performing a connectivity test to ensure reliable electrical connection between the chip and the test equipment. The functional test involves using a signal generator to generate a standard DTMF signal, connecting it to the input terminal of the DUT, introducing the DTMF signal, and using an oscilloscope to record the DUT's output to ensure correct decoding of each digit. The performance test involves performing basic performance tests at room temperature, recording decoding delay and accuracy, gradually changing the operating temperature from a first preset temperature to a second preset temperature, and then... Decoding tests are conducted at preset temperature intervals, and the stability and accuracy of decoding are recorded. The power supply voltage test involves increasing the voltage from a first preset voltage to a second preset voltage using an adjustable power supply, and recording the chip's decoding capability for DTMF signals at different voltage levels, while keeping the DTMF signal strength constant during the test. The anti-interference test involves applying noise while the signal generator outputs the DTMF signal, and recording the changes in the chip's decoding to test its stability under different interference levels, and recording the error rate of the decoded signal. The long-term reliability test involves placing the chip under test in a preset environment for a preset duration, and then determining whether the chip's function is normal and whether its decoding capability is affected.

[0047] This application embodiment also provides a chip testing device based on ATE and physical integration, including a processor, a communication interface, a memory, and a communication bus. The processor, communication interface, and memory communicate with each other through the communication bus. The memory is used to store the chip testing program based on ATE and physical integration. When the processor executes the program stored in the memory, it implements the above-mentioned chip testing method based on ATE and physical integration.

[0048] The communication bus mentioned in the aforementioned chip testing equipment based on ATE and physical integration can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc.

[0049] The communication interface is used for communication between the aforementioned ATE-based chip testing equipment and other devices.

[0050] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0051] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0052] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).

[0053] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0054] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0055] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

[0056] It should be understood that the above are merely illustrative examples and do not constitute any limitation on the technical solutions of the present invention. In specific applications, those skilled in the art can make settings as needed, and the present invention does not impose any restrictions on this.

[0057] It should be noted that the workflow described above is merely illustrative and does not limit the scope of protection of this invention. In practical applications, those skilled in the art can select some or all of the workflow to achieve the purpose of this embodiment according to actual needs, and no restrictions are imposed here.

[0058] In addition, for technical details not described in detail in this embodiment, please refer to the chip testing method based on ATE and physical integration provided in any embodiment of the present invention, which will not be repeated here.

[0059] Furthermore, it should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0060] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0061] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as read-only memory (ROM) / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0062] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

[0063] It is understood that the system provided in the embodiments of the present invention corresponds to the method provided in the embodiments of the present invention, and the explanation, examples and beneficial effects of the relevant content can be referred to the corresponding parts of the above methods.

Claims

1. A chip testing system based on ATE and physical integration, characterized in that, The chip testing system based on ATE and physical integration includes: a chip interface unit, a testing and analysis unit, and a result processing unit, wherein the chip interface unit is electrically connected to the testing and analysis unit and the result processing unit; The chip interface unit is used to establish an electrical connection with the chip under test. The chip interface unit includes an adapter fixture and a connecting circuit board. The adapter fixture is provided with a precision contact array to achieve reliable connection between the chip under test and the connecting circuit board. The detection and analysis unit is used to execute various types of detection programs for the chip under test and collect detection data. The result processing unit is used to receive, integrate and process the detection data collected by the detection and analysis unit, and generate a detection report. The result processing unit is built with a high-performance computer and equipped with dedicated data processing software to collect and parse the detection data in real time. The testing procedure includes connectivity testing, functional testing, performance testing, power supply voltage testing, anti-interference testing, and long-term reliability testing. The connectivity testing involves establishing a hardware connection between the chip under test (DUT) and the testing equipment via an adapter. A matching test locking socket is procured based on the DUT's packaging process, a PCB board is designed, and the locking socket is soldered before the connectivity test is performed to ensure reliable electrical connection between the chip and the testing equipment. The functional testing involves using a signal generator to generate a standard DTMF signal, connecting it to the input terminal of the DUT, introducing the DTMF signal, and using an oscilloscope to record the DUT's output to ensure correct decoding of each digit. The performance testing involves performing basic performance tests at room temperature, recording decoding delay and accuracy, and gradually changing the operating temperature. The chip's decoding capability is tested by increasing the temperature from a first preset temperature to a second preset temperature at preset temperature intervals, recording the stability and accuracy of the decoding. The power supply voltage test involves increasing the voltage from the first preset voltage to the second preset voltage using an adjustable power supply at preset voltage levels, recording the chip's decoding capability for DTMF signals at different voltages, while keeping the DTMF signal strength constant during the test. The anti-interference test involves applying noise while the signal generator outputs the DTMF signal, recording the changes in the chip's decoding to test stability under different interference levels, and recording the error rate of the decoded signal. The long-term reliability test involves placing the chip under test in a preset environment for a preset duration, then determining whether the chip's function is normal and whether its decoding capability is affected.

2. The chip testing system based on ATE and physical integration as described in claim 1, characterized in that, The detection and analysis unit includes at least: an ATE automatic detection device, a spectrum analyzer, a bit error rate detector, a waveform observer, and a modulation signal generator. The ATE automatic detection device is used to run the chip test program and control the entire detection process. The spectrum analyzer is used to analyze the spectral characteristics of the chip. The bit error rate detector is used to detect the bit error rate of the chip during signal transmission. The waveform observer is used to observe the output waveform of the chip. The modulation signal generator is used to generate a modulation signal to test the modulation and demodulation capabilities of the chip.

3. The chip testing system based on ATE and physical integration as described in claim 2, characterized in that, The ATE automatic testing equipment is used to perform a program start-up self-test during the system initialization phase to check the hardware and software status of the ATE equipment and ensure that the equipment is operating normally. It is also used during the chip testability design verification phase, including boundary scan testing and functional verification testing, to verify whether the internal structure and function of the chip are normal.

4. A chip testing method based on ATE and physical integration, characterized in that, The chip testing method based on ATE and physical integration is applied to the chip testing system based on ATE and physical integration as described in any one of claims 1 to 3, and the method includes: The chip interface unit establishes an electrical connection with the chip under test. The chip interface unit includes an adapter fixture and a connecting circuit board. The adapter fixture is equipped with a precision contact array to achieve reliable connection between the chip under test and the connecting circuit board. The detection and analysis unit executes various types of detection programs for the chip under test and collects detection data; The result processing unit receives, integrates, and processes the detection data collected by the detection and analysis unit, and generates a detection report. The result processing unit is built using a high-performance computer and equipped with dedicated data processing software to collect and analyze the detection data in real time.

5. The chip testing method based on ATE and physical integration as described in claim 4, characterized in that, The detection and analysis unit includes at least: an ATE automatic detection device, a spectrum analyzer, a bit error rate detector, a waveform observer, and a modulation signal generator. The ATE automatic detection device is used to run the chip test program and control the entire detection process. The spectrum analyzer is used to analyze the spectral characteristics of the chip. The bit error rate detector is used to detect the bit error rate of the chip during signal transmission. The waveform observer is used to observe the output waveform of the chip. The modulation signal generator is used to generate a modulation signal to test the modulation and demodulation capabilities of the chip.

6. The chip testing method based on ATE and physical integration as described in claim 5, characterized in that, The method further includes: During the system initialization phase, the ATE automatic testing equipment executes a program to start a self-test, checking the hardware and software status of the ATE equipment to ensure normal operation. During the chip testability design verification phase, including boundary scan testing and functional verification testing, it is used to verify whether the internal structure and function of the chip are normal.

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