Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a data signal line, a signal line, a fan-out line, a multiplex circuit and a side bonding pad, the multiplexing circuit comprises a plurality of multiplexing units; the input end of the multiplexing unit is connected with the signal line, and the multiple output ends of the multiplexing unit are connected with the multiple data signal lines in a one-to-one correspondence mode; the side bonding pads are connected with the input end of the multiplexing circuit through corresponding signal wires; the fan-out wires comprise first fan-out wires or second fan-out wires; the first fan-out wires are used for being electrically connected with the N side bonding pads and providing signals for the N multiplexing units; the second fan-out wires are used for being electrically connected with the M side bonding pads and providing signals for the M multiplexing units. According to the invention, one signal line provides signals for a plurality of data signal lines through the multiplexing unit, the number of the signal lines is reduced, and different fan-out lines are adopted to connect the side bonding pads according to different multiplexing requirements of the multiplexing circuit, so that the compatibility design is realized.

Description

Technical Field

[0001] The present invention relates to the field of display, and in particular to a display panel and a display device. Background Art

[0002] A display panel typically includes a display panel and a driver chip. The driver chip has multiple driver units. Each driver unit is connected to the driver circuit of each color sub-pixel of the display panel via a data line. The driver chip drives the display panel to display the image by sending data signals to each data line. This connection method is relatively simple to design. The analysis of the problem of the display panel is also relatively simple. However, due to the large number of data lines, it is not conducive to reducing the frame size, and it also limits the further improvement of the pixel density of the display panel. Therefore, how to reduce the number of data lines, thereby reducing the frame size and improving the pixel density of the display panel has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0003] Embodiments of the present invention provide a display panel and a display device, which reduce the number of signal lines, thereby reducing the size of the frame and improving the pixel density of the display panel.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, which includes: multiple data signal lines, multiple signal routings, and multiple fan-out routings; a multiplexing circuit, including multiple multiplexing units; the input end of the multiplexing unit is connected to the signal routing, and the multiple output ends of the multiplexing unit are respectively connected to the multiple data signal lines in a one-to-one correspondence; multiple side pads, which are connected to the input end of the multiplexing unit through corresponding signal routings; the multiple fan-out routings include a first fan-out routing or a second fan-out routing; the first fan-out routing is used to electrically connect to the corresponding N side pads and provide data signals to the N multiplexing units; the second fan-out routing is used to electrically connect to the corresponding M side pads and provide data signals to the M multiplexing units; wherein M is greater than N, and M is a multiple of N.

[0005] In a second aspect, the present invention provides a display device comprising the display panel of the present invention.

[0006] Compared with the prior art, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0007] The display panel provided by the present invention includes: multiple data signal lines, multiple signal routing lines, multiple fan-out routing lines, a multiplexing circuit, and multiple side pads; the multiplexing circuit includes multiple multiplexing units; the input end of the multiplexing unit is connected to the signal routing line, and the multiple output ends of the multiplexing unit are respectively connected to the multiple data signal lines in a one-to-one correspondence; the side pads are connected to the input end of the multiplexing unit through the corresponding signal routing line; the multiple fan-out routing lines include a first fan-out routing line or a second fan-out routing line; the first fan-out routing line is used to electrically connect to the corresponding N side pads and provide data signals to the N multiplexing units; the second fan-out routing line is used to electrically connect to the corresponding M side pads and provide data signals to the M multiplexing units; wherein M is greater than N and M is a multiple of N. According to an embodiment of the present invention, one signal routing line provides data signals to multiple data signal lines through the multiplexing unit, so there is no need to provide a signal routing line for each data line, thereby reducing the number of signal routing lines. In addition, the side pads are connected to the corresponding multiplexing units through signal routing. For different multiplexing requirements of the multiplexing circuit, N multiplexing units in the multiplexing circuit provide the same data signal, and the N side pads can be connected through the first fan-out routing, so that the first fan-out routing provides data signals to the corresponding N multiplexing units through the N side pads, or M multiplexing units in the multiplexing circuit provide the same data signal, and the M side pads can be connected through the second fan-out routing, so that the second fan-out routing provides data signals to the corresponding M multiplexing units through the M side pads, thereby achieving compatibility design. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Other features, objects and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which like or similar reference numerals designate like or similar features and which are not drawn to scale.

[0009] Figure 1 A schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0010] Figure 2 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0011] Figure 3 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0012] Figure 4 A schematic diagram of a hierarchical structure of a display panel provided by an embodiment of the present invention;

[0013] Figure 5 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0014] Figure 6A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0015] Figure 7 A schematic diagram of an orthographic projection of multiple side pads provided by an embodiment of the present invention;

[0016] Figure 8 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0017] Figure 9 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0018] Figure 10 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The features and exemplary embodiments of various aspects of the present invention will be described in detail below. In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present invention and are not configured to limit the present invention. For those skilled in the art, the present invention can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present invention by illustrating examples of the present invention.

[0020] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0021] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly on the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the component is turned over, the layer or region will be "below" or "beneath" the other layer or region.

[0022] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0023] In the embodiment of the present invention, the term “electrically connected” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.

[0024] In the embodiment of the present invention, the first node, the second node and the third node are only defined for the convenience of describing the circuit structure. The first node, the second node and the third node are not actual circuit units.

[0025] It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the present invention. Therefore, the present invention is intended to cover modifications and variations of the present invention that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the embodiments provided in the embodiments of the present invention may be combined with each other unless there is any contradiction.

[0026] Before describing the technical solutions provided by the embodiments of the present invention, in order to facilitate understanding of the embodiments of the present invention, the present invention first specifically describes the problems existing in the related art:

[0027] A display panel typically includes a display panel and a driver chip. The driver chip has multiple driver units, each of which is connected to the driver circuit of each color sub-pixel of the display panel via a data line. The driver chip drives the display panel to display the image by sending data signals to each data line. This connection method is relatively simple to design. Analyzing the problem of the display panel is also relatively simple. However, due to the large number of data lines, it is not conducive to reducing the size of the bezel and also limits the further improvement of the pixel density of the display panel.

[0028] In view of the above technical problems, embodiments of the present invention provide a display panel and a display device. The embodiments of the present invention will be described below with reference to the accompanying drawings.

[0029] Figure 1 A schematic structural diagram of a display panel provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, the display panel includes: a plurality of data signal lines 11 , a plurality of signal traces 12 , a plurality of fan-out traces 13 , a multiplexing circuit 20 and a plurality of side pads 30 .

[0030] Multiplexing circuit 20 includes multiplexing units 21. The inputs of multiplexing units 21 are connected to signal traces 12. The outputs of multiplexing units 21 are connected one-to-one to multiple data signal lines 11. Side pads 30 are connected to the inputs of multiplexing units 21 via corresponding signal traces 12. Fan-out traces 13 are used to electrically connect to side pads 30 and provide data signals to multiplexing units 21.

[0031] Specifically, the driver chip 40 is connected to each fan-out trace 13 and provides a data signal to the fan-out trace 13. The fan-out trace 13 is electrically connected to the side pad 30, and the side pad 30 is connected to the input end of the multiplexing unit 21 through the corresponding signal trace 12. Therefore, the data signal provided by the fan-out trace 13 is provided to the multiplexing unit 21 through the side pad 30 and the signal trace 12, and then output to the corresponding data signal line 11 by the multiple output ends of the multiplexing unit 21, and provided to the corresponding column of sub-pixels 50 by the data signal line 11. As a result, the present invention realizes that the data signal provided by the fan-out trace 13 can be provided to multiple data signal lines 11 through only one signal trace 12 and the multiplexing unit 21. Compared with the related art in which each data signal line needs to be connected to the corresponding side pad through a signal trace, the present invention reduces the number of signal traces, thereby reducing the frame size, and thus increasing the pixel density of the display panel.

[0032] The multiple fan-out traces include a first fan-out trace or a second fan-out trace; the first fan-out trace is used to electrically connect to the corresponding N side pads and provide data signals to the N multiplexing units; the second fan-out trace is used to electrically connect to the corresponding M side pads and provide data signals to the M multiplexing units; wherein M is greater than N and M is a multiple of N.

[0033] For example, a multiplexing unit has three output terminals, N is 1, and M is 2. The first fan-out trace is used to electrically connect to a corresponding side pad and provide a data signal to one multiplexing unit. The second fan-out trace is used to electrically connect to two corresponding side pads and provide data signals to two multiplexing units.

[0034] As an example, when the multiplexing requirement of the multiplexing circuit is to provide the same data signal to three data signal lines, the plurality of fan-out lines all use the first fan-out line. Figure 2 A structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 2As shown, the first fan-out trace 131 is used to electrically connect to a corresponding side pad 30 and provide a data signal to a multiplexing unit 21. The side pad 30 is connected to the input end of the multiplexing unit 21 through the corresponding signal trace 12. The three output ends of the multiplexing unit 21 are respectively connected to the corresponding data signal lines 11 in a one-to-one correspondence. The data signal lines 11 are connected to the corresponding sub-pixels 50. The data signal provided by the first fan-out trace 131 is provided to the multiplexing unit 21 through the side pad 30 and the signal trace 12. The multiplexing unit 21 then provides the data signal to the corresponding sub-pixels 50 through its three output ends. Therefore, the data signal provided by each first fan-out trace 131 can be provided to three data signal lines 11 through a corresponding multiplexing unit 21, thereby providing data signals to three sub-pixels 50.

[0035] As another example, when the multiplexing requirement of the multiplexing circuit is to provide the same data signal to six data signal lines, the plurality of fan-out lines all use the second fan-out line. Figure 3 A structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 3 As shown, the second fan-out trace 132 is used to electrically connect to the corresponding two side pads 30 and provide data signals to the two multiplexing units 21. The side pads 30 are connected to the input end of the multiplexing unit 21 through the corresponding signal trace 12. The three output ends of the multiplexing unit 21 are respectively connected to the corresponding data signal lines 11 in a one-to-one correspondence. The data signal lines 11 are connected to the corresponding sub-pixels 50. The data signals provided by the second fan-out trace 132 are provided to the two multiplexing units 21 through the two side pads 30 and the corresponding signal trace 12. Each multiplexing unit 21 then provides the data signals to the corresponding sub-pixels 50 through its three output ends. Therefore, the data signals provided by each second fan-out trace 132 can be provided to six data signal lines 11 through the two correspondingly connected multiplexing units 21, thereby providing data signals to the six sub-pixels 50.

[0036] Therefore, the side pads provided by the present invention are connected to the corresponding multiplexing units through signal routing. For different multiplexing requirements of the multiplexing circuit, there are N multiplexing units in the multiplexing circuit providing the same data signal. The N side pads can be connected through the first fan-out routing, so that the first fan-out routing provides data signals to the corresponding N multiplexing units through the N side pads, or there are M multiplexing units in the multiplexing circuit providing the same data signal. The M side pads can be connected through the second fan-out routing, so that the second fan-out routing provides data signals to the corresponding M multiplexing units through the M side pads, thereby achieving compatibility design.

[0037] It should be noted that the multiplexing unit has three output terminals, N is 1, and M is 2 are just examples. The number of output terminals of the multiplexing unit, as well as the specific numbers of N and M can be set according to actual conditions and are not specifically limited here.

[0038] In some embodiments, Figure 4 A schematic diagram of a hierarchical structure of a display panel provided by an embodiment of the present invention is shown in FIG. Figure 4 As shown, the orthographic projection of the fan-out trace 13 at least partially overlaps with the orthographic projection of the corresponding side pad 30 , and the fan-out trace 13 is electrically connected to the corresponding side pad 30 through a via.

[0039] Specifically, the orthographic projection of the fan-out trace 13 at least partially overlaps with the orthographic projection of the corresponding side pad 30 , and a via is provided at the overlapping position so that the fan-out trace 13 can be electrically connected to the corresponding side pad 30 through the via.

[0040] In some embodiments, when the first fan-out trace is adopted, the width of the position where the orthographic projections of the plurality of fan-out traces overlap with the orthographic projections of the side pads is the first width.

[0041] When the second fan-out routing is adopted, the width of the position where the orthographic projections of the plurality of fan-out routings overlap with the orthographic projections of the side pads is the second width.

[0042] The first width is smaller than the second width.

[0043] Exemplarily, the first fan-out trace is connected to N side pads, and the second fan-out trace is connected to M side pads, where N is less than M and M is a multiple of N. Therefore, N and M can be, for example, 1 and 2 or 2 and 4, that is, the first fan-out trace is connected to 1 side pad, and the second fan-out trace is connected to 2 side pads, or the first fan-out trace is connected to 2 side pads, and the second fan-out trace is connected to 4 side pads, etc. It can be seen that the number of side pads connected to the second fan-out trace is always greater than the number of side pads connected to the first fan-out trace. Therefore, it is necessary to set the second width corresponding to the second fan-out trace to be greater than the first width corresponding to the first fan-out trace, so that the number of side pads covered by the second fan-out trace is greater than the number of side pads covered by the first fan-out trace, and vias are provided at the position where the orthographic projection of the first fan-out trace coincides with the orthographic projection of the side pad, and at the position where the orthographic projection of the second fan-out trace coincides with the orthographic projection of the side pad, so that the first fan-out trace and the second fan-out trace can be connected to the side pads covered by each through the vias.

[0044] In some embodiments, see Figure 4One end of the fan-out trace 13 is electrically connected to the side pad 30 on the front side of the display panel 100 , and the other end of the fan-out trace 13 is electrically connected to the driver chip 40 on the back side of the display panel 100 .

[0045] Specifically, the driver chip 40 is disposed on the back side of the display panel 100. The side pads 30 located on the front side of the display panel 100 are connected to the driver chip 40 via fan-out traces 13. This allows the data signals provided by the driver chip 40 to be transmitted to the side pads 30 and then output to the transistors via the data lines and the multiplexing unit, thereby achieving data transmission between the driver chip 40 and the transistors. Furthermore, the driver chip 40 is disposed on the back side of the display panel 100, so that the corresponding connection pads of the driver chip 40 and other signal traces related to the driver chip 40 are all disposed on the back side of the display panel 100. This reduces the number of traces on the front side of the display panel 100, thereby reducing the bezel size of the display panel 100 and increasing the pixel density of the display panel 100.

[0046] In some embodiments, the driving chip is arranged in a binding area on the back side of the display panel, and the binding area includes multiple first pads and multiple second pads; the first pads are used to connect to the corresponding fan-out traces, and the second pads are used to connect to other traces; the pad width of the first pad is greater than the pad width of the second pad.

[0047] Specifically, when using a second fan-out trace or a first fan-out trace, and N is greater than or equal to 2, since both the first fan-out trace and the second fan-out trace are connected to multiple side pads, the first fan-out trace and the second fan-out trace need to simultaneously provide data signals to the multiple side pads during data transmission. In order to provide data signals to the first fan-out trace and the second fan-out trace while ensuring the quality of the data signals, it is necessary to increase the width of the first pad connected to the fan-out trace, thereby improving the ability of the driver chip to transmit data signals outward through the first pad. The second pad is used to connect to other traces. This part of the trace is used to provide a fixed voltage, and the data signal will not change significantly. Therefore, there is no need to enhance the data transmission capacity of the corresponding second pad. The first pad is increased in width to enhance the signal transmission capacity, so the pad width of the first pad is greater than the pad width of the second pad.

[0048] In some embodiments, when the first fan-out line is used and N is greater than or equal to 2, the width of the fan-out line providing the data signal is greater than the width of other signal lines.

[0049] For example, when N is equal to 1, the first fan-out trace is connected to only one side pad, and therefore the first fan-out trace only provides data signals to one side pad. That is, the data signal transmission rate provided by the first fan-out trace to the side pad remains unchanged, and the trace width of the first fan-out trace does not need to be increased. When N is greater than or equal to 2, the number of side pads connected to the first fan-out trace increases, requiring the first fan-out trace to provide data signals to multiple side pads simultaneously. Therefore, to meet the data transmission rate requirement for the first fan-out trace to provide data signals to multiple side pads, the trace width of the first fan-out trace is increased, so that multiple data signals can be transmitted to each side pad while ensuring quality.

[0050] In some embodiments, when the second fan-out line is used, the width of the fan-out line providing the data signal is greater than the width of other signal lines.

[0051] Exemplarily, the second fan-out trace is electrically connected to M corresponding side pads, and M is greater than N, and M is a multiple of N. Therefore, the second fan-out trace connects to at least two side pads. Compared with fan-out traces in conventional technologies, the second fan-out trace connects to more side pads. The second fan-out trace needs to provide data signals to multiple side pads simultaneously. Therefore, in order to meet the data transmission capacity requirement of the second fan-out trace to provide data signals to multiple side pads, the trace width of the second fan-out trace is increased, so that multiple data signals can be transmitted to each side pad while ensuring quality.

[0052] In some embodiments, the first fan-out trace is configured to be electrically connected to a corresponding side pad and to provide a data signal to a multiplexing unit.

[0053] The second fan-out trace is used to be electrically connected to the corresponding two side pads and to provide data signals to the two multiplexing circuits.

[0054] Exemplarily, the side pads are connected to the input end of the multiplexing unit through corresponding signal traces, multiple output ends of the multiplexing unit are connected to corresponding data signal lines one by one, and the data signal traces are connected to corresponding transistors.

[0055] When the first fan-out routing is used, the data signal provided by the first fan-out routing is provided to a multiplexing unit through a side pad and a signal routing. The multiplexing unit then provides the data signal to the corresponding transistors through multiple output terminals. Therefore, the data signal provided by each first fan-out routing can be provided to multiple data signal lines through a correspondingly connected multiplexing unit, thereby providing data signals to multiple transistors.

[0056] When the second fan-out routing is used, the data signal provided by the second fan-out routing is provided to two multiplexing units through two side pads and corresponding signal routings. Each multiplexing unit then provides the data signal to the corresponding transistor through multiple output terminals. Therefore, the data signal provided by each second fan-out routing can be provided to multiple data signal lines through two correspondingly connected multiplexing units, thereby providing data signals to multiple transistors.

[0057] Therefore, for different multiplexing requirements of the multiplexing circuit, the present invention has only one multiplexing unit in the multiplexing circuit providing the same data signal. A side pad can be connected through a first fan-out trace, so that the first fan-out trace provides a data signal to a corresponding multiplexing unit through a side pad. Or, if there are two multiplexing units in the multiplexing circuit providing the same data signal, two side pads can be connected through a second fan-out trace, so that the second fan-out trace provides data signals to the corresponding two multiplexing units through two side pads, thereby achieving a compatible design.

[0058] In some embodiments, when the first fan-out routing is adopted, a third pad is included between at least two adjacent side pads, wherein the third pad is used to connect to other signal lines.

[0059] For example, Figure 5 A structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 5 As shown, when the first fan-out trace 131 is used, a third pad 31 is included between two adjacent side pads 30. The first fan-out trace 131 is electrically connected to only one side pad 30, so adjacent side pads 30 are each connected to a corresponding first fan-out trace 131, and there is a gap between them. A third pad 31 is provided in the gap between adjacent side pads 30. The third pad 31 is used to connect other signal lines, which are led out from the gap, thereby improving the utilization of the space between each side pad 30 and helping to reduce the border size of the display panel.

[0060] When the second fan-out trace is used, a fourth pad is included between at least two adjacent side pads that are not electrically connected to the same second fan-out trace, wherein the fourth pad is used to connect to other signal lines.

[0061] For example, Figure 6 A structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 6As shown, when the second fan-out trace 132 is used, a fourth pad 32 is included between two adjacent side pads 30 that are not electrically connected to the same second fan-out trace 132. The second fan-out trace 132 is electrically connected to two adjacent side pads 30, and every two different adjacent side pads 30 are electrically connected to the second fan-out trace 132. There is a gap between two adjacent side pads 30 that are not electrically connected to the same second fan-out trace 132. The fourth pad 32 is provided in the gap. The fourth pad 32 is used to connect to other signal lines, which are led out from the gap. This improves the utilization rate of the space between the side pads 30, which helps to reduce the bezel size of the display panel.

[0062] In some embodiments, when a second fan-out trace is used, the width of a single fan-out trace is at least greater than the first distance and less than the second distance; wherein the first distance is the minimum width distance that only covers two side pads; and the second distance is the maximum width distance that only covers two side pads.

[0063] Specifically, Figure 7 A schematic diagram of an orthographic projection of multiple side pads provided in an embodiment of the present invention, such as Figure 7 As shown, two adjacent side pads 30 include a first side pad 301, a second side pad 302, a third side pad 303, and a fourth side pad 304, and the fan-out trace is electrically connected to the second side pad 302 and the third side pad 303. The distance between the left edge of the second side pad 302 and the right edge of the third side pad 303 is a first distance L1. When the width of the fan-out trace is the first distance L1, it can cover the distance from the left edge of the second side pad 302 to the right edge of the third side pad 303, that is, the first distance L1 is the minimum width distance that can completely wrap the second side pad 302 and the third side pad 303. The distance between the right side boundary of the first side pad 301 and the left side boundary of the fourth side pad 304 is the second distance L2. When the width of the fan-out trace is the second distance L2, the area between the right side boundary of the first side pad 301 and the left side boundary of the fourth side pad 304 can be covered, so the second side pad 302 and the third side pad 303 can be completely covered, and the first side pad 301 and the fourth side pad 304 will not be covered, that is, the second distance L2 is the maximum width distance that can completely wrap the second side pad 302 and the third side pad 303.

[0064] In some embodiments, Figure 8 A structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 8 As shown, the display panel further includes a first control signal line group 61 and a second control signal line group 62 .

[0065] The multiplexing units 21 include a plurality of first multiplexing units 211 and a plurality of second multiplexing units 212 that are alternately arranged.

[0066] Each control signal line 611 of the first control signal line group 61 is connected in sequence to the control end of the transistor 2111 of the corresponding first multiplexing unit 211; each control signal line 621 of the second control signal line group 62 is connected in sequence to the control end of the transistor 2121 of the corresponding second multiplexing unit 212.

[0067] In the case of adopting the first fan-out routing, the control signal line 611 of the first control signal line group 61 and the corresponding control signal line 621 of the second control signal line group 62 provide control signals simultaneously.

[0068] When the second fan-out routing is adopted, the control signal lines 611 of the first control signal line group 61 and the control signal lines 621 of the second control signal line group 62 provide control signals in a time-sharing manner.

[0069] For example, when using the first fan-out trace, the input end of the first multiplexing unit 211 and the input end of the second multiplexing unit 212 are respectively connected to the side pads 30 via corresponding signal traces, and each side pad 30 is correspondingly connected to a first fan-out trace (not shown in the figure). Each first fan-out trace provides a data signal to the side pad 30, so that the corresponding first multiplexing unit 211 and the second multiplexing unit 212 respectively receive the data signal provided by the corresponding first fan-out trace. After receiving the data signal, the first multiplexing unit 211 and the second multiplexing unit 212 are temporarily closed until the control signal line 611 of the first control signal line group 61 and the corresponding control signal line 621 of the second control signal line group 62 provide a control signal simultaneously. At this time, the transistor 2111 of the first multiplexing unit 211 and the transistor 2121 of the second multiplexing unit 212 are closed, so that the data signal is provided to the subsequent circuit through the closed transistors. When the first fan-out routing is adopted, the control signal lines 611 of the first control signal line group 61 and the control signal lines 621 of the second control signal line group 62 are used to provide control signals to the transistor 2111 of the first multiplexing unit 211 and the transistor 2121 of the second multiplexing unit 212, so that the first multiplexing unit 211 and the second multiplexing unit 212 provide the same data signal.

[0070] When using a second fan-out routing, the input terminals of the first multiplexing unit 211 and the input terminals of the second multiplexing unit 212 are respectively connected to the side pads via corresponding signal routings. Two adjacent side pads are each connected to a second fan-out routing. Each second fan-out routing provides a data signal to the two side pads, so that the corresponding first multiplexing unit 211 and second multiplexing unit 212 receive the data signal provided by the corresponding second fan-out routing. After the first multiplexing unit 211 and the second multiplexing unit 212 receive the data signal, the transistor 2111 of the first multiplexing unit 211 and the transistor 2121 of the second multiplexing unit 212 are temporarily turned off. When the control signal line 611 of the first control signal line group 61 and the corresponding control signal line 621 of the second control signal line group 62 provide control signals in a time-sharing manner, the transistor 2111 of the first multiplexing unit 211 and the transistor 2121 of the second multiplexing unit 212 are turned on in a time-sharing manner, so that the data signal is sequentially provided to the subsequent circuits through the turned-on transistors. When the second fan-out routing is adopted, control signals are provided to the transistor 2111 of the first multiplexing unit 211 and the transistor 2121 of the second multiplexing unit 212 in a time-sharing manner through the control signal lines 611 of the first control signal line group 61 and the control signal lines 621 of the second control signal line group 62, so that the transistor 2111 of the first multiplexing unit 211 and the transistor 2121 of the second multiplexing unit 212 are turned on in a time-sharing manner to provide data signals.

[0071] In some embodiments, Figure 9 A structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 9 As shown, the first control signal line group 61 includes a first control signal line 6111 , a second control signal line 6112 and a third control signal line 6113 ; the second control signal line group 62 includes a fourth control signal line 6211 , a fifth control signal line 6212 and a sixth control signal line 6213 .

[0072] The first multiplexing unit 211 includes a first transistor Q1 , a second transistor Q2 , and a third transistor Q3 ; the second multiplexing unit 212 includes a fourth transistor Q4 , a fifth transistor Q5 , and a sixth transistor Q6 .

[0073] The plurality of signal traces 12 include a first signal trace 121 and a second signal trace 122 .

[0074] The control end of the first transistor Q1 is connected to the first control signal line 6111, the first end of the first transistor Q1 is connected to the first signal routing 121, and the second end of the first transistor Q1 is connected to the first color sub-pixel 51 in the same column through the data signal line 11; the control end of the second transistor Q2 is connected to the second control signal line 6112, the first end of the second transistor Q2 is connected to the first signal routing 121, and the second end of the second transistor Q2 is connected to the second color sub-pixel 52 in the same column through the data signal line 11; the control end of the third transistor Q3 is connected to the third control signal line 6113, the first end of the third transistor Q3 is connected to the first signal routing 121, and the second end of the third transistor Q3 is connected to the third color sub-pixel 53 in the same column through the data signal line 11.

[0075] The control end of the fourth transistor Q4 is connected to the fourth control signal line 6211, the first end of the fourth transistor Q4 is connected to the second signal wiring 122, and the second end of the fourth transistor Q4 is connected to the first color sub-pixel 51 in the same column through the data signal line 11; the control end of the fifth transistor Q5 is connected to the fifth control signal line 6212, the first end of the fifth transistor Q5 is connected to the second signal wiring 122, and the second end of the fifth transistor Q5 is connected to the second color sub-pixel 52 in the same column through the data signal line 11; the control end of the sixth transistor Q6 is connected to the sixth control signal line 6213, the first end of the sixth transistor Q6 is connected to the second signal wiring 122, and the second end of the sixth transistor Q6 is connected to the third color sub-pixel 53 in the same column through the data signal line 11.

[0076] Specifically, each fan-out trace (not shown) provides a data signal to the corresponding side pad 30, and each side pad 30 then provides a data signal to the corresponding first signal trace 121 and second signal trace 122. The first control signal line 6111, the second control signal line 6112, the third control signal line 6113, the fourth control signal line 6211, the fifth control signal line 6212, and the sixth control signal line 6213 can provide control signals in a time-sharing manner, turning on the first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, and the sixth transistor Q6 in a time-sharing manner, and sequentially providing data signals to the corresponding connected sub-pixels, thereby lighting the sub-pixels. It is also possible to make the first control signal line 6111 and the fourth control signal line 6211 provide control signals at the same time, the second control signal line 6112 and the fifth control signal line 6212 provide control signals at the same time, and the third control signal line 6113 and the sixth control signal line 6213 provide control signals at the same time, and the first control signal line 6111 and the fourth control signal line 6211, the second control signal line 6112 and the fifth control signal line 6212, and the third control signal line 6113 and the sixth control signal line 6213 provide control signals in a time-sharing manner, so that the first transistor Q1 and the fourth transistor Q4 are turned on at the same time, the second transistor Q2 and the fifth transistor Q5 are turned on at the same time, and the third transistor Q3 and the sixth transistor Q6 are turned on at the same time, and the first transistor Q1 and the fourth transistor Q4, the second transistor Q2 and the fifth transistor Q5, and the third transistor Q3 and the sixth transistor Q6 are turned on in a time-sharing manner, thereby making the sub-pixels of the same color light up at the same time, and the sub-pixels of different colors light up in a time-sharing manner.

[0077] In some embodiments, when the first fan-out routing is adopted, the first signal routing 121 and the second signal routing 122 are respectively connected to a fan-out routing.

[0078] The first control signal line 6111 and the fourth control signal line 6211 simultaneously provide the first control signal to control the first transistor Q1 and the fourth transistor Q4 to be turned on.

[0079] The second control signal line 6112 and the fifth control signal line 6212 simultaneously provide the second control signal to control the second transistor Q2 and the fifth transistor Q5 to be turned on.

[0080] The third control signal line 6113 and the sixth control signal line 6213 simultaneously provide a third control signal to control the third transistor Q3 and the sixth transistor Q6 to be turned on.

[0081] Specifically, when using a first fan-out routing, the first signal routing 121 and the second signal routing 122 are each connected to a fan-out routing, and each fan-out routing provides a data signal to the first signal routing 121 and the second signal routing 122. The first control signal line 6111 and the fourth control signal line 6211 simultaneously provide a first control signal, the second control signal line 6112 and the fifth control signal line 6212 simultaneously provide a second control signal, and the third control signal line 6113 and the sixth control signal line 6213 simultaneously provide a third control signal. The first, second, and third control signals are provided in a time-sharing manner, causing the first transistor Q1 and the fourth transistor Q4 to be simultaneously turned on, the second transistor Q2 and the fifth transistor Q5 to be simultaneously turned on, and the third transistor Q3 and the sixth transistor Q6 to be simultaneously turned on. Furthermore, the first transistor Q1 and the fourth transistor Q4, the second transistor Q2 and the fifth transistor Q5, and the third transistor Q3 and the sixth transistor Q6 to be turned on in a time-sharing manner, thereby causing sub-pixels of the same color to be illuminated simultaneously, while sub-pixels of different colors to be illuminated in a time-sharing manner.

[0082] In some embodiments, when the second fan-out line is used, the first signal line 121 and the second signal line 122 are connected to the same fan-out line.

[0083] The first control signal line 6111, the second control signal line 6112, the third control signal line 6113, the fourth control signal line 6211, the fifth control signal line 6212 and the sixth control signal line 6213 provide control signals in a time-sharing manner to control the first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5 and the sixth transistor Q6 to be turned on in a time-sharing manner.

[0084] Specifically, when the second fan-out routing is used, the first signal routing 121 and the second signal routing 122 are connected to the same fan-out routing, and the fan-out routing simultaneously provides data signals to the first signal routing 121 and the second signal routing 122. The first control signal line 6111, the second control signal line 6112, the third control signal line 6113, the fourth control signal line 6211, the fifth control signal line 6212, and the sixth control signal line 6213 provide control signals in a time-sharing manner, causing the first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, and the sixth transistor Q6 to be turned on in a time-sharing manner, thereby illuminating each sub-pixel in a time-sharing manner.

[0085] In some embodiments, each color sub-pixel includes a PAM control circuit, a PWM control circuit, and a light-emitting circuit. The PAM control circuit is used to control the current in the light-emitting circuit, and the PWM control circuit is used to control the light-emitting time of the light-emitting circuit.

[0086] The present invention also provides a display device, including the display panel provided by the present invention. Figure 10 , Figure 10 A schematic structural diagram of a display device provided by an embodiment of the present invention. Figure 10 The provided display device 1000 includes the display panel 100 provided by any of the above embodiments of the present invention. Figure 10 The embodiment only uses a mobile phone as an example to illustrate the display device 1000. It is understood that the display device provided by the embodiment of the present invention can be a wearable product, a computer, a television, an in-vehicle display device, or other display device with a display function, and the present invention does not specifically limit this. The display device provided by the embodiment of the present invention has the beneficial effects of the display panel provided by the embodiment of the present invention. For details, please refer to the specific description of the display panel in the above embodiments, and this embodiment will not be repeated here.

[0087] It can be seen from the above embodiments that the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0088] The display panel provided by the present invention includes: multiple data signal lines, multiple signal routing lines, multiple fan-out routing lines, a multiplexing circuit, and multiple side pads; the multiplexing circuit includes multiple multiplexing units; the input end of the multiplexing unit is connected to the signal routing line, and the multiple output ends of the multiplexing unit are respectively connected to the multiple data signal lines in a one-to-one correspondence; the side pads are connected to the input end of the multiplexing unit through the corresponding signal routing line; the multiple fan-out routing lines include a first fan-out routing line or a second fan-out routing line; the first fan-out routing line is used to electrically connect to the corresponding N side pads and provide data signals to the N multiplexing units; the second fan-out routing line is used to electrically connect to the corresponding M side pads and provide data signals to the M multiplexing units; wherein M is greater than N and M is a multiple of N. According to an embodiment of the present invention, one signal routing line provides data signals to multiple data signal lines through the multiplexing unit, so there is no need to provide a signal routing line for each data line, thereby reducing the number of signal routing lines. In addition, the side pads are connected to the corresponding multiplexing units through signal routing. For different multiplexing requirements of the multiplexing circuit, N multiplexing units in the multiplexing circuit provide the same data signal, and the N side pads can be connected through the first fan-out routing, so that the first fan-out routing provides data signals to the corresponding N multiplexing units through the N side pads, or M multiplexing units in the multiplexing circuit provide the same data signal, and the M side pads can be connected through the second fan-out routing, so that the second fan-out routing provides data signals to the corresponding M multiplexing units through the M side pads, thereby achieving compatibility design.

[0089] While the embodiments of the present invention are described above, these embodiments do not necessarily describe all details, nor do they limit this application to the specific embodiments described. Obviously, many modifications and variations are possible based on the above description. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better utilize the present invention and its modifications. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that: include: Multiple data signal lines, multiple signal traces, and multiple fan-out traces; A multiplexing circuit includes a plurality of multiplexing units; an input end of the multiplexing unit is connected to the signal line, and a plurality of output ends of the multiplexing unit are respectively connected to a plurality of data signal lines in a one-to-one correspondence; A plurality of side pads, each of which is connected to an input terminal of the multiplexing unit through a corresponding signal trace; The plurality of fan-out lines include a first fan-out line or a second fan-out line; The first fan-out trace is used to electrically connect to the corresponding N side pads and provide data signals to the N multiplexing units; The second fan-out trace is used to be electrically connected to the corresponding M side pads and to provide data signals to the M multiplexing units; Wherein, M is greater than N, and M is a multiple of N.

2. The display panel according to claim 1, wherein: The orthographic projection of the fan-out trace at least partially overlaps with the orthographic projection of the corresponding side pad, and the fan-out trace is electrically connected to the corresponding side pad through a via.

3. The display panel according to claim 2, wherein: In the case of adopting the first fan-out routing, the width of the position where the orthographic projections of the plurality of fan-out routings overlap with the orthographic projections of the side pads is the first width; In the case of adopting the second fan-out routing, the width of the position where the orthographic projections of the plurality of fan-out routings overlap with the orthographic projections of the side pads is the second width; Wherein, the first width is smaller than the second width.

4. The display panel according to claim 1, wherein: One end of the fan-out line is electrically connected to the side pad on the front side of the display panel, and the other end of the fan-out line is electrically connected to the driving chip on the back side of the display panel.

5. The display panel according to claim 4, wherein: The driver chip is arranged in a binding area on the back side of the display panel, and the binding area includes a plurality of first pads and a plurality of second pads; the first pads are used to connect to corresponding fan-out traces, and the second pads are used to connect to other traces; A pad width of the first pad is greater than a pad width of the second pad.

6. The display panel according to claim 5, wherein: When the first fan-out line is used and N is greater than or equal to 2, the width of the fan-out line providing the data signal is greater than the width of other signal lines.

7. The display panel according to claim 5, wherein: When the second fan-out line is used, the width of the fan-out line providing the data signal is greater than the width of other signal lines.

8. The display panel according to claim 1, wherein: The first fan-out trace is used to be electrically connected to a corresponding one of the side pads and to provide a data signal to a multiplexing unit; The second fan-out trace is used to be electrically connected to the corresponding two side pads and to provide data signals to two multiplexing circuits.

9. The display panel according to claim 8, wherein: In the case of adopting the first fan-out routing, a third pad is included between at least two adjacent side pads; In the case of adopting the second fan-out trace, a fourth pad is included between at least two adjacent side pads that are not electrically connected to the same fan-out trace; The third pad and the fourth pad are both used to connect other signal lines.

10. The display panel according to claim 8, wherein When the second fan-out line is used, the width of a single fan-out line is at least greater than the first distance and smaller than the second distance; The first distance is the minimum width distance covering only the two side pads; the second distance is the maximum width distance covering only the two side pads.

11. The display panel according to claim 8, wherein The display panel further includes a first control signal line group and a second control signal line group; The multiplexing units include a plurality of first multiplexing units and a plurality of second multiplexing units that are alternately arranged; Each control signal line of the first control signal line group is sequentially connected to the control end of the transistor of the corresponding first multiplexing unit; Each control signal line of the second control signal line group is sequentially connected to the control end of the transistor of the corresponding second multiplexing unit; In the case of adopting the first fan-out routing, the control signal line of the first control signal line group and the corresponding control signal line of the second control signal line group provide control signals simultaneously; When the second fan-out routing is adopted, each control signal line of the first control signal line group and each control signal line of the second control signal line group provide control signals in a time-sharing manner.

12. The display panel according to claim 11, wherein: The first control signal line group includes a first control signal line, a second control signal line, and a third control signal line; the second control signal line group includes a fourth control signal line, a fifth control signal line, and a sixth control signal line; The first multiplexing unit includes a first transistor, a second transistor, and a third transistor; the second multiplexing unit includes a fourth transistor, a fifth transistor, and a sixth transistor; The plurality of signal lines include a first signal line and a second signal line; a control terminal of the first transistor connected to the first control signal line, a first terminal of the first transistor connected to the first signal routing line, and a second terminal of the first transistor connected to a first color sub-pixel in the same column via a data signal line; a control terminal of the second transistor connected to the second control signal line, a first terminal of the second transistor connected to the first signal routing line, and a second terminal of the second transistor connected to a second color sub-pixel in the same column via a data signal line; a control terminal of the third transistor connected to the third control signal line, a first terminal of the third transistor connected to the first signal routing line, and a second terminal of the third transistor connected to a third color sub-pixel in the same column via a data signal line; The control end of the fourth transistor is connected to the fourth control signal line, the first end of the fourth transistor is connected to the second signal routing, and the second end of the fourth transistor is connected to the first color sub-pixel in the same column through the data signal line; the control end of the fifth transistor is connected to the fifth control signal line, the first end of the fifth transistor is connected to the second signal routing, and the second end of the fifth transistor is connected to the second color sub-pixel in the same column through the data signal line; the control end of the sixth transistor is connected to the sixth control signal line, the first end of the sixth transistor is connected to the second signal routing, and the second end of the sixth transistor is connected to the third color sub-pixel in the same column through the data signal line.

13. The display panel according to claim 12, wherein: When the first fan-out routing is adopted, the first signal routing and the second signal routing are respectively connected to a fan-out routing; The first control signal line and the fourth control signal line simultaneously provide a first control signal to control the first transistor and the fourth transistor to be turned on; The second control signal line and the fifth control signal line simultaneously provide a second control signal to control the second transistor and the fifth transistor to be turned on; The third control signal line and the sixth control signal line simultaneously provide a third control signal to control the third transistor and the sixth transistor to be turned on.

14. The display panel according to claim 12, wherein: When the second fan-out routing is adopted, the first signal routing and the second signal routing are connected to the same fan-out routing; The first control signal line, the second control signal line, the third control signal line, the fourth control signal line, the fifth control signal line and the sixth control signal line provide control signals in a time-sharing manner to control the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor to be turned on in a time-sharing manner.

15. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 14.

Images