Digital primary and secondary fusion pole-mounted circuit breaker and traveling wave distance measurement time synchronization method thereof

Abstract

The invention discloses a digital primary and secondary fusion pole-mounted circuit breaker and a traveling wave distance measurement time synchronization method thereof. The circuit breaker comprises a feeder terminal and a mutual inductor digitization unit, the feeder terminal is connected with the satellite synchronous clock, and uplink communication connection from the feeder terminal to the mutual inductor digitization unit is achieved between the feeder terminal and the mutual inductor digitization unit through a cable. The feeder terminal periodically and uniformly sends the data frames to the mutual inductor digitization unit based on the second pulse signals, the mutual inductor digitization unit obtains the timestamps synchronous with the second pulse signals based on the received data frames and obtains the traveling wave data with the timestamps, and therefore the accuracy of distance measurement is improved.

Description

Technical Field

[0001] The present invention belongs to the field of power grid fault detection, and in particular relates to a digital primary and secondary fusion pole-mounted circuit breaker, and also relates to a traveling wave ranging and timing method for the digital primary and secondary fusion pole-mounted circuit breaker. Background Art

[0002] Traveling wave ranging (TWL) is a technology that uses the propagation characteristics of traveling wave signals generated by faults on transmission lines to locate faults. Two-terminal ranging is a common TWL method. It involves installing traveling wave acquisition devices at both ends of the line to record the arrival time of the fault traveling wave. Since the propagation speed of traveling wave signals on the transmission line is constant, the fault distance can be calculated using the time difference and the traveling wave propagation speed. The accuracy of two-terminal ranging depends on the time synchronization accuracy of the traveling wave acquisition devices at both ends, making time synchronization a key technology in two-terminal ranging.

[0003] Currently, digital primary / secondary integrated pole-mounted circuit breakers are widely used in distribution networks. They feature traveling wave acquisition capabilities and can be used for two-terminal ranging. These integrated pole-mounted circuit breakers typically consist of an instrument transformer digitization unit (ADMU) and a feeder terminal (FTU). The ADMU, connected to the electronic instrument transformer, converts the power frequency and traveling wave signals into digital signals and transmits the collected power frequency and traveling wave data downlink to the feeder terminal via a cable (typically about 10 meters long). The feeder terminal is connected to a satellite-synchronized clock, enabling it to obtain high-precision pulse-per-second signals for time synchronization. However, because the ADMU is designed to be pluggable to support hot-swap replacement, it cannot directly access the satellite-synchronized clock signal via coaxial cable. Therefore, in practice, the ADMU relies on its internal clock to timestamp the collected traveling wave data before downlinking it to the feeder terminal. The feeder terminal then uploads the timestamped traveling wave data to the master station via GPRS for fault diagnosis. Since the internal clock of the mutual inductor digitization unit is not synchronized with the satellite synchronization clock, the two sets of traveling wave data received by the master station are not based on a unified satellite synchronization clock reference, making it impossible to accurately calculate the time difference, which ultimately affects the accuracy and reliability of dual-end ranging. Summary of the Invention

[0004] The present invention proposes a digital primary-secondary fusion pole-mounted circuit breaker and a traveling wave ranging and timing method thereof, the purpose of which is to solve the problem of inaccurate ranging caused by the traveling wave data obtained by the pole-mounted circuit breaker being unable to synchronize with the satellite synchronous clock.

[0005] The technical solutions of the present invention are as follows:

[0006] A digital primary / secondary integrated pole-mounted circuit breaker includes a feeder terminal and a transformer digitization unit. A cable is used to connect the feeder terminal and the transformer digitization unit to achieve downlink communication from the transformer digitization unit to the feeder terminal. The feeder terminal is connected to a satellite synchronous clock, which is used to provide a second pulse signal.

[0007] The feeder terminal and the mutual inductor digitization unit are also connected via cables to realize an uplink communication connection from the feeder terminal to the mutual inductor digitization unit;

[0008] The feeder terminal periodically and evenly sends data frames to the mutual inductor digitization unit based on the second pulse signal. The mutual inductor digitization unit obtains a timestamp synchronized with the second pulse signal based on the received data frame and obtains traveling wave data with the timestamp.

[0009] As a further improvement of the digital primary and secondary fusion pole-mounted circuit breaker: the feeder terminal includes a frame protocol encoder and a frame timing logic control module;

[0010] The frame protocol encoder is used to encode and send uplink communication data;

[0011] The frame timing logic control module is used to control the frame protocol encoder to perform encoding based on the pulse per second signal and trigger the sending of each data frame.

[0012] As a further improvement of the digital primary-secondary fusion pole-mounted circuit breaker: the feeder terminal also includes a crystal oscillator error elimination module, which obtains correction data D3 based on the second pulse signal, and sends the correction data D3 to the frame timing logic control module to adjust the frame timing, thereby eliminating the error caused by the internal crystal oscillator of the feeder terminal.

[0013] As a further improvement of the digital primary-secondary fusion pole-mounted circuit breaker: the feeder terminal also includes a coding phase adjustment module, which is used to adjust the coding period to achieve phase synchronization between the coding period and the second pulse signal.

[0014] As a further improvement of the digital primary and secondary fusion column mounted circuit breaker: it also includes a second pulse synthesis circuit and a timekeeping module;

[0015] The satellite synchronous clock sends the original pulse-per-second signal PPS to the pulse-per-second synthesis circuit and timekeeping module;

[0016] The timing module performs statistics on the original second pulse signal PPS, obtains the second position change signal PPS_B based on the statistics, and sends the second position change signal PPS_B to the second pulse synthesis circuit;

[0017] The pulse-per-second synthesis circuit obtains the pulse-per-second signal PPS1 based on the original pulse-per-second signal PPS and the second-position change signal PPS_B. When the original pulse-per-second signal PPS is valid, the pulse-per-second signal PPS1 is synchronized with the original pulse-per-second signal PPS, otherwise the pulse-per-second signal PPS1 is synchronized with the second-position change signal PPS_B.

[0018] The pulse-per-second signal PPS1 serves as a reference for encoding and sending by the feeder terminal.

[0019] The present invention also discloses a traveling wave ranging and timing method for a digital primary and secondary fusion pole-mounted circuit breaker. Specifically, in the feeder terminal of the digital primary and secondary fusion pole-mounted circuit breaker:

[0020] The frame timing logic control module performs a countdown of the inter-frame crystal oscillator cycle. After each crystal oscillator cycle, the count value is reduced by 1. When the count value of the inter-frame crystal oscillator cycle countdown becomes 0, a control signal S3 is sent to the frame counter and a control signal S4 is sent to the frame protocol encoder. The initial value of the inter-frame crystal oscillator cycle countdown is reset to start the next countdown. The frame timing logic control module also controls the initial value of the inter-frame crystal oscillator cycle countdown according to the received second pulse signal PPS1.

[0021] The frame counter counts the data frames between adjacent second pulse signals, starting from 0. Every time a control signal S3 is received, the count value is increased by 1, and the current frame count D4 is sent to the frame protocol encoder; the maximum value of the frame count is N f -1, reset to 0 after reaching the maximum value, N f is the number of data frames between adjacent preset second pulse signals;

[0022] The frame protocol encoder completes encoding of the data frame according to the frame count D4 and triggers sending of the data frame according to the control signal S4.

[0023] As a further improvement of the traveling wave ranging and timing method of the digital primary and secondary fusion column mounted circuit breaker: the frame counter also sends the frame count D4 to the frame timing logic control module;

[0024] When the frame timing logic control module receives the second pulse signal PPS1, it adjusts the initial value of the inter-frame crystal oscillator cycle countdown according to the current frame count and the count value of the inter-frame crystal oscillator cycle countdown, changes the sending rhythm of the data frame, and makes the sending time of the 0th frame close to the arrival time of the second pulse signal PPS1, ensuring that the frame timing is synchronized with the second pulse signal PPS1.

[0025] As a further improvement of the traveling wave ranging and timing method of the digital primary and secondary fusion column mounted circuit breaker: a crystal oscillator error elimination module is further provided in the feeder terminal;

[0026] The crystal oscillator error elimination module receives the pulse-per-second signal PPS1 and counts the number of local clock crystal oscillator cycles between adjacent pulse-per-second signals PPS1 to obtain a statistical value of the number of crystal oscillator cycles per second, then calculates the crystal oscillator error cycle number a = the statistical value of the number of crystal oscillator cycles per second - the theoretical value of the number of crystal oscillator cycles per second, and sends the crystal oscillator error cycle number a as the correction data D3 to the frame timing logic control module; the theoretical value of the number of crystal oscillator cycles per second refers to the number of crystal oscillator cycles corresponding to 1 second calculated based on the theoretical value of the local crystal oscillator cycle of the feeder terminal;

[0027] The frame timing logic control module adjusts the initial value of the inter-frame crystal oscillator period countdown based on the crystal oscillator error period number a: select a data frames from other data frames except frame 0 to adjust the initial value of the inter-frame crystal oscillator period countdown; if a is greater than zero, the initial value of the inter-frame crystal oscillator period countdown corresponding to each selected data frame is added by 1 on the basis of the original initial value, otherwise it is subtracted by 1.

[0028] As a further improvement of the traveling wave ranging and timing method of the digital primary and secondary fusion column mounted circuit breaker: the frame protocol encoder is further provided with a coding phase adjustment module;

[0029] After receiving the pulse-second signal PPS1, the coding phase adjustment module waits for a fixed time and then controls the frame protocol encoder to send the 0th frame. At the same time, within this fixed time, the coding phase adjustment module adjusts the coding period according to the phase relationship between the coding period and the pulse-second signal, thereby completing the phase synchronization between the coding period and the pulse-second signal without changing the number of coding periods within the fixed time.

[0030] In the frame protocol encoder, when the control signal S4 is received, it is determined whether the current frame count is 0. If it is 0, the current 0th frame is sent at the end of the fixed time length. Otherwise, the current data frame is sent directly under the triggering of the control signal S4.

[0031] As a further improvement to the traveling wave ranging and timing method of the digital primary and secondary fusion pole-mounted circuit breaker, the encoding phase adjustment module adjusts the encoding period in the following manner within a fixed time length:

[0032] The fixed waiting time is defined as M crystal oscillator cycles, which correspond to P coding cycles. After the second pulse signal PPS1 arrives, the number of crystal oscillator cycles N between the falling edge of the second pulse signal PPS1 and the next rising edge of the coding pulse is obtained, and then PN coding cycles are selected from the P-1 coding cycles from the rising edge to the end of the fixed waiting time, and the number of crystal oscillator cycles corresponding to each selected coding cycle is increased by 1.

[0033] Compared with the prior art, the present invention has the following positive effects:

[0034] 1. The present invention establishes an uplink communication connection from the feeder terminal FTU to the mutual inductor digitization unit ADMU. The feeder terminal sends data frames to the mutual inductor digitization unit periodically and uniformly based on the second pulse signal of the satellite synchronous clock, so that the mutual inductor digitization unit obtains a precise timestamp synchronized with the second pulse signal and adds the timestamp to the traveling wave data, thereby improving the accuracy of ranging.

[0035] 2. The present invention performs timekeeping based on the second pulse of the satellite synchronous clock in the feeder terminal and synthesizes the second pulse signal PPS1. When the satellite synchronous clock signal is lost, the timekeeping module can be used to ensure the normal transmission of data frames to avoid communication interruption.

[0036] 3. The present invention counts the actual number of crystal oscillator cycles between adjacent second pulse signals, calculates the difference between the statistical value and the theoretical value, and selects some data frames to adjust the initial value of the inter-frame crystal oscillator cycle countdown, thereby eliminating the impact of the crystal oscillator cumulative error and enabling the feeder terminal to accurately complete the transmission of a specified number of data frames between two second pulse signals.

[0037] 4. When the frame timing is not synchronized with the pulse-per-second signal, the present invention can dynamically adjust the initial value of the inter-frame crystal oscillator period countdown, adaptively change the sending rhythm of the data frame, and achieve synchronization between the frame timing and the pulse-per-second signal.

[0038] 5. When triggering the transmission of frame 0 based on a pulse-second signal, the present invention delays the transmission of frame 0 by waiting for a fixed duration. During this fixed waiting period, the coding period is adjusted based on the phase difference between the coding period and the pulse-second signal. This ensures that the phase of the coding period is consistent at the end of the waiting period without changing the number of coding periods within the fixed waiting period, thus achieving phase synchronization between the coding period and the pulse-second signal. This approach not only resolves the problem of communication frame loss caused by phase difference, but also, because both devices simultaneously delay for an equal fixed duration, prevents ranging errors caused by the introduction of delays. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a schematic diagram of the architecture of a digital primary / secondary fusion pole-mounted circuit breaker;

[0040] Figure 2 The corresponding relationship between the second pulse, coding pulse and clock crystal pulse when the second pulse signal arrives;

[0041] Figure 3 Schematic diagram of the downlink data encoding structure. DETAILED DESCRIPTION

[0042] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the embodiments described are only a part of the embodiments of the present invention, rather than all the embodiments.

[0043] Example 1

[0044] This embodiment discloses a digital primary-secondary fusion pole-mounted circuit breaker and a traveling wave ranging and timing method thereof.

[0045] like Figure 1 The digital primary-secondary integrated pole-mounted circuit breaker in this embodiment includes a feeder terminal and a mutual inductor digitization unit.

[0046] The feeder terminal is connected to a satellite synchronous clock, and the satellite synchronous clock is used to provide a second pulse signal.

[0047] A cable is used between the feeder terminal and the mutual inductor digitization unit to realize a downlink communication connection from the mutual inductor digitization unit to the feeder terminal. A cable is also used between the feeder terminal and the mutual inductor digitization unit to realize an uplink communication connection from the feeder terminal to the mutual inductor digitization unit.

[0048] The feeder terminal periodically and evenly sends data frames based on the pulse-second signal to the transformer digitization unit. The transformer digitization unit obtains a time stamp synchronized with the pulse-second signal based on the received data frame and sends the traveling wave data with the time stamp to the feeder terminal via the downlink communication connection.

[0049] For digital primary / secondary integrated circuit breakers, which are part of the State Grid standard, only the digital transformer unit with traveling wave fault location functionality needs to be replaced, leaving the rest of the hardware unchanged. This is possible thanks to the fact that the original digital solution standardization document includes a 2-core cable reserve in the 10-core cable, allowing for uplink communication from the feeder terminal to the digital transformer unit.

[0050] The uplink communication adopts a serial communication mode, the link layer adopts (but is not limited to) the FT3 format, and uses the Manchester encoding mode (it can also be other encoding modes).

[0051] The feeder terminal includes a pulse-per-second synthesis circuit and a timing module. Upon receiving the pulse-per-second signal, the feeder terminal first performs filtering and de-jittering to prevent multiple triggering within a single second. The resulting raw pulse-per-second signal (PPS) is then sent to the pulse-per-second synthesis circuit and the timing module. The timing module performs statistics on the raw pulse-per-second signal (PPS), deriving a position-shifting signal (PPS_B) based on the statistics, and then sends PPS_B to the pulse-per-second synthesis circuit. The pulse-per-second synthesis circuit derives a pulse-per-second signal (PPS1) based on the raw pulse-per-second signal (PPS) and the position-shifting signal (PPS_B). When the raw pulse-per-second signal (PPS) is valid, PPS1 is synchronized with the raw pulse-per-second signal (PPS); otherwise, PPS1 is synchronized with the position-shifting signal (PPS_B). This mechanism ensures that PPS1 can still be transmitted even if the raw pulse-per-second signal (PPS) is lost, providing a time reference for encoding and transmission at the feeder terminal.

[0052] Furthermore, the feeder terminal includes a frame protocol encoder and a frame timing logic control module. The frame protocol encoder is used to encode and send uplink communication data. The frame timing logic control module is used to control the frame protocol encoder to encode and trigger the sending of each data frame based on the pulse per second signal.

[0053] Specifically, the frame timing logic control module performs a countdown of the inter-frame crystal oscillator cycle. After each crystal oscillator cycle, the count value is reduced by 1. When the count value of the inter-frame crystal oscillator cycle countdown becomes 0, a control signal S3 is sent to the frame counter, a control signal S4 is sent to the frame protocol encoder, and the initial value of the inter-frame crystal oscillator cycle countdown is reset to start the next countdown.

[0054] The default value of the inter-frame crystal oscillator cycle countdown initial value is the inter-frame crystal oscillator cycle theoretical value cyclecnt_0. The inter-frame crystal oscillator cycle theoretical value refers to the crystal oscillator cycle number corresponding to the time interval between adjacent data frames, that is, cyclecnt_0=T / N f T is the theoretical value of the number of crystal oscillator cycles corresponding to 1 second, N f The number of data frames between two adjacent second pulse signals is preset. In this embodiment, the FTU local crystal oscillator frequency is 160MHz, the crystal oscillator period is 6.25ns, and the theoretical value of the number of crystal oscillator periods per second is T=1.6*10^8. The number of data frames between each two second pulses is N. f =8000, so the theoretical value of the inter-frame crystal oscillator cycle count, cyclecnt_0, is 2*10^4. That is, the theoretical interval between two data frames is 20,000 crystal oscillator cycles, with a duration of 125us. The initial value of the inter-frame crystal oscillator cycle countdown is adjustable, and the initial value corresponding to each frame can be adjusted independently.

[0055] The frame counter counts the data frames between adjacent second pulse signals, starting from 0. Every time a control signal S3 is received, the count value is increased by 1, and the current frame count D4 is sent to the frame protocol encoder. The maximum value of the frame count is N f -1, reset to 0 after reaching the maximum value.

[0056] The frame protocol encoder completes the encoding of the data frame according to the frame count D4, and at the same time obtains the check code D2 through the check code generator and adds it to the data frame, and triggers the transmission of the data frame according to the control signal S4. Figure 1 The signal S1 in .

[0057] Furthermore, when the satellite synchronous clock is first connected or the satellite synchronous clock signal is restored after being lost, the frame count may not be synchronized with the second pulse signal of the satellite synchronous clock, that is, the Nth frame may not have been sent yet. f -1 data frame. Forced synchronization would result in frame loss. To address this issue, the frame timing logic control module in this embodiment also controls the initial value of the inter-frame crystal oscillator period countdown based on the received pulse-per-second signal PPS1, thereby changing the data frame transmission rhythm and ensuring that the frame timing is always synchronized with the pulse-per-second signal PPS1.

[0058] Specifically, the frame counter also sends the frame count D4 to the frame timing logic control module. When the frame timing logic control module receives the pulse per second signal PPS1, it reads the current frame count SmpCnt (i.e., D4) and the count value cyclecnt of the inter-frame crystal oscillator cycle countdown, and then performs the following processing:

[0059] (1) If the current frame count SmpCnt is equal to N f -1, and the count value cyclecnt is less than the first threshold, it is determined that the frame timing is synchronized with the pulse per second signal PPS1.

[0060] In this embodiment, the first threshold is 8000.

[0061] (2) If the current frame count SmpCnt is equal to N f -1, and the count value cyclecnt is greater than or equal to the first threshold and less than the second threshold, the initial value of the inter-frame crystal oscillator cycle countdown is adjusted to last_init-1, and last_init is the initial value of the inter-frame crystal oscillator cycle countdown before adjustment.

[0062] In this embodiment, the second threshold is 16000.

[0063] (3) If the current frame count SmpCnt is equal to N f-1, and the count value cyclecnt is greater than or equal to the second threshold, the initial value of the crystal oscillator cycle countdown between all frames is adjusted to last_init-cyclecnt / N f .

[0064] (4) If the current frame count SmpCnt is not equal to N f When -1, the initial value of the inter-frame crystal oscillator period countdown is adjusted in different ways according to the numerical range of the frame count SmpCnt:

[0065] In this embodiment, N f =8000, the theoretical value of the crystal oscillator cycle number between frames cyclecnt_0=20000, then the division of the value range and the corresponding adjustment method are as follows:

[0066] (4.1) If SmpCnt is greater than or equal to 1 and less than 2400, the initial value of the crystal oscillator period countdown between all frames is adjusted to last_init+SmpCnt*20000 / 8000.

[0067] (4.2) If SmpCnt is greater than or equal to 2400 and less than 4000, the initial value of the crystal oscillator period countdown between all frames is adjusted to last_init+6000.

[0068] (4.3) If SmpCnt is greater than or equal to 4000 and less than 5600, the initial value of the crystal oscillator period countdown between all frames is adjusted to last_init-6000.

[0069] (4.4) If SmpCnt is greater than or equal to 5600 and less than 7998, adjust the initial value of the crystal oscillator period countdown between all frames to last_init-SmpCnt*20000 / 8000.

[0070] (4.5) If SmpCnt is equal to 0 and cyclecnt is less than or equal to 12000, the initial value of the crystal oscillator cycle countdown between all frames is adjusted to last_init + (19999 - cyclecnt) / 8000.

[0071] (4.6) If SmpCnt is equal to 0 and cyclecnt is greater than 12000 and less than or equal to 18000, the initial value of the crystal oscillator cycle countdown between all frames is adjusted to last_init+1.

[0072] (4.7) If SmpCnt is equal to 0 and cyclecnt is greater than 18000, only the last data frame (Nth fThe initial value of the inter-frame crystal oscillator cycle countdown (-1 frame) is adjusted to 19999-cyclecnt.

[0073] This adjustment method dynamically adjusts the initial value of the inter-frame crystal oscillator cycle countdown when the frame timing is out of sync with the pulse-per-second signal (PPS1). Although the initial value of the inter-frame crystal oscillator cycle countdown will fluctuate during this process, the data frame transmission rhythm will also change accordingly. Ultimately, by adjusting the algorithm's adaptive capabilities, the initial value of the inter-frame crystal oscillator cycle countdown will gradually approach and equal the theoretical value of the inter-frame crystal oscillator cycle, maintaining synchronization between the frame timing and the pulse-per-second signal.

[0074] Furthermore, the feeder terminal usually uses a common temperature-compensated crystal oscillator. Unlike expensive constant-temperature crystal oscillators and other complex clock circuits, the temperature-compensated crystal oscillator clock has a certain error, resulting in the data frame being triggered by the inter-frame crystal oscillator cycle countdown, and the N second pulse signal cannot be accurately completed between two second pulse signals. f Therefore, it is necessary to correct the error caused by the crystal oscillator.

[0075] The correction method is as follows: a crystal oscillator error elimination module is also provided in the feeder terminal, which obtains correction data D3 based on the second pulse signal, and sends the correction data D3 to the frame timing logic control module to adjust the frame timing, thereby eliminating the error caused by the internal crystal oscillator of the feeder terminal.

[0076] The specific process is:

[0077] The crystal oscillator error elimination module receives the pulse-per-second signal PPS1 and counts the number of local clock crystal oscillator cycles between adjacent pulse-per-second signals PPS1 to obtain a statistical value of the number of crystal oscillator cycles per second. The module then calculates the crystal oscillator error cycle number a = the statistical value of the number of crystal oscillator cycles per second minus the theoretical value of the number of crystal oscillator cycles per second. The crystal oscillator error cycle number a is sent as correction data D3 to the frame timing logic control module. The theoretical value of the number of crystal oscillator cycles per second refers to the number of crystal oscillator cycles corresponding to one second, calculated based on the theoretical value of the local crystal oscillator cycle at the feeder terminal.

[0078] The frame timing logic control module adjusts the initial value of the inter-frame crystal oscillator period countdown based on the crystal oscillator error period number a: select a data frames from other data frames except frame 0 to adjust the initial value of the inter-frame crystal oscillator period countdown; if a is greater than zero, the initial value of the inter-frame crystal oscillator period countdown corresponding to each selected data frame is added by 1 on the basis of the original initial value, otherwise it is subtracted by 1.

[0079] In this embodiment, the method of selecting the a data frames is: calculating N f / a is rounded to get b, and then N outside the 0th frame between the second pulse signals f-1 data frame, select the 1*bth, 2*bth, ... a*bth data frames for adjustment.

[0080] It should be noted that through theoretical calculation and derivation, it is found that the crystal oscillator error period number a must be less than N f Because if a=N f =8000, then the deviation between the crystal oscillator and the second pulse = 8000*6.25ns=50uS, which is much larger than the error range of the crystal oscillator.

[0081] Through the above correction method, the dynamic adjustment of the initial value of the inter-frame crystal oscillator period countdown can be achieved, so that the feeder terminal can accurately complete N seconds between two second pulse signals. f The sending of data frames.

[0082] Furthermore, the arrival time of the second pulse has a certain degree of randomness, and the coding period of the data frame corresponds to multiple crystal oscillator periods of the feeder terminal. In this embodiment, the coding rate is 10MHz and the coding period is 100ns, corresponding to 16 crystal oscillator periods of 6.25ns. For the convenience of description, the number of crystal oscillator periods corresponding to one coding period is set to Z. Therefore, there are Z phase relationships between the second pulse signal PPS1 and the coding period, and the maximum phase difference is Z-1 crystal oscillator periods. In the case of synchronization, since the arrival of the second pulse needs to immediately trigger the frame protocol encoder to send the 0th frame, a large phase difference means that the previous coding period has not yet ended. Forced termination will lead to an increase in the frame loss rate and even cause decoding errors in the subsequent stage; if the 0th frame is sent after the end of this coding period, there will be a random error between the second pulse and the 0th frame, which will cause the subsequent digitization unit to be unable to obtain a synchronous clock signal.

[0083] To this end, the feeder terminal of this embodiment further includes a coding phase adjustment module, which is used to adjust the coding period to achieve phase synchronization between the coding period and the pulse per second signal.

[0084] After receiving the pulse-second signal PPS1, the coding phase adjustment module waits for a fixed time before controlling the frame protocol encoder to send frame 0. At the same time, within this fixed time, the coding phase adjustment module adjusts the coding period according to the phase relationship between the coding period and the pulse-second signal, thereby completing the phase synchronization between the coding period and the pulse-second signal without changing the number of coding periods within the fixed time:

[0085] like Figure 2Define the fixed waiting time as M crystal oscillator cycles, which corresponds to P encoding cycles. Since the end of the data frame is idle, all encoding cycles corresponding to the pulse-per-second signal are rising edges. After the pulse-per-second signal arrives, calculate the number of crystal oscillator cycles N between the falling edge of the pulse-per-second signal and the next rising edge of the encoding pulse. One encoding cycle corresponds to one encoding pulse. Then, select PN encoding cycles from the P-1 encoding cycles between the rising edge and the end of the fixed waiting time. The number of crystal oscillator cycles corresponding to each selected encoding cycle is incremented by 1.

[0086] In this embodiment, the fixed waiting time is 1600ns, so M = 256. This fixed waiting time corresponds to 16 coding cycles (coding pulses), and one coding cycle of 100ns corresponds to 16 crystal oscillator cycles. After the arrival of the pulse-per-second signal, the number of crystal oscillator cycles (N) between the falling edge of the pulse-per-second signal and the next rising edge of the coding pulse is obtained. Then, the first 15-N coding cycles are selected from the 15 coding cycles from the rising edge to the end of the fixed waiting time (that is, 1600ns after the falling edge of the pulse-per-second signal). The number of crystal oscillator cycles corresponding to each selected coding cycle is incremented by 1. After adjustment, the duration from the falling edge of the second pulse signal to the rising edge of the first subsequent encoding pulse is N*6.25ns, and the duration of the subsequent 15 encoding cycles is 15*16*6.25ns+(15-N)*6.25ns. Therefore, no matter what the value of N is, the total fixed duration must be 16*16*6.25ns=1600ns. That is, the frame protocol encoder advances the encoding pulse by adding N crystal oscillator cycles, thereby compensating for the phase difference of N crystal oscillator cycles between the second pulse and the encoding cycle, so that the phase of the encoding cycle is adjusted, and the phase synchronization between the second pulse signal and the encoding cycle is achieved, thereby ensuring that the 0th frame and the second pulse signal are strictly synchronized each time, so that the serial data sequence S1 contains synchronous clock information.

[0087] Correspondingly, in the frame protocol encoder, when the control signal S4 is received, it is determined whether the current frame count is 0. If it is 0, the current 0th frame is sent at the end of the fixed time length; otherwise, the current data frame is sent directly under the triggering of the control signal S4.

[0088] It's important to note that because both devices in the dual-end ranging system delay the same fixed duration, this delay does not cause ranging errors. Furthermore, when the mutual inductor digitization unit subsequently adds the timestamp, it compensates for the zeroth frame based on this preset fixed duration, ensuring that the timestamp is synchronized with the arrival of the pulse-per-second signal.

[0089] In addition, the communication data processor can also add the data D1 sent by the maintenance interface to the uplink communication data to implement operations such as upgrade and maintenance.

[0090] like Figure 1 After the transformer digitization unit receives signal S1, the frame decoding circuit decodes signal S1 to generate synchronization signal S10, which is then sent to the programmable logic device, frame protocol encoder, and frame protocol decoding simulator. If the frame protocol decoding simulator does not receive synchronization signal S10 within a certain period of time, it will generate a pseudo-synchronization signal S20 and send it to the frame decoding circuit, thereby forcibly triggering the generation of synchronization signal S10 and avoiding affecting the normal operation of the transformer digitization unit.

[0091] The current and voltage signals collected by the current transformer and voltage transformer are simultaneously sent to the analog-to-digital converter. The analog-to-digital converter sends the converted current and voltage digital signal D5 to the frame protocol encoder. Simultaneously, the state quantity acquisition circuit sends the collected state quantity data D7 to the frame protocol encoder. The frame protocol encoder also derives power frequency voltage data D13 from the current and voltage digital signal D5 and sends it to the programmable logic device.

[0092] The current and voltage signals collected by the current and voltage transformers are simultaneously sent to a high-speed analog-to-digital converter (A / D converter). The A / D converter then transmits the converted high-speed digital current and voltage signal D11 to a programmable logic device (PLD). The PLD generates data D10 based on the current and voltage high-speed digital signal D11 and the power frequency voltage data D13, and transmits this data to a microprocessor. The PLD also generates a pulse-per-second signal (PPS4) based on synchronization signal S10 and transmits it to the microprocessor in the transformer digitization unit (PPS3, generated by a frame protocol decoder, can also be used instead).

[0093] The microprocessor of the transformer digitization unit uses a grounding algorithm based on data D10 to determine whether a ground fault has occurred. This algorithm is conventional and will not be described in detail here. If a ground fault has occurred, a fault occurrence timestamp D21 is obtained based on the pulse per second signal PPS4 and sent to the programmable logic device.

[0094] The programmable logic device intercepts the current and voltage high-speed data corresponding to the fault occurrence timestamp D21 from the high-speed data cache, then encapsulates the timestamp and the corresponding current and voltage high-speed data into data D6, and sends the data D6 to the frame protocol encoder.

[0095] When the programmable logic device is working, it interacts with the high-speed data cache by sending and receiving data D14 to improve the processing speed.

[0096] The frame protocol encoder takes the current and voltage digital signal D5 as the power frequency data and the data D6 as the traveling wave data, and adds them together with the state quantity data D7 to the downlink communication data signal S2 and sends them to the feeder terminal.

[0097] like Figure 3 Based on FT3 format encoding, this embodiment places traveling wave data after the power frequency data in an extended frame format. The frame format of the traveling wave data is the same as that of the power frequency data. Based on relevant specifications and data length calculations, it is known that while retaining 20 free bits, four more valid data sets can be added to the original four sets of power frequency data for transmitting traveling wave data. This significantly improves the transmission rate compared to transmission using other protocols.

[0098] The microprocessor of the mutual inductor digitization unit may also send relevant data D20 of the fault judgment to the master station through the communication module of the mutual inductor digitization unit.

[0099] After receiving signal S2, the feeder terminal obtains power frequency data D5, traveling wave data D6, state quantity data D7, and synchronization signal PPS2 from it, and then sends them to the microprocessor of the feeder terminal. The microprocessor of the feeder terminal encapsulates the relevant data into data D8 and sends it to the master station through the communication module of the feeder terminal.

[0100] Meanwhile, during the maintenance operation, the microprocessor of the feeder terminal may also encapsulate maintenance-related data into data D30 and send the data to the maintenance interface via the communication data processor.

[0101] Example 2

[0102] This embodiment differs from the first embodiment in that, after receiving the pulse-per-second signal PPS1, the frame timing logic controller calculates the time difference between the pulse-per-second signal and the current frame header, and corrects the time difference within the next 1 second to ensure that the feeder terminal is sending an idle bit when the next pulse-per-second signal arrives. At this time, the feeder terminal can directly send frame 0 to achieve synchronization with the transformer digitization unit. This method can also achieve synchronization between the pulse-per-second signal and frame 0, but there will be a frame loss problem. To solve this problem, it is necessary to add a flag bit to the synchronized frame 0 to notify the transformer digitization unit that the frame count change at this position is normal.

[0103] Example 3

[0104] This embodiment differs from the first embodiment in that the feeder terminal lacks a crystal oscillator error elimination module and does not correct errors generated by the crystal oscillator. The transformer digitization unit obtains a pulse-per-second signal from frame 0 of signal S1. Then, based on the same crystal oscillator error elimination principle as in the first embodiment, it eliminates errors generated by its local clock, generating a more accurate synchronization signal and using it to determine the timestamp.

[0105] Other implementations

[0106] After receiving signal S1, the transformer digitization unit can obtain a corresponding synchronization signal for each data frame, and thus, based on this synchronization signal, a timestamp synchronized with the pulse-per-second signal PPS1 can be obtained. Obviously, the use of this timestamp is not limited to the above embodiment. Those skilled in the art can also use other methods to include the synchronization signal in fault diagnosis and downlink data transmission, ensuring that the relevant data is accompanied by synchronized time information.

[0107] It should be noted that it will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. The scope of the present invention is defined by the claims rather than the foregoing description.

Claims

1. A digital primary / secondary integrated pole-mounted circuit breaker, comprising a feeder terminal and a transformer digitization unit, wherein a cable is used to connect the feeder terminal and the transformer digitization unit to achieve a downlink communication connection from the transformer digitization unit to the feeder terminal, characterized in that: The feeder terminal is connected to a satellite synchronous clock, and the satellite synchronous clock is used to provide a second pulse signal; The feeder terminal and the mutual inductor digitization unit are also connected via cables to realize an uplink communication connection from the feeder terminal to the mutual inductor digitization unit; The feeder terminal periodically and evenly sends data frames to the mutual inductor digitization unit based on the second pulse signal. The mutual inductor digitization unit obtains a timestamp synchronized with the second pulse signal based on the received data frame and obtains traveling wave data with the timestamp.

2. The digital primary / secondary fusion pole mounted circuit breaker according to claim 1, characterized in that: The feeder terminal includes a frame protocol encoder and a frame timing logic control module; The frame protocol encoder is used to encode and send uplink communication data; The frame timing logic control module is used to control the frame protocol encoder to perform encoding and trigger the sending of each data frame based on the second pulse signal.

3. The digital primary and secondary fusion pole mounted circuit breaker according to claim 2, characterized in that: The feeder terminal also includes a crystal oscillator error elimination module, which obtains correction data D3 based on the second pulse signal and sends the correction data D3 to the frame timing logic control module to adjust the frame timing to eliminate the error caused by the internal crystal oscillator of the feeder terminal.

4. The digital primary / secondary fusion pole mounted circuit breaker according to claim 2, characterized in that: The feeder terminal further comprises a coding phase adjustment module, which is used to adjust the coding period to achieve phase synchronization between the coding period and the pulse per second signal.

5. The digital primary and secondary fusion pole mounted circuit breaker according to claim 2, characterized in that: It also includes a second pulse synthesis circuit and a timekeeping module; The satellite synchronous clock sends the original pulse-per-second signal PPS to the pulse-per-second synthesis circuit and timekeeping module; The timing module performs statistics on the original second pulse signal PPS, obtains the second position change signal PPS_B based on the statistics, and sends the second position change signal PPS_B to the second pulse synthesis circuit; The pulse-per-second synthesis circuit obtains the pulse-per-second signal PPS1 based on the original pulse-per-second signal PPS and the second-position change signal PPS_B. When the original pulse-per-second signal PPS is valid, the pulse-per-second signal PPS1 is synchronized with the original pulse-per-second signal PPS, otherwise the pulse-per-second signal PPS1 is synchronized with the second-position change signal PPS_B. The pulse-per-second signal PPS1 serves as a reference for encoding and sending by the feeder terminal.

6. A traveling wave ranging and timing method for a digital primary and secondary fusion pole-mounted circuit breaker, characterized in that: In the feeder terminal of the digital primary and secondary fusion pole-mounted circuit breaker: The frame timing logic control module performs a countdown of the inter-frame crystal oscillator cycle. After each crystal oscillator cycle, the count value is reduced by 1. When the count value of the inter-frame crystal oscillator cycle countdown becomes 0, a control signal S3 is sent to the frame counter and a control signal S4 is sent to the frame protocol encoder. The initial value of the inter-frame crystal oscillator cycle countdown is reset to start the next countdown. The frame timing logic control module also controls the initial value of the inter-frame crystal oscillator cycle countdown according to the received second pulse signal PPS1. The frame counter counts the data frames between adjacent second pulse signals, starting from 0. Every time a control signal S3 is received, the count value is increased by 1, and the current frame count D4 is sent to the frame protocol encoder; the maximum value of the frame count is N f -1, reset to 0 after reaching the maximum value, N f is the number of data frames between adjacent preset second pulse signals; The frame protocol encoder completes encoding of the data frame according to the frame count D4 and triggers sending of the data frame according to the control signal S4.

7. The traveling wave ranging and timing method for a digital primary / secondary integrated pole-mounted circuit breaker according to claim 6 is characterized in that: The frame counter also sends the frame count D4 to the frame timing logic control module; When the frame timing logic control module receives the second pulse signal PPS1, it adjusts the initial value of the inter-frame crystal oscillator cycle countdown according to the current frame count and the count value of the inter-frame crystal oscillator cycle countdown, changes the sending rhythm of the data frame, and makes the sending time of the 0th frame close to the arrival time of the second pulse signal PPS1, ensuring that the frame timing is synchronized with the second pulse signal PPS1.

8. The traveling wave ranging and timing method for a digital primary / secondary integrated pole-mounted circuit breaker according to claim 6 is characterized in that: A crystal oscillator error elimination module is also provided in the feeder terminal; The crystal oscillator error elimination module receives the pulse-per-second signal PPS1 and counts the number of local clock crystal oscillator cycles between adjacent pulse-per-second signals PPS1 to obtain a statistical value of the number of crystal oscillator cycles per second, then calculates the crystal oscillator error cycle number a = the statistical value of the number of crystal oscillator cycles per second - the theoretical value of the number of crystal oscillator cycles per second, and sends the crystal oscillator error cycle number a as the correction data D3 to the frame timing logic control module; the theoretical value of the number of crystal oscillator cycles per second refers to the number of crystal oscillator cycles corresponding to 1 second calculated based on the theoretical value of the local crystal oscillator cycle of the feeder terminal; The frame timing logic control module adjusts the initial value of the inter-frame crystal oscillator cycle countdown based on the crystal oscillator error cycle number a: selects a data frames from other data frames except the 0th frame to adjust the initial value of the inter-frame crystal oscillator cycle countdown; If a is greater than zero, the initial value of the inter-frame crystal oscillator period countdown corresponding to each selected data frame is increased by 1 based on the original initial value, otherwise it is decreased by 1.

9. The traveling wave ranging and timing method for a digital primary / secondary integrated pole-mounted circuit breaker according to claim 6 is characterized in that: The frame protocol encoder is also provided with a coding phase adjustment module; After receiving the pulse-second signal PPS1, the coding phase adjustment module waits for a fixed time and then controls the frame protocol encoder to send the 0th frame. At the same time, within this fixed time, the coding phase adjustment module adjusts the coding period according to the phase relationship between the coding period and the pulse-second signal, thereby completing the phase synchronization between the coding period and the pulse-second signal without changing the number of coding periods within the fixed time. In the frame protocol encoder, when the control signal S4 is received, it is determined whether the current frame count is 0. If it is 0, the current 0th frame is sent at the end of the fixed time length. Otherwise, the current data frame is sent directly under the triggering of the control signal S4.

10. The traveling wave ranging and timing method for a digital primary and secondary integrated pole mounted circuit breaker according to claim 9 is characterized in that: The encoding phase adjustment module adjusts the encoding period within a fixed time period as follows: The fixed waiting time is defined as M crystal oscillator cycles, which correspond to P coding cycles. After the second pulse signal PPS1 arrives, the number of crystal oscillator cycles N between the falling edge of the second pulse signal PPS1 and the next rising edge of the coding pulse is obtained, and then PN coding cycles are selected from the P-1 coding cycles from the rising edge to the end of the fixed waiting time, and the number of crystal oscillator cycles corresponding to each selected coding cycle is increased by 1.

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