An anti-interference protection circuit for power semiconductor switch testing

Abstract

An anti-interference protection circuit for power semiconductor switch testing includes a differential sampling module, a shutdown module, and a window threshold judgment module. The output signal of the differential sampling module is delayed by a delay module and then enters the left input terminal of the window threshold judgment module. The output signal of the differential sampling module also enters the right input terminal of the window threshold judgment module. The output terminal of the window threshold judgment module is connected to the input terminal of the shutdown module. When both the left and right signals of the window are detected to be greater than a threshold voltage, the window threshold judgment module outputs a shutdown signal. The differential sampling module acquires voltage signals, generates a time window reference through a delay circuit composed of voltage followers, and obtains initial and delayed sample values ​​respectively. Through threshold discrimination, the two sampled signals are synchronously compared with a preset threshold voltage to determine whether to cut off. This invention prevents interference from current spikes in power semiconductor switch testing while retaining the original function of the overcurrent protection circuit.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, and particularly relates to an anti-interference protection circuit for power semiconductor switch testing. Background Technology

[0002] In the research and development of power semiconductors, switching tests are an indispensable step. Since power devices are quickly damaged under high current, it is particularly important to add overcurrent protection circuits to the test circuit. However, due to the reverse recovery problem of devices such as diodes during testing, high current spikes can cause the overcurrent protection circuit to turn off falsely. Therefore, it is necessary to add anti-false-touch design to the overcurrent protection circuit to eliminate the interference of current spikes.

[0003] Traditional strategies for dealing with spike interference include patent CN113067565A (An Anti-interference Short-Circuit Protection Circuit with Adjustable Blanking Time for SiC MOSFETs), published on March 12, 2024, which uses a digital blanking scheme to achieve anti-interference design. However, this scheme requires combining digital and analog circuits, resulting in a complex structure and redundant design. Another example is patent CN114123099A (Overcurrent Protection Circuit for GaN HEMT Devices), published on December 5, 2023, which uses an RC delay scheme to achieve anti-interference. However, this scheme is limited by the physical constraints of capacitors and resistors, leading to excessively long delay times, resulting in situations where the device under test is damaged before the circuit is turned off. Generally speaking, the short-circuit current withstand capability of power semiconductor devices is typically 300ns to 500ns, while the RC delay scheme requires more than 10us to determine and turn off. Digital blanking structures are complex and also have the problem of long delays, making it difficult to break through 1us for turn-off delay. When a large current actually occurs, the delay of false touch detection causes the overcurrent protection circuit to fail to turn off in time, resulting in device damage. Summary of the Invention

[0004] To address the problems existing in the prior art, this invention provides an anti-interference protection circuit for power semiconductor switch testing, which prevents interference from current spikes during power semiconductor switch testing, while fully retaining the original function of the overcurrent protection circuit, promptly shutting down the circuit when it is in an overcurrent state.

[0005] The present invention adopts the following technical solution:

[0006] An anti-interference protection circuit for power semiconductor switch testing includes a differential sampling module and a shutdown module. It is characterized by further including a window threshold judgment module. The output signal of the differential sampling module is delayed by a delay module before entering the left input terminal of the window threshold judgment module. The output signal of the differential sampling module also enters the right input terminal of the window threshold judgment module. The output terminal of the window threshold judgment module is connected to the input terminal of the shutdown module. When both the left and right signals of the window are detected to be greater than a threshold voltage, the window threshold judgment module outputs a shutdown signal.

[0007] Furthermore, when the peak width of the spike current signal passing through the test circuit is greater than the set window delay width, the window threshold judgment module outputs a shutdown signal.

[0008] Furthermore, the delay module includes a second operational amplifier U2, the inverting input of which is connected to the output of the differential sampling module; the non-inverting input of the second operational amplifier U2 is shorted to the output and connected to the left input of the window threshold judgment module.

[0009] Furthermore, the window threshold determination module includes a third operational amplifier U3, a fourth operational amplifier U4, a sixth resistor R6, a first DC voltage source V1, a second DC voltage source V2, and a third DC voltage source V3.

[0010] The non-inverting input of the third operational amplifier U3 is used as the left input of the window threshold judgment module. The inverting input of the third operational amplifier U3 is connected to the positive terminal of the first DC voltage source V1, and the negative terminal of the first DC voltage source V1 is grounded.

[0011] The non-inverting input of the fourth operational amplifier U4 is used as the right-side input of the window threshold judgment module, and the inverting input of the fourth operational amplifier U4 is connected to the positive terminal of the second DC voltage source V2, while the negative terminal of the second DC voltage source V2 is grounded.

[0012] One end of the sixth resistor R6 is connected to the output terminals of the third operational amplifier U3 and the fourth operational amplifier U4 and serves as the output terminal of the window threshold judgment module. The other end of the sixth resistor R6 is connected to the positive terminal of the third DC voltage source V3, and the negative terminal of the third DC voltage source V3 is grounded.

[0013] Furthermore, the differential sampling module includes test resistors R1, R2, R3, R4, R5, inductor L1, inductor L2, and operational amplifier U1.

[0014] One end of the first inductor L1 is connected to one end of the first resistor R1 and is used to connect the transistor under test in the transistor double pulse test circuit. The other end is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the non-inverting input terminal of the first operational amplifier U1. The fourth resistor R4 is connected between the non-inverting input terminal and the output terminal of the first operational amplifier U1.

[0015] One end of the second inductor L2 is connected to the other end of the first resistor R1 and is used to connect to the ground terminal of the transistor double pulse test circuit. The other end is connected to one end of the third resistor R3. The other end of the third resistor R3 is connected to the inverting input terminal of the first operational amplifier U1. The two ends of the fifth resistor R5 are respectively connected to the inverting input terminal of the first operational amplifier U1 and the ground potential.

[0016] Furthermore, the shutdown module includes a fifth operational amplifier U5, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a first IGBT Q1, a second IGBT Q2, and a third IGBT Q3. The inverting input terminal of the fifth operational amplifier U5 serves as the input terminal of the shutdown module. One end of the seventh resistor R7 is grounded, and the other end, along with one end of the eighth resistor R8, is connected to the non-inverting input terminal of the fifth operational amplifier U5. The other end of the eighth resistor R8 is connected to the output terminal of the fifth operational amplifier U5. One end of the ninth resistor R9 is connected to the output terminal of the fifth operational amplifier U5, and the other end is connected to the gates of the first IGBT, the second IGBT, and the third IGBT. The sources and drains of the first IGBT Q1, the second IGBT Q2, and the third IGBT Q3 are connected in series in a transistor double-pulse test circuit, forming a three-parallel shutdown structure.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] This invention addresses the issue of current spikes during switching tests by employing a window-based rapid detection and blanking method. It selects operational amplifiers with different bandwidths in the delay circuit to set the required window width. When the voltage on the left side of the window exceeds a threshold voltage, it quickly checks whether the voltage on the right side of the window exceeds the threshold voltage. If no trigger is detected, the dual-pulse test circuit operates normally, thus suppressing interference from current spikes in the test circuit. Without affecting the switching test method or circuit, or introducing additional delays or control signals, this invention effectively suppresses the phenomenon of current spikes causing false triggering of the overcurrent protection circuit due to reverse recovery of the freewheeling diode during dual-pulse testing. This prevents the test circuit from frequently and erroneously shutting down during the test. From the overall circuit structure, only a delay circuit and a comparator circuit are needed to achieve the above-mentioned objectives, making it easy to implement and cost-effective. Attached Figure Description

[0019] Figure 1This is a schematic diagram of the window blanking protection circuit structure for power semiconductor switch testing in an example of the present invention;

[0020] Figure 2 This is a timing diagram of the window blanking protection circuit for power semiconductor switch testing in an example of the present invention.

[0021] Figure 3 This is a simulation circuit diagram of a power semiconductor double-pulse test with added anti-interference circuitry in an example of the present invention.

[0022] Figure 4 A waveform comparison of current spike detection using the traditional method and window blanking in power semiconductor switch testing;

[0023] Figure 5 This is a waveform comparison chart of overcurrent detection using the traditional method and window blanking in power semiconductor switch testing. Detailed Implementation

[0024] To better understand the purpose, structure, and function of this invention, the following detailed description of an anti-interference protection circuit for power semiconductor switch testing is provided in conjunction with the accompanying drawings.

[0025] like Figure 1 As shown, an anti-interference protection circuit for power semiconductor switch testing is characterized by comprising:

[0026] Differential sampling module, delay module, threshold judgment module, shutdown module.

[0027] The differential sampling module includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first inductor L1, a second inductor L2, and a first operational amplifier U1. The first resistor R1 is connected between the test transistor and ground; one end of the first inductor L1 is connected to the test transistor terminal of the first resistor R1, and the other end is connected to one end of the second resistor R2; one end of the second inductor L2 is connected to the ground terminal of the first resistor R1, and the other end is connected to one end of the third resistor R3; the other end of the second resistor R2 is connected to the non-inverting input terminal of the first operational amplifier U1; the other end of the third resistor R3 is connected to the inverting input terminal of the first operational amplifier U1; the fourth resistor R4 is connected between the non-inverting input terminal and the output terminal of the first operational amplifier U1; and the fifth resistor R5 is connected between the inverting input terminal of the first operational amplifier U1 and ground potential.

[0028] The delay module includes a second operational amplifier U2. The inverting input of the second operational amplifier U2 is connected to the output of the first operational amplifier U1; the non-inverting input of the second operational amplifier U2 is shorted to its output; and the output of the second operational amplifier U2 is connected to the non-inverting input of the third operational amplifier U3.

[0029] The threshold judgment module includes a third operational amplifier U3, a fourth operational amplifier U4, a sixth resistor R6, a first DC voltage source V1, a second DC voltage source V2, and a third DC voltage source V3. The inverting input terminal of the third operational amplifier U3 is connected to the positive terminal of the first DC voltage source V1, and the negative terminal of the first DC voltage source V1 is grounded.

[0030] The non-inverting input of the fourth operational amplifier U4 is connected to the output of the first operational amplifier U1; the inverting input of the fourth operational amplifier U4 is connected to the positive terminal of the second DC voltage source V2, and the negative terminal of the second DC voltage source V2 is grounded; one end of the sixth resistor R6 is connected to the outputs of the third operational amplifier U3 and the fourth operational amplifier U4, and the other end is connected to the positive terminal of the third DC voltage source V3, and the negative terminal of the third DC voltage source V3 is grounded.

[0031] The shutdown module includes a fifth operational amplifier U5, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a first IGBT Q1, a second IGBT Q2, and a third IGBT Q3. The inverting input of the fifth operational amplifier U5 is connected to the output of the third operational amplifier U3; one end of the seventh resistor R7 is grounded, and the other end, along with one end of the eighth resistor R8, is connected to the non-inverting input of the fifth operational amplifier U5; the other end of the eighth resistor R8 is connected to the output of the fifth operational amplifier U5; one end of the ninth resistor R9 is connected to the output of the fifth operational amplifier U5, and the other end is connected to the gates of the first, second, and third IGBTs; the source and drain of the first IGBT Q1 are connected in series in the main test circuit; the sources of the second and third IGBTs Q2 and Q3 are connected to the source of the first IGBT Q1, and their drains are connected to the drain of the first IGBT Q1, forming a three-parallel shutdown structure.

[0032] In one embodiment of the present invention, the differential sampling circuit is configured to work in conjunction with a dual-inductor common-mode filter topology and a differential amplifier network. The right-side signal of the window is used to generate a controllable delayed DC signal via a delay module, while the left-side signal is directly connected to a high-speed comparison unit to form a real-time trigger DC signal. A threshold judgment module, cascaded with the differential sampling module, is configured to fuse the dual trigger signals via wired-AND logic and generate a shutdown command based on the threshold comparison result. The shutdown module is configured to employ a parallel IGBT array and an isolated drive architecture to implement multiple blocking mechanisms for the test circuit in response to protection commands.

[0033] In one embodiment of the present invention, the inputs of the shutdown circuit include a delayed voltage signal V1 on the left side of the window and a real-time voltage signal V2 on the right side of the window. The two signals are input to the shutdown array after logical processing.

[0034] In one embodiment of the present invention, the delay duration of the delayed voltage signal can be changed by selecting the bandwidth of the operational amplifier U2 that constitutes the voltage follower. The delay duration can be [missing information].

[0035] In one embodiment of the present invention, when the signal on the left side of the window is detected to be greater than the threshold voltage, the signal on the right side of the window is detected. If the signal on the right side of the window is also greater than the threshold voltage, the isolated driver sends a shutdown signal to shut down the main circuit. The threshold voltage range is 2-3V, and is generally set to 2.7V.

[0036] In one embodiment of the present invention, when the test circuit passes a narrow spike current signal, the spike width is less than the set window delay width, and the protection circuit does not turn off, thus achieving anti-interference design; when the test circuit passes a wide spike current signal, the spike width is greater than the set window delay width, and the protection circuit turns off; when the test circuit is in a continuous overcurrent state, after judging the window time width, the protection circuit turns off immediately, thus achieving overcurrent protection. The window delay width of the delay circuit can be adjusted by selecting different operational amplifiers, with an adjustment range between 20ns and 300ns. In power semiconductor switch testing, 300ns is generally used. Current spikes with a time width less than the delay width are defined as narrow spikes, and current spikes with a time width greater than the delay width are defined as wide spikes.

[0037] Figure 2 This is a timing diagram of the window blanking protection circuit for power semiconductor switch testing in an example of the present invention. The following is in conjunction with... Figure 2 Explanation of the working principle of this embodiment:

[0038] The window blanking protection circuit for power semiconductor switch testing samples the current signal through a sampling circuit. The acquired signal is shown in the original waveform. Since the sampling circuit uses a high-speed operational amplifier, there is almost no delay difference between the input signal on the right side of the window and the original waveform. However, the signal on the left side of the window, after being delayed by the voltage follower, will have a propagation delay difference compared to the original waveform, typically on the order of nanoseconds. Setting Va as the threshold voltage, the right side of the window is observed when the left side triggers the threshold voltage.

[0039] At time t0, the voltage signal on the left side of the window reaches the threshold voltage Va. At this time, the signal on the right side of the window is detected. If the signal on the right side of the window is lower than the threshold voltage Va, it means that the triggered signal is a narrow current spike pulse, which is regarded as an interference signal, and the output remains unchanged.

[0040] At time t1, the voltage signal on the left side of the window reaches the threshold voltage Va. At this time, the signal on the right side of the window is detected and is higher than the threshold voltage Va. The triggered signal is a current spike pulse wider than the power device's withstand threshold voltage. At time t2, the voltage signal on the left side of the window is also found to reach the threshold voltage Va. At this time, the signal on the right side of the window is detected and is higher than the threshold voltage Va. At this time, the power device enters an overcurrent operating state. In both cases, the device is at risk of damage and overcurrent protection is required. The shutdown circuit is used for shutdown protection.

[0041] To compare the anti-narrow pulse interference effect of this invention in power semiconductor switch testing, this embodiment uses LTspice software to build a simulation circuit model, and the simulation circuit structure diagram is shown below. Figure 3 As shown in the diagram. Power transistors Q4 and Q5 are modeled using the GS66508T from GaNSyStem. Diode D1 in the main circuit is a 1N4148, and auxiliary transistors Q1, Q2, and Q3 are GS61008P. Capacitors C1 and C2 are 470uF and 10uF, respectively. Compared to a traditional crosstalk suppression circuit, the simulation circuit model in this embodiment has a load inductance L3 of 0.3mH, a load resistance R1 of 0.1Ω, and a DC input voltage VDC of 400V. The drive resistor R10 is 5Ω, and in the crosstalk suppression circuit, resistors R2, R3, R4, and R5 are 10kΩ, resistor R6 is 1kΩ, resistor R7 is 100Ω, and resistor R8 is 1kΩ. The DC input voltages V1 and V2 are 2.6V, and the DC input voltage V3 is 5V. Setting the turn-off array to three IGBTs in parallel provides superior performance at high currents. Based on this simulation circuit model, waveforms of narrow current spikes and overcurrent signals are compared.

[0042] Figure 4 This image shows a waveform comparison between traditional and window blanking methods for current spike detection in power semiconductor switch testing. The current spike width is widened by adjusting the parallel capacitor of the reverse freewheeling diode, set to 300ns. At time t0, the narrow current spike exceeds the Va current threshold, and both the window blanking and traditional methods enter judgment mode. At time t1, the window blanking circuit, due to its short window time (typically on the order of 150ns), detects the wide pulse and immediately shuts off. The traditional method, however, must perform the judgment at the end of the delay. If the device is intact, the spike is only detected and judged at time t2, by which time the device has already experienced the wide current spike, potentially shortening its lifespan or even causing damage.

[0043] Figure 5This chart compares the waveforms of overcurrent detection using a traditional method and window blanking in power semiconductor switch testing. At time t0, the current of the device under test (DUT) exceeds the Va current threshold. Both the window blanking and traditional methods enter judgment mode. At time t1, the window blanking circuit, due to its short window time (typically on the order of 150ns), detects a wide pulse and immediately shuts down the device. The traditional method, however, must perform the judgment at the end of the delay. At time t2, the traditional method's delay ends before the second detection, by which time the device has already endured a prolonged overcurrent, easily leading to reduced lifespan or even damage. Therefore, from... Figure 4 and Figure 5 It can be seen that the delay scheme used in the traditional solution has very poor detection sensitivity for narrow pulses and overcurrent conditions, which is far lower than that of the window blanking circuit. Therefore, the window blanking protection circuit tested with power semiconductor switches can increase the resistance to current spike pulses while achieving a higher overcurrent protection response speed.

[0044] This invention focuses on optimizing the anti-current spike interference performance of power semiconductor switching test systems while also improving the overcurrent protection efficiency of the circuit. It provides a current spike suppression circuit based on a time window screening mechanism, which effectively eliminates the transient current false triggering problem caused by the reverse recovery characteristics of the freewheeling diode in double-pulse testing and promptly shuts down the circuit when overcurrent occurs. Through a unique circuit architecture and dynamic threshold control strategy, it significantly suppresses the risk of malfunction of the overcurrent protection circuit without affecting the switching speed of the device under test, introducing additional control signals, or incurring energy losses. Simultaneously, it accelerates the response speed to overcurrent detection risks, providing an innovative technical solution for improving the testing accuracy and system reliability of power semiconductor power devices.

[0045] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. An anti-interference protection circuit for power semiconductor switch testing, comprising a differential sampling module and a shutdown module, characterized in that... It also includes a window threshold judgment module. The output signal of the differential sampling module is delayed by the delay module and then enters the left input terminal of the window of the window threshold judgment module. The output signal of the differential sampling module also enters the right input terminal of the window of the window threshold judgment module. The output terminal of the window threshold judgment module is connected to the input terminal of the shutdown module. When the signals on the left and right sides of the window are both detected to be greater than the threshold voltage, the window threshold judgment module outputs a shutdown signal. The window threshold determination module includes a third operational amplifier U3, a fourth operational amplifier U4, a sixth resistor R6, a first DC voltage source V1, a second DC voltage source V2, and a third DC voltage source V3. The non-inverting input of the third operational amplifier U3 is used as the left input of the window threshold judgment module. The inverting input of the third operational amplifier U3 is connected to the positive terminal of the first DC voltage source V1, and the negative terminal of the first DC voltage source V1 is grounded. The non-inverting input of the fourth operational amplifier U4 is used as the right-side input of the window threshold judgment module, and the inverting input of the fourth operational amplifier U4 is connected to the positive terminal of the second DC voltage source V2, while the negative terminal of the second DC voltage source V2 is grounded. One end of the sixth resistor R6 is connected to the output terminals of the third operational amplifier U3 and the fourth operational amplifier U4 and serves as the output terminal of the window threshold judgment module. The other end of the sixth resistor R6 is connected to the positive terminal of the third DC voltage source V3, and the negative terminal of the third DC voltage source V3 is grounded.

2. The anti-interference protection circuit for power semiconductor switch testing according to claim 1, characterized in that, When the peak width of the spike current signal passing through the test circuit is greater than the set window delay width, the window threshold judgment module outputs a shutdown signal.

3. The anti-interference protection circuit for power semiconductor switch testing according to claim 1 or 2, characterized in that, The delay module includes a second operational amplifier U2. The inverting input of the second operational amplifier U2 is connected to the output of the differential sampling module. The non-inverting input of the second operational amplifier U2 is shorted to the output and connected to the left input of the window threshold judgment module.

4. The anti-interference protection circuit for power semiconductor switch testing according to claim 3, characterized in that, The differential sampling module includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first inductor L1, a second inductor L2, and a first operational amplifier U1. One end of the first inductor L1 is connected to one end of the first resistor R1 and is used to connect the transistor under test in the transistor double pulse test circuit. The other end is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the non-inverting input terminal of the first operational amplifier U1. The fourth resistor R4 is connected between the non-inverting input terminal and the output terminal of the first operational amplifier U1. One end of the second inductor L2 is connected to the other end of the first resistor R1 and is used to connect to the ground terminal of the transistor double pulse test circuit. The other end is connected to one end of the third resistor R3. The other end of the third resistor R3 is connected to the inverting input terminal of the first operational amplifier U1. The two ends of the fifth resistor R5 are respectively connected to the inverting input terminal of the first operational amplifier U1 and the ground potential.

5. The anti-interference protection circuit for power semiconductor switch testing according to claim 4, characterized in that, The shutdown module includes a fifth operational amplifier U5, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a first IGBT Q1, a second IGBT Q2, and a third IGBT Q3. The inverting input of the fifth operational amplifier U5 serves as the input of the shutdown module. One end of the seventh resistor R7 is grounded, and the other end, along with one end of the eighth resistor R8, is connected to the non-inverting input of the fifth operational amplifier U5. The other end of the eighth resistor R8 is connected to the output of the fifth operational amplifier U5. One end of the ninth resistor R9 is connected to the output of the fifth operational amplifier U5, and the other end is connected to the gates of the first IGBT Q1, the second IGBT Q2, and the third IGBT Q3. The sources and drains of the first IGBT Q1, the second IGBT Q2, and the third IGBT Q3 are connected in series and used in a transistor double-pulse test circuit.

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