Preparation circuit generation method and device, preparation circuit preparation method and device, electronic equipment, storage medium and computer program product

Abstract

The invention relates to a preparation circuit generation method and device, electronic equipment, a storage medium and a computer program product. The method comprises the following steps: determining a target bit set under the limitation of a binary tree, and acting a single-bit flipping gate on a first target child node bit; acting a double-bit phase shift gate between sub-node bits; acting a double-bit interchange gate between the first target sub-node bit and the second target sub-node bit; taking the child node bit as a root node bit, and performing iterative execution until the child node bit is a leaf node bit; and acting a double-bit phase shift gate between leaf node bits under path limitation, and acting a single-bit phase shift gate on the leaf node bits to obtain a preparation circuit. By adopting the method, the circuit depth can be effectively reduced.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, device, electronic device, storage medium and computer program product for preparing a circuit and its preparation. Background Art

[0002] With the development of computer technology, fabrication techniques have emerged. The process of loading classical data into states such as the ground state, excited state, superposition state, and entangled state is called fabrication. In a system, due to decoherence, if the circuit depth is too large, the circuit will degenerate into a classical circuit. In actual devices, the spatial arrangement of bits or other factors may limit the interaction between bits. Therefore, in fabricated circuits, the bits that a CNOT gate (Controlled NOT gate) can act on are limited by the specific physical device.

[0003] At present, directly improving existing fabricated circuits within circuit limitations can significantly increase circuit depth. Summary of the Invention

[0004] Based on this, it is necessary to provide a circuit generation and preparation method, device, electronic device, storage medium and computer program product that can effectively reduce the circuit depth to address the above technical problems.

[0005] In one aspect, the present application provides a method for preparing a circuit. The method comprises:

[0006] Get single-bit flip gate, single-bit phase shift gate, double-bit swap gate and double-bit phase shift gate under path restriction;

[0007] Determine a target bit set under the binary tree constraint, apply a single-bit flip gate to the first target child node bit corresponding to the root node bit in the target bit set, and obtain a flip gate subcircuit;

[0008] Applying a two-bit phase shift gate between the child node bits corresponding to the root node bit to obtain a phase shift gate subcircuit;

[0009] Applying a two-bit swap gate between the first target sub-node bit and the second target sub-node bit to obtain a swap gate sub-circuit, wherein the second target sub-node bit is a sub-node bit of the first target sub-node bit;

[0010] The child node bit is used as the root node bit, and the steps of applying the two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain the phase shift gate subcircuit are executed until the child node bit becomes a leaf node bit.

[0011] Apply the two-bit phase shift gate under the path constraint to the leaf node bits corresponding to the parent node bits in the target bit set to obtain the leaf phase shift gate subcircuit, and apply the single-bit phase shift gate to the leaf node bits to obtain the single-bit phase shift subcircuit.

[0012] The flip gate subcircuit, the phase shift gate subcircuit, the interchange gate subcircuit, the leaf phase shift gate subcircuit and the single-bit phase shift subcircuit are combined into a prepared circuit.

[0013] On the other hand, the present application also provides a circuit generation device. The device includes:

[0014] An acquisition module, used to acquire a single-bit flip gate, a single-bit phase shift gate, a double-bit swap gate, and a double-bit phase shift gate under path constraints;

[0015] A flip gate action module is used to determine a target bit set under the binary tree constraint, and to apply a single-bit flip gate to the first target child node bit corresponding to the root node bit in the target bit set to obtain a flip gate subcircuit;

[0016] A phase shift gate action module is used to apply a dual-bit phase shift gate between the child node bits corresponding to the root node bit to obtain a phase shift gate subcircuit;

[0017] a swap gate action module, configured to apply a two-bit swap gate between a first target sub-node bit and a second target sub-node bit to obtain a swap gate sub-circuit, wherein the second target sub-node bit is a sub-node bit of the first target sub-node bit;

[0018] an iterative module, configured to treat the child node bit as a root node bit and return to the step of applying a two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain a phase shift gate subcircuit, until the child node bit becomes a leaf node bit;

[0019] A leaf node action module is configured to apply a two-bit phase shift gate under path constraints to the leaf node bits corresponding to the parent node bits in the target bit set to obtain a leaf phase shift gate subcircuit, and to apply a single-bit phase shift gate to the leaf node bits to obtain a single-bit phase shift subcircuit;

[0020] The combination module is used to combine the flip gate subcircuit, the phase shift gate subcircuit, the interchange gate subcircuit, the leaf phase shift gate subcircuit and the single-bit phase shift subcircuit into a prepared circuit.

[0021] On the other hand, the present application further provides a chip, including a preparation circuit, characterized in that the preparation circuit is implemented by a method for generating a preparation circuit, and the method for generating the preparation circuit includes:

[0022] Get single-bit flip gate, single-bit phase shift gate, double-bit swap gate and double-bit phase shift gate under path restriction;

[0023] Determine a target bit set under the binary tree constraint, apply a single-bit flip gate to the first target child node bit corresponding to the root node bit in the target bit set, and obtain a flip gate subcircuit;

[0024] Applying a two-bit phase shift gate between the child node bits corresponding to the root node bit to obtain a phase shift gate subcircuit;

[0025] Applying a two-bit swap gate between the first target sub-node bit and the second target sub-node bit to obtain a swap gate sub-circuit, wherein the second target sub-node bit is a sub-node bit of the first target sub-node bit;

[0026] The child node bit is used as the root node bit, and the steps of applying the two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain the phase shift gate subcircuit are executed until the child node bit becomes a leaf node bit.

[0027] Apply the two-bit phase shift gate under the path constraint to the leaf node bits corresponding to the parent node bits in the target bit set to obtain the leaf phase shift gate subcircuit, and apply the single-bit phase shift gate to the leaf node bits to obtain the single-bit phase shift subcircuit.

[0028] The flip gate subcircuit, the phase shift gate subcircuit, the interchange gate subcircuit, the leaf phase shift gate subcircuit and the single-bit phase shift subcircuit are combined into a prepared circuit.

[0029] On the other hand, the present application also provides an electronic device. The electronic device includes a memory and a processor, the memory stores a computer program, and the processor performs the following steps when executing the computer program:

[0030] Get single-bit flip gate, single-bit phase shift gate, double-bit swap gate and double-bit phase shift gate under path restriction;

[0031] Determine a target bit set under the binary tree constraint, apply a single-bit flip gate to the first target child node bit corresponding to the root node bit in the target bit set, and obtain a flip gate subcircuit;

[0032] Applying a two-bit phase shift gate between the child node bits corresponding to the root node bit to obtain a phase shift gate subcircuit;

[0033] Applying a two-bit swap gate between the first target sub-node bit and the second target sub-node bit to obtain a swap gate sub-circuit, wherein the second target sub-node bit is a sub-node bit of the first target sub-node bit;

[0034] The child node bit is used as the root node bit, and the steps of applying the two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain the phase shift gate subcircuit are executed until the child node bit becomes a leaf node bit.

[0035] Apply the two-bit phase shift gate under the path constraint to the leaf node bits corresponding to the parent node bits in the target bit set to obtain the leaf phase shift gate subcircuit, and apply the single-bit phase shift gate to the leaf node bits to obtain the single-bit phase shift subcircuit.

[0036] The flip gate subcircuit, the phase shift gate subcircuit, the interchange gate subcircuit, the leaf phase shift gate subcircuit and the single-bit phase shift subcircuit are combined into a prepared circuit.

[0037] On the other hand, the present application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the following steps:

[0038] Get single-bit flip gate, single-bit phase shift gate, double-bit swap gate and double-bit phase shift gate under path restriction;

[0039] Determine a target bit set under the binary tree constraint, apply a single-bit flip gate to the first target child node bit corresponding to the root node bit in the target bit set, and obtain a flip gate subcircuit;

[0040] Applying a two-bit phase shift gate between the child node bits corresponding to the root node bit to obtain a phase shift gate subcircuit;

[0041] Applying a two-bit swap gate between the first target sub-node bit and the second target sub-node bit to obtain a swap gate sub-circuit, wherein the second target sub-node bit is a sub-node bit of the first target sub-node bit;

[0042] The child node bit is used as the root node bit, and the steps of applying the two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain the phase shift gate subcircuit are executed until the child node bit becomes a leaf node bit.

[0043] Apply the two-bit phase shift gate under the path constraint to the leaf node bits corresponding to the parent node bits in the target bit set to obtain the leaf phase shift gate subcircuit, and apply the single-bit phase shift gate to the leaf node bits to obtain the single-bit phase shift subcircuit.

[0044] The flip gate subcircuit, the phase shift gate subcircuit, the interchange gate subcircuit, the leaf phase shift gate subcircuit and the single-bit phase shift subcircuit are combined into a prepared circuit.

[0045] On the other hand, the present application also provides a computer program product. The computer program product includes a computer program, which, when executed by a processor, implements the following steps:

[0046] Get single-bit flip gate, single-bit phase shift gate, double-bit swap gate and double-bit phase shift gate under path restriction;

[0047] Determine a target bit set under the binary tree constraint, apply a single-bit flip gate to the first target child node bit corresponding to the root node bit in the target bit set, and obtain a flip gate subcircuit;

[0048] Applying a two-bit phase shift gate between the child node bits corresponding to the root node bit to obtain a phase shift gate subcircuit;

[0049] Applying a two-bit swap gate between the first target sub-node bit and the second target sub-node bit to obtain a swap gate sub-circuit, wherein the second target sub-node bit is a sub-node bit of the first target sub-node bit;

[0050] The child node bit is used as the root node bit, and the steps of applying the two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain the phase shift gate subcircuit are executed until the child node bit becomes a leaf node bit.

[0051] Apply the two-bit phase shift gate under the path constraint to the leaf node bits corresponding to the parent node bits in the target bit set to obtain the leaf phase shift gate subcircuit, and apply the single-bit phase shift gate to the leaf node bits to obtain the single-bit phase shift subcircuit.

[0052] The flip gate subcircuit, the phase shift gate subcircuit, the interchange gate subcircuit, the leaf phase shift gate subcircuit and the single-bit phase shift subcircuit are combined into a prepared circuit.

[0053] The above-mentioned circuit generation method, device, electronic device, storage medium and computer program product are prepared by determining the target bit set under the binary tree constraint, applying a single-bit flip gate to the first target child node bit corresponding to the root node bit in the target bit set to obtain a flip gate subcircuit; applying a two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain a phase shift gate subcircuit; applying a two-bit swap gate to the first target child node bit and the second target child node bit to obtain a swap gate subcircuit, where the second target child node bit is a child node bit of the first target child node bit; taking the child node bit as the root node bit, and returning the two-bit phase shift gate applied to the root node bit. The steps of obtaining a phase-shift gate subcircuit between child node bits corresponding to a node bit are executed until the child node bit becomes a leaf node bit; a dual-bit phase-shift gate under path restriction is applied between leaf node bits corresponding to a parent node bit in a target bit set to obtain a leaf phase-shift gate subcircuit, and a single-bit phase-shift gate is applied to a leaf node bit to obtain a single-bit phase-shift subcircuit; a flip gate subcircuit, a phase-shift gate subcircuit, an interchange gate subcircuit, a leaf phase-shift gate subcircuit and a single-bit phase-shift subcircuit are combined into a preparation circuit, thereby effectively reducing the circuit depth of the preparation circuit, thereby effectively reducing the preparation time and improving the operation efficiency of the calculation.

[0054] In one aspect, the present application provides a preparation method. The method comprises:

[0055] Obtain a target data vector, and obtain a target single-bit flip gate, a target single-bit phase shift gate, a target double-bit swap gate, and a target double-bit phase shift gate under path constraints based on the target data vector;

[0056] Determine a target bit set under the binary tree constraint, apply a target single-bit flip gate to the first target child node bit corresponding to the root node bit in the target bit set, and obtain a target flip gate subcircuit;

[0057] Apply the target two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain the target phase shift gate subcircuit;

[0058] Applying a target two-bit swap gate between a first target sub-node bit and a second target sub-node bit to obtain a target swap gate sub-circuit, wherein the second target sub-node bit is a sub-node bit of the first target sub-node bit;

[0059] The child node bit is used as the root node bit, and the steps of applying the target two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain the target phase shift gate subcircuit are executed until the child node bit becomes a leaf node bit.

[0060] Apply the target two-bit phase shift gate under the path constraint to the leaf node bits corresponding to the parent node bits in the target bit set to obtain the target leaf phase shift gate subcircuit, and apply the target single-bit phase shift gate to the leaf node bits to obtain the target single-bit phase shift subcircuit.

[0061] Combining a target flip gate subcircuit, a target phase shift gate subcircuit, a target swap gate subcircuit, a target leaf phase shift gate subcircuit, and a target single-bit phase shift subcircuit into a target preparation circuit corresponding to a target data vector;

[0062] The preset initial state is input into the target preparation circuit for preparation to obtain the state corresponding to the target data vector.

[0063] On the other hand, the present application also provides a preparation device. The device comprises:

[0064] A target acquisition module is used to acquire a target data vector, and acquire a target single-bit flip gate, a target single-bit phase shift gate, a target double-bit swap gate, and a target double-bit phase shift gate under path constraints based on the target data vector;

[0065] A target flip gate action module is used to determine a target bit set under the binary tree constraint, and to apply a target single-bit flip gate to the first target child node bit corresponding to the root node bit in the target bit set to obtain a target flip gate subcircuit;

[0066] A target phase shift gate action module is used to apply a target two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain a target phase shift gate subcircuit;

[0067] a target swap gate action module, configured to apply a target two-bit swap gate between a first target sub-node bit and a second target sub-node bit to obtain a target swap gate sub-circuit, wherein the second target sub-node bit is a sub-node bit of the first target sub-node bit;

[0068] a target iteration module, configured to take the child node bit as the root node bit and return to the step of applying the target two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain the target phase shift gate subcircuit until the child node bit becomes a leaf node bit;

[0069] The target leaf node action module is used to apply the target double-bit phase shift gate under the path constraint to the leaf node bits corresponding to the parent node bits in the target bit set to obtain the target leaf phase shift gate subcircuit, and apply the target single-bit phase shift gate to the leaf node bits to obtain the target single-bit phase shift subcircuit;

[0070] a target combination module, configured to combine a target flip gate subcircuit, a target phase shift gate subcircuit, a target swap gate subcircuit, a target leaf phase shift gate subcircuit, and a target single-bit phase shift subcircuit into a target preparation circuit corresponding to a target data vector;

[0071] The preparation module is used to input the preset initial state into the target preparation circuit for preparation to obtain the state corresponding to the target data vector.

[0072] On the other hand, the present application further provides a chip, including a preparation circuit, characterized in that the preparation circuit is implemented by a method for generating a preparation circuit, and the method for generating the preparation circuit includes:

[0073] Obtain a target data vector, and obtain a target single-bit flip gate, a target single-bit phase shift gate, a target double-bit swap gate, and a target double-bit phase shift gate under path constraints based on the target data vector;

[0074] Determine a target bit set under the binary tree constraint, apply a target single-bit flip gate to the first target child node bit corresponding to the root node bit in the target bit set, and obtain a target flip gate subcircuit;

[0075] Apply the target two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain the target phase shift gate subcircuit;

[0076] Applying a target two-bit swap gate between a first target sub-node bit and a second target sub-node bit to obtain a target swap gate sub-circuit, wherein the second target sub-node bit is a sub-node bit of the first target sub-node bit;

[0077] The child node bit is used as the root node bit, and the steps of applying the target two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain the target phase shift gate subcircuit are executed until the child node bit becomes a leaf node bit.

[0078] Apply the target two-bit phase shift gate under the path constraint to the leaf node bits corresponding to the parent node bits in the target bit set to obtain the target leaf phase shift gate subcircuit, and apply the target single-bit phase shift gate to the leaf node bits to obtain the target single-bit phase shift subcircuit.

[0079] Combining a target flip gate subcircuit, a target phase shift gate subcircuit, a target swap gate subcircuit, a target leaf phase shift gate subcircuit, and a target single-bit phase shift subcircuit into a target preparation circuit corresponding to a target data vector;

[0080] The preset initial state is input into the target preparation circuit for preparation to obtain the state corresponding to the target data vector.

[0081] On the other hand, the present application also provides an electronic device. The electronic device includes a memory and a processor, the memory stores a computer program, and the processor performs the following steps when executing the computer program:

[0082] Obtain a target data vector, and obtain a target single-bit flip gate, a target single-bit phase shift gate, a target double-bit swap gate, and a target double-bit phase shift gate under path constraints based on the target data vector;

[0083] Determine a target bit set under the binary tree constraint, apply a target single-bit flip gate to the first target child node bit corresponding to the root node bit in the target bit set, and obtain a target flip gate subcircuit;

[0084] Apply the target two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain the target phase shift gate subcircuit;

[0085] Applying a target two-bit swap gate between a first target sub-node bit and a second target sub-node bit to obtain a target swap gate sub-circuit, wherein the second target sub-node bit is a sub-node bit of the first target sub-node bit;

[0086] The child node bit is used as the root node bit, and the steps of applying the target two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain the target phase shift gate subcircuit are executed until the child node bit becomes a leaf node bit.

[0087] Apply the target two-bit phase shift gate under the path constraint to the leaf node bits corresponding to the parent node bits in the target bit set to obtain the target leaf phase shift gate subcircuit, and apply the target single-bit phase shift gate to the leaf node bits to obtain the target single-bit phase shift subcircuit.

[0088] Combining a target flip gate subcircuit, a target phase shift gate subcircuit, a target swap gate subcircuit, a target leaf phase shift gate subcircuit, and a target single-bit phase shift subcircuit into a target preparation circuit corresponding to a target data vector;

[0089] The preset initial state is input into the target preparation circuit for preparation to obtain the state corresponding to the target data vector.

[0090] On the other hand, the present application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the following steps:

[0091] Obtain a target data vector, and obtain a target single-bit flip gate, a target single-bit phase shift gate, a target double-bit swap gate, and a target double-bit phase shift gate under path constraints based on the target data vector;

[0092] Determine a target bit set under the binary tree constraint, apply a target single-bit flip gate to the first target child node bit corresponding to the root node bit in the target bit set, and obtain a target flip gate subcircuit;

[0093] Apply the target two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain the target phase shift gate subcircuit;

[0094] Applying a target two-bit swap gate between a first target sub-node bit and a second target sub-node bit to obtain a target swap gate sub-circuit, wherein the second target sub-node bit is a sub-node bit of the first target sub-node bit;

[0095] The child node bit is used as the root node bit, and the steps of applying the target two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain the target phase shift gate subcircuit are executed until the child node bit becomes a leaf node bit.

[0096] Apply the target two-bit phase shift gate under the path constraint to the leaf node bits corresponding to the parent node bits in the target bit set to obtain the target leaf phase shift gate subcircuit, and apply the target single-bit phase shift gate to the leaf node bits to obtain the target single-bit phase shift subcircuit.

[0097] Combining a target flip gate subcircuit, a target phase shift gate subcircuit, a target swap gate subcircuit, a target leaf phase shift gate subcircuit, and a target single-bit phase shift subcircuit into a target preparation circuit corresponding to a target data vector;

[0098] The preset initial state is input into the target preparation circuit for preparation to obtain the state corresponding to the target data vector.

[0099] On the other hand, the present application also provides a computer program product. The computer program product includes a computer program, which, when executed by a processor, implements the following steps:

[0100] Obtain a target data vector, and obtain a target single-bit flip gate, a target single-bit phase shift gate, a target double-bit swap gate, and a target double-bit phase shift gate under path constraints based on the target data vector;

[0101] Determine a target bit set under the binary tree constraint, apply a target single-bit flip gate to the first target child node bit corresponding to the root node bit in the target bit set, and obtain a target flip gate subcircuit;

[0102] Apply the target two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain the target phase shift gate subcircuit;

[0103] Applying a target two-bit swap gate between a first target sub-node bit and a second target sub-node bit to obtain a target swap gate sub-circuit, wherein the second target sub-node bit is a sub-node bit of the first target sub-node bit;

[0104] The child node bit is used as the root node bit, and the steps of applying the target two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain the target phase shift gate subcircuit are executed until the child node bit becomes a leaf node bit.

[0105] Apply the target two-bit phase shift gate under the path constraint to the leaf node bits corresponding to the parent node bits in the target bit set to obtain the target leaf phase shift gate subcircuit, and apply the target single-bit phase shift gate to the leaf node bits to obtain the target single-bit phase shift subcircuit.

[0106] Combining a target flip gate subcircuit, a target phase shift gate subcircuit, a target swap gate subcircuit, a target leaf phase shift gate subcircuit, and a target single-bit phase shift subcircuit into a target preparation circuit corresponding to a target data vector;

[0107] The preset initial state is input into the target preparation circuit for preparation to obtain the state corresponding to the target data vector.

[0108] The above-mentioned preparation method, device, electronic device, storage medium and computer program product obtain the target single-bit flip gate, target single-bit phase offset gate, target double-bit swap gate and target double-bit phase offset gate under path restriction corresponding to the target data vector, and then use the target single-bit flip gate, target single-bit phase offset gate, target double-bit swap gate and target double-bit phase offset gate under path restriction to generate the target preparation circuit corresponding to the target data vector, thereby effectively reducing the circuit depth of the preparation circuit, and then inputting the preset initial state into the target preparation circuit for preparation to obtain the state corresponding to the target data vector, thereby effectively reducing the preparation time, improving the calculation operation efficiency, and thus improving the preparation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0109] Figure 1 A diagram illustrating an application environment for preparing a circuit generation method in one embodiment;

[0110] Figure 2 is a schematic diagram of a binary tree restriction of a circuit in one embodiment;

[0111] Figure 3is a schematic diagram of n-path limitation of an n-bit circuit in one embodiment;

[0112] Figure 4 A two-bit swap gate in one embodiment Schematic diagram of the circuit implementation;

[0113] Figure 5 A double-bit revolving door in one embodiment Schematic diagram of the circuit implementation;

[0114] Figure 6 A CNOT gate in one embodiment Schematic diagram of circuit implementation under path constraints;

[0115] Figure 7 A schematic diagram of a process for preparing a circuit in one embodiment;

[0116] Figure 8 A schematic diagram of a flow chart of a preparation circuit for generating three bits in one embodiment;

[0117] Figure 9 Schematic diagram of a process for obtaining a state corresponding to a target data vector in one embodiment;

[0118] Figure 10 A schematic diagram of a recommended process in an embodiment;

[0119] Figure 11 Schematic diagram of a preparation method in one embodiment;

[0120] Figure 12 Generate a schematic diagram of a fabricated circuit for a specific embodiment;

[0121] Figure 13 A structural block diagram of a circuit generating device in one embodiment is provided;

[0122] Figure 14 It is a structural block diagram of a preparation device in one embodiment;

[0123] Figure 15 FIG. 1 is a diagram showing the internal structure of an electronic device in one embodiment. DETAILED DESCRIPTION

[0124] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0125] The method for producing a circuit provided in the embodiment of the present application can be applied to Figure 1In the application environment shown. Among them, the electronic device 102 communicates with the chip 104 through the network. The data storage system can store data that the electronic device 102 needs to process. The data storage system can be integrated on the electronic device 102, or it can be placed on the cloud or other network servers. The electronic device 102 can be used to generate a preparation circuit 1042, and the electronic device 102 obtains a single-bit flip gate, a single-bit phase shift gate, a double-bit swap gate, and a double-bit phase shift gate under path constraints; the electronic device 102 determines the target bit set under the binary tree constraint, and applies the single-bit flip gate to the first target sub-node bit corresponding to the root node bit in the target bit set to obtain a flip gate sub-circuit; the electronic device 102 applies the double-bit phase shift gate between the sub-node bits corresponding to the root node bit to obtain a phase shift gate sub-circuit; the electronic device 102 applies the double-bit swap gate between the first target sub-node bit and the second target sub-node bit to obtain an swap gate sub-circuit, and the second target sub-node bit is the first target sub-node bit. The electronic device 102 uses the child node bit as the root node bit and returns to the step of applying a two-bit phase-shift gate between the child node bits corresponding to the root node bit to obtain a phase-shift gate subcircuit until the child node bit becomes a leaf node bit. The electronic device 102 applies a two-bit phase-shift gate under path constraints between the leaf node bits corresponding to the parent node bit in the target bit set to obtain a leaf phase-shift gate subcircuit, and applies a single-bit phase-shift gate to the leaf node bit to obtain a single-bit phase-shift subcircuit. The electronic device 102 combines the flip gate subcircuit, the phase-shift gate subcircuit, the swap gate subcircuit, the leaf phase-shift gate subcircuit, and the single-bit phase-shift subcircuit into a fabricated circuit 1042. The fabricated circuit 1042 can ultimately be used to fabricate the chip 104.

[0126] Electronic device 102 may be an industrial intelligent device used to fabricate circuit 1042, such as a photolithography device, a robotic arm, or other equipment required for industrial production. After chip 104 is fabricated using fabricated circuit 1042, chip 104 can be integrated into various smart terminals, including smartphones, tablets, laptops, desktop computers, smart speakers, smart watches, IoT devices, and portable wearable devices. IoT devices may include smart speakers, smart TVs, smart air conditioners, and smart car devices. Portable wearable devices may include smart watches, smart bracelets, and head-mounted devices.

[0127] Before further explaining the embodiments of the present application in detail, the nouns, terms, symbols, parameters and basic gates involved in the embodiments of the present application are explained. The nouns and terms involved in the embodiments of the present application are subject to the following interpretations:

[0128] (1) Computation: A computing method that uses properties such as superposition and entanglement of states to quickly complete computing tasks.

[0129] (2) Bit: the form in which information is carried.

[0130] (3) Circuit: A computational model consisting of a sequence of gates that perform computations.

[0131] (4) Chip: The central processing unit of a computer. This computer uses the superposition principle and entanglement of mechanics to perform calculations. It has strong parallel processing capabilities and can solve some problems that are difficult for classical computers to calculate.

[0132] (5) Basic symbols involved in this application: Representing a collection . Represents a binary domain. Represents an empty string. , Indicates the label is A vector with 1 as its element and 0 as its other elements. For any bit number , Indicates status It is in Bit The status on.

[0133] (6) Basic gates involved in this application: In order to better describe the structure of the circuit under the binary tree constraint, this application first introduces some basic gates.

[0134] The single-bit flip gate X is defined as: .

[0135] For any real number , single-bit gate and They are defined as:

[0136]

[0137] .

[0138] Acting on bits and Dual bit rotation (phase shift) gate on The rotation (phase shift) around the y-axis is defined as:

[0139]

[0140]

[0141]

[0142] .

[0143] Acting on bits and CNOT (Controlled NOT) gate on is defined as:

[0144] .

[0145] Acting on bits and Interchange door on is defined as:

[0146] .

[0147] (7) Binary tree restriction: If a CNOT gate is only allowed to act on two adjacent bits, then the circuit is said to be under the binary tree restriction. Figure 2 Represents the binary tree restriction of the circuit, with vertices Respectively If two bits are connected by an edge in the binary tree, then the CNOT gate can act on these two bits.

[0148] (8) n-path restriction: If in an n-bit circuit, a CNOT gate is only allowed to act on two adjacent bits, then the circuit is said to be under n-path restriction. Figure 3 represents the n-path restriction of an n-bit circuit, vertex If two bits are connected by an edge, the CNOT gate can act on these two bits.

[0149] (9) This application first describes the implementation of four sub-circuits:

[0150] 1. Two-bit swap gate The circuit implementation is as follows Figure 4 As shown;

[0151] 2. Dual-bit rotation (phase shift) gate The circuit implementation is as follows Figure 5 As shown;

[0152] 3. CNOT door Circuit implementation under path constraints: Under path constraints, Can be both deep and large The CNOT circuit is realized as Figure 6 As shown;

[0153] 4. Double-bit revolving door under path restriction Circuit implementation: combined with a double-bit revolving gate Circuit implementation ( Figure 5 ) and CNOT gate Circuit implementation under path constraints ( Figure 6 ) It can be seen that under the path restriction Can be deep circuit implementation.

[0154] In one embodiment, Figure 7 As shown, a method for preparing a circuit is provided, which is applied to Figure 1 The electronic device in FIG is taken as an example to illustrate, including the following steps:

[0155] Step 702: Obtain a single-bit flip gate, a single-bit phase shift gate, a double-bit swap gate, and a double-bit phase shift gate under path constraints.

[0156] The single-bit flip gate is used to flip a bit. The single-bit phase shift gate is used to shift the phase of a bit. The double-bit swap gate is used to swap two bits. The double-bit phase shift gate is used to shift the phase of two bits.

[0157] Specifically, the electronic device obtains an initial vector and determines a single-bit flip gate, a single-bit phase shift gate, a double-bit swap gate, and a double-bit phase shift gate under path constraints based on the initial vector. The initial vector is a vector of initial classical data and can be pre-set. The electronic device can also directly obtain the single-bit flip gate, single-bit phase shift gate, double-bit swap gate, and double-bit phase shift gate under path constraints from a database. The electronic device can also obtain the single-bit flip gate, single-bit phase shift gate, double-bit swap gate, and double-bit phase shift gate under path constraints uploaded by the terminal.

[0158] Step 704 : determine a target bit set under the binary tree constraint, apply a single-bit flip gate to the first target child node bit corresponding to the root node bit in the target bit set, and obtain a flip gate subcircuit.

[0159] The target bit set under the binary tree constraint refers to the set of bits in the target bit set arranged in a binary tree, with the CNOT gate only allowed to act on two adjacent bits. The root node bit refers to the bit at the root node position in the binary tree. The first target child node bit refers to the bit at the target child node position corresponding to the root node bit, which can be the left child node position or the right byte position. The flip gate subcircuit refers to the circuit obtained by applying a single-bit flip gate to the first target child node bit.

[0160] Specifically, the electronic device obtains each bit and uses it to determine a target bit set within the binary tree constraints. A single-bit flip gate is then applied to the first target child node bit corresponding to the root node bit in the target bit set, resulting in a flip gate subcircuit. Specifically, a single-bit flip gate is implemented on the first target child node bit corresponding to the root node bit in the target bit set.

[0161] Step 706: Apply a two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain a phase shift gate subcircuit.

[0162] The term "between child node bits" refers to the bit between the left child node and the bit between the right child node. The phase-shift gate subcircuit is a circuit formed by applying a two-bit phase-shift gate between the bit between the left child node and the bit between the right child node of a root node bit.

[0163] Specifically, the electronic device applies a two-bit phase shift gate under path constraints between the child node bits corresponding to the root node bit to obtain a phase shift gate subcircuit, that is, a two-bit phase shift gate is implemented between the bit at the left child node position and the bit at the right child node position.

[0164] Step 708 : Apply a two-bit swap gate between the first target sub-node bit and the second target sub-node bit to obtain a swap gate sub-circuit, where the second target sub-node bit is a sub-node bit of the first target sub-node bit.

[0165] The second target subnode bit is a child node bit of the first target subnode bit. The second target subnode bit refers to the bit at the target subnode position corresponding to the first target subnode bit as the parent node bit. The target subnode position can be a left subnode position or a right byte position. The swap gate subcircuit is a circuit obtained by applying a dual-bit swap gate between the first target subnode bit and the second target subnode bit.

[0166] Specifically, the electronic device applies a two-bit swap gate between the first target subnode bit and the second target subnode bit to obtain a swap gate subcircuit, that is, the electronic device implements a two-bit swap gate between the first target subnode bit and the second target subnode bit.

[0167] In one embodiment, when the first target subnode bit is the bit at the left subnode position corresponding to the root node bit, the second target subnode bit is the bit at the left subnode position corresponding to the first target subnode bit. When the first target subnode bit is the bit at the right subnode position corresponding to the root node bit, the second target subnode bit is the bit at the right subnode position corresponding to the first target subnode bit.

[0168] In step 710, the child node bit is used as the root node bit, and the step of applying the dual-bit phase shift gate between the child node bits corresponding to the root node bit to obtain the phase shift gate subcircuit is performed until the child node bit becomes a leaf node bit.

[0169] The leaf node bit refers to the bit at the leaf node position in the binary tree.

[0170] Specifically, after obtaining the interchange gate sub-circuit, the electronic device determines whether the child node bit is a leaf node bit. When the child node bit is not a leaf node bit, the child node bit is used as the root node bit, and the step of applying the dual-bit phase shift gate between the child node bits corresponding to the root node bit to obtain the phase shift gate sub-circuit is returned. That is, the electronic device performs iteration, uses the child node bit as the parent node bit, and then applies the dual-bit phase shift gate between the two child node bits of the parent node bit to obtain the phase shift gate sub-circuit, until the child node bit is a leaf node bit and the iteration is completed. At this time, each phase shift gate sub-circuit and each interchange gate sub-circuit are obtained.

[0171] Step 712: Apply the two-bit phase shift gate under the path constraint to the leaf node bits corresponding to the parent node bits in the target bit set to obtain a leaf phase shift gate sub-circuit, and apply the single-bit phase shift gate to the leaf node bits to obtain a single-bit phase shift sub-circuit.

[0172] The parent node bit refers to the bit at the parent node position corresponding to the leaf node position. The leaf phase-shift gate subcircuit is a circuit obtained by applying a two-bit phase-shift gate under path constraints between the leaf node bits corresponding to the parent node bit. The single-bit phase-shift subcircuit is a circuit obtained by applying a single-bit phase-shift gate to the leaf node bit.

[0173] Specifically, the electronic device then determines that the child node bit is a leaf node bit. At this time, the iteration is completed, and then the leaf node bit is processed, that is, the dual-bit phase shift gate under the path constraint is applied between the leaf node bits corresponding to the parent node bit in the target bit set to obtain a leaf phase shift gate sub-circuit, and the single-bit phase shift gate is applied to the leaf node bit to obtain a single-bit phase shift sub-circuit.

[0174] Step 714 , combining the flip gate sub-circuit, the phase shift gate sub-circuit, the swap gate sub-circuit, the leaf phase shift gate sub-circuit, and the single-bit phase shift sub-circuit into a prepared circuit.

[0175] The prepared circuit refers to the prepared circuit corresponding to the generated initial vector. When it is necessary to generate a prepared circuit for another classical data vector, the parameters in the prepared circuit are updated using the other classical data vector to obtain the prepared circuit corresponding to the other classical data vector.

[0176] Specifically, the electronic device combines a flip gate subcircuit, a phase shift gate subcircuit, a swap gate subcircuit, a leaf phase shift gate subcircuit and a single-bit phase shift subcircuit to obtain a prepared circuit.

[0177] The above-mentioned preparation circuit generation method determines the target bit set under the binary tree constraint, applies a single-bit flip gate to the first target sub-node bit corresponding to the root node bit in the target bit set, and obtains a flip gate sub-circuit; applies a two-bit phase shift gate to the sub-node bits corresponding to the root node bit, and obtains a phase shift gate sub-circuit; applies a two-bit swap gate to the first target sub-node bit and the second target sub-node bit, and obtains a swap gate sub-circuit, wherein the second target sub-node bit is a sub-node bit of the first target sub-node bit; uses the sub-node bit as the root node bit, and returns the result of applying the two-bit phase shift gate to the sub-node bit corresponding to the root node bit. The steps of obtaining a phase shift gate subcircuit are executed between the child node bits until the child node bit is a leaf node bit; the dual-bit phase shift gate under the path constraint is applied to the leaf node bits corresponding to the parent node bit in the target bit set to obtain a leaf phase shift gate subcircuit, and the single-bit phase shift gate is applied to the leaf node bit to obtain a single-bit phase shift subcircuit; the flip gate subcircuit, the phase shift gate subcircuit, the interchange gate subcircuit, the leaf phase shift gate subcircuit and the single-bit phase shift subcircuit are combined into a preparation circuit, thereby effectively reducing the circuit depth of the preparation circuit, and then effectively reducing the preparation time and improving the operation efficiency of the calculation.

[0178] In one embodiment, step 702, i.e., obtaining a two-bit swap gate and a two-bit phase shift gate under path constraints, includes:

[0179] A single-bit gate and a controllable NOT gate under path restriction are obtained; a double-bit swap gate and a double-bit phase shift gate under path restriction are combined based on the single-bit gate and the controllable NOT gate under path restriction.

[0180] The single-bit gate refers to a gate that operates on one bit, including but not limited to a single-bit flip gate, a single-bit phase shift gate, etc. The controlled NOT gate under path restriction refers to a CNOT gate under path restriction.

[0181] Specifically, the electronic device can obtain a single-bit gate and a controllable NOT gate under path constraints from a database, and then combine the single-bit gate and the controllable NOT gate under path constraints to obtain a double-bit swap gate and a double-bit phase shift gate under path constraints.

[0182] In one embodiment, the number of bits in the target bit set is , n is a positive integer greater than or equal to 1. Specifically, the electronic device obtains -bit, then according to -bit to obtain the auxiliary bit, and then according to -bits and auxiliary bits are obtained under the binary tree restriction bits, that is, the target bit set is obtained, and then the target bit set is generated -Preparation circuit can be prepared -Bit Status .

[0183] In one embodiment, Figure 8 As shown, the circuit generation method further includes:

[0184] Step 802, when n is 1, determine three bits under the binary tree constraint;

[0185] Step 804: Apply a single-bit flip gate to the first target leaf node bit corresponding to the root node bit among the three bits to obtain a flip gate subcircuit.

[0186] Step 806 , applying a two-bit phase shift gate between the leaf node bits corresponding to the root node bit to obtain a phase shift gate subcircuit;

[0187] Step 808: Apply a single-bit phase shift gate to the leaf node bit to obtain a single-bit phase shift sub-circuit.

[0188] Step 810: Combine the flip gate sub-circuit, the phase shift gate sub-circuit, and the single-bit phase shift sub-circuit into a preparation circuit corresponding to three bits.

[0189] Specifically, when n is 1, a 2-bit circuit is generated to prepare a 2-bit state. At this point, the electronic device obtains one auxiliary bit and two bits, determining three bits within the binary tree constraints. The electronic device then applies a single-bit flip gate to the first target leaf node bit corresponding to the root node bit of the three bits, generating a flip gate subcircuit. If the child node bit is already a leaf node bit, the leaf node bit is directly processed. A two-bit phase shift gate is applied between the leaf node bits corresponding to the root node bit, generating a phase shift gate subcircuit. A single-bit phase shift gate is then applied to the leaf node bit, generating a single-bit phase shift subcircuit. Finally, the flip gate subcircuit, phase shift gate subcircuit, and single-bit phase shift subcircuit are combined to obtain the prepared circuit for n = 1. When n is greater than 1, a two-bit swap gate is applied between the parent node bit and the child node bit, followed by a two-bit phase shift gate applied between the child node bits corresponding to the parent node bit. This process is then repeated iteratively to ultimately obtain the prepared circuit.

[0190] In one embodiment, the circuit depth of the flip gate subcircuit is 1; the circuit depth of the phase shift gate subcircuit is O(1); the circuit depth of the swap gate subcircuit is 3; the circuit depth of the leaf phase shift gate subcircuit is O(1); and the circuit depth of the single-bit phase shift subcircuit is 1. The method further includes:

[0191] The circuit depth of the prepared circuit is determined based on the circuit depths corresponding to the flip gate subcircuit, the phase shift gate subcircuit, the interchange gate subcircuit, the leaf phase shift gate subcircuit and the single-bit phase shift subcircuit respectively; wherein the circuit depth is O(n).

[0192] Specifically, the flip gate subcircuit contains only one single-bit flip gate, so the circuit depth is 1. Under the path restriction of length 3, the circuit depth of the phase shift gate subcircuit is O(1), and the length 3 means that the path length formed by the root node bit and the two child node bits is 3. From the circuit implementation, it can be seen that the circuit depth of the interchange gate subcircuit is 3. Because under the binary tree restriction, the path restrictions formed by the root node bit and the two child node bits do not intersect, so the two-bit phase shift gate on the right can be implemented in parallel, and the depth is still O(1). The single-bit phase shift subcircuit is composed of single-bit gates acting on different bits, so the circuit depth is 1. The circuit depth of the final prepared circuit is O(n). That is, the depth of the unary coded preparation circuit generated in this application under the binary tree restriction is linear depth. This application allows only CNOT gates to act on two bits with connected edges in the binary tree, that is, when the circuit is under the binary tree restriction, any unary coded -Bit Status can be represented by a circuit with a depth of of -bit circuit preparation. In this application, only arbitrary single-bit gates and CNOT gates are allowed in the circuit. That is, the prepared circuit generated by this application significantly reduces the circuit depth.

[0193] In one embodiment, the first target subnode bit includes a first left subnode bit, and the second target subnode bit includes a second left subnode bit;

[0194] Step 704: Apply a single-bit flip gate to the first target child node bit corresponding to the root node bit in the target bit set to obtain a flip gate subcircuit, including the following steps:

[0195] A single-bit flip gate is applied to the first left child node bit corresponding to the root node bit in the target bit set to obtain a flip gate subcircuit.

[0196] The first left child node bit refers to the bit at the left node position in the child node corresponding to the root node bit.

[0197] Specifically, the electronic device may apply a single-bit flip gate to the first left subnode bit to obtain a flip gate subcircuit.

[0198] Step 708: Apply a two-bit swap gate between the first target sub-node bit and the second target sub-node bit to obtain a swap gate sub-circuit, including the following steps:

[0199] A two-bit swap gate is applied between the first left child node bit and the second left child node bit to obtain a swap gate subcircuit.

[0200] The second left child node bit refers to the bit at the left node position in the child node corresponding to the first left child node bit.

[0201] Specifically, the electronic device may apply a two-bit swap gate between the first left subnode bit and the second left subnode bit to obtain a swap gate subcircuit.

[0202] In one embodiment, the first target subnode bit includes a first right subnode bit, and the second target subnode bit includes a second right subnode bit;

[0203] Step 704: Apply a single-bit flip gate to the first target child node bit corresponding to the root node bit in the target bit set to obtain a flip gate subcircuit, including:

[0204] A single-bit flip gate is applied to the first right child node bit corresponding to the root node bit in the target bit set to obtain a flip gate subcircuit.

[0205] The first right child node bit refers to the bit at the right node position in the child node corresponding to the root node bit.

[0206] Specifically, the electronic device may apply a single-bit flip gate to the first right subnode bit to obtain a flip gate subcircuit.

[0207] Step 708: Apply a two-bit swap gate between the first target sub-node bit and the second target sub-node bit to obtain a swap gate sub-circuit, including:

[0208] A two-bit swap gate is applied between the first right child node bit and the second right child node bit to obtain a swap gate subcircuit.

[0209] The second right child node bit refers to the bit at the right node position in the child node corresponding to the first right child node bit.

[0210] Specifically, when the electronic device applies a two-bit swap gate to a target subnode bit, it is necessary to apply the two-bit swap gate between subnode bits at the same position as the target subnode bit to ensure the correctness of the obtained swap gate subcircuit.

[0211] In the above embodiment, when the electronic device applies the single-bit flip gate to the bit of the child node, it applies the double-bit swap gate to the bits of the same-direction nodes, thereby ensuring the correctness of the obtained swap gate subcircuit.

[0212] In a specific embodiment, the specific definition of the unary encoding state preparation problem under the binary tree constraint is as follows: Given any The complex vector , given the initial state ,preparation The status of the bit.

[0213]

[0214] in Indicates that the bit value labeled x is 1, and the values of other positions are 0. And the CNOT gate in the circuit can only act on two bits that have an edge in the binary tree.

[0215] The construction of the unary encoding state preparation circuit under the binary tree constraint is described as follows:

[0216] First, under the binary tree restriction Bits are numbered:

[0217] 1. The bit mark on the root node of the binary tree is ,in Represents an empty string. At this time, the root node of the binary tree is at level 0.

[0218] 2. For any and , on the kth level of the binary tree, bits The left child of , the right child node is marked as .

[0219] The initial state of all the above bits is . Any unary state can be as follows:

[0220]

[0221] in and .for and ,definition .

[0222] Then, a circuit is generated for the unary encoding state under the binary tree constraint. The construction process is as follows:

[0223] Step 0:

[0224] In Bit Top-acting single-bit gate .

[0225] Step 1:

[0226] Step 1.1, in the path Restricted effect ,in and .

[0227] Step 1.2, in and Upper acting exchange gate ,exist and Upper acting exchange gate .

[0228] Step 2:

[0229] Step 2.1, in the path Restricted effect ,in and In the path Restricted effect ,in and .

[0230] Step 2.2, in and Upper acting exchange gate ,exist and Upper acting exchange gate ,exist and Upper acting exchange gate ,exist and Upper acting exchange gate .

[0231] step :

[0232] step , for all , in the path Restricted effect ,in and .

[0233] step , for all ,exist and Upper acting exchange gate ,exist and Upper acting exchange gate .

[0234] Step n:

[0235] step For all , in the path Restricted effect ,in and .

[0236] step For all ,exist Upper effect .

[0237] The correctness of the circuit structure for preparing the unary encoding state under the restriction of the binary tree is explained above. According to the above structure, we can know that:

[0238]

[0239]

[0240]

[0241]

[0242] Finally, the state of the unary code is obtained, so the correctness of the circuit is guaranteed.

[0243] The circuit depth of the above circuit structure for preparing the unary encoding state under the binary tree constraint is as follows:

[0244] 1. Step 0: Contains only one X gate and the circuit depth is 1.

[0245] 2. Step 1: From the circuit implementation of the two-bit revolving gate under path restriction in the implementation of the four sub-circuits in this application, it can be seen that step 1.1 is under the path restriction of length 3. The depth can be From the implementation of the two-bit swap gate in the implementation of the four sub-circuits in this application, it can be seen that step 1.2 can be implemented by a circuit with a depth of 3.

[0246] 3. Steps : For all From the circuit implementation of the dual-bit rotating gate under path restriction in the implementation of the four sub-circuits in this application, it can be seen that in the path Under restrictions The gate can be And since these path constraints are disjoint, the steps All two-bit revolving doors in can be implemented in parallel, and the depth is still From the implementation of the two-bit swap gate in the four sub-circuits in this application, it can be seen that the steps It can be implemented by a circuit with a depth of 3.

[0247] 4. Step n: For all From the circuit implementation of the dual-bit rotating gate under path restriction in the implementation of the four sub-circuits in this application, it can be seen that in the path Under restrictions The gate can be And since these path constraints are disjoint, the steps All two-bit revolving doors in can be implemented in parallel, and the depth is still . Due to the steps It is composed of single-bit gates acting on different bits, so the circuit depth is 1.

[0248] In summary, the circuit depth of the unary coded state preparation circuit is O(n).

[0249] In one embodiment, Figure 9 As shown, after step 714, that is, after combining the flip gate sub-circuit, the phase shift gate sub-circuit, the swap gate sub-circuit, the leaf phase shift gate sub-circuit, and the single-bit phase shift sub-circuit into a prepared circuit, the following further includes:

[0250] Step 902: Obtain target data vector.

[0251] The target data vector refers to a vector corresponding to the target data, which is classical data. The classical data can be text data, image data, video data, voice data, etc. The target data is the data for which a corresponding state needs to be prepared.

[0252] Specifically, the electronic device obtains the target data vector to be prepared. The electronic device may obtain the target data vector from a database, a terminal, or a service provider.

[0253] Step 904 : Determine a bit operator based on the target data vector, and update the bit gates in the preparation circuit based on the bit operator to obtain a target preparation circuit corresponding to the target data vector.

[0254] The bit operator is obtained by determining the parameters corresponding to the bit gate based on the target data vector. Bit operators include but are not limited to a dual-bit phase shift operator and a single-bit phase shift operator. The dual-bit phase shift operator is obtained by determining the phase shift parameters corresponding to the dual-bit phase shift gate based on the target data vector. The single-bit phase shift operator is obtained by determining the phase shift parameters corresponding to the single-bit phase shift gate based on the target data vector. The target preparation circuit refers to the preparation circuit corresponding to the target data vector and is used to prepare the state corresponding to the target data vector.

[0255] Specifically, the electronic device determines a bit operator based on the target data vector and then uses the bit operator to update the bit gates in the prepared circuit to obtain the target prepared circuit corresponding to the target data vector. That is, the electronic device replaces the same bit gates in the prepared circuit with the bit operator corresponding to the target data vector, thereby obtaining the prepared circuit after the gates are updated, i.e., obtaining the target prepared circuit corresponding to the target data vector.

[0256] Step 906: Input the preset initial state into the target preparation circuit for preparation to obtain the state corresponding to the target data vector.

[0257] The preset initial state refers to a pre-set initial state, which can be .

[0258] Specifically, the electronic device inputs a preset initial state into a target preparation circuit, and the target preparation circuit uses a bit operator to perform operations, and finally obtains a state corresponding to the output target data vector.

[0259] In the above embodiment, a target data vector is used to determine a bit operator, and a bit gate in the preparation circuit is updated based on the bit operator to obtain a target preparation circuit corresponding to the target data vector. A preset initial state is then input into the target preparation circuit for preparation to obtain the state corresponding to the target data vector. In other words, by using a sub-bit operator to update the preparation circuit to obtain the target preparation circuit, and then performing preparation, the efficiency of obtaining the state corresponding to the target data vector is improved.

[0260] In one embodiment, Figure 10 As shown, the circuit generation method further includes:

[0261] Step 1002: Obtain recommendation preference data vector.

[0262] The recommendation preference data vector refers to a vector corresponding to the recommendation preference data, and the recommendation preference data is used to represent the preference information of the object to be recommended.

[0263] Specifically, the electronic device may obtain the recommendation preference data from the recommendation service system, and then vectorize the recommendation preference data to obtain a recommendation preference data vector.

[0264] Step 1004 : determining a bit operator based on the recommended preference data vector, and updating a bit gate in the preparation circuit based on the bit operator to obtain a recommended preparation circuit corresponding to the recommended preference data vector.

[0265] Among them, the recommendation preparation circuit is a circuit used to prepare the corresponding state of the recommendation preference data vector.

[0266] Specifically, the electronic device uses the recommended preference data vector to calculate a bit operator corresponding to the recommended preference data vector, including but not limited to a dual-bit phase shift operator and a single-bit phase shift operator. The bit operator is then used to update the bit gates in the preparation circuit to obtain the recommended preparation circuit corresponding to the recommended preference data vector. That is, the electronic device replaces the same bit gates in the preparation circuit with the bit operator corresponding to the recommended preference data vector, thereby obtaining the preparation circuit with updated gates, i.e., the recommended preparation circuit corresponding to the recommended preference data vector.

[0267] Step 1006: Input the preset initial state into the recommendation preparation circuit for preparation to obtain the state corresponding to the recommendation preference data vector.

[0268] The preset initial state refers to a pre-set initial state, which can be .

[0269] Specifically, the electronic device inputs a preset initial state into the recommendation preparation circuit, and the recommendation preparation circuit uses a bit operator to perform operations, and finally obtains a state corresponding to the output recommendation preference data vector.

[0270] Step 1008 , performing calculations based on the state corresponding to the recommended preference data vector and the singular value estimation algorithm circuit to obtain a target state, and performing measurements based on the target state to obtain a recommendation result corresponding to the recommended preference data vector.

[0271] The singular value estimation algorithm circuit refers to the circuit corresponding to the singular value estimation algorithm. The target state refers to the state output by the singular value estimation algorithm circuit after calculating the state corresponding to the recommendation preference data vector. Measurement will cause collapse, turning uncertainty into certainty. Measurement can obtain the certain value after collapse. The recommendation result corresponding to the recommendation preference data vector refers to the result of whether the recommendation is made corresponding to the recommendation preference data vector, and the recommendation result can include whether the recommendation is made or not.

[0272] Specifically, the electronic device inputs the state corresponding to the recommendation preference data vector into a singular value estimation algorithm circuit for calculation, obtaining an output target state. The electronic device then measures the target state, i.e., performs a square operation, to obtain a recommendation result corresponding to the recommendation preference data vector. If the recommendation result is a recommendation, the electronic device can send the recommendation information to the terminal to which the recommendation preference data corresponds. If the recommendation result is a non-recommendation, no processing is performed, i.e., the recommendation information does not need to be sent to the terminal to which the recommendation preference data corresponds.

[0273] In the above embodiment, the recommended preference data vector is prepared using a recommendation preparation circuit to obtain the state corresponding to the recommended preference data vector, and then a singular value estimation algorithm circuit is used to perform calculations to obtain the target state. Based on the target state, measurements are performed to obtain the recommendation result corresponding to the recommended preference data vector, thereby improving the efficiency of obtaining the recommendation result.

[0274] In a specific embodiment, in a recommendation system, the classic data is the preference matrix Before executing the recommendation system, each row of data in the preference matrix needs to be Load to the corresponding state Among them Represents a set of orthogonal bases. In addition to recommendation systems, algorithms such as support vector machines for solving linear equations, clustering algorithms, and Hamiltonian simulations also require converting classical data into data by preparing circuits.

[0275] In one embodiment, Figure 11 As shown, a preparation method is provided, which is applied to Figure 1 The electronic device in FIG is taken as an example to illustrate, including the following steps:

[0276] Step 1102 : Obtain a target data vector, and based on the target data vector, obtain a target single-bit flip gate, a target single-bit phase shift gate, a target double-bit swap gate, and a target double-bit phase shift gate under path constraints.

[0277] The target data vector refers to the vector corresponding to the target data, which is classical data. This classical data can be text data, image data, video data, voice data, etc. The target data is the data for which a corresponding state needs to be prepared. The target single-bit flip gate refers to the single-bit flip gate corresponding to the target data vector. The target single-bit phase shift gate refers to the single-bit phase shift gate corresponding to the target data vector. The target double-bit swap gate refers to the double-bit swap gate corresponding to the target data vector. The target double-bit phase shift gate refers to the double-bit phase shift gate corresponding to the target data vector.

[0278] Specifically, the electronic device obtains a target data vector to be prepared. The electronic device may obtain the target data vector from a database. Alternatively, the electronic device may obtain the target data vector uploaded by a terminal. Alternatively, the electronic device may obtain the target data vector from a service provider. Based on the target data vector, a target single-bit flip gate, a target single-bit phase shift gate, a target double-bit swap gate, and a target double-bit phase shift gate under path constraints are obtained.

[0279] Step 1102 , determine a target bit set under the binary tree constraint, apply a target single-bit flip gate to the first target child node bit corresponding to the root node bit in the target bit set, and obtain a target flip gate subcircuit.

[0280] The target flip gate subcircuit refers to a circuit obtained by applying a target single-bit flip gate to the first target subnode bit.

[0281] Specifically, the electronic device obtains each bit and uses it to determine a target bit set within the binary tree constraint. A target single-bit flip gate is then applied to the first target child node bit corresponding to the root node bit in the target bit set, resulting in a target flip gate subcircuit. Specifically, the target single-bit flip gate is implemented on the first target child node bit corresponding to the root node bit in the target bit set.

[0282] Step 1104 : Apply the target two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain a target phase shift gate subcircuit.

[0283] The target phase shift gate subcircuit is a circuit obtained by applying the target two-bit phase shift gate to the bit between the bit at the left child node position and the bit at the right child node position of the root node bit.

[0284] Specifically, the electronic device applies a path-constrained two-bit phase-shift gate between the child node bits corresponding to the root node bit, thereby obtaining a target phase-shift gate subcircuit. Specifically, the two-bit phase-shift gate is implemented between the bit at the left child node and the bit at the right child node. Since the two-bit phase-shift gate is implemented by combining a single-bit gate and a path-constrained CNOT gate, the phase-shift gate subcircuit is obtained by combining a path-constrained CNOT gate between the bit at the left child node and the root node bit, a path-constrained CNOT gate between the bit at the right child node and the root node bit, and a single-bit gate applied to the bit at the left child node, the bit at the right child node, and the root node bit.

[0285] Step 1106 , applying a target two-bit swap gate between the first target sub-node bit and the second target sub-node bit to obtain a target swap gate sub-circuit, wherein the second target sub-node bit is a sub-node bit of the first target sub-node bit.

[0286] The target swap gate subcircuit refers to a circuit obtained by applying a target two-bit swap gate between the first target subnode bit and the second target subnode bit.

[0287] Specifically, the electronic device applies the target two-bit swap gate between the first target sub-node bit and the second target sub-node bit to obtain a target swap gate sub-circuit, that is, the electronic device implements the target two-bit swap gate between the first target sub-node bit and the second target sub-node bit.

[0288] In step 1108, the child node bit is used as the root node bit, and the target two-bit phase shift gate is applied between the child node bits corresponding to the root node bit to obtain the target phase shift gate subcircuit. This step is repeated until the child node bit becomes a leaf node bit.

[0289] Specifically, the electronic device uses the child node bit as the root node bit and returns to the step of applying the target two-bit phase-shift gate between the child node bits corresponding to the root node bit to obtain the target phase-shift gate subcircuit. This step is repeated until the child node bit becomes a leaf node bit. At this point, the electronic device completes the iteration. If the child node bit is not a leaf node bit, the iteration continues. Upon completion of the iteration, the electronic device obtains each target phase-shift gate subcircuit and each target swap gate subcircuit.

[0290] Step 1110, the target dual-bit phase shift gate under the path constraint is applied between the leaf node bits corresponding to the parent node bits in the target bit set to obtain the target leaf phase shift gate sub-circuit, and the target single-bit phase shift gate is applied to the leaf node bit to obtain the target single-bit phase shift sub-circuit.

[0291] The target leaf phase shift gate subcircuit is a circuit obtained by applying a target two-bit phase shift gate to leaf node bits corresponding to parent node bits under path constraints. The single-bit phase shift subcircuit is a circuit obtained by applying a target single-bit phase shift gate to leaf node bits.

[0292] Specifically, when the electronic device determines that a child node bit is a leaf node bit, it applies the target dual-bit phase shift gate under the path constraint between the leaf node bits corresponding to the parent node bit in the target bit set to obtain a target leaf phase shift gate sub-circuit, and applies the target single-bit phase shift gate to the leaf node bit to obtain a target single-bit phase shift sub-circuit.

[0293] Step 1112: Combine the target flip gate subcircuit, the target phase shift gate subcircuit, the target swap gate subcircuit, the target leaf phase shift gate subcircuit, and the target single-bit phase shift subcircuit into a target preparation circuit corresponding to the target data vector.

[0294] The target preparation circuit corresponding to the target data vector refers to the preparation circuit corresponding to the generated target data vector.

[0295] Specifically, the electronic device combines the target flip gate subcircuit, the target phase shift gate subcircuit, the target interchange gate subcircuit, the target leaf phase shift gate subcircuit and the target single-bit phase shift subcircuit into a target preparation circuit corresponding to the target data vector.

[0296] Step 1114: input the preset initial state into the target preparation circuit for preparation to obtain the state corresponding to the target data vector.

[0297] The preset initial state refers to a pre-set initial state, which can be .

[0298] Specifically, the electronic device inputs a preset initial state into a target preparation circuit, and the target preparation circuit uses a bit operator to perform operations, and finally obtains a state corresponding to the output target data vector.

[0299] The above preparation method obtains the target single-bit flip gate, target single-bit phase offset gate, target double-bit swap gate and target double-bit phase offset gate under path restriction corresponding to the target data vector, and then uses the target single-bit flip gate, target single-bit phase offset gate, target double-bit swap gate and target double-bit phase offset gate under path restriction to generate the target preparation circuit corresponding to the target data vector, thereby effectively reducing the circuit depth of the preparation circuit, and then inputting the preset initial state into the target preparation circuit for preparation to obtain the state corresponding to the target data vector, thereby effectively reducing the preparation time, improving the calculation operation efficiency, and thus improving the preparation efficiency.

[0300] In a specific embodiment, the generation of the binary code state preparation circuit is restricted by the binary tree. Specifically, the vector to be prepared is obtained as follows:

[0301]

[0302] The two-bit operator corresponding to the vector to be prepared is obtained as follows:

[0303]

[0304] like Figure 12 As shown in FIG, a schematic diagram of the circuit implementation of the unary encoding state preparation corresponding to the preparation vector is shown, specifically:

[0305] Step 0: In Bit Upper effect Door.

[0306] Step 1:

[0307] Step 1.1, in the path Restricted implementation Two-bit revolving door .

[0308] Step 1.2, while Upper effect ,exist Upper effect .

[0309] Step 2:

[0310] Step 2.1, while in the path Restricted implementation Two-bit revolving door , in the path Restricted implementation Two-bit revolving door .

[0311] Step 2.2, while Upper effect ,exist Upper effect ,exist Upper effect ,exist Upper effect .

[0312] Step 3:

[0313] Step 3.1, while in the path Restricted implementation Two-bit revolving door , in the path Restricted implementation Two-bit revolving door , in the path Restricted implementation Two-bit revolving door , in the path Restricted implementation Two-bit revolving door .

[0314] Step 3.1 For all , while in Bit Top-acting single-bit gate .

[0315] In summary, the unary encoding state preparation circuit corresponding to the vector to be prepared is obtained, and the circuit depth of the unary encoding state preparation circuit is .

[0316] It should be understood that, although the various steps in the flowcharts involved in the various embodiments described above are displayed in sequence according to the instructions of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowcharts involved in the various embodiments described above can include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0317] Based on the same inventive concept, the embodiments of the present application also provide a circuit generation device, or a method and device for implementing the aforementioned circuit generation method. The solution to the problem provided by the device is similar to the solution described in the aforementioned method. Therefore, the specific limitations of one or more circuit generation devices or device embodiments provided below can be found in the above-mentioned limitations of the circuit generation method or method, and will not be repeated here.

[0318] In one embodiment, Figure 13 As shown, a circuit preparation generating device 1300 is provided, comprising: an acquisition module 1302, a flip gate function module 1304, a phase shift gate function module 1306, an interchange gate function module 1308, an iteration module 1310, a leaf node function module 1312, and a combination module 1314, wherein:

[0319] An acquisition module 1302 is configured to acquire a single-bit flip gate, a single-bit phase shift gate, a double-bit swap gate, and a double-bit phase shift gate under path constraints;

[0320] A flip gate application module 1304 is configured to determine a target bit set under the binary tree constraint and apply a single-bit flip gate to the first target child node bit corresponding to the root node bit in the target bit set to obtain a flip gate subcircuit.

[0321] A phase shift gate application module 1306 is configured to apply a two-bit phase shift gate between the child node bits corresponding to the root node bit to obtain a phase shift gate subcircuit;

[0322] A swap gate application module 1308 is configured to apply a two-bit swap gate between a first target sub-node bit and a second target sub-node bit to obtain a swap gate sub-circuit, wherein the second target sub-node bit is a sub-node bit of the first target sub-node bit;

[0323] Iterative module 1310 is configured to use the child node bit as the root node bit and return to the step of applying the two-bit phase shift gate between the child node bits corresponding to the root node bit to obtain the phase shift gate subcircuit until the child node bit becomes a leaf node bit.

[0324] The leaf node action module 1312 is configured to apply a two-bit phase shift gate under path constraints to the leaf node bits corresponding to the parent node bits in the target bit set to obtain a leaf phase shift gate subcircuit, and to apply a single-bit phase shift gate to the leaf node bits to obtain a single-bit phase shift subcircuit.

[0325] The combining module 1314 is used to combine the flip gate subcircuit, the phase shift gate subcircuit, the swap gate subcircuit, the leaf phase shift gate subcircuit and the single-bit phase shift subcircuit into a prepared circuit.

[0326] In one embodiment, the acquisition module 1302 is further configured to acquire a single-bit gate and a controllable NOT gate under path constraints; and to combine the single-bit gate and the controllable NOT gate under path constraints into a double-bit swap gate and a double-bit phase shift gate under path constraints.

[0327] In one embodiment, the number of bits in the target bit set is , n is a positive integer greater than or equal to 1.

[0328] In one embodiment, the circuit generation device 1300 is prepared, further comprising:

[0329] A generation module is used to determine three bits under the binary tree constraint when n is 1; apply a single-bit flip gate to the first target leaf node bit corresponding to the root node bit among the three bits to obtain a flip gate subcircuit; apply a two-bit phase shift gate between the leaf node bits corresponding to the root node bit to obtain a phase shift gate subcircuit; apply a single-bit phase shift gate to the leaf node bit to obtain a single-bit phase shift subcircuit; and combine the flip gate subcircuit, the phase shift gate subcircuit, and the single-bit phase shift subcircuit into a preparation circuit corresponding to the three bits.

[0330] In one embodiment, the circuit depth of the flip gate sub-circuit is 1; the circuit depth of the phase shift gate sub-circuit is ; The circuit depth of the interchange gate subcircuit is 3; the circuit depth of the leaf phase shift gate subcircuit is The circuit depth of the single-bit phase shift subcircuit is 1; the circuit generation device 1300 further includes:

[0331] The circuit depth determination module is used to determine the circuit depth of the prepared circuit based on the circuit depths corresponding to the flip gate subcircuit, the phase shift gate subcircuit, the interchange gate subcircuit, the leaf phase shift gate subcircuit and the single-bit phase shift subcircuit respectively; wherein the circuit depth is .

[0332] In one embodiment, the first target subnode bit includes a first left subnode bit, and the second target subnode bit includes a second left subnode bit;

[0333] The flip gate application module 1304 is further configured to apply a single-bit flip gate to the first left child node bit corresponding to the root node bit in the target bit set to obtain a flip gate subcircuit;

[0334] The swap gate application module 1308 is further configured to apply a two-bit swap gate between the first left subnode bit and the second left subnode bit to obtain a swap gate subcircuit.

[0335] In one embodiment, the first target subnode bit includes a first right subnode bit, and the second target subnode bit includes a second right subnode bit;

[0336] The flip gate application module 1304 is further configured to apply a single-bit flip gate to the first right child node bit corresponding to the root node bit in the target bit set to obtain a flip gate subcircuit.

[0337] The swap gate application module 1308 is further configured to apply a two-bit swap gate between the first right subnode bit and the second right subnode bit to obtain a swap gate subcircuit.

[0338] In one embodiment, the circuit generation device 1300 is prepared, further comprising:

[0339] A preparation module is used to obtain a target data vector; determine a bit operator based on the target data vector, update a bit gate in the preparation circuit based on the bit operator, and obtain a target preparation circuit corresponding to the target data vector; input a preset initial state into the target preparation circuit for preparation to obtain a state corresponding to the target data vector.

[0340] In one embodiment, the circuit generation device 1300 is prepared, further comprising:

[0341] The recommendation module is used to obtain a recommendation preference data vector; determine a bit operator based on the recommendation preference data vector, update a bit gate in the preparation circuit based on the bit operator, and obtain a recommendation preparation circuit corresponding to the recommendation preference data vector; input a preset initial state into the recommendation preparation circuit for preparation to obtain a state corresponding to the recommendation preference data vector; perform calculations based on the state corresponding to the recommendation preference data vector and a singular value estimation algorithm circuit to obtain a target state, perform measurements based on the target state, and obtain a recommendation result corresponding to the recommendation preference data vector.

[0342] In one embodiment, Figure 14 As shown, a preparation device 1400 is provided, comprising: a target acquisition module 1402, a target flip gate action module 1404, a target phase shift gate action module 1406, a target swap gate action module 1408, a target iteration module 1410, a target leaf node action module 1412, a target combination module 1414, and a preparation module 1416, wherein:

[0343] A target acquisition module 1402 is configured to acquire a target data vector, and acquire a target single-bit flip gate, a target single-bit phase shift gate, a target double-bit swap gate, and a target double-bit phase shift gate under path constraints based on the target data vector;

[0344] A target flip gate application module 1404 is configured to determine a target bit set under the binary tree constraint, apply a target single-bit flip gate to the first target child node bit corresponding to the root node bit in the target bit set, and obtain a target flip gate subcircuit.

[0345] A target phase shift gate application module 1406 is configured to apply a target two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain a target phase shift gate subcircuit;

[0346] a target swap gate application module 1408 for applying a target two-bit swap gate between the first target sub-node bit and the second target sub-node bit to obtain a target swap gate sub-circuit, wherein the second target sub-node bit is a sub-node bit of the first target sub-node bit;

[0347] A target iteration module 1410 is configured to use the child node bit as the root node bit and return to the step of applying the target two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain the target phase shift gate subcircuit until the child node bit becomes a leaf node bit.

[0348] The target leaf node action module 1412 is used for the target leaf node action module to apply the target two-bit phase shift gate under the path constraint to the leaf node bits corresponding to the parent node bits in the target bit set to obtain the target leaf phase shift gate subcircuit, and apply the target single-bit phase shift gate to the leaf node bits to obtain the target single-bit phase shift subcircuit;

[0349] a target combining module 1414, configured to combine the target flip gate subcircuit, the target phase shift gate subcircuit, the target swap gate subcircuit, the target leaf phase shift gate subcircuit, and the target single-bit phase shift subcircuit into a target preparation circuit corresponding to the target data vector;

[0350] The preparation module 1416 is used to input the preset initial state into the target preparation circuit for preparation to obtain the state corresponding to the target data vector.

[0351] The aforementioned circuit generation device or each module within the device may be implemented in whole or in part via software, hardware, or a combination thereof. Each module may be embedded in or independent of a processor within an electronic device in hardware form, or may be stored in a memory within the electronic device in software form, so that the processor can call and execute operations corresponding to each module.

[0352] In one embodiment, an electronic device is provided. The electronic device may be an industrial intelligent device, and its internal structure may be as shown in FIG. Figure 15As shown. The electronic device includes a processor, a memory, an input / output interface (Input / Output, abbreviated as I / O) and a communication interface. The processor, memory and input / output interface are connected via a system bus, and the communication interface is connected to the system bus via the input / output interface. The processor of the electronic device is used to provide computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The database of the electronic device is used to store target data vectors. The input / output interface of the electronic device is used to exchange information between the processor and an external device. The communication interface of the electronic device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a method for generating or preparing a circuit is implemented.

[0353] Those skilled in the art will understand that Figure 15 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the electronic device to which the solution of the present application is applied. The specific electronic device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0354] In one embodiment, a chip is provided, including a fabricated circuit, wherein the fabricated circuit is implemented by the method for generating the fabricated circuit in the present application. The chip can be applied to various smart terminals and vehicle-mounted devices.

[0355] In one embodiment, an electronic device is further provided, including a memory and a processor. The memory stores a computer program, and the processor implements the steps in the above method embodiments when executing the computer program.

[0356] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0357] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0358] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, storage, and display, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For information pushed, the recommended terminal can refuse or conveniently refuse advertising push information, etc.

[0359] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments. In particular, any reference to memory, database, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The databases involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the various embodiments provided herein may be, but are not limited to, general-purpose processors, central processing units (CPUs), graphics processors (GPUs), digital signal processors (DSPs), programmable logic devices (PLDs), computation-based data processing logic devices, and the like.

[0360] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0361] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A method for preparing a circuit, characterized in that: The method comprises: Get single-bit flip gate, single-bit phase shift gate, double-bit swap gate and double-bit phase shift gate under path restriction; Determine a target bit set under the binary tree constraint, apply the single-bit flip gate to the first target child node bit corresponding to the root node bit in the target bit set, and obtain a flip gate subcircuit; Applying the dual-bit phase shift gate between the child node bits corresponding to the root node bit to obtain a phase shift gate subcircuit; Applying the two-bit swap gate between the first target sub-node bit and the second target sub-node bit to obtain a swap gate sub-circuit, wherein the second target sub-node bit is a sub-node bit of the first target sub-node bit; The child node bit is used as the root node bit, and the step of applying the two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain the phase shift gate subcircuit is performed until the child node bit becomes a leaf node bit; Applying the two-bit phase shift gate under path restriction to the leaf node bits corresponding to the parent node bits in the target bit set to obtain a leaf phase shift gate subcircuit, and applying the single-bit phase shift gate to the leaf node bits to obtain a single-bit phase shift subcircuit; The flip gate subcircuit, the phase shift gate subcircuit, the interchange gate subcircuit, the leaf phase shift gate subcircuit and the single-bit phase shift subcircuit are combined into a prepared circuit.

2. The method according to claim 1, characterized in that The obtaining of the two-bit swap gate and the two-bit phase shift gate under path restriction includes: Obtain single-bit gates and controlled NOT gates under path constraints; The single-bit gate and the controllable NOT gate under path restriction are combined to form the double-bit swap gate and the double-bit phase shift gate under path restriction.

3. The method according to claim 1, characterized in that The number of bits in the target bit set is , n is a positive integer greater than or equal to 1.

4. The method according to claim 3, characterized in that The method further comprises: When n is 1, three bits under the binary tree restriction are determined; Applying the single-bit flip gate to the first target leaf node bit corresponding to the root node bit among the three bits to obtain a flip gate subcircuit; Applying the dual-bit phase shift gate between the leaf node bits corresponding to the root node bit to obtain a phase shift gate subcircuit; Applying the single-bit phase shift gate to the leaf node bit to obtain a single-bit phase shift sub-circuit; The flip gate subcircuit, the phase shift gate subcircuit and the single-bit phase shift subcircuit are combined into a preparation circuit corresponding to the three bits.

5. The method according to claim 3, characterized in that The circuit depth of the flip gate subcircuit is 1; the circuit depth of the phase shift gate subcircuit is The circuit depth of the interchange gate subcircuit is 3; the circuit depth of the leaf phase shift gate subcircuit is ; The circuit depth of the single-bit phase shift subcircuit is 1; the method further includes: The circuit depth of the prepared circuit is determined based on the circuit depths corresponding to the flip gate subcircuit, the phase shift gate subcircuit, the interchange gate subcircuit, the leaf phase shift gate subcircuit, and the single-bit phase shift subcircuit; wherein the circuit depth is .

6. The method according to claim 1, characterized in that The first target subnode bit includes a first left subnode bit, and the second target subnode bit includes a second left subnode bit; The method of applying the single-bit flip gate to the first target sub-node bit corresponding to the root node bit in the target bit set to obtain a flip gate sub-circuit includes: Applying the single-bit flip gate to the first left child node bit corresponding to the root node bit in the target bit set to obtain the flip gate subcircuit; The step of applying the dual-bit swap gate between the first target sub-node bit and the second target sub-node bit to obtain a swap gate sub-circuit includes: The dual-bit swap gate is applied between the first left subnode bit and the second left subnode bit to obtain the swap gate subcircuit.

7. The method according to claim 1, characterized in that The first target subnode bit includes a first right subnode bit, and the second target subnode bit includes a second right subnode bit; The method of applying the single-bit flip gate to the first target sub-node bit corresponding to the root node bit in the target bit set to obtain a flip gate sub-circuit includes: Applying the single-bit flip gate to the first right child node bit corresponding to the root node bit in the target bit set to obtain the flip gate subcircuit; The step of applying the dual-bit swap gate between the first target sub-node bit and the second target sub-node bit to obtain a swap gate sub-circuit includes: The two-bit swap gate is applied between the first right subnode bit and the second right subnode bit to obtain the swap gate subcircuit.

8. The method according to claim 1, characterized in that After combining the flip gate subcircuit, the phase shift gate subcircuit, the interchange gate subcircuit, the leaf phase shift gate subcircuit, and the single-bit phase shift subcircuit into a preparation circuit, the method further includes: Get the target data vector; Determining a bit operator based on the target data vector, and updating a bit gate in the preparation circuit based on the bit operator to obtain a target preparation circuit corresponding to the target data vector; The preset initial state is input into the target preparation circuit for preparation to obtain the state corresponding to the target data vector.

9. The method according to claim 1, characterized in that The method further comprises: Obtain recommendation preference data vector; Determining a bit operator based on the recommended preference data vector, and updating a bit gate in the preparation circuit based on the bit operator to obtain a recommended preparation circuit corresponding to the recommended preference data vector; Inputting a preset initial state into the recommendation preparation circuit for preparation to obtain a state corresponding to the recommendation preference data vector; An operation is performed based on the state corresponding to the recommendation preference data vector and a singular value estimation algorithm circuit to obtain a target state, and a measurement is performed based on the target state to obtain a recommendation result corresponding to the recommendation preference data vector.

10. A preparation method, characterized in that: The method comprises: Obtain a target data vector, and obtain a target single-bit flip gate, a target single-bit phase shift gate, a target double-bit swap gate, and a target double-bit phase shift gate under path constraints based on the target data vector; Determine a target bit set under the binary tree constraint, apply the target single-bit flip gate to the first target child node bit corresponding to the root node bit in the target bit set, and obtain a target flip gate subcircuit; Applying the target two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain a target phase shift gate subcircuit; Applying the target two-bit swap gate between the first target sub-node bit and the second target sub-node bit to obtain a target swap gate sub-circuit, wherein the second target sub-node bit is a sub-node bit of the first target sub-node bit; The child node bit is used as the root node bit, and the step of applying the target two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain the target phase shift gate subcircuit is performed until the child node bit becomes a leaf node bit; Applying the target two-bit phase shift gate under the path constraint to the leaf node bits corresponding to the parent node bits in the target bit set to obtain a target leaf phase shift gate subcircuit, and applying the target single-bit phase shift gate to the leaf node bits to obtain a target single-bit phase shift subcircuit; Combining the target flip gate subcircuit, the target phase shift gate subcircuit, the target swap gate subcircuit, the target leaf phase shift gate subcircuit and the target single-bit phase shift subcircuit into a target preparation circuit corresponding to the target data vector; The preset initial state is input into the target preparation circuit for preparation to obtain the state corresponding to the target data vector.

11. A circuit generating device, characterized in that: The device comprises: An acquisition module, used to acquire a single-bit flip gate, a single-bit phase shift gate, a double-bit swap gate, and a double-bit phase shift gate under path constraints; A flip gate action module is used to determine a target bit set under the binary tree constraint, and apply the single-bit flip gate to the first target child node bit corresponding to the root node bit in the target bit set to obtain a flip gate subcircuit; A phase shift gate application module, configured to apply the dual-bit phase shift gate between the child node bits corresponding to the root node bit to obtain a phase shift gate subcircuit; a swap gate action module, configured to apply the dual-bit swap gate between the first target sub-node bit and the second target sub-node bit to obtain a swap gate sub-circuit, wherein the second target sub-node bit is a sub-node bit of the first target sub-node bit; an iterative module, configured to use the child node bit as a root node bit and return to the step of applying the two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain a phase shift gate subcircuit, until the child node bit becomes a leaf node bit; a leaf node action module, configured to apply the two-bit phase shift gate under path restriction to the leaf node bits corresponding to the parent node bits in the target bit set to obtain a leaf phase shift gate subcircuit, and apply the single-bit phase shift gate to the leaf node bits to obtain a single-bit phase shift subcircuit; A combination module is used to combine the flip gate subcircuit, the phase shift gate subcircuit, the interchange gate subcircuit, the leaf phase shift gate subcircuit and the single-bit phase shift subcircuit into a preparation circuit.

12. A preparation device, characterized in that: The device comprises: A target acquisition module is used to acquire a target data vector, and acquire a target single-bit flip gate, a target single-bit phase shift gate, a target double-bit swap gate, and a target double-bit phase shift gate under path constraints based on the target data vector; a target flip gate action module, configured to determine a target bit set under a binary tree constraint, and apply the target single-bit flip gate to the first target child node bit corresponding to the root node bit in the target bit set to obtain a target flip gate subcircuit; a target phase shift gate application module, configured to apply the target two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain a target phase shift gate subcircuit; a target swap gate action module, configured to apply the target two-bit swap gate between the first target sub-node bit and the second target sub-node bit to obtain a target swap gate sub-circuit, wherein the second target sub-node bit is a sub-node bit of the first target sub-node bit; a target iteration module, configured to use the child node bit as a root node bit and return to the step of applying the target two-bit phase shift gate to the child node bits corresponding to the root node bit to obtain a target phase shift gate subcircuit until the child node bit becomes a leaf node bit; a target leaf node action module, configured to apply the target dual-bit phase shift gate under path restriction to the leaf node bits corresponding to the parent node bits in the target bit set to obtain a target leaf phase shift gate subcircuit, and apply the target single-bit phase shift gate to the leaf node bits to obtain a target single-bit phase shift subcircuit; a target combination module, configured to combine the target flip gate subcircuit, the target phase shift gate subcircuit, the target swap gate subcircuit, the target leaf phase shift gate subcircuit, and the target single-bit phase shift subcircuit into a target preparation circuit corresponding to the target data vector; The preparation module is used to input a preset initial state into the target preparation circuit for preparation, so as to obtain a unary encoding state corresponding to the target data vector.

13. A chip comprising a fabrication circuit, characterized in that: The fabricated circuit is realized by the method for producing the fabricated circuit according to any one of claims 1 to 10.

14. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 10 are implemented.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 10 are implemented.

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