Display panel, driving method thereof and display device

Abstract

The invention provides a display panel, a driving method thereof and a display device, which are used for realizing frequency differentiation design of different positions in a display area. The display panel comprises a plurality of data lines and a plurality of sub-pixels, and each sub-pixel comprises a first transistor and a second transistor which are electrically connected between the data lines and a storage capacitor in series; grid electrodes of the first transistor and the second transistor receive a first grid electrode driving signal and a second grid electrode driving signal respectively, in the first mode, the work cycle of the display panel at least comprises a first time period, and in the first time period, when the second grid electrode driving signal received by the first sub-pixel is a second enabling level, the first sub-pixel is switched on; a first gate driving signal received by the first sub-pixel is a first disable level; and when the second gate driving signal received by the second sub-pixel is the second enable level, the first gate driving signal received by the second sub-pixel is the first enable level.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a driving method thereof, and a display device. Background Art

[0002] With the continuous advancement of science and technology, more and more display devices are being widely used in people's daily lives and work, becoming an indispensable tool for people today. Furthermore, with the continuous development of display technology, consumers' requirements for displays are constantly increasing. The ability to achieve frequency differentiation in different locations within the display area has become a research focus for relevant technicians. Summary of the Invention

[0003] In view of this, the present invention provides a display panel and a driving method thereof, and a display device, for realizing frequency differentiation design at different positions in a display area.

[0004] In a first aspect, the present invention provides a display panel comprising a plurality of data lines and a plurality of sub-pixel rows arranged along a first direction, wherein the sub-pixel rows include a plurality of sub-pixels arranged along a second direction, wherein the first direction and the second direction intersect; the sub-pixels include a first transistor, a second transistor, and a storage capacitor; wherein the first transistor and the second transistor are electrically connected in series between the data lines and the storage capacitor; The gate of the first transistor receives a first gate driving signal, The gate of the second transistor receives a second gate driving signal, The operating mode of the display panel includes a first mode. In the first mode, the display panel includes at least a first sub-pixel and a second sub-pixel. The operating cycle of the display panel includes at least a first period. In the first period, When the second gate driving signal received by the first sub-pixel is at the second enable level, the first gate driving signal received by the first sub-pixel is at the first disable level; When the second gate driving signal received by the second sub-pixel is at the second enable level, the first gate driving signal received by the second sub-pixel is at the first enable level; The first enable level refers to a level for controlling the first transistor to be turned on, the first disable level refers to a level for controlling the first transistor to be turned off, and the second enable level refers to a level for controlling the second transistor to be turned on.

[0005] In a second aspect, the present invention provides a method for driving a display panel, wherein the display panel includes a plurality of data lines and a plurality of sub-pixel rows arranged along a first direction, the sub-pixel rows including a plurality of sub-pixels arranged along a second direction, the first direction and the second direction intersecting; the sub-pixels including a first transistor, a second transistor, and a storage capacitor; wherein the first transistor and the second transistor are electrically connected in series between the data lines and the storage capacitor, the gate of the first transistor receives a first gate drive signal, and the gate of the second transistor receives a second gate drive signal. The operating mode of the display panel includes a first mode. In the first mode, the display panel includes at least a first sub-pixel and a second sub-pixel. In the first mode, a working cycle of the display panel includes at least a first period. In the first period, the driving method includes: When the second gate driving signal received by the first sub-pixel is at the second enable level, controlling the first gate driving signal received by the first sub-pixel to be at the first disable level; When the second gate driving signal received by the second sub-pixel is at the second enable level, controlling the first gate driving signal received by the second sub-pixel to be at the first enable level; The first enable level refers to a level for controlling the first transistor to be turned on, the first disable level refers to a level for controlling the first transistor to be turned off, and the second enable level refers to a level for controlling the second transistor to be turned on.

[0006] In a third aspect, the present invention provides a display device comprising the display panel of the present invention.

[0007] Compared with the prior art, the display panel, driving method thereof, and display device provided by the present invention achieve at least the following beneficial effects: The display panel provided by the present invention includes a plurality of data lines and a plurality of sub-pixel rows arranged along a first direction, the sub-pixel rows including a plurality of sub-pixels arranged along a second direction, the first direction and the second direction intersecting; the sub-pixels including a first transistor, a second transistor and a storage capacitor; wherein the first transistor and the second transistor are electrically connected in series between the data line and the storage capacitor; the gate of the first transistor receives a first gate drive signal, and the gate of the second transistor receives a second gate drive signal; the operating mode of the display panel includes a first mode, in which the display panel includes at least a first sub-pixel and a second sub-pixel, and the operating cycle of the display panel includes at least a first time period, in which, when the second gate drive signal received by the first sub-pixel is a second enable level, the first gate drive signal received by the first sub-pixel is a first disable level; when the second gate drive signal received by the second sub-pixel is a second enable level, the first gate drive signal received by the second sub-pixel is a first enable level; wherein the first enable level refers to a level for controlling the first transistor to be turned on, the first disable level refers to a level for controlling the first transistor to be turned off, and the second enable level refers to a level for controlling the second transistor to be turned on. The present invention provides a subpixel comprising a first transistor, a second transistor, and a storage capacitor; wherein the first transistor and the second transistor are electrically connected in series between a data line and the storage capacitor, such that whether the subpixel is charged or not can be determined by both the second gate drive signal and the first gate drive signal. The present invention provides a display panel operating mode comprising a first mode. In the first mode, the display panel comprises at least a first subpixel and a second subpixel, and the display panel operating cycle comprises at least a first period. During the first period, under the control of the first gate drive signal, the data voltage write path of the first subpixel is turned off, and under the control of the first gate drive signal, the data voltage write path of the second subpixel is turned on. Thus, in the first mode, the data refresh frequency of the first subpixel can be lower than the data refresh frequency of the second subpixel, thereby achieving a differentiated design of the data refresh frequency of the first subpixel and the data refresh frequency of the second subpixel. The data refresh frequency of a subpixel refers to the number of times a data voltage is written to the subpixel per unit time. Based on the method provided by the present invention, the data refresh frequency of the first subpixel can be lower than the frequency of the second gate drive signal. That is, without changing the frequency of the second gate drive signal, at least the first subpixel can be driven at a reduced frequency by designing the timing of the first gate drive signal received by the first subpixel. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0009] Figure 1 A schematic diagram of a display panel provided by an embodiment of the present invention; Figure 2 An equivalent circuit diagram of a sub-pixel provided by an embodiment of the present invention; Figure 3 A driving timing diagram of a first sub-pixel and a second sub-pixel in a first mode provided by an embodiment of the present invention; Figure 4 Another operation timing diagram of a first sub-pixel and a second sub-pixel in a first mode provided by an embodiment of the present invention; Figure 5 A schematic diagram of another display panel provided by an embodiment of the present invention; Figure 6 A schematic diagram of another display panel provided by an embodiment of the present invention; Figure 7 A timing diagram of a mode control line provided by an embodiment of the present invention; Figure 8 A timing diagram of a second gate line connected to a first sub-pixel, a second gate line connected to a second sub-pixel, and a gate drive bus provided by an embodiment of the present invention; Figure 9 Another timing diagram of a second gate line connected to a first sub-pixel, a second gate line connected to a second sub-pixel, and a gate drive bus provided by an embodiment of the present invention; Figure 10 A schematic diagram of another display panel provided by an embodiment of the present invention; Figure 11 A timing diagram of an operation of a display panel in a first mode provided by an embodiment of the present invention; Figure 12 Another operating timing diagram of a display panel in the first mode provided by an embodiment of the present invention; Figure 13 A schematic diagram of another display panel provided by an embodiment of the present invention; Figure 14 A timing diagram of a second gate driving signal provided to a first sub-pixel and a second sub-pixel, a gate driving bus connected to the first sub-pixel, and a gate driving bus connected to the second sub-pixel, provided in an embodiment of the present invention; Figure 15Another timing diagram of a second gate driving signal provided to a first sub-pixel and a second sub-pixel, a gate driving bus connected to the first sub-pixel, and a gate driving bus connected to the second sub-pixel, provided in an embodiment of the present invention; Figure 16 for Figure 13 An operating timing diagram of the display panel in the first mode shown; Figure 17 for Figure 13 Another working timing diagram of the display panel in the first mode is shown; Figure 18 A schematic diagram of another display panel provided by an embodiment of the present invention; Figure 19 for Figure 18 An operating timing diagram of the display panel in the first mode shown; Figure 20 A schematic diagram of another display panel provided by an embodiment of the present invention; Figure 21 for Figure 20 An operating timing diagram of the display panel in the first mode shown; Figure 22 A schematic diagram of another display panel provided by an embodiment of the present invention; Figure 23 for Figure 22 An operating timing diagram of the display panel in the first mode shown; Figure 24 A schematic diagram of a first gate control circuit provided by an embodiment of the present invention; Figure 25 A driving timing diagram of another display panel provided by an embodiment of the present invention; Figure 26 A schematic diagram of another display panel provided by an embodiment of the present invention; Figure 27 A schematic diagram of wiring of a display panel provided by an embodiment of the present invention; Figure 28 A schematic diagram of an equivalent circuit of another sub-pixel provided by an embodiment of the present invention; Figure 29 A schematic diagram of another display panel provided by an embodiment of the present invention; Figure 30 A schematic diagram of another display panel provided by an embodiment of the present invention; Figure 31 A schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0010] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0011] It should be understood that the embodiments described are only a portion of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative work are within the scope of protection of the present invention.

[0012] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The singular forms "a", "an", "the" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0013] It should be understood that the term "and / or" as used herein simply describes a relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A alone, A and B together, or B alone. Furthermore, the character " / " in this document generally indicates an "or" relationship between the associated objects.

[0014] The present invention provides a display panel, such as Figure 1 As shown, Figure 1 A schematic diagram of a display panel provided in an embodiment of the present invention includes a plurality of data lines Data, a first gate line 21, a second gate line 22, and a plurality of sub-pixel rows 1 arranged along a first direction h1. The sub-pixel row 1 includes a plurality of sub-pixels 10 arranged along a second direction h2. The first direction h1 and the second direction h2 intersect. Figure 1 As an illustration, the first direction h1 and the second direction h2 are perpendicular to each other.

[0015] For example, Figure 2 As shown, Figure 2 This is an equivalent circuit diagram of a sub-pixel provided in an embodiment of the present invention. The sub-pixel 10 includes a first transistor M1, a second transistor M2, and a storage capacitor Cst. The first transistor M1 and the second transistor M2 are electrically connected in series between a data line Data and the storage capacitor Cst. When both the first transistor M1 and the second transistor M2 are turned on, the signal on the data line Data is written to the storage capacitor Cst through the turned-on first transistor M1 and the turned-on second transistor M2, thereby charging the storage capacitor Cst. When either transistor is turned off, the signal on the data line Data stops being written to the storage capacitor Cst.

[0016] like Figure 2As shown, the first gate line 21 is electrically connected to the gate of the first transistor M1, and the second gate line 22 is electrically connected to the gate of the second transistor M2. The gate of the first transistor M1 receives a first gate drive signal GateV through the first gate line 21, and the gate of the second transistor M2 receives a second gate drive signal GateH through the second gate line 22.

[0017] For example, Figure 1 As shown, the second gate lines 22 are electrically connected to the sub-pixel row 1. When the display panel is working, the plurality of second gate lines 22 sequentially provide the second enable level according to the scanning sequence of the display panel.

[0018] In an embodiment of the present invention, the operating mode of the display panel includes a first mode. Exemplarily, the first mode may be a mode in which at least two sub-pixels in the display panel are driven at different data refresh frequencies.

[0019] In the first mode, if Figure 1 As shown, the display panel includes at least one first sub-pixel 101 and at least one second sub-pixel 102. Figure 3 As shown, Figure 3 An embodiment of the present invention provides a driving timing diagram of a first sub-pixel and a second sub-pixel in a first mode, wherein a duty cycle T of the display panel includes at least a first period P1.

[0020] During the first period P1, when the second gate drive signal GateH_101 received by the first subpixel 101 is at the second enable level, the first gate drive signal GateV_101 received by the first subpixel 101 is at the first disable level; that is, the data voltage write path of the first subpixel 101 is disabled. For example, during the first period P1, the voltage on the storage capacitor Cst of the first subpixel 101 can maintain the data voltage written before the first period P1. That is, this period can be the data voltage retention period for the first subpixel 101.

[0021] In the first time period P1, when the second gate driving signal GateH_102 received by the second sub-pixel 102 is the second enable level, the first gate driving signal GateV_102 received by the second sub-pixel 102 is the first enable level; that is, the data voltage writing path of the second sub-pixel 102 can be turned on, so that the data voltage on the data line Data is written into the storage capacitor Cst through the turned-on first transistor M1 and second transistor M2; that is, this time period can be the data voltage writing period of the second sub-pixel 102.

[0022] Based on this configuration, the data refresh frequency of the first sub-pixel 101 can be lower than the frequency of the second gate drive signal GateH. For example, if the frequency of the second gate drive signal GateH is f0, the data refresh frequency of the first sub-pixel 101 is f1, and the data refresh frequency of the second sub-pixel 102 is f2, based on the configuration provided in this embodiment of the present invention, the following relationship can be achieved: f1 < f2 ≤ f0.

[0023] In the display panel provided by the embodiment of the present invention, the sub-pixel 10 includes the first transistor M1 and the second transistor M2 , so that whether the sub-pixel 10 is charged or not can be determined by both the second gate driving signal GateH and the first gate driving signal GateV.

[0024] In an embodiment of the present invention, the operating mode of the display panel may include a first mode. In the first mode, the display panel includes at least a first sub-pixel 101 and a second sub-pixel 102. The operating cycle T of the display panel includes at least a first period P1. In the first period P1, under the control of a first gate drive signal GateV_101, the data voltage write path of the first sub-pixel 101 is turned off, and under the control of a first gate drive signal GateV_102, the data voltage write path of the second sub-pixel 102 is turned on. Therefore, in the first mode, the data refresh frequency of the first sub-pixel 101 can be lower than the data refresh frequency of the second sub-pixel 102, thereby achieving a differentiated design of the data refresh frequency of the first sub-pixel 101 and the data refresh frequency of the second sub-pixel 102. The data refresh frequency of the sub-pixel 10 refers to the number of times the data voltage is written to the sub-pixel 10 per unit time.

[0025] Based on the method provided in the embodiment of the present invention, there is no need to adjust the frequency of the second gate drive signal GateH, and accordingly, there is no need to adjust the circuit providing the second gate drive signal, so that the data refresh frequency of the first sub-pixel 101 can be lower than the frequency of the second gate drive signal GateH. That is, without changing the frequency of the second gate drive signal GateH, at least the frequency reduction drive of the first sub-pixel 101 can be achieved by designing the timing of the first gate drive signal GateV_1 received by the first sub-pixel 101.

[0026] For example, Figure 3As shown, in the first mode, the working cycle T of the display panel also includes at least a second period P2, and the second period P2 is located before the first period P1. In the second period P2, when the second gate drive signal GateH_101 received by the first sub-pixel 101 is the second enable level, the first gate drive signal GateV_101 received by the first sub-pixel 101 is the first enable level; when the second gate drive signal GateH_102 received by the second sub-pixel 102 is the second enable level, the first gate drive signal GateV_102 received by the second sub-pixel 102 is the first enable level.

[0027] In the second period P2 , the data voltage writing path of the first subpixel 101 and the data voltage writing path of the second subpixel 102 are both turned on. Therefore, in the second period P2 , the first subpixel 101 and the second subpixel 102 can both perform data voltage writing operations.

[0028] The voltage on the storage capacitor Cst of the first sub-pixel 101 can maintain the data voltage written in the second period P2 during the first period P1.

[0029] from Figure 3 It can be seen that a working cycle T of the display panel includes a second period P2 and a first period P1. Within a working cycle T of the display panel, the first subpixel 101 performs a data voltage write once within the second period P2, and the second subpixel 102 performs a data voltage write once within the second period P2 and once within the first period P1, i.e., a total of two data voltage writes are performed. In other words, within a working cycle T of the display panel, the first subpixel 101 can be charged once, and the second subpixel 102 can be charged twice. That is, the frequency f0 of the second gate drive signal GateH, the data refresh frequency f1 of the first subpixel 101, and the data refresh frequency f2 of the second subpixel 102 can satisfy the following relationship: f0:f1:f2=2:1:2. Taking the frequency f0 of the second gate drive signal GateH as 60 Hz, based on this setting, the data refresh frequency f1 of the first subpixel 101 can be 30 Hz, and the data refresh frequency f2 of the second subpixel 102 can be 60 Hz.

[0030] For example, Figure 4 As shown, Figure 4 Another working timing diagram of the first sub-pixel and the second sub-pixel in the first mode is provided in an embodiment of the present invention. In the first mode, in addition to the above-mentioned first period P1 and second period P2, the working cycle T of the display panel also includes at least a third period P3 and a fourth period P4.

[0031] In the third period P3, when the second gate drive signal GateH_101 received by the first sub-pixel 101 is the second enable level, the first gate drive signal GateV_101 received by the first sub-pixel 101 is the first disable level; when the second gate drive signal GateH_102 received by the second sub-pixel 102 is the second enable level, the first gate drive signal GateV_102 received by the second sub-pixel 102 is the first disable level.

[0032] That is, in the third period P3, the second transistors M2 in the data voltage writing paths of the first sub-pixel 101 and the second sub-pixel 102 are both turned off, the first sub-pixel 101 and the second sub-pixel 102 stop writing the data voltage in the third period P3, and the voltage on the storage capacitor Cst maintains the data voltage written in the second period P2.

[0033] In the fourth period P4, when the second gate drive signal GateH_101 received by the first sub-pixel 101 is the second enable level, the first gate drive signal GateV_101 received by the first sub-pixel 101 is the first enable level; when the second gate drive signal GateH_102 received by the second sub-pixel is the second enable level, the first gate drive signal GateV_102 received by the second sub-pixel 102 is the first non-enable level.

[0034] That is, in the fourth period P4 , the data voltage writing path in the first sub-pixel 101 is turned on, and the data voltage writing path in the second sub-pixel 102 is turned off.

[0035] On the basis of making the data voltage refresh frequency of the first sub-pixel 101 lower than the data voltage refresh frequency of the second sub-pixel 102, the setting of the third period P3 and the fourth period P4 can make the data refresh frequency of the second sub-pixel 102 also lower than the frequency of the second gate drive signal GateH, which can increase the selectable range of the data refresh frequency of the second sub-pixel 102.

[0036] from Figure 4 It can be seen that one working cycle T of the display panel includes one second period P2, two third periods P3, two first periods P1 and one fourth period P4.

[0037] During one operating cycle T of the display panel, the first sub-pixel 101 performs data voltage writing once in the second period P2 and once in the fourth period P4, i.e., the data voltage writing is performed twice in total. The second sub-pixel 102 performs data voltage writing once in the second period P2 and once in the two first periods P1, i.e., the data voltage writing is performed three times in total.

[0038] That is, within one operating cycle T of the display panel, the first sub-pixel 101 can be charged twice, and the second sub-pixel 102 can be charged three times. That is, the frequency f0 of the second gate drive signal GateH, the data refresh frequency f1 of the first sub-pixel 101, and the data refresh frequency f2 of the second sub-pixel 102 satisfy the following formula: f0:f1:f2=6:2:3. Taking the frequency f0 of the second gate drive signal GateH as 60 Hz as an example, based on this setting, the data refresh frequency f1 of the first sub-pixel 101 can be set to 20 Hz, and the data refresh frequency f2 of the second sub-pixel 102 can be set to 30 Hz.

[0039] Optionally, in the display panel, the area where the second sub-pixel 102 with a higher data refresh rate is located can be used to display dynamic images such as animations or videos to ensure smoothness of the image. The area where the first sub-pixel 101 with a lower data refresh rate is located can be used to display static images such as text or pictures to reduce power consumption.

[0040] Optionally, the operating mode of the display panel further includes a second mode. In the second mode, the data refresh frequencies of the sub-pixels in the display panel may be equal.

[0041] Exemplarily, the second mode includes a first sub-mode or a second sub-mode. In the first sub-mode, the data refresh frequency of each sub-pixel in the display panel may be consistent with the frequency of the second gate drive signal GateH. In this case, the first gate drive signal GateV provided to each sub-pixel may always be maintained at the first enable level.

[0042] In the second sub-mode, the data refresh frequency of each sub-pixel in the display panel can be lower than the frequency of the second gate drive signal GateH. In this case, the first gate drive signal GateV provided to each sub-pixel can be the same and set according to the first gate drive signal GateV received by the first sub-pixel 101.

[0043] It should be noted that Figure 2 The structure of the sub-pixel 10 shown is only a schematic diagram. In the embodiment of the present invention, the structure of the sub-pixel 10 can be adjusted according to different design requirements. For example, the sub-pixel 10 can be configured to include a larger number of transistors.

[0044] as well as, Figure 2The design of the first transistor M1 and the second transistor M2 as N-type transistors is only for illustration. The transistors in the sub-pixel 10 provided in the embodiment of the present invention can be N-type transistors or P-type transistors. For N-type transistors, the enable level is a high level, and the non-enable level is a low level. That is, when the gate of the N-type transistor is at a high level, the first and second poles thereof are connected, and when the gate of the N-type transistor is at a low level, the first and second poles thereof are disconnected. For P-type transistors, the enable level is a low level, and the non-enable level is a high level. That is, when the gate of the P-type transistor is at a low level, the first and second poles thereof are connected, and when the gate of the P-type transistor is at a high level, the first and second poles thereof are disconnected.

[0045] In a specific implementation, the gate of each of the above-mentioned transistors serves as its control electrode, and, depending on the signal of the gate of each transistor and its type, its first electrode can be used as the source and the second electrode as the drain, or its first electrode can be used as the drain and the second electrode as the source, without making any distinction here. In addition, the enable level and non-enable level in the embodiment of the present invention are both general terms, the enable level refers to any level that can turn on the transistor, and the non-enable level refers to any level that can cut off / turn off the transistor.

[0046] Exemplarily, the display panel includes a liquid crystal display panel. The liquid crystal display panel includes a liquid crystal layer, a pixel electrode, and a common electrode. The pixel electrode can be electrically connected to the data line Data through the first transistor M1 and the second transistor M2. When the first transistor M1 and the second transistor M2 are turned on, the pixel electrode can receive the data voltage provided by the data line Data. The common electrode can receive a common voltage. Exemplarily, the pixel electrode can be electrically connected to the first plate of the storage capacitor Cst, and the common electrode can be electrically connected to the second plate of the storage capacitor Cst. The liquid crystal molecules can be deflected under the voltage difference between the pixel electrode and the common electrode.

[0047] For example, Figure 5 As shown, Figure 5 This is a schematic diagram of another display panel provided by an embodiment of the present invention. The display panel includes a display area AA and a non-display area NA. The display area AA includes a first gate line 21 , a second gate line 22 and the above-mentioned sub-pixel 10 .

[0048] The display panel includes a first gate control circuit 31, and the first gate control circuit 31 includes a gate drive bus 310. In the first mode, the gate drive bus 310 is electrically connected to the first gate line 21, and the gate drive bus 310 is used to transmit the first gate drive signal GateV. Figure 5 As shown, at least a portion of the first gate control circuit 31 may be located in the non-display area NA.

[0049] For example, Figure 5 As shown, the embodiment of the present invention can make the gate driving bus 310 directly electrically connected to the first gate line 21 .

[0050] Or, as Figure 6 As shown, Figure 6 Schematic diagram of another display panel provided by an embodiment of the present invention, the first gate control circuit 31 further includes a mode control line 311 and a control transistor M3. The gate drive bus 310 is electrically connected to the first gate line 21 through the control transistor M3.

[0051] like Figure 6 As shown, the gate of the control transistor M3 is electrically connected to the mode control line 311 , the first electrode is electrically connected to the gate drive bus 310 , and the second electrode is electrically connected to the first gate line 21 .

[0052] Combine Figure 7 As shown, Figure 7 This is a timing diagram of a mode control line provided by an embodiment of the present invention. The working mode of the display panel also includes a low power consumption mode MD0.

[0053] The mode control line 311 provides an enable level at least in the first mode MD1 to turn on the control transistor M3 at least in the first mode MD1 , thereby providing the first gate driving signal transmitted by the gate driving bus 310 to the first gate line 21 .

[0054] In the low power consumption mode MD0 , the mode control line 311 provides a non-enable level to turn off the control transistor M3 , thereby stopping the transmission of the signal of the gate driving bus 310 to the first gate line 21 .

[0055] It can be seen that in the low power mode MD0, the connection between the gate drive bus 310 and the first gate line 21 is disconnected, and the signal on the gate drive bus 310 does not affect the signal on the first gate line 21. Therefore, in the low power mode MD0, no signal may be provided to the gate drive bus 310, that is, the gate drive bus 310 may be in a floating state with no signal transmission, thereby reducing the power consumption of the display panel.

[0056] In the low power consumption mode MD0 , the first gate line 21 may maintain the signal provided by the mode control line 311 before being switched to the non-enable level.

[0057] For example, if the gate drive bus 310 transmits the first enable level before the mode control line 311 switches to the disable level, then when the mode control line 311 switches to the disable level, the first gate line 21 maintains the first enable level. If the gate drive bus 310 transmits the first disable level before the mode control line 311 switches to the disable level, then when the mode control line 311 switches to the disable level, the first gate line 21 maintains the first disable level.

[0058] Figure 6 and Figure 7 As an example, the control transistor M3 is configured as an N-type transistor, and the enable level transmitted by the mode control line 311 is a high level, while the disable level is a low level. Alternatively, in an embodiment of the present invention, the control transistor M3 may be configured as a P-type transistor, and accordingly, the enable level transmitted by the mode control line 311 may be set to a low level, while the disable level may be set to a high level.

[0059] Exemplarily, the display panel further includes a driving chip (not shown), and the gate driving bus 310 and the mode control line 311 are electrically connected to the driving chip to receive the first gate driving signal and the response signal of the control transistor M3 respectively from the driving chip.

[0060] For example, Figure 5 As shown, the embodiment of the present invention can connect the first sub-pixel 101 and the second sub-pixel 102 to the same gate driving bus 310 and locate them in different sub-pixel rows 1 , that is, connect them to different second gate lines 22 .

[0061] In this case, it is equivalent to Figure 3 and Figure 4 The first gate driving signal GateV_101 and the first gate driving signal GateV_102 are provided by the same gate driving bus 310 .

[0062] like Figure 8 and Figure 9 As shown, Figure 8 and Figure 9 The following are timing diagrams of two types of second gate lines connected to the first sub-pixel, the second gate lines connected to the second sub-pixel, and the gate drive bus provided in the embodiments of the present invention, Figure 8 With the above Figure 3 Corresponding to, Figure 9 With the above Figure 4 Corresponding, that is, based on Figure 8 In the manner shown, the frequency f0 of the second gate driving signal GateH, the data refresh frequency f1 of the first sub-pixel 101, and the data refresh frequency f2 of the second sub-pixel 102 can satisfy f0:f1:f2=2:1:2. Figure 9 In the manner shown, the frequency f0 of the second gate driving signal GateH, the data refresh frequency f1 of the first sub-pixel 101 and the data refresh frequency f2 of the second sub-pixel 102 can satisfy f0:f1:f2=6:2:3.

[0063] Figure 8 and Figure 9 As an example, the second sub-pixel 102 is scanned after the first sub-pixel 101 , that is, the second enable level of the second gate driving signal GateH_102 is located after the second enable level of the second gate driving signal GateH_101 .

[0064] like Figure 8 and Figure 9 As shown, the first gate driving signal GateV provided by the gate driving bus 310 satisfies: In the first period P1, when the second gate driving signal GateH_101 received by the first sub-pixel 101 is the second enable level, the gate driving bus 310 provides a first disable level; when the second gate driving signal GateH_102 received by the second sub-pixel 102 is the second enable level, the gate driving bus 310 provides a first enable level.

[0065] In the second time period P2, when the second gate drive signal GateH_101 received by the first sub-pixel 101 is the second enable level, the gate drive bus 310 provides the first enable level, and when the second gate drive signal GateH_102 received by the second sub-pixel 102 is the second enable level, the gate drive bus 310 provides the first enable level, so that the first sub-pixel 101 writes the data voltage in the second time period P2, and the second sub-pixel 102 writes the data voltage in the second time period P2.

[0066] like Figure 9 As shown, in the third period P3, when the second gate drive signal GateH_101 received by the first sub-pixel 101 is the second enable level, the gate drive bus 310 provides a first disable level; when the second gate drive signal GateH_102 received by the second sub-pixel 102 is the second enable level, the gate drive bus 310 provides a first disable level.

[0067] In the fourth period P4, when the second gate driving signal GateH_101 received by the first sub-pixel 101 is the second enable level, the gate driving bus 310 provides the first enable level; when the second gate driving signal GateH_102 received by the second sub-pixel is the second enable level, the gate driving bus 310 provides the first disable level.

[0068] Based on this configuration, by adjusting the signals transmitted by the gate driving bus 310 at different times, the data refresh frequencies of the first sub-pixel 101 and the second sub-pixel 102 electrically connected to the gate driving bus 310 can be designed differently.

[0069] For example, Figure 6 As shown, the display panel may include a plurality of sub-pixel columns 4, each of which includes a plurality of sub-pixels 10 arranged along a first direction h1. The plurality of sub-pixels 10 in the same sub-pixel column 4 may be electrically connected to the same data line Data.

[0070] Optionally, in the embodiment of the present invention, the first sub-pixel 101 and the second sub-pixel 102 may be located in the same sub-pixel column 4 , or may be located in different sub-pixel columns 4 . Figure 5 and Figure 6 Two optional positions of the second sub-pixel 102 are shown to represent two positional relationships between the first sub-pixel 101 and the second sub-pixel 102. The first sub-pixel 101 and the second sub-pixel 102 indicated by the solid line are located in the same sub-pixel column 4 and are connected to the same data line Data. The first sub-pixel 101 and the second sub-pixel 102 indicated by the dotted line are located in different sub-pixel columns 4 and are connected to different data lines Data.

[0071] For example, Figure 5 and Figure 6 As shown, the display area AA may include multiple first gate lines 21, and the first gate lines 21 are electrically connected to multiple sub-pixels 10 in at least one sub-pixel column 4. The first gate control circuit 31 includes a gate drive bus 310, and the gate drive bus 310 is electrically connected to the multiple first gate drive lines 21. That is, in the first mode, different first gate lines 21 can receive the same signal.

[0072] It should be noted that Figure 6 The provision of one control transistor M3 for each first gate line 21 is merely illustrative. Alternatively, one control transistor M3 may be connected to at least two first gate lines 21 .

[0073] For example, Figure 10 As shown, Figure 10 A schematic diagram of another display panel provided in an embodiment of the present invention, wherein the display area AA includes a first display area AA1 and a second display area AA2, which are arranged along a first direction h1, the first display area AA1 includes a plurality of first sub-pixels 101, and the data refresh frequencies of the plurality of first sub-pixels 101 are equal, and the second display area AA2 includes a plurality of second sub-pixels 102, and the data refresh frequencies of the plurality of second sub-pixels 102 are equal.

[0074] like Figure 10As shown, the display area AA includes a plurality of first gate lines 21 , and the first gate lines 21 pass through the second display area AA2 and the first display area AA1 .

[0075] Optional, such as Figure 10 As shown, the display area AA includes n subpixel rows 1. From top to bottom, the n subpixel rows 1 are labeled 1_1, 1_2, ..., 1_m, 1_m+1, ..., 1_n. Both m and n are positive integers, with m < n. The second display area AA2 includes the first subpixel row 1_1 to the mth subpixel row 1_m, and the first display area AA1 includes the m+1th subpixel row 1_m+1 to the nth subpixel row 1_n.

[0076] like Figure 10 As shown, the first gate control circuit 31 includes a gate driving bus 310. In the first mode, the gate driving bus 310 is electrically connected to the first gate line 21 passing through the first display area AA1 and the second display area AA2.

[0077] When the display panel is working, in the first mode, such as Figure 11 and Figure 12 As shown, Figure 11 and Figure 12 These are the working timing diagrams of the two display panels provided in the embodiment of the present invention in the first mode, Figure 11 With the above Figure 3 Corresponding to, Figure 12 With the above Figure 4 Corresponding, that is, based on Figure 11 The method shown can make the frequency f0 of the second gate driving signal GateH, the data refresh frequency f1 of the first display area AA1 and the data refresh frequency f2 of the second display area AA2 meet the following formula: f0:f1:f2=2:1:2. Figure 12 In the manner shown, the frequency f0 of the second gate driving signal GateH, the data refresh frequency f1 of the first display area AA1 and the data refresh frequency f2 of the second display area AA2 can satisfy f0:f1:f2=6:2:3.

[0078] like Figure 11 and Figure 12 As shown, in the second period P2, during the process of scanning the entire display area AA, that is, from the time when the second gate line 22_1 electrically connected to the first sub-pixel row 1_1 provides the second enable level to the time when the second gate line 22_n electrically connected to the n-th sub-pixel row 1_n provides the second enable level, the gate drive bus 310 provides the first enable level. During this process, data voltages are sequentially written to each sub-pixel row 1 in the second display area AA2 and the first display area AA1 according to the scanning order of the second gate line 22.

[0079] like Figure 11 and Figure 12 As shown, the first period P1 includes a first sub-period P11 and a second sub-period P12. The first sub-period P11 is a scanning period for the second display area AA2. That is, during the first sub-period P11, the first sub-pixel row 1_1 to the m-th sub-pixel row 1_m are sequentially scanned. The second gate line 22_1 electrically connected to the first sub-pixel row 1_1 to the second gate line 22_m electrically connected to the m-th sub-pixel row 1_m sequentially provide the second enable level. The gate drive bus 310 provides the first enable level during the first sub-period P11. That is, during the first sub-period P11, data voltages are sequentially written to each sub-pixel row 1 in the second display area AA2 according to the scanning order of the second gate line 22.

[0080] The second sub-period P12 is a scanning period for the first display area AA1. That is, during the second sub-period P12, the m+1th sub-pixel row 1_m+1 to the nth sub-pixel row 1_n are sequentially scanned. That is, the second gate line 22 electrically connected to the m+1th sub-pixel row 1_m+1 to the second gate line 22 electrically connected to the nth sub-pixel row 1_n sequentially provides the second enable level, and the gate drive bus 310 provides the first enable level during the second sub-period P12. That is, during the second sub-period P12, each sub-pixel row 1 in the first display area AA1 stops writing data voltages and maintains the data voltages written during the second period P2.

[0081] like Figure 12 As shown, in the third period P3, during the process of scanning the entire display area AA, that is, during the process from the second gate line 22_1 electrically connected to the first sub-pixel row 1_1 providing the second enable level to the second gate line 22_n electrically connected to the n-th sub-pixel row 1_n providing the second enable level, the gate drive bus 310 provides the first non-enable level. In other words, during this process, the writing of data voltages to each sub-pixel row 1 in the second display area AA2 and the first display area AA1 is stopped.

[0082] like Figure 12 As shown, the fourth period P4 includes a third sub-period P41 and a fourth sub-period P42. The third sub-period P41 is a scanning period for the second display area AA2. That is, during the third sub-period P41, the first sub-pixel row 1_1 to the m-th sub-pixel row 1_m are sequentially scanned. That is, the second gate line 22_1 electrically connected to the first sub-pixel row 1_1 to the second gate line 22_m electrically connected to the m-th sub-pixel row 1_m sequentially provide the second enable level. The gate drive bus 310 provides the first disable level during the third sub-period P41. That is, during the third sub-period P41, each sub-pixel row 1 in the second display area AA2 stops writing data voltages and maintains the data voltages written during the second period P2.

[0083] The fourth sub-period P42 is a scanning period for the first display area AA1. That is, during the fourth sub-period P42, the m+1th sub-pixel row 1_m+1 to the nth sub-pixel row 1_n are sequentially scanned. That is, the second gate line 22_m+1 electrically connected to the m+1th sub-pixel row 1_m+1 to the second gate line 22_n electrically connected to the nth sub-pixel row 1_n sequentially provide the second enable level. The gate drive bus 310 provides the first enable level during the fourth sub-period P42. That is, during the fourth sub-period P42, data voltages are written to each sub-pixel row 1 in the first display area AA1 according to the scanning order of the second gate line 22.

[0084] For example, when driving the display panel, the first display area AA1 with a lower data refresh rate can be used to display text or static images to reduce power consumption of the first display area AA1. The second display area AA2 with a higher data refresh rate can be used to display dynamic images such as animations or videos to improve the smoothness of the images displayed in the second display area AA2.

[0085] In the embodiment of the present invention, the period TH of the signal on the gate drive bus 310 determines the duty cycle T of the display panel in the first mode. In other words, the embodiment of the present invention can adjust the duty cycle T of the display panel in the first mode by adjusting the period TH of the signal on the gate drive bus 310.

[0086] Exemplarily, the period TH of the signal on the gate driving bus 310 and the period T0 of the second gate driving signal GateH satisfy: TH=N×T0, where N is an integer, and N≥2. Figure 11 Take N=2 as an example, Figure 12 Take N=6 as an example.

[0087] It should be noted that Figure 3 and Figure 4 The time-sharing provision of the second enable level of the second gate drive signal GateH_101 and the second enable level of the second gate drive signal GateH_102 shown is only an illustration. In another optional implementation, the embodiment of the present invention can also enable the second enable level of the second gate drive signal GateH_101 and the second enable level of the second gate drive signal GateH_102 to be provided simultaneously, that is, the first sub-pixel 101 and the second sub-pixel 102 are electrically connected to the same second gate line 22.

[0088] Optional, such as Figure 13 As shown, Figure 13 Schematic diagram of another display panel provided by an embodiment of the present invention, wherein the first sub-pixel 101 and the second sub-pixel 102 have different Figure 10 The position relationship, such as Figure 13 As shown, the same sub-pixel row 1 includes the first sub-pixel 101 and the second sub-pixel 102 with different frequencies; that is, the first sub-pixel 101 and the second sub-pixel 102 are electrically connected to the same second gate line 22 to receive the same second gate driving signal GateH.

[0089] In the embodiment of the present invention, the first gate control circuit 31 includes at least two gate drive buses 310. Figure 13 As an example, the first gate control circuit 31 includes two gate drive buses, which are labeled 310_1 and 310_2 . In the first mode, one gate drive bus 310_1 is electrically connected to the first sub-pixel 101 , and the other gate drive bus 310_2 is electrically connected to the second sub-pixel 102 .

[0090] The embodiment of the present invention electrically connects the first sub-pixel 101 and the second sub-pixel 102 located in the same sub-pixel row 1 to different gate drive buses 310 and performs differentiated design on the signals on the different gate drive buses 310, thereby achieving differentiated design of the data refresh frequency of the first sub-pixel 101 and the data refresh frequency of the second sub-pixel 102 located in the same sub-pixel row 1.

[0091] For example, when the display panel is working, in the first mode, as shown in FIG. Figure 14 and Figure 15 As shown, Figure 14 and Figure 15 A timing diagram of two second gate drive signals provided to the first sub-pixel and the second sub-pixel, a gate drive bus connected to the first sub-pixel, and a gate drive bus connected to the second sub-pixel provided in an embodiment of the present invention, Figure 14 and Figure 15 GateH_101 and GateH_102 in Figure 13 The second gate driving signal is received by the first sub-pixel 101 and the second sub-pixel 102 located in one of the sub-pixel rows 1. Figure 14 With the above Figure 3 Corresponding to, Figure 15 With the above Figure 4 Corresponding, that is, based on Figure 14 In the manner shown, the frequency f0 of the second gate driving signal GateH, the data refresh frequency f1 of the first sub-pixel 101, and the data refresh frequency f2 of the second sub-pixel 102 can satisfy f0:f1:f2=2:1:2. Figure 15In the manner shown, the frequency f0 of the second gate driving signal GateH, the data refresh frequency f1 of the first sub-pixel 101 and the data refresh frequency f2 of the second sub-pixel 102 can satisfy f0:f1:f2=6:2:3.

[0092] like Figure 14 and Figure 15 As shown, the first gate driving signal provided by the gate driving bus 310 satisfies: During the first period P1, when the second gate driving signal GateH_101 received by the first sub-pixel 101 and the second gate driving signal GateH_102 received by the second sub-pixel 102 are at the second enable level, the gate driving bus 310_1 provides a first disable level so that the gate driving bus 310_1 controls the first sub-pixel 101 to stop writing the data voltage during the first period P1. The gate driving bus 310_2 provides a first enable level so that the gate driving bus 310_2 controls the second sub-pixel 102 to write the data voltage during the second period P2.

[0093] In the second time period P2, when the second gate drive signal GateH_101 received by the first sub-pixel 101 and the second gate drive signal GateH_102 received by the second sub-pixel 102 are the second enable level, the gate drive bus 310_1 and the gate drive bus 310_2 both provide the first enable level, so that the gate drive bus 310_1 controls the first sub-pixel 101 to write the data voltage in the second time period P2, and the gate drive bus 310_2 controls the second sub-pixel 102 to write the data voltage in the second time period P2.

[0094] For example, Figure 15 As shown, the operating cycle T of the display panel also includes at least the third period P3 and the fourth period P4. During the third period P3, when the second gate drive signal GateH_101 received by the first sub-pixel 101 and the second gate drive signal GateH_102 received by the second sub-pixel 102 are at the second enable level, the gate drive bus 310_1 and the gate drive bus 310_2 both provide the first disable level, so that the gate drive bus 310 controls the first sub-pixel 101 to stop writing the data voltage during the third period P3, and the gate drive bus 310_2 controls the second sub-pixel 102 to stop writing the data voltage during the third period P3.

[0095] During the fourth period P4, when the second gate driving signal GateH_101 received by the first sub-pixel 101 and the second gate driving signal GateH_102 received by the second sub-pixel 102 are at the second enable level, the gate driving bus 310_1 provides the first enable level to control the first sub-pixel 101 to write the data voltage during the fourth period P4. The gate driving bus 310_2 provides the first disable level to control the second sub-pixel 102 to stop writing the data voltage during the fourth period P4.

[0096] In the embodiment of the present invention, the period TH1 of the signal on the gate drive bus 310_1 electrically connected to the first sub-pixel 101 determines the duty cycle of the first sub-pixel 101 in the first mode. In other words, the embodiment of the present invention can adjust the duty cycle of the first sub-pixel 101 in the first mode by adjusting the period TH1 of the signal on the gate drive bus 310_1.

[0097] Exemplarily, in the embodiment of the present invention, TH1≥N1×T0, where T0 is the period of the second gate driving signal GateH and N1 is an integer.

[0098] Optionally, in this embodiment of the present invention, TH1 can be set to N1×T0. That is, the time interval between two adjacent identical pulses in the first gate drive signal GateV received by the first sub-pixel 101 is N1×T0. Based on this setting, the data refresh frequencies of the plurality of first sub-pixels 101 connected to the gate drive bus 310_1 can be made equal. For example, the data refresh frequency f1 of the plurality of first sub-pixels 101 and the frequency f0 of the second gate drive signal GateH can satisfy the following relationship: f0:f1=N1:1. Figure 14 Take TH1=2T0 as an example, Figure 15 Take TH1=3T0 as an example.

[0099] Alternatively, in the embodiment of the present invention, TH1>N1×T0 can be set so that the data refresh frequencies of the at least two first sub-pixels 101 connected to the gate driving bus 310_1 are different.

[0100] like Figure 14 As shown, the first gate drive signal GateV provided by the second gate drive bus 310_2 can be constantly set at the first enable level. Based on this configuration, the data refresh frequency f2 of the second sub-pixel can be made consistent with the frequency f0 of the second gate drive signal GateH. For example, when the frequency f0 of the second gate drive signal GateH is 60 Hz, based on this configuration, the data refresh frequency f2 of the second sub-pixel 102 can be made 60 Hz.

[0101] Or, as Figure 15As shown, the embodiment of the present invention can also make the signal transmitted by the gate drive bus 310_2 a periodic pulse signal that can switch between a first enable level and a first non-enable level. Based on this setting, while making the data refresh frequency of the first sub-pixel 101 lower than the data refresh frequency of the second sub-pixel 102, the data refresh frequency of the second sub-pixel 102 can also be lower than the frequency of the second gate drive signal GateH.

[0102] When the gate drive bus 310_2 transmits a pulse signal, the period TH2 of the signal on the gate drive bus 310_2 electrically connected to the second sub-pixel 102 determines the duty cycle of the second sub-pixel 102 in the first mode. In other words, the embodiment of the present invention can adjust the duty cycle of the second sub-pixel 102 in the first mode by adjusting the period TH2 of the signal on the gate drive bus 310_2.

[0103] Illustratively, in the embodiment of the present invention, TH2≥N2×T0; N2 is an integer, and N2<N1.

[0104] Optionally, in this embodiment of the present invention, TH2 can be set to N2×T0. That is, the time interval between two adjacent identical pulses in the first gate drive signal GateV received by the second sub-pixel 102 is N2×T0. Based on this configuration, the data refresh frequencies of the plurality of second sub-pixels 102 connected to the gate drive bus 310_2 can be made equal. For example, the data refresh frequency f2 of the plurality of second sub-pixels 102 and the frequency f0 of the second gate drive signal GateH can satisfy the following relationship: f0:f2=N2:1. Figure 15 Take TH1=3T0 and TH2=2T0 as an example.

[0105] Alternatively, in the embodiment of the present invention, TH2>N2×T0 can be set so that the data refresh frequencies of the at least two second sub-pixels 102 connected to the gate driving bus 310_2 are different.

[0106] In another optional embodiment, as Figure 13 As shown, the display area AA includes a first display area AA1 and a second display area AA2, which are arranged along the second direction h2. The first display area AA1 includes a plurality of first sub-pixels 101, and the data refresh frequencies of the plurality of first sub-pixels 101 are equal. The second display area AA2 includes a plurality of second sub-pixels 102, and the data refresh frequencies of the plurality of second sub-pixels 102 are equal.

[0107] like Figure 13As shown, the display area AA includes a plurality of first gate lines 21. Some of the first gate lines 21 are located in the first display area AA1 and are electrically connected to the plurality of first sub-pixels 101 in the first display area AA1. Another portion of the first gate lines 21 are located in the second display area AA2 and are electrically connected to the plurality of second sub-pixels 102 in the second display area AA2.

[0108] Optional, such as Figure 13 As shown, the display area AA includes r subpixel columns 4, each of which includes a plurality of subpixels 10 arranged along a first direction h1. From left to right, the r subpixel columns 4 are labeled 4_1, 4_2, ..., 4_s, 4_s+1, ..., 4_r. The first display area AA1 includes the first subpixel column 4_1 to the s-th subpixel row 4_s, and the second display area AA2 includes the s+1-th subpixel column 4_s+1 to the r-th subpixel column 4_r.

[0109] The first gate control circuit 31 includes a gate drive bus 310_1 and a gate drive bus 310_2. In the first mode, the gate drive bus 310_1 is electrically connected to the first gate lines 21 in the first display area AA1, and the gate drive bus 310_2 is electrically connected to the first gate lines 21 in the second display area AA2.

[0110] When the display panel is working, in the first mode, such as Figure 16 and Figure 17 As shown, Figure 15 and Figure 16 for Figure 13 The two working timing diagrams of the display panel in the first mode are shown. Figure 16 With the above Figure 3 Corresponding to Figure 16 In the above-mentioned case, N1=2, and the first gate driving signal GateV provided by the gate driving bus 310_2 is set to a constant signal. Figure 17 With the above Figure 4 Corresponding to Figure 17 In the example, N1=3, the first gate driving signal GateV provided by the gate driving bus 310_2 is a pulse signal, and its period TH2 and the period T0 of the second gate driving signal GateH satisfy: TH2=2T0. That is, N2=2.

[0111] based on Figure 16 In the manner shown, the frequency f0 of the second gate driving signal GateH, the data refresh frequency f1 of the first display area AA1 and the data refresh frequency f2 of the second display area AA2 can satisfy f0:f1:f2=2:1:2.

[0112] based on Figure 17In the manner shown, the frequency f0 of the second gate driving signal GateH, the data refresh frequency f1 of the first display area AA1 and the data refresh frequency f2 of the second display area AA2 can satisfy f0:f1:f2=6:2:3.

[0113] like Figure 16 and Figure 17 As shown, in the second period P2, during the process of scanning the entire display area AA, that is, during the process from the second gate line 22_1 electrically connected to the first sub-pixel row 1_1 providing the second enable level to the second gate line 22_n electrically connected to the n-th sub-pixel row 1_n providing the second enable level, the gate drive bus 310_1 and the gate drive bus 310_2 both provide the first enable level. During this process, data voltages are sequentially written to each sub-pixel row 1 in the second display area AA2 and the first display area AA1 according to the scanning order of the second gate line 22.

[0114] During the first period P1, while scanning the entire display area AA, that is, from the time the second gate line 22_1 electrically connected to the first sub-pixel row 1_1 provides the second enable level to the time the second gate line 22_n electrically connected to the nth sub-pixel row 1_n provides the second enable level, the gate drive bus 310_1 provides the first disable level, and the gate drive bus 310_2 provides the first enable level. That is, during the first period P1, data voltage writing to each sub-pixel row 1 in the first display area AA1 ceases, while data voltage writing to each sub-pixel row 1 in the second display area AA2 begins in sequence according to the scanning order of the second gate line 22.

[0115] like Figure 17 As shown, the working cycle T of the display panel at least further includes the third period P3 and the fourth period P4 mentioned above.

[0116] During the third period P3, during the scanning process from the first sub-pixel row 1_1 to the last sub-pixel row, i.e., the n-th sub-pixel row 1_n, that is, during the process from the second gate line 22_1 electrically connected to the first sub-pixel row 1_1 providing the second enable level to the second gate line 22_n electrically connected to the n-th sub-pixel row 1_n providing the second enable level, both the gate drive bus 310_1 and the gate drive bus 310_2 provide the first non-enable level. During this process, data voltage writing is stopped for each sub-pixel row 1 in the first display area AA1 and the second display area AA2.

[0117] During the fourth period P4, during the scanning process from the first sub-pixel row 1_1 to the last sub-pixel row, i.e., the n-th sub-pixel row 1_n, that is, during the process from the second gate line 22_1 electrically connected to the first sub-pixel row 1_1 providing the second enable level to the second gate line 22_n electrically connected to the n-th sub-pixel row 1_n providing the second enable level, the gate drive bus 310_1 provides the first enable level, and the gate drive bus 310_2 provides the first disable level. During this process, data voltages are written to each sub-pixel row 1 in the first display area AA1. Data voltages are not written to each sub-pixel row 1 in the second display area AA2.

[0118] For example, when driving the display panel, the first display area AA1 with a lower data refresh rate can be used to display text or static images to reduce power consumption of the first display area AA1. The second display area AA2 with a higher data refresh rate can be used to display dynamic images such as animations or videos to improve the smoothness of the images displayed in the second display area AA2.

[0119] In another optional embodiment, as Figure 18 As shown, Figure 18 This is a schematic diagram of another display panel provided by an embodiment of the present invention. The display area AA includes a first display area AA1 and a second display area AA2. The first display area AA1 surrounds the second display area AA2.

[0120] For example, Figure 18 As shown, the first display area AA1 includes a first sub-display area AA11, a second sub-display area AA12, a third sub-display area AA13, and a fourth sub-display area AA14. Along the first direction h1, the second sub-display area AA12 and the third sub-display area AA13 are located on both sides of the second display area AA2. Along the second direction h2, the first sub-display area AA11 and the fourth sub-display area AA14 are located on both sides of the second display area AA2.

[0121] like Figure 18 As shown, the display area AA includes multiple first gate lines 21, some of which are located in the first display area AA1 and electrically connected to the multiple first sub-pixels 101 in the first display area AA1, and some of the first gate lines 21 extend through the first display area AA1 and the second display area AA2.

[0122] Optionally, the sub-pixels in the display area AA are arranged in n rows and r columns, that is, the display area AA includes n sub-pixel rows and r sub-pixel columns. Figure 18 Sub-pixels are not shown.

[0123] From left to right, the first sub-display area AA11 includes the first to x-th sub-pixel columns, the second sub-display area AA12, the second sub-display area AA2, and the third sub-display area AA13 each include portions of the x+1-th to y-th sub-pixel columns. The fourth sub-display area AA14 includes the y+1-th to r-th sub-pixel columns.

[0124] The first sub-pixel column, the xth sub-pixel column, the x+1th sub-pixel column, the yth sub-pixel column, the y+1th sub-pixel column and the rth sub-pixel column are respectively Figure 18 As shown, the first first gate line 21_1, the xth first gate line 21_x, the x+1th first gate line 21_x+1, the first gate line 21_y, the y+1th first gate line 21_y+1 and the rth first gate line 21_r are electrically connected correspondingly.

[0125] In order from top to bottom, the second sub-display area AA12 includes the part from the first sub-pixel row to the u-th sub-pixel row, the second display area AA2 includes the part from the u+1-th sub-pixel row to the v-th sub-pixel row, and the third sub-display area AA13 includes the part from the v+1-th sub-pixel row to the n-th sub-pixel row.

[0126] The first sub-pixel row, the u-th sub-pixel row, the u+1-th sub-pixel row, the v-th sub-pixel row, the v+1-th sub-pixel row and the n-th sub-pixel row are respectively Figure 18 The first second gate line 22_1, the uth second gate line 22_u, the u+1th second gate line 22_u+1, the vth second gate line 22_v, the v+1th second gate line 22_v+1, and the nth second gate line 22_n are electrically connected to each other accordingly.

[0127] The first gate control circuit 31 includes at least two gate drive buses, Figure 18 Taking the first gate control circuit 31 as an example, which includes a gate drive bus 310_1 and a gate drive bus 310_2, in a first mode, the gate drive bus 310_1 is electrically connected to a plurality of first gate lines 21 in the first sub-display area AA11 and the fourth sub-display area AA14. The gate drive bus 310_2 is electrically connected to the first gate lines 21 passing through the second sub-display area AA12, the second display area AA2, and the third sub-display area AA13.

[0128] When the display panel is working, in the first mode, such as Figure 19 As shown, Figure 19 for Figure 18 The display panel shown is a working timing diagram in the first mode, During the second period P2, during the scanning process from the first sub-pixel row to the n-th sub-pixel row, that is, during the process from the second gate line 22_1 electrically connected to the first sub-pixel row providing the second enable level to the second gate line 22_n electrically connected to the n-th sub-pixel row providing the second enable level, both the gate drive bus 310_1 and the gate drive bus 310_2 provide the first enable level. During this process, data voltages are sequentially written to the sub-pixel rows in the second display area AA2 and the first display area AA1 according to the scanning order of the second gate line 22.

[0129] like Figure 19 As shown, the first period P1 includes a first sub-period P11, a second sub-period P12, and a third sub-period P13. The first sub-period P11 is a scanning period for the first to u-th sub-pixel rows in the first and fourth sub-display areas AA11 and AA14, and the second sub-display area AA12. That is, in the first sub-period P11, the first to u-th sub-pixel rows are sequentially scanned. That is, the second gate line 22_1 electrically connected to the first sub-pixel row to the second gate line 22_u electrically connected to the u-th sub-pixel row sequentially provide the second enable level, and the gate drive bus 310_2 provides the first disable level in the first sub-period P11. That is, in the first sub-period P11, the writing of data voltages to the sub-pixel rows in the second sub-display area AA12 is stopped.

[0130] The second sub-period P12 is a scanning period for the u+1th to vth sub-pixel rows in the first and fourth sub-display areas AA11 and AA14, and the second display area AA2. That is, during the second sub-period P12, the u+1th to vth sub-pixel rows are sequentially scanned. That is, the second gate line 22_u+1 electrically connected to the u+1th sub-pixel row through the second gate line 22_v electrically connected to the vth sub-pixel row sequentially provide the second enable level, and the gate drive bus 310_2 provides the first enable level during the second sub-period P12. That is, during the second sub-period P12, data voltages are written to the sub-pixel rows in the second display area AA2 according to the scanning order of the second gate line 22.

[0131] The third sub-period P13 is a scanning period for the v+1th to nth sub-pixel rows of the first and fourth sub-display areas AA11 and AA14, as well as the third sub-display area AA13. That is, during the third sub-period P13, the v+1th to nth sub-pixel rows are sequentially scanned. That is, the second gate line 22_v+1 electrically connected to the v+1th sub-pixel row through the second gate line 22_n electrically connected to the nth sub-pixel row sequentially provide the second enable level. The gate drive bus 310_2 provides the first disable level during the third sub-period P13. That is, during the third sub-period P13, data voltage writing to the sub-pixel rows in the third sub-display area AA13 is stopped.

[0132] During the first, second, and third sub-periods P11, P12, and P13, the gate drive bus 310_1 provides the first non-enable level. That is, during the first, second, and third sub-periods P11, P12, and P13, the sub-pixel rows in the first and fourth sub-display areas AA11 and AA14 stop writing data voltages.

[0133] The operations of the second period P2 and the first period P1 can be repeated. Based on this configuration, the data refresh frequency of the first display area AA1 can be lower than the data refresh frequency of the second display area AA2.

[0134] For example, Figure 18 As shown, in this embodiment of the present invention, the sub-pixels in the first sub-display area AA11 and the fourth sub-display area AA14 are all connected to the gate drive signal line 310_1. The sub-pixels in the second sub-display area AA12, the second display area AA2, and the fourth sub-display area AA14 are all connected to the gate drive signal line 310_2.

[0135] Or, as Figure 20 As shown, Figure 20 A schematic diagram of another display panel provided in an embodiment of the present invention. In an embodiment of the present invention, the gate drive bus 310_1 and the gate drive bus 310_2 can also be split into two signal lines. For example, the gate drive bus 310_1 can be split into a gate drive bus 310_11 and a gate drive bus 310_12, and the gate drive bus 310_2 can be split into a gate drive bus 310_21 and a gate drive bus 310_22.

[0136] Combine Figure 20 and Figure 21 As shown, Figure 21 for Figure 20The display panel is shown in a working timing diagram in the first mode. The timing of the gate drive bus 310_11 and the gate drive bus 310_12 are the same, and the timing of the gate drive bus 310_21 and the gate drive bus 310_22 are the same. like Figure 20 As shown, the gate drive bus 310_11 is electrically connected to the first gate line 21 in the first sub-display area AA11, and the gate drive bus 310_12 is electrically connected to the first gate line 21 in the fourth sub-display area AA14. The gate drive bus 310_21 is electrically connected to a portion of the first gate line 21 passing through the second sub-display area AA12, the second display area AA2, and the fourth sub-display area AA14, and the gate drive bus 310_22 is electrically connected to another portion of the first gate line 21 passing through the second sub-display area AA12, the second display area AA2, and the fourth sub-display area AA14.

[0137] Based on this configuration, the number of sub-pixels connected to one gate driving bus 310 can be reduced, which is beneficial for reducing the load of one gate driving bus 310 .

[0138] In another optional implementation, the embodiment of the present invention may also make the number of gate drive buses 310 the same as the number of sub-pixel columns in the display area AA. Figure 22 As shown, Figure 22 This is a schematic diagram of another display panel provided by an embodiment of the present invention. In this embodiment of the present invention, the first gate control circuit may include r first gate drive buses, and the r first gate drive buses 310 are electrically connected to r sub-pixel columns in a one-to-one correspondence. Figure 22 The sub-pixel columns are not shown, but the first gate lines 21 electrically connected to the corresponding sub-pixel columns are shown.

[0139] Based on this configuration, the first gate drive signals provided to different sub-pixel columns can be made independent of each other, enabling the frequencies of different sub-pixel columns to be set differently. In other words, a sub-pixel column can be used as a minimum frequency unit, which facilitates fine-tuning of the frequency division region in the display panel.

[0140] For example, combined with Figure 22 and Figure 23 As shown, Figure 23 for Figure 22 The following diagram illustrates an operating timing diagram of the display panel in the first mode, in which the timings of gate drive bus 310_1 and gate drive bus 310_2 are different, while the timings of gate drive bus 310_2 through gate drive bus 310_r are the same. This configuration enables the data refresh rate of sub-pixels in rows u+1 through v of the sub-pixel column electrically connected to gate drive bus 310_1 to be twice that of other sub-pixels.

[0141] For example, Figure 24 As shown, Figure 24 This is a schematic diagram of another first gate control circuit provided by an embodiment of the present invention. The control transistor M3 includes a first control transistor M31 and a second control transistor M32 . The mode control signal line 311 includes a first signal line 3111 and a second signal line 3112 .

[0142] The gate of the first control transistor M31 is electrically connected to the first signal line 3111, and the gate of the second control transistor M32 is electrically connected to the second signal line 3112. The first electrode of the first control transistor M31 and the first electrode of the second control transistor M32 are both electrically connected to the gate drive bus 310 to receive the first gate drive signal GateV. The second electrode of the first control transistor M31 and the second electrode of the second control transistor M32 are both electrically connected to the first gate line 21.

[0143] In the embodiment of the present invention, in the first mode, the first signal line 3111 and the second signal line 3112 provide signals for turning on the first control transistor M31 and the second control transistor M32 in a time-sharing manner.

[0144] like Figure 25 As shown, Figure 25 Another driving timing diagram of a display panel in a first mode is provided in an embodiment of the present invention. In the first mode, the signals provided by the first signal line 3111 and the second signal line 3112 are both signals that alternately switch between an enable level and a disable level.

[0145] In the first mode, during the second period P2, the first signal line 3111 provides a signal to turn on the first control transistor M31. The first control transistor M31 is turned on, and the signal on the gate drive bus 310 is written into the first gate line 21 through the first control transistor M31. The second signal line 3112 provides a signal to turn off the second control transistor M32. In the first period P1, the second signal line 3112 provides a signal to turn on the second control transistor M32, the second control transistor M32 is turned on, and the signal on the gate drive bus 310 is written into the first gate line 21 through the second control transistor M32; the first signal line 3111 provides a signal to turn off the first control transistor M31.

[0146] It can be seen that at any time in the first mode, only one of the first control transistor M31 and the second control transistor M32 is turned on. Based on this configuration, in the first mode, the first control transistor M31 and the second control transistor M32 can be controlled to be turned on in a time-sharing manner, which can prevent the first control transistor M31 or the second control transistor M32 from being turned on for a long time, thereby improving the operating reliability of the first control transistor M31 or the second control transistor M32.

[0147] Figure 24 The first control transistor M31 and the second control transistor M32 are set as N-type transistors as an example. Accordingly, Figure 25 The first signal line 3111 and the second signal line 3112 transmit a high level as an enable level and a low level as a disable level for illustration. Of course, the first control transistor M31 or the second control transistor M32 can also be set as a P-type transistor, which is not illustrated here.

[0148] Furthermore, it is understandable that Figure 24 The connection of multiple first gate lines 21 to the same gate driving bus 310 is merely used as an illustration. At least two first gate lines 21 may also be connected to different gate driving busses 310 , which is not illustrated in the drawings here.

[0149] Optional, such as Figure 26 As shown, Figure 26 A schematic diagram of another display panel provided in an embodiment of the present invention shows a first gate line 21 electrically connected to at least two sub-pixels 10 in the same sub-pixel row 1. Based on this configuration, a first gate drive signal GateV can be shared by at least two sub-pixels 10 in the same sub-pixel row 1.

[0150] When the display panel is working, at least two sub-pixels 10 that share the same first gate drive signal GateV have the same data refresh frequency, that is, they can serve as a minimum refresh unit in the display panel. Figure 26 Taking three adjacent sub-pixels 10 connected to the same first gate line 21 as an example, in this case, the three adjacent sub-pixels 10 in the same sub-pixel row 1 can be used as a minimum refresh unit in the display panel. Figure 26 As shown, the three sub-pixels 10 are respectively connected to different data lines Data.

[0151] For example, Figure 26 and Figure 27 As shown, Figure 27 A wiring diagram of a display panel provided by an embodiment of the present invention is shown. At least a portion of the first gate line 21 extends along a first direction h1 ; at least a portion of the second gate line 22 extends along a second direction h2 .

[0152] The display panel further includes a gate connection line 5 , which electrically connects the first gate line 21 and at least two sub-pixels 10 in the same sub-pixel row 1 ; specifically, connects the gates of the first transistors M1 of at least two sub-pixels 10 in the same sub-pixel row 1 .

[0153] Optional, such as Figure 26 and Figure 27 As shown, at least a portion of the gate connection line 5 extends along the second direction h2. At least a portion of the second gate line 22 extends along the second direction h2.

[0154] The provision of the gate connection line 5 can reduce the number of first gate lines 21 while achieving at least two sub-pixels 10 being driven at the same data refresh frequency, thereby facilitating reduction of the distance between two adjacent sub-pixels 10 in the second direction h2.

[0155] For example, Figure 27 As shown, the multiple sub-pixels 10 include at least a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B arranged along the second direction h2; at least a portion of the orthographic projection of the first gate line 21 on the plane where the display panel is located is located on a side of the orthographic projection of the blue sub-pixel B on the plane where the display panel is located that is away from the orthographic projection of the green sub-pixel G on the plane where the display panel is located. When the display panel is configured as a liquid crystal display panel, the liquid crystal display panel also includes multiple color resists having different colors. For example, the color resists include a red color resist corresponding to the red sub-pixel R, a green color resist corresponding to the green sub-pixel G, and a blue color resist corresponding to the blue sub-pixel B. Compared with the red and green color resists, the blue color resist has a higher transmittance. Therefore, in order to balance the transmittance of the sub-pixels of different colors, it is generally necessary to set the aperture ratio of the red and green sub-pixels to be larger. In an embodiment of the present invention, by arranging at least a portion of the orthographic projection of the first gate line 21 on the plane where the display panel is located to be located on a side of the orthographic projection of the blue sub-pixel B on the plane where the display panel is located away from the orthographic projection of the green sub-pixel G on the plane where the display panel is located, it is possible to avoid the setting of the first gate line 21 affecting the aperture ratio of the red sub-pixel R and the green sub-pixel B.

[0156] For example, Figure 27 As shown, the display panel further includes a black matrix 6, the orthographic projection of the black matrix 6 on the plane where the display panel is located at least partially covers the first gate line 21, the second gate line 22, the gate connection line 5 and the data line Data.

[0157] When setting the sub-pixel 10, for example, Figure 2As shown, in this embodiment of the present invention, the first electrode of the second transistor M2 can be electrically connected to the data line Data, the second electrode of the second transistor M2 can be electrically connected to the first electrode of the first transistor M1; and the second electrode of the first transistor M1 can be electrically connected to the first plate of the storage capacitor Cst.

[0158] When the display panel is displaying, the second transistor M2 of the sub-pixel 10 can be turned on at the frequency of the second gate drive signal GateH. In the embodiment of the present invention, by electrically connecting the first transistor M1 to the data line Data through the second transistor M2, that is, by allowing the data voltage provided by the data line Data to be written to the storage capacitor Cst in the order of first passing through the second transistor M2 and then passing through the first transistor M1, the data voltage provided by the data line Data can be written to the second electrode of the second transistor M2 at a relatively high frequency. The second electrode of the second transistor M2 is connected to the first transistor M1, which can avoid the situation where no data voltage is written to the connection node between the first transistor M1 and the second transistor M2 for a long time. Therefore, during the period when the first transistor M1 is turned off, the potential of the first electrode of the first transistor M1 can still be refreshed at a certain frequency, thereby improving the potential stability of the first plate of the storage capacitor Cst electrically connected to the first transistor M1, and improving the brightness stability of the sub-pixel with a lower data refresh frequency.

[0159] Or, as Figure 28 As shown, Figure 28 This is a schematic diagram of an equivalent circuit of another sub-pixel provided in an embodiment of the present invention. In this embodiment of the present invention, the first electrode of the first transistor M1 can be electrically connected to the data line Data, the second electrode of the first transistor M1 can be electrically connected to the first electrode of the second transistor M2; and the second electrode of the second transistor M2 can be electrically connected to the first plate of the storage capacitor Cst.

[0160] For example, Figure 29 As shown, Figure 29 A schematic diagram of another display panel provided in an embodiment of the present invention, wherein the non-display area NA includes a first non-display area NA1 and a second non-display area NA2. The first non-display area NA1 and the display area AA are arranged along a first direction h1, and the second non-display area NA2 and the display area AA are arranged along a second direction h2. like Figure 29 As shown, the second non-display area NA2 includes a second gate control circuit 32 , which includes a plurality of cascaded gate control units 320 . The gate control unit 320 is electrically connected to the second gate line 22 for providing the second gate driving signal GateH to the second gate line 22 .

[0161] For example, Figure 29As shown, the first non-display area NA1 includes at least part of the first gate control circuit 31; for example, the first non-display area NA1 includes Figure 24 One or more of the first control transistor M31, the second control transistor M32, the first signal line 3111, the second signal line 3112, and the gate drive bus 310 are shown. Based on this configuration, the first gate control circuit 31 and the second gate control circuit 32 can be dispersed, which can prevent the width of a single side frame of the display panel from being too large.

[0162] Or, as Figure 30 As shown, Figure 30 A schematic diagram of another display panel provided by an embodiment of the present invention, wherein the second non-display area NA2 includes at least a portion of the first gate control circuit 31. For example, the second non-display area NA2 includes Figure 24 One or more of the first control transistor M31 , the second control transistor M32 , the first signal line 3111 , the second signal line 3112 , and the gate drive bus 310 shown.

[0163] Based on the same inventive concept, an embodiment of the present invention further provides a method for driving a display panel, such as Figure 1 As shown, the display panel includes a plurality of data lines Data and a plurality of sub-pixel rows 1 arranged along a first direction h1. The sub-pixel row 1 includes a plurality of sub-pixels 10 arranged along a second direction h2. The first direction h1 and the second direction h2 intersect.

[0164] like Figure 2 As shown, the sub-pixel 10 includes a first transistor M1, a second transistor M2 and a storage capacitor Cst; wherein the first transistor M1 and the second transistor M2 are electrically connected in series between the data line Data and the storage capacitor Cst, the gate of the first transistor M1 receives a first gate drive signal GateV, and the gate of the second transistor M2 receives a second gate drive signal GateH.

[0165] In the embodiment of the present invention, the working mode of the display panel includes a first mode. In the first mode, the display panel includes at least a first sub-pixel 101 and a second sub-pixel 102. The working cycle of the display panel includes at least a first period. Figure 3 and Figure 4 As shown, in the first mode, the driving method of the display panel includes: In the first time period P1, when the second gate drive signal GateH_101 received by the first sub-pixel 101 is the second enable level, the first gate drive signal GateV_101 received by the first sub-pixel 101 is controlled to be the first non-enable level; when the second gate drive signal GateH_102 received by the second sub-pixel 102 is the second enable level, the first gate drive signal GateV_102 received by the second sub-pixel 102 is controlled to be the first enable level.

[0166] The first enable level refers to a level for controlling the first transistor M1 to be turned on, the first disable level refers to a level for controlling the first transistor M1 to be turned off, and the second enable level refers to a level for controlling the second transistor M2 to be turned on.

[0167] The driving method of the display panel provided by an embodiment of the present invention enables the sub-pixel 10 to include a first transistor M1 and a second transistor M2, so that whether the data voltage Vdata provided by the data line Data is written into the storage capacitor Cst, that is, whether the sub-pixel 10 is charged or not can be jointly determined by the second gate driving signal GateH and the first gate driving signal GateV.

[0168] On this basis, the embodiment of the present invention can make the working mode of the display panel include a first mode. In the first mode, the display panel includes at least a first sub-pixel 101 and a second sub-pixel 102. The working cycle T1 of the display panel includes at least a first time period P1. In the first time period P1, under the control of the first gate drive signal GateV_101, the data voltage writing path of the first sub-pixel 101 is turned off, and under the control of the first gate drive signal GateV_102, the data voltage writing path of the second sub-pixel 102 is turned on, so that in the first mode, the data refresh frequency of the first sub-pixel 101 can be lower than the frequency of the second gate drive signal GateH, that is, the data refresh frequency of the first sub-pixel 101 can be lower than the data refresh frequency of the second sub-pixel 102, thereby realizing a differentiated design of the data refresh frequency of the first sub-pixel 101 and the data refresh frequency of the second sub-pixel 102.

[0169] Moreover, based on the method provided in the embodiment of the present invention, the data refresh frequency of the first sub-pixel 101 can be made lower than the frequency of the second gate drive signal GateH. That is, without changing the frequency of the second gate drive signal GateH, at least the frequency reduction drive of the first sub-pixel 101 can be achieved by designing the timing of the first gate drive signal GateV_1 received by the first sub-pixel 101.

[0170] like Figure 1 and Figure 2As shown, the display panel further includes a first gate line 21 and a second gate line 22 . The first gate line 21 provides the first gate driving signal GateV; the second gate line 22 provides the second gate driving signal GateH.

[0171] In an optional embodiment, as Figure 5 As shown, the first gate control circuit 31 includes a gate driving bus 310 , and one gate driving bus 310 connects the first sub-pixel 101 and the second sub-pixel 102 .

[0172] like Figure 5 As shown, the first sub-pixel 101 and the second sub-pixel 102 are connected to different second gate lines 22 .

[0173] Combine Figure 8 and Figure 9 As shown, the method of controlling the first gate driving signal GateV_101 received by the first sub-pixel 101 to be the first non-enable level; and controlling the first gate driving signal GateV_102 received by the second sub-pixel 102 to be the first enable level includes: When the second gate driving signal GateH_101 received by the first sub-pixel 101 is at the second enable level, the gate driving bus 310 is controlled to provide the first enable level; When the second gate driving signal GateH_102 received by the second sub-pixel 102 is at the second enable level, the gate driving bus 310 is controlled to provide the first disable level; Based on this configuration, by adjusting the signals transmitted by the gate driving bus 310 at different times, the data refresh frequencies of the first sub-pixel 101 and the second sub-pixel 102 electrically connected to the gate driving bus 310 can be designed differently.

[0174] Optional, such as Figure 13 As shown, the same sub-pixel row 1 includes a first sub-pixel 101 and a second sub-pixel 102 ; that is, the first sub-pixel 101 and the second sub-pixel 102 are electrically connected to the same second gate line 22 to receive the same second gate driving signal GateH.

[0175] The first gate control circuit 31 includes at least two gate driving buses 310 . In the first mode, one gate driving bus 310_1 is electrically connected to the first sub-pixel 101 , and the other gate driving bus 310_2 is electrically connected to the second sub-pixel 102 .

[0176] Optional, combined Figure 14 and Figure 15As shown, the method of controlling the first gate driving signal GateV_101 received by the first sub-pixel 101 to be the first non-enable level; and controlling the first gate driving signal GateV_102 received by the second sub-pixel 102 to be the first enable level includes: When the second gate drive signal GateH received by the first sub-pixel 101 and the second sub-pixel 102 is the second enable level, the gate drive bus 310_1 is controlled to provide a first disable level so that the first gate drive signal GateV_101 received by the first sub-pixel 101 is the first disable level, and the writing of the data voltage to the first sub-pixel 101 is stopped, and the gate drive bus 310_2 is controlled to provide a first enable level so that the first gate drive signal GateV_102 received by the second sub-pixel 102 is the first enable level, so that the data voltage is written to the second sub-pixel 102.

[0177] For example, Figure 14 As shown, the gate drive bus 310_2 can provide a constant first enable level. Alternatively, as shown Figure 15 As shown, both the gate drive bus 310_1 and the gate drive bus 310_2 can provide periodic pulse signals, wherein the period TH1 of the signal on the gate drive bus 310_1 satisfies TH1=N1×T0, and the period TH2 of the signal on the gate drive bus 310_2 satisfies TH2=N2×T0; N1 and N2 are integers, and 1<N2<N1.

[0178] Based on the same inventive concept, an embodiment of the present invention further provides a display device, such as Figure 31 As shown, Figure 31 Schematic diagram of a display device provided by an embodiment of the present invention, the display device includes the above-mentioned display panel 100. The specific structure of the display panel 100 has been described in detail in the above embodiment and will not be repeated here. Figure 31 The display device shown is for illustrative purposes only. The display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e-reader, a car display screen, or a television.

[0179] It can be seen from the above embodiments that the display panel, driving method thereof, and display device provided by the present invention achieve at least the following beneficial effects: The display panel provided by the present invention includes a plurality of data lines and a plurality of sub-pixel rows arranged along a first direction, the sub-pixel rows including a plurality of sub-pixels arranged along a second direction, the first direction and the second direction intersecting; the sub-pixels including a first transistor, a second transistor and a storage capacitor; wherein the first transistor and the second transistor are electrically connected in series between the data line and the storage capacitor; the gate of the first transistor receives a first gate drive signal, and the gate of the second transistor receives a second gate drive signal; the operating mode of the display panel includes a first mode, in which the display panel includes at least a first sub-pixel and a second sub-pixel, and the operating cycle of the display panel includes at least a first time period, in which, when the second gate drive signal received by the first sub-pixel is a second enable level, the first gate drive signal received by the first sub-pixel is a first disable level; when the second gate drive signal received by the second sub-pixel is a second enable level, the first gate drive signal received by the second sub-pixel is a first enable level; wherein the first enable level refers to a level for controlling the first transistor to be turned on, the first disable level refers to a level for controlling the first transistor to be turned off, and the second enable level refers to a level for controlling the second transistor to be turned on. The present invention provides a subpixel comprising a first transistor, a second transistor, and a storage capacitor; wherein the first transistor and the second transistor are electrically connected in series between a data line and the storage capacitor, such that whether the subpixel is charged or not can be determined by both the second gate drive signal and the first gate drive signal. The present invention provides a display panel operating mode comprising a first mode. In the first mode, the display panel comprises at least a first subpixel and a second subpixel, and the display panel operating cycle comprises at least a first period. During the first period, under the control of the first gate drive signal, the data voltage write path of the first subpixel is turned off, and under the control of the first gate drive signal, the data voltage write path of the second subpixel is turned on. Thus, in the first mode, the data refresh frequency of the first subpixel can be lower than the data refresh frequency of the second subpixel, thereby achieving a differentiated design of the data refresh frequency of the first subpixel and the data refresh frequency of the second subpixel. The data refresh frequency of a subpixel refers to the number of times a data voltage is written to the subpixel per unit time. Based on the method provided by the present invention, the data refresh frequency of the first subpixel can be lower than the frequency of the second gate drive signal. That is, without changing the frequency of the second gate drive signal, at least the first subpixel can be driven at a reduced frequency by designing the timing of the first gate drive signal received by the first subpixel.

[0180] It should be understood that, in the absence of conflict, the above-mentioned embodiments of the present invention and the above-mentioned features in the embodiments may be combined with each other.

[0181] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A display panel, characterized in that: The invention comprises a plurality of data lines and a plurality of sub-pixel rows arranged along a first direction, wherein the sub-pixel rows include a plurality of sub-pixels arranged along a second direction, wherein the first direction and the second direction intersect; the sub-pixels include a first transistor, a second transistor, and a storage capacitor; wherein the first transistor and the second transistor are electrically connected in series between the data lines and the storage capacitor; The gate of the first transistor receives a first gate driving signal, The gate of the second transistor receives a second gate driving signal, The operating mode of the display panel includes a first mode. In the first mode, the display panel includes at least a first sub-pixel and a second sub-pixel. The working cycle of the display panel includes at least a first period, In the first period, when the second gate driving signal received by the first sub-pixel is at a second enable level, the first gate driving signal received by the first sub-pixel is at a first disable level; When the second gate driving signal received by the second sub-pixel is at the second enable level, the first gate driving signal received by the second sub-pixel is at the first enable level; The first enable level refers to a level for controlling the first transistor to be turned on, the first disable level refers to a level for controlling the first transistor to be turned off, and the second enable level refers to a level for controlling the second transistor to be turned on.

2. The display panel according to claim 1, wherein: Also included is a first gate control circuit and a plurality of first gate lines, wherein the first gate lines are electrically connected to the gates of the first transistors; The first gate control circuit includes a gate drive bus. In the first mode, the gate drive bus is electrically connected to the first gate line, and the gate drive bus is used to transmit the first gate drive signal.

3. The display panel according to claim 2, wherein: The first sub-pixel and the second sub-pixel are located in different sub-pixel rows; the first sub-pixel and the second sub-pixel are connected to the same gate drive bus; and When the second gate driving signal received by the first sub-pixel is at a second enable level, the gate driving bus provides a first enable level; When the second gate driving signal received by the second sub-pixel is at a second enable level, the gate driving bus provides a first disable level.

4. The display panel according to claim 2, wherein: The same sub-pixel row includes the first sub-pixel and the second sub-pixel; The first gate control circuit includes at least two gate drive buses, wherein one gate drive bus is electrically connected to the first sub-pixel, and the other gate drive bus is electrically connected to the second sub-pixel; When the second gate drive signal received by the first sub-pixel and the second sub-pixel is a second enable level, the gate drive bus electrically connected to the first sub-pixel provides a first disable level, and the gate drive bus electrically connected to the second sub-pixel provides a first disable level.

5. The display panel according to claim 4, wherein: The period of the signal of the gate driving bus electrically connected to the first sub-pixel is TH1, TH1≥N1×T0, where T0 is the period of the second gate driving signal; N1 is an integer, N1≥2; The signal of the gate driving bus electrically connected to the second sub-pixel is constantly at the first enable level, or the period of the signal of the gate driving bus electrically connected to the second sub-pixel is TH2, TH2≥N2×T0, 2≤N2<N1.

6. The display panel according to claim 2, wherein: The first gate control circuit includes: a first control transistor, a gate of which is electrically connected to a first signal line; a second control transistor, a gate of which is electrically connected to a second signal line; The first electrode of the first control transistor and the first electrode of the second control transistor are both electrically connected to the gate drive bus, The second electrode of the first control transistor and the second electrode of the second control transistor are both electrically connected to the first gate line; In the first mode, the first signal line and the second signal line provide conduction signals in a time-sharing manner.

7. The display panel according to claim 2, wherein: One first gate line is electrically connected to at least two sub-pixels in the same sub-pixel row.

8. The display panel according to claim 7, wherein: At least a portion of the first gate line extends along the first direction; The display panel further includes a gate connection line, wherein the gate connection line electrically connects the first gate line and at least two sub-pixels in the same sub-pixel row; At least a portion of the gate connection line extends along the second direction.

9. The display panel according to claim 8, wherein: The plurality of sub-pixels include at least a red sub-pixel, a green sub-pixel, and a blue sub-pixel arranged along the second direction; At least part of the orthographic projection of the first gate line on the plane where the display panel is located is located on a side where the orthographic projection of the blue sub-pixel on the plane where the display panel is located is away from the orthographic projection of the green sub-pixel on the plane where the display panel is located.

10. The display panel according to claim 1, wherein A first electrode of the second transistor is electrically connected to the data line, a second electrode of the second transistor is electrically connected to the first electrode of the first transistor; and the second electrode of the first transistor is electrically connected to the first plate of the storage capacitor.

11. The display panel according to claim 2, wherein: The display panel includes a first non-display area and a second non-display area, the first non-display area and the display area are arranged along the first direction, and the second non-display area and the display area are arranged along the second direction; The second non-display area includes a second gate control circuit, which includes a plurality of cascaded gate control units. The gate control units are electrically connected to the second transistor and are configured to provide the second gate driving signal to the second transistor.

12. The display panel according to claim 11, wherein: The first non-display area includes at least a portion of the first gate control circuit; Alternatively, the second non-display area includes at least a portion of the first gate control circuit.

13. A method for driving a display panel, characterized in that: The display panel includes a plurality of data lines and a plurality of sub-pixel rows arranged along a first direction, the sub-pixel rows including a plurality of sub-pixels arranged along a second direction, the first direction and the second direction intersecting each other; the sub-pixels include a first transistor, a second transistor, and a storage capacitor; wherein the first transistor and the second transistor are electrically connected in series between the data lines and the storage capacitor, the gate of the first transistor receives a first gate drive signal, and the gate of the second transistor receives a second gate drive signal. The operating mode of the display panel includes a first mode. In the first mode, the display panel includes at least a first sub-pixel and a second sub-pixel. The operating cycle of the display panel includes at least a first period. In the first mode, the driving method includes: During the first period, when the second gate driving signal received by the first sub-pixel is at a second enable level, controlling the first gate driving signal received by the first sub-pixel to be at a first disable level; When the second gate driving signal received by the second sub-pixel is at a second enable level, controlling the first gate driving signal received by the second sub-pixel to be at a first enable level; The first enable level refers to a level for controlling the first transistor to be turned on, the first disable level refers to a level for controlling the first transistor to be turned off, and the second enable level refers to a level for controlling the second transistor to be turned on.

14. The driving method according to claim 13, wherein: The display panel includes a display area and a non-display area; The display area includes a plurality of first gate lines, wherein the first gate lines are electrically connected to the gates of the first transistors; The non-display area includes a first gate control circuit, which includes a gate drive bus. In the first mode, the gate drive bus is electrically connected to the first gate line, and the gate drive bus is used to transmit the first gate drive signal.

15. The driving method according to claim 14, wherein: The first sub-pixel and the second sub-pixel are located in different sub-pixel rows; The first sub-pixel and the second sub-pixel are connected to the same gate driving bus; The method of controlling the first gate driving signal received by the first sub-pixel to be a first non-enable level and the first gate driving signal received by the second sub-pixel to be a first enable level includes: When the second gate driving signal received by the first sub-pixel is at the second enable level, controlling the gate driving bus to provide the first enable level, When the second gate driving signal received by the second sub-pixel is at a second enable level, the gate driving bus is controlled to provide a first disable level.

16. The driving method according to claim 14, wherein: The same sub-pixel row includes the first sub-pixel and the second sub-pixel; The first gate control circuit includes at least two gate drive buses, wherein one gate drive bus is electrically connected to the first sub-pixel, and the other gate drive bus is electrically connected to the second sub-pixel; controlling the first gate driving signal received by the first sub-pixel to be a first non-enable level; The method of controlling the first gate driving signal received by the second sub-pixel to be a first enable level includes: When the second gate drive signal received by the first sub-pixel and the second sub-pixel is a second enable level, the gate drive bus electrically connected to the first sub-pixel is controlled to provide a first non-enable level, and the gate drive bus electrically connected to the second sub-pixel is controlled to provide a first enable level.

17. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 12.

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