Display device

Abstract

A display device includes a display panel, a data driver, and a channel controller. The display panel comprises a plurality of sub-pixels, a plurality of pixel columns and a plurality of data lines. The plurality of data lines includes: a first data line connected to a third sub-pixel in the first pixel column and a third sub-pixel in the third pixel column; a second data line connected to a second sub-pixel in the second pixel column; a third data line connected to the first sub-pixel in the third pixel column; a fourth data line connected to the second sub-pixel in the fourth pixel column; and an additional data line connected to the first sub-pixel in the first pixel column. The data driver includes an additional source channel that supplies an additional data voltage to the additional data line, and the data driver adjusts a voltage level of the additional data voltage by applying an offset value. The channel controller selects an additional source channel among the plurality of source channels and generates an offset value for the additional source channel.

Description

Technical Field

[0001] Example embodiments relate generally to display devices, and more particularly, to a display device for improving display quality. Background Art

[0002] In recent years, flat panel displays (FPDs) have been widely used as display devices, which can easily cover a large area and can be thin and lightweight. For example, FPDs may include, but are not limited to, liquid crystal displays (LCDs) and organic light emitting displays (OLEDs).

[0003] By arranging sub-pixels emitting red, green, and blue light in various shapes and arrangements, each pixel included in a display device can have various pixel structures. For example, each pixel can have Pixel structure or DIAMOND Structure, etc. Various methods of efficiently operating a display device including such various pixel structures are being proposed. Summary of the Invention

[0004] Some example embodiments provide a display device capable of preventing degradation of display quality while including a display panel having a structure for reducing power consumption.

[0005] According to some example embodiments, a display device includes a display panel, a data driver, and a channel controller. The display panel includes a plurality of sub-pixels, a plurality of pixel columns, and a plurality of data lines. Each of the plurality of sub-pixels includes a pixel circuit and a light-emitting element, and the plurality of sub-pixels includes: a plurality of first sub-pixels that display a first color; a plurality of second sub-pixels that display a second color; and a plurality of third sub-pixels that display a third color. The plurality of pixel columns include: a first pixel column in which first sub-pixels among the plurality of first sub-pixels and third sub-pixels among the plurality of third sub-pixels are alternately arranged; a second pixel column in which second sub-pixels among the plurality of second sub-pixels are arranged; a third pixel column in which third sub-pixels among the plurality of third sub-pixels and first sub-pixels among the plurality of first sub-pixels are alternately arranged; and a fourth pixel column in which second sub-pixels among the plurality of second sub-pixels are arranged. The plurality of data lines includes: a first data line connected to the third subpixel in the first pixel column and the third subpixel in the third pixel column; a second data line connected to the second subpixel in the second pixel column; a third data line connected to the first subpixel in the third pixel column; a fourth data line connected to the second subpixel in the fourth pixel column; and an additional data line connected to the first subpixel in the first pixel column. A data driver adjusts the voltage level of an additional data voltage by applying an offset value to the additional data voltage, and the data driver includes a plurality of source channels. The plurality of source channels includes: a first source channel that provides a first data voltage corresponding to a third color to the first data line; a second source channel that provides a second data voltage corresponding to a second color to the second data line; a third source channel that provides a third data voltage corresponding to the first color to the third data line; a fourth source channel that provides a fourth data voltage corresponding to the second color to the fourth data line; and an additional source channel that provides an additional data voltage corresponding to the first color to the additional data line. A channel controller selects the additional source channel from the plurality of source channels and generates an offset value for the additional source channel.

[0006] In an example embodiment, the offset value may be changeable.

[0007] In example embodiments, the channel controller may change an offset value applied to the additional data voltage depending on a position of the first sub-pixel connected to the additional data line in the first pixel column.

[0008] In an example embodiment, the channel controller may select at least one selected source channel excluding the additional source channel from among the plurality of source channels and may generate a second offset value for the at least one selected source channel. The data driver may adjust a voltage level of the selected data voltage by applying the second offset value to the selected data voltage provided by the at least one selected source channel.

[0009] In example embodiments, the display device may further include a temperature sensor that detects an operating temperature. The channel controller may select the at least one selected source channel based on the operating temperature detected by the temperature sensor.

[0010] In example embodiments, the channel controller may select the at least one selected source channel based on brightness of an image displayed in the display panel.

[0011] In example embodiments, the channel controller may select at least one selected source channel based on a plurality of positions of the plurality of source channels.

[0012] In example embodiments, among the plurality of source channels, a source channel connected to a sub-pixel disposed at the center of the display panel among the plurality of sub-pixels may be selected as the at least one selected source channel.

[0013] In an example embodiment, the plurality of pixel columns may further include: a fifth pixel column in which a first subpixel among the plurality of first subpixels and a third subpixel among the plurality of third subpixels are alternately arranged; a sixth pixel column in which a second subpixel among the plurality of second subpixels is arranged; a seventh pixel column in which a third subpixel among the plurality of third subpixels and a first subpixel among the plurality of first subpixels are alternately arranged; and an eighth pixel column in which a second subpixel among the plurality of second subpixels is arranged. The plurality of data lines may further include: a fifth data line connected to the third subpixel in the fifth pixel column and the third subpixel in the seventh pixel column; a sixth data line connected to the second subpixel in the sixth pixel column; a seventh data line connected to the first subpixel in the seventh pixel column; and an eighth data line connected to the second subpixel in the eighth pixel column. The display panel may further include: a plurality of first fan-out lines connected to the first data line, the second data line, the third data line, and the fourth data line; and a plurality of second fan-out lines connected to the fifth data line, the sixth data line, the seventh data line, and the eighth data line. A plurality of first fan-out lines and a plurality of second fan-out lines may be alternately disposed in a peripheral area of ​​the display panel.

[0014] In an example embodiment, the plurality of source channels may further include: a fifth source channel that provides a fifth data voltage corresponding to a third color to a fifth data line; a sixth source channel that provides a sixth data voltage corresponding to a second color to a sixth data line; a seventh source channel that provides a seventh data voltage corresponding to the first color to a seventh data line; and an eighth source channel that provides an eighth data voltage corresponding to the second color to an eighth data line. Source output remapping may be performed on at least some of the first, second, third, fourth, fifth, sixth, seventh, and eighth source channels. The channel controller may select a plurality of remapped source channels from among the first, second, third, fourth, fifth, sixth, seventh, and eighth source channels for which source output remapping is performed and may generate second offset values ​​for the plurality of remapped source channels. The data driver may apply the second offset value to the plurality of data voltages provided by the plurality of remapped source channels.

[0015] According to some example embodiments, a display device includes a display panel, a data driver, and a channel controller. The display panel includes a plurality of sub-pixels, a plurality of data lines, and a plurality of fan-out lines. Each of the plurality of sub-pixels includes a pixel circuit and a light-emitting element, and the plurality of sub-pixels includes: a plurality of first sub-pixels that display a first color; a plurality of second sub-pixels that display a second color; and a plurality of third sub-pixels that display a third color. The plurality of data lines includes: a plurality of first data lines connected to the plurality of first sub-pixels; a plurality of second data lines connected to the plurality of second sub-pixels; and a plurality of third data lines connected to the plurality of third sub-pixels. The plurality of fan-out lines includes: a plurality of first fan-out lines connected to data lines connected to sub-pixels in a first display area of ​​the display panel among the plurality of sub-pixels; a plurality of second fan-out lines connected to data lines connected to sub-pixels in a second display area of ​​the display panel among the plurality of sub-pixels; and a plurality of third fan-out lines connected to data lines connected to sub-pixels in a third display area of ​​the display panel among the plurality of sub-pixels. The second display area is adjacent to the first display area, and a plurality of first fan-out lines and a plurality of second fan-out lines are alternately arranged in the peripheral area of ​​the display panel. The third display area is adjacent to the second display area. A data driver outputs a plurality of remapped data voltages to a plurality of remapped source channels that perform source output remapping. The data driver adjusts the plurality of voltage levels of the plurality of remapped data voltages by applying offset values ​​to the plurality of remapped data voltages. The data driver includes a plurality of source channels. The plurality of source channels include: a plurality of first source channels that provide a plurality of first data voltages corresponding to a first color to a plurality of first data lines; a plurality of second source channels configured to provide a plurality of second data voltages corresponding to a second color to a plurality of second data lines; and a plurality of third source channels configured to provide a plurality of third data voltages corresponding to a third color to a plurality of third data lines. A channel controller selects the plurality of remapped source channels as some of the plurality of source channels and generates offset values ​​for the plurality of remapped source channels.

[0016] In an example embodiment, the offset value may be changeable.

[0017] In example embodiments, the channel controller may change offset values ​​applied to the plurality of remapped data voltages according to the plurality of positions of the plurality of remapped source channels.

[0018] In an example embodiment, the channel controller may select at least one selected source channel other than the plurality of remapped source channels from among the plurality of source channels and may generate a second offset value for the at least one selected source channel. The data driver may adjust a voltage level of the selected data voltage by applying the second offset value to the selected data voltage provided by the at least one selected source channel.

[0019] In example embodiments, the display device may further include a temperature sensor that detects an operating temperature. The channel controller may select the at least one selected source channel based on the operating temperature detected by the temperature sensor.

[0020] In example embodiments, the channel controller may select the at least one selected source channel based on brightness of an image displayed in the display panel.

[0021] In example embodiments, the channel controller may select at least one selected source channel based on a plurality of positions of the plurality of source channels.

[0022] In example embodiments, among the plurality of source channels, a source channel connected to a sub-pixel disposed at the center of the display panel among the plurality of sub-pixels may be selected as the at least one selected source channel.

[0023] In an example embodiment, the display panel may further include a plurality of pixel columns. The plurality of pixel columns may include: a first pixel column in which a first subpixel among the plurality of first subpixels and a third subpixel among the plurality of third subpixels are alternately arranged; a second pixel column in which a second subpixel among the plurality of second subpixels is alternately arranged; a third pixel column in which a third subpixel among the plurality of third subpixels and a first subpixel among the plurality of first subpixels are alternately arranged; and a fourth pixel column in which a second subpixel among the plurality of second subpixels is alternately arranged. One of the plurality of third data lines may be connected to the third subpixel in the first pixel column and the third subpixel in the third pixel column. One of the plurality of second data lines may be connected to the second subpixel in the second pixel column. One of the plurality of first data lines may be connected to the first subpixel in the third pixel column. Another of the plurality of second data lines may be connected to the second subpixel in the fourth pixel column. The plurality of data lines may further include: an additional data line connected to the first subpixel in the first pixel column. The plurality of fan-out lines may further include: a fourth fan-out line connected to the additional data line.

[0024] In an example embodiment, the plurality of source channels may further include an additional source channel configured to provide an additional data voltage corresponding to the first color to an additional data line. The channel controller may select the additional source channel and may generate a second offset value for the additional source channel. The data driver may apply the second offset value to the additional data voltage provided by the additional source channel.

[0025] In a display device according to an exemplary embodiment, the source channel to which an offset value is applied can be selected based on the structure and driving scheme of the display panel, and another source channel to which another offset value is applied can be additionally selected based on the characteristics and / or operating environment of the display panel. For example, the offset value can be applied differently for each channel and / or line in the display device, and the offset value can be further applied differently for temperature, brightness, and / or position in the display device. Therefore, load deviation can be efficiently compensated and degradation of display quality can be prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0027] Figure 1 is a block diagram illustrating a display apparatus according to example embodiments.

[0028] Figure 2 is a block diagram illustrating an example of a channel controller included in a display apparatus according to example embodiments.

[0029] Figure 3A 、 Figure 3B and Figure 4 is a diagram illustrating an example of (pixels of) a display panel and a data driver included in a display device according to example embodiments.

[0030] Figure 5A 、 Figure 5B and Figure 5C is used to describe Figure 3A 、 Figure 3B and Figure 4 A diagram showing the operation of the display panel and the data driver.

[0031] Figure 6 、 Figure 7 and Figure 8 is a diagram illustrating an example of a display panel and a data driver included in a display device according to example embodiments.

[0032] Figure 9 、 Figure 10A and Figure 10B is used to describe Figure 6 、 Figure 7 and Figure 8A diagram showing the operation of the display panel and the data driver.

[0033] Figure 11 and Figure 12 is a diagram illustrating an example of a display panel and a data driver included in a display device according to example embodiments.

[0034] Figure 13 is a block diagram illustrating a display apparatus according to example embodiments.

[0035] Figure 14A and Figure 14B is used to describe Figure 13 A diagram showing the operation of the device.

[0036] Figure 15 is a block diagram illustrating a display apparatus according to example embodiments.

[0037] Figure 16A and Figure 16B is used to describe Figure 15 A diagram showing the operation of the device.

[0038] Figure 17 is a block diagram illustrating a display apparatus according to example embodiments.

[0039] Figure 18A 、 Figure 18B 、 Figure 18C and Figure 18D is used to describe Figure 17 A diagram showing the operation of the device.

[0040] Figure 19 is a block diagram illustrating an electronic system including a display device according to example embodiments. DETAILED DESCRIPTION

[0041] Example embodiments are described more fully hereinafter with reference to the accompanying drawings.The same or similar reference numerals refer to the same or similar elements throughout.

[0042] Figure 1 is a block diagram illustrating a display apparatus 10 according to an example embodiment.

[0043] Reference Figure 1 The display device 10 includes a display panel 100 , a data driver 400 , and a channel controller 500 . The display device 10 may further include a timing controller 200 and a gate driver 300 .

[0044] The display panel 100 operates (e.g., displays an image) based on the output image data DAT. The display panel 100 is connected to a plurality of gate lines GL and a plurality of data lines DL. The plurality of gate lines GL may extend in a first direction DR1, and the plurality of data lines DL may extend in a second direction DR2 that intersects (e.g., is substantially perpendicular to) the first direction DR1.

[0045] The display panel 100 includes a plurality of sub-pixels PX arranged in a matrix. Each of the plurality of sub-pixels PX may be electrically connected to a corresponding one of a plurality of gate lines GL and a corresponding one of a plurality of data lines DL. Figure 6 As described, the display panel 100 may include a display area AA including a plurality of sub-pixels PX and a peripheral area PA surrounding the display area AA.

[0046] In an exemplary embodiment, the display panel 100 may be an organic light-emitting display (OLED) panel, and each of the plurality of sub-pixels PX may be a sub-pixel for an OLED panel including an organic light-emitting diode and a driving transistor. In an exemplary embodiment, the display panel 100 may be a liquid crystal display (LCD) panel, and each of the plurality of sub-pixels PX may be a sub-pixel for an LCD panel including a liquid crystal and a driving transistor. In an exemplary embodiment, the display panel 100 may be a micro light-emitting diode (LED) display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display (QLED) panel. However, exemplary embodiments are not limited thereto, and the display panel 100 and the plurality of sub-pixels PX may be implemented in various ways.

[0047] In an example embodiment, the plurality of sub-pixels PX may include a plurality of red sub-pixels that output red light, a plurality of green sub-pixels that output green light, and a plurality of blue sub-pixels that output blue light. In an example embodiment, the plurality of sub-pixels PX may include a plurality of yellow sub-pixels that output yellow light, a plurality of cyan sub-pixels that output cyan light, and a plurality of magenta sub-pixels that output magenta light. In an example embodiment, the plurality of sub-pixels PX may further include a plurality of white sub-pixels that output white light, or may include sub-pixels that output light of other colors.

[0048] The timing controller 200 controls the operation of the display panel 100, the gate driver 300, and the data driver 400. The timing controller 200 receives input image data IDAT and input control signals ICONT from an external device (e.g., a host device or a graphics processor). For example, the input image data IDAT may include a plurality of sub-pixel data for a plurality of sub-pixels PX. For example, the input control signals ICONT may include a master clock signal, a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and the like.

[0049] The timing controller 200 generates output image data DAT based on the input image data IDAT. For example, the timing controller 200 can selectively perform image quality compensation, spot compensation, adaptive color correction (ACC), and / or dynamic capacitance compensation (DCC) on the input image data IDAT to generate output image data DAT.

[0050] The timing controller 200 generates a first control signal GCONT for controlling the gate driver 300 and a second control signal DCONT for controlling the data driver 400 based on the input control signal ICONT. For example, the first control signal GCONT may include a vertical start signal, a gate clock signal, etc. For example, the second control signal DCONT may include a horizontal start signal, a data clock signal, a data load signal, etc.

[0051] The gate driver 300 is connected to the display panel 100 through a plurality of gate lines GL. The gate driver 300 generates a plurality of gate signals GS for driving the display panel 100 based on the first control signal GCONT. For example, the gate driver 300 may sequentially apply or provide the plurality of gate signals GS to the display panel 100 through the plurality of gate lines GL.

[0052] In example embodiments, the gate driver 300 may be an amorphous silicon gate (ASG) unit integrated in a peripheral region of the display panel 100. In example embodiments, the gate driver 300 may be provided at any region located outside the display panel 100.

[0053] The data driver 400 is connected to the display panel 100 through a plurality of data lines DL. The data driver 400 generates a plurality of data voltages DV (e.g., analog voltages) for driving the display panel 100 based on output image data DAT (e.g., digital data) and a second control signal DCONT. For example, the data driver 400 may sequentially apply or provide the plurality of data voltages DV to a plurality of lines (e.g., horizontal lines) in the display panel 100 through the plurality of data lines DL.

[0054] In example embodiments, the data driver 400 may be provided in the display panel 100 (eg, directly mounted on the display panel 100) or may be connected to the display panel 100 in a tape carrier package (TCP) type. In embodiments, the data driver 400 may be integrated in the display panel 100.

[0055] In an example embodiment, the timing controller 200, the gate driver 300, and the data driver 400 may be implemented as one integrated circuit (IC). In an example embodiment, the timing controller 200, the gate driver 300, and the data driver 400 may be implemented as two or more ICs. A driving module including at least the timing controller 200 and the data driver 400 may be referred to as a timing controller embedded data driver (TED).

[0056] If you will refer to Figure 4 and Figure 7 As described above, the data driver 400 may include a plurality of source channels that provide a plurality of data voltages DV to a plurality of data lines DL. The channel controller 500 may select at least one source channel from the plurality of source channels and may generate an offset signal OFS including an offset value applied to the selected source channel. The data driver 400 may adjust the voltage level of the data voltage provided by the selected source channel by applying the offset value to the data voltage provided by the selected source channel based on the offset signal OFS. For example, when an image having the same color and the same grayscale (or brightness or luminance) is to be displayed in the display panel 100 using a selected source channel to which the offset value is applied and an unselected source channel to which the offset value is not applied, the voltage level of the data voltage provided by the selected source channel and the voltage level of the data voltage provided by the unselected source channel may be different from each other. For example, the offset value may be changeable or variable.

[0057] In an example embodiment, as will be referred to Figure 3A 、 Figure 3B 、 Figure 4 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 11 and Figure 12 As described above, the display panel 100 may be implemented in various structures, and the source channel to which the offset value is applied may be selected and / or determined according to the structure and driving scheme of the display panel 100. In an example embodiment, as will be referred to Figure 13 、 Figure 15 and Figure 17 As described, another source channel to which another offset value is applied may be additionally selected and / or determined according to characteristics and / or operating environment of the display panel 100 .

[0058] Figure 2 is a block diagram illustrating an example of a channel controller 500 included in a display apparatus according to example embodiments.

[0059] Reference Figure 2 , also refer to Figure 1, the channel controller 500 may include a channel selection circuit 510 and a data offset control circuit 520 .

[0060] The channel selection circuit 510 may provide channel selection information CSINF for selecting at least one of a plurality of source channels included in the data driver 400. For example, the channel selection information CSINF may be pre-stored or stored in advance according to the structure and driving scheme of the display panel 100. For example, the channel selection information CSINF may be additionally provided according to the characteristics and / or operating environment of the display panel 100.

[0061] The data offset control circuit 520 may generate an offset signal OFS including an offset value applied to a selected source channel based on the channel selection information CSINF. For example, the offset value may be stored in the form of a lookup table (LUT).

[0062] In example embodiments, at least some of the components and elements of the channel controller 500 may be included in the data driver 400 and / or the timing controller 200 .

[0063] Figure 3A 、 Figure 3B and Figure 4 is a diagram illustrating an example of (the pixels PXij of) a display panel 100 a and a data driver 400 a included in a display device according to example embodiments.

[0064] Reference Figure 3A 、 Figure 3B and Figure 4 The display panel 100a may include a plurality of sub-pixels PX11, PX21, PX31, PX41, PX12, PX22, PX32, PX42, PX13, PX23, PX33, PX43, PX14, PX24, PX34, PX44, PX15, PX25, PX35, PX45, PX16, PX26, PX36, PX46, PX X17, PX27, PX37, PX47, PX18, PX28, PX38 and PX48, multiple pixel columns PC1, PC2, PC3, PC4, PC5, PC6, PC7 and PC8, multiple data lines DL1, DL2, DL3, DL4, DL5, DL6, DL7, DL8 and DLA, and multiple gate lines GL1, GL2, GL3 and GL4.

[0065] The plurality of sub-pixels PX11 to PX48 may include a first sub-pixel R displaying a first color, a second sub-pixel G displaying a second color, and a third sub-pixel B displaying a third color. Figure 3A and Figure 4An example is shown in which the first color, the second color, and the third color are red, green, and blue, respectively. However, example embodiments are not limited thereto.

[0066] The first pixel column PC1 may include subpixels PX11 to PX41. In the first pixel column PC1, the subpixels PX11 to PX41 may be alternately arranged or disposed in the order of first subpixels R and third subpixels B along a second direction DR2, which is the direction in which data lines DL1 to DL8 and DLA extend. For example, subpixels PX11 and PX31 may be first subpixels R, and subpixels PX21 and PX41 may be third subpixels B.

[0067] The second pixel column PC2 may include sub-pixels PX12 to PX42. In the second pixel column PC2, the sub-pixels PX12 to PX42 may be arranged along the second direction DR2. For example, the sub-pixels PX12 to PX42 may be second sub-pixels G.

[0068] The third pixel column PC3 may include subpixels PX13 to PX43. In the third pixel column PC3, the subpixels PX13 to PX43 may be alternately arranged along the second direction DR2 in the order of third subpixels B and first subpixels R. For example, subpixels PX13 and PX33 may be third subpixels B, and subpixels PX23 and PX43 may be first subpixels R.

[0069] The fourth pixel column PC4 may include sub-pixels PX14 to PX44. In the fourth pixel column PC4, the sub-pixels PX14 to PX44 may be arranged along the second direction DR2. For example, the sub-pixels PX14 to PX44 may be second sub-pixels G.

[0070] The fifth pixel column PC5 may include sub-pixels PX15 to PX45, the sixth pixel column PC6 may include sub-pixels PX16 to PX46, the seventh pixel column PC7 may include sub-pixels PX17 to PX47, and the eighth pixel column PC8 may include sub-pixels PX18 to PX48. The arrangement of the sub-pixels PX15 to PX45 in the fifth pixel column PC5, the sub-pixels PX16 to PX46 in the sixth pixel column PC6, the sub-pixels PX17 to PX47 in the seventh pixel column PC7, and the sub-pixels PX18 to PX48 in the eighth pixel column PC8 may be substantially the same as the arrangement of the sub-pixels PX11 to PX41 in the first pixel column PC1, the sub-pixels PX12 to PX42 in the second pixel column PC2, the sub-pixels PX13 to PX43 in the third pixel column PC3, and the sub-pixels PX14 to PX44 in the fourth pixel column PC4, respectively.

[0071] like Figure 3BAs shown in FIG, each of the plurality of sub-pixels PX11 to PX48 may include a pixel circuit PXC and a light emitting element LD. For ease of explanation, the sub-pixel PXij located on the i-th horizontal line and connected to the j-th data line DLj may be Figure 3B , where each of i and j is a positive integer. However, the sub-pixel PXij is not limited to Figure 3B The structure shown in , and may have various structures.

[0072] The pixel circuit PXC may include a plurality of transistors T1 , T2 , T3 , T4 , T5 , T6 , and T7 and a storage capacitor CST.

[0073] The first transistor (or driving transistor) T1 may have a gate electrode connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The first transistor T1 may control a driving current Id in response to a voltage at the first node N1. The driving current Id flows from a first power line providing a first power supply voltage VDD to a second power line providing a second power supply voltage VSS via the light-emitting element LD. For example, the first power supply voltage VDD may be set to a higher voltage level than the second power supply voltage VSS.

[0074] The second transistor T2 may be connected between the j-th data line DLj and the second node N2 and may have a gate electrode connected to the i-th gate line GLi. The second transistor T2 may be turned on in response to a gate-on voltage level of a gate signal supplied to the i-th gate line GLi, and when the second transistor T2 is turned on, the j-th data line DLj and the second node N2 may be electrically connected.

[0075] The third transistor T3 may be connected between the first electrode (or the fourth node N4) of the light emitting element LD and an initialization line that supplies the initialization voltage VINT, and the third transistor T3 may have a gate electrode connected to the i-th gate line GLi. The third transistor T3 may be turned on in response to a gate-on voltage level of a gate signal supplied to the i-th gate line GLi, and when the third transistor T3 is turned on, the initialization voltage VINT may be supplied to the first electrode (or the fourth node N4) of the light emitting element LD.

[0076] The fourth transistor T4 may be connected between the first node N1 and the initialization line, and the fourth transistor T4 may have a gate electrode connected to the (i-1)th gate line GLi-1. The fourth transistor T4 may be turned on by the gate-on voltage level of the gate signal supplied to the (i-1)th gate line GLi-1, and when the fourth transistor T4 is turned on, the initialization voltage VINT may be supplied to the first node N1.

[0077] The fifth transistor T5 may be connected between the first power line and the second node N2, and may have a gate electrode connected to the i-th emission control line Ei. The fifth transistor T5 may be turned on by the gate-on voltage level of the emission control signal supplied to the i-th emission control line Ei. For example, the display device may further include an emission driver that generates the emission control signal, and / or the gate driver 300 may further generate / provide the emission control signal.

[0078] The sixth transistor T6 may be connected between the second electrode (or third node N3) of the first transistor T1 and the first electrode (or fourth node N4) of the light-emitting element LD, and may have a gate electrode connected to the i-th emission control line Ei. The sixth transistor T6 may be turned on in response to the gate-on voltage level of the emission control signal supplied to the i-th emission control line Ei. Thus, the fifth transistor T5 and the sixth transistor T6 may be controlled simultaneously.

[0079] The seventh transistor T7 may be connected between the second electrode (or third node N3) of the first transistor T1 and the first node N1, and may have a gate electrode connected to the i-th gate line GLi. The seventh transistor T7 may be turned on in response to the gate-on voltage level of the gate signal supplied to the i-th gate line GLi, and when the seventh transistor T7 is turned on, the second electrode of the first transistor T1 and the first node N1 may be electrically connected. In other words, when the seventh transistor T7 is turned on, the first transistor T1 may be connected in a diode configuration.

[0080] The storage capacitor CST may be connected between the first power line and the first node N1 .

[0081] The light emitting element LD may have a first electrode (or anode) connected to the fourth node N4 and a second electrode (or cathode) connected to the second power line. The light emitting element LD may generate light having a predetermined brightness or luminance in response to the amount of current supplied from the first transistor T1.

[0082] In example embodiments, the light emitting element LD may be an organic light emitting diode including an organic light emitting layer. In example embodiments, the light emitting element LD may be an inorganic light emitting element including an inorganic material. For example, the light emitting element LD may have a form in which the inorganic light emitting element is connected in parallel and / or in series between the second power line and the fourth node N4.

[0083] In example embodiments, the gate lines to which the transistors T2, T3, T4, and T7 are connected may be determined based on various pixel structures. For example, the fourth transistor T4 may be connected to another gate line other than the (i-1)th gate line GLi-1, and the fourth transistor T4 may be driven by the other gate line. For example, the third transistor T3 may be connected to another gate line other than the i-th gate line GLi, and the third transistor T3 may be driven by the other gate line.

[0084] The first data line DL1 can be electrically connected to the third sub-pixels B (e.g., sub-pixels PX13, PX21, PX33, and PX41) in the first pixel column PC1 and the third pixel column PC3. In other words, the first data line DL1 can be alternately connected to the sub-pixels on both sides (e.g., left / right) relative to the first data line DL1, and the first data line DL1 can be referred to as a third color data line connected to the third sub-pixel B.

[0085] The second data line DL2 can be electrically connected to the second sub-pixels G (e.g., sub-pixels PX12 to PX42) in the second pixel column PC2. In other words, the second data line DL2 can be connected to the sub-pixels on one side (e.g., the left side) relative to the second data line DL2, and the second data line DL2 can be referred to as a second color data line connected to the second sub-pixels G.

[0086] The third data line DL3 may be electrically connected to the first sub-pixels R (e.g., sub-pixels PX15, PX23, PX35, and PX43) in the third pixel column PC3 and the fifth pixel column PC5. In other words, the third data line DL3 may be alternately connected to the sub-pixels on both sides relative to the third data line DL3, and the third data line DL3 may be referred to as a first color data line connected to the first sub-pixels R.

[0087] The fourth data line DL4 can be electrically connected to the second sub-pixels G (e.g., sub-pixels PX14 to PX44) in the fourth pixel column PC4. Like the second data line DL2, the fourth data line DL4 can be connected to the sub-pixels on the side relative to the fourth data line DL4, and the fourth data line DL4 can be referred to as a second color data line connected to the second sub-pixels G.

[0088] The connections between the fifth data line DL5, the sixth data line DL6, the seventh data line DL7, and the eighth data line DL8 and the subpixels may be substantially the same as the connections between the first data line DL1, the second data line DL2, the third data line DL3, and the fourth data line DL4 and the subpixels, respectively. For example, the fifth data line DL5 may be electrically connected to the subpixels PX17, PX25, PX37, and PX45 (e.g., the third subpixel B) in the fifth pixel column PC5 and the seventh pixel column PC7, the sixth data line DL6 may be electrically connected to the subpixels PX16 to PX46 (e.g., the second subpixel G) in the sixth pixel column PC6, the seventh data line DL7 may be electrically connected to the subpixels PX27 and PX47 (e.g., the first subpixel R) in the seventh pixel column PC7 and other first subpixels (not shown) in the ninth pixel column, and the eighth data line DL8 may be electrically connected to the subpixels PX18 to PX48 (e.g., the second subpixel G) in the eighth pixel column PC8.

[0089] The additional data line DLA may be electrically connected to the first sub-pixels R (e.g., sub-pixels PX11 and PX31) in the first pixel column PC1. The additional data line DLA may be connected to the sub-pixels on one side (e.g., the right side) relative to the additional data line DLA, and the additional data line DLA may be referred to as a first color data line connected to the first sub-pixels R. The additional data line DLA may also be referred to as a dummy data line.

[0090] Subpixels PX11 to PX18 may be electrically connected to a first gate line GL1 and may form a first pixel row. Similarly, subpixels PX21 to PX28 may be electrically connected to a second gate line GL2 and may form a second pixel row, subpixels PX31 to PX38 may be electrically connected to a third gate line GL3 and may form a third pixel row, and subpixels PX41 to PX48 may be electrically connected to a fourth gate line GL4 and may form a fourth pixel row.

[0091] exist Figure 3A and Figure 4 In the display panel 100 a , sub-pixels (eg, PX11 to PX14 ) of the RGBG structure may form one pixel, and a plurality of pixels may be disposed or arranged along the first direction DR1 and the second direction DR2 . Figure 3A and Figure 4 An example in which the display panel 100 a includes thirty-two sub-pixels (eg, eight pixels) is shown, however, the number of sub-pixels and / or pixels may be variously determined according to example embodiments.

[0092] In addition, Figure 3A and Figure 4In the display panel 100a, connections between sub-pixels and data lines may be implemented using a combination of an alternating structure and a non-alternating structure, and therefore, the number of data lines may be one more than the number of pixel columns. Figure 3A and Figure 4 An example is shown where the additional data line DLA is located at the leftmost side of the display panel 100 a , however, the additional data line DLA may be located at the rightmost side of the display panel according to example embodiments.

[0093] The data driver 400 a may include a plurality of source channels CH1 , CH2 , CH3 , CH4 , CH5 , CH6 , CH7 , CH8 , and CHA.

[0094] The first source channel CH1 can provide a first data voltage corresponding to the third color to the first data line DL1. The second source channel CH2 can provide a second data voltage corresponding to the second color to the second data line DL2. The third source channel CH3 can provide a third data voltage corresponding to the first color to the third data line DL3. The fourth source channel CH4 can provide a fourth data voltage corresponding to the second color to the fourth data line DL4. The fifth source channel CH5 can provide a fifth data voltage corresponding to the third color to the fifth data line DL5. The sixth source channel CH6 can provide a sixth data voltage corresponding to the second color to the sixth data line DL6. The seventh source channel CH7 can provide a seventh data voltage corresponding to the first color to the seventh data line DL7. The eighth source channel CH8 can provide an eighth data voltage corresponding to the second color to the eighth data line DL8. The additional source channel CHA can provide an additional data voltage corresponding to the first color to the additional data line DLA. The additional source channel CHA can be referred to as a dummy source channel.

[0095] When the display panel 100 a has the above-described structure, each of the plurality of source channels CH1 to CH8 and CHA may generate and output a data voltage corresponding to a single color, thereby reducing power consumption.

[0096] Figure 5A 、 Figure 5B and Figure 5C is used to describe Figure 3A 、 Figure 3B and Figure 4 FIG. 1 is a diagram illustrating operations of the display panel 100 a and the data driver 400 a.

[0097] Reference Figure 1 and Figure 5A , also refer to Figure 3A and Figure 4, shows an example of a change in data voltage during time intervals t1, t2, t3, and t4. For example, each of the time intervals t1, t2, t3, and t4 may represent one horizontal time interval (1H), during which one line image is displayed in the display panel.

[0098] When the display panel 100a has Figure 3A 、 Figure 3B and Figure 4 , the channel controller 500 may select an additional source channel CHA from among the plurality of source channels CH1 to CH8 and CHA, and may generate an offset signal OFS including an offset value OV11 applied to the additional source channel CHA. The data driver 400a may adjust the voltage level of the additional data voltage DV@DLA by applying the offset value OV11 to the additional data voltage DV@DLA.

[0099] Figure 5A 1 shows an example of a difference in data voltages depending on whether an offset value OV11 is applied when an image having the same grayscale is displayed on the display panel 100a. For example, the difference in data voltages DV@DL3 and DV@DLA for data lines DL3 and DLA connected to first subpixels R having the same color is shown.

[0100] When the sub-pixels PX15, PX23, PX35, and PX43 connected to the third data line DL3 are driven to have a first grayscale (e.g., the same grayscale), the third data voltage DV@DL3 provided to the third data line DL3 by the third source channel CH3 may have a first voltage level VL1 as a constant voltage level. For example, the sub-pixel PX15 in the first pixel row may be driven during the time interval t1, the sub-pixel PX23 in the second pixel row may be driven during the time interval t2, the sub-pixel PX35 in the third pixel row may be driven during the time interval t3, and the sub-pixel PX43 in the fourth pixel row may be driven during the time interval t4.

[0101] In contrast, when the subpixels PX11 and PX31 connected to the additional data line DLA are driven to have a first grayscale level, the additional data voltage DV@DLA provided by the additional source channel CHA to the additional data line DLA may have an offset value OV11 applied to the voltage level of the first voltage level VL1. For example, the offset value OV11 may be a real number greater than zero. For example, the subpixel PX11 in the first pixel row may be driven during time interval t1, and the subpixel PX31 in the third pixel row may be driven during time interval t3.

[0102] Reference Figure 1 、 Figure 5B and Figure 5C , also refer to Figure 3A and Figure 4 , shows an example of the change of the additional data voltage DV@DLA during the time intervals t1, t2, t3 and t4. For the sake of brevity, the Figure 5A Description of duplicate description.

[0103] In an example embodiment, Figure 5B As shown in , the offset value OV12 applied to the additional source channel CHA and the additional data voltage DV@DLA may be a real number less than 0. In other words, not only a positive offset value but also a negative offset value may be applied.

[0104] In an example embodiment, Figure 5C As shown in FIG, the offset values ​​OV11 and OV11′ applied to the additional source channel CHA and the additional data voltage DV@DLA may vary depending on the position of the subpixels PX11 and PX31 (e.g., depending on time intervals t1 and t3 and / or depending on a horizontal line). For example, in time interval t1 when driving the subpixel PX11 and the corresponding line image, the additional data voltage DV@DLA may have a voltage level at which the offset value OV11 is applied to the first voltage level VL1. For example, in time interval t3 when driving the subpixel PX31 and the corresponding line image, the additional data voltage DV@DLA may have a voltage level at which the offset value OV11 is applied to the first voltage level VL1, which is different from (e.g., greater than) the offset value OV11. Although not shown in detail, according to example embodiments, different negative offset values ​​may be applied for different time intervals, and / or a positive offset value may be applied for some time intervals and a negative offset value may be applied for other time intervals.

[0105] As described above, when the display panel 100a has Figure 3A 、 Figure 3B and Figure 4 , and when offset values ​​are applied to the additional source channels CHA (eg, when offset values ​​are applied differently for channels and / or lines), load deviations caused by structural differences in the data lines can be efficiently compensated.

[0106] However, example embodiments are not limited thereto. For example, another offset value may be additionally applied to at least one of the source channels CH1 to CH8 in addition to the additional source channel CHA. For example, the another offset value applied to the other source channel may be different from or substantially the same as the offset value applied to the additional source channel CHA.

[0107] Figure 6 、 Figure 7and Figure 8 is a diagram illustrating an example of a display panel 100 b and a data driver 400 b included in a display device according to an example embodiment. Figure 6 is a plan view showing a display panel 100b and a data driver 400b, Figure 7 yes Figure 6 A magnified view of region A in FIG, and Figure 8 It shows the settings Figure 6 Schematic diagram of the sub-pixel PX in area AA1 in FIG.

[0108] Reference Figure 6 、 Figure 7 and Figure 8 , also refer to Figure 1 , the display panel 100b may include a display area AA including a plurality of sub-pixels PX and a peripheral area PA surrounding the display area AA. For example, the data driver 400b may be installed in / on the peripheral area PA.

[0109] The display area AA may include a first display area AA1, a second display area AA2 disposed adjacent to the first display area AA1 along a first direction DR1, and a third display area AA3 disposed adjacent to the second display area AA2 along the first direction DR1. For example, the first display area AA1 may include an edge area of ​​the display area AA. For example, the edge area of ​​the display area AA may have a curved shape.

[0110] The plurality of sub-pixels PX may include a first sub-pixel R displaying a first color, a second sub-pixel G displaying a second color, and a third sub-pixel B displaying a third color. For example, the plurality of sub-pixels PX may include a first sub-pixel R displaying a first color, a second sub-pixel G displaying a second color, and a third sub-pixel B displaying a third color. Figure 8 are arranged and connected as shown in .

[0111] The display panel 100b may include a plurality of data lines RDL, GDL, and BDL. The first data line RDL may be connected to the first subpixel R, the second data line GDL may be connected to the second subpixel G, and the third data line BDL may be connected to the third subpixel B.

[0112] At least one of the first data line RDL and the third data line BDL may be connected to sub-pixels that are arranged in different columns and emit light of the same color. Figure 8 As shown in FIG, the third data line BDL may be connected to third sub-pixels B displaying a third color in different columns (eg, in the first column and the third column).

[0113] The arrangement and connection of the above sub-pixels R, G, and B and the above data lines RDL, GDL, and BDL may be the same as those in the referenced embodiment, except that the additional data line DLA is omitted. Figure 3A 、 Figure 3Band Figure 4 The arrangements and connections described are similar.

[0114] The display panel 100b may include a plurality of fan-out lines FL1, FL2, and FL3. The first fan-out line FL1 may be connected to the data lines RDL, GDL, and BDL connected to the sub-pixels disposed in the first display area AA1. The second fan-out line FL2 may be connected to the data lines RDL, GDL, and BDL connected to the sub-pixels disposed in the second display area AA2. The first fan-out lines FL1 and the second fan-out lines FL2 may be alternately disposed in the peripheral area PA. The third fan-out line FL3 may be connected to the data lines RDL, GDL, and BDL connected to the sub-pixels disposed in the third display area AA3.

[0115] The first fan-out line FL1 may be connected to the data lines RDL, GDL, and BDL via the display area AA and the peripheral area PA. In other words, the first fan-out line FL1 may be disposed in the display area AA and the peripheral area PA. For example, the first fan-out line FL1 and the data lines RDL, GDL, and BDL disposed in the first display area AA1 may be disposed on different layers and may contact each other through the contact hole CNT.

[0116] The second fan-out line FL2 and the third fan-out line FL3 can be connected to the data lines RDL, GDL, and BDL via the peripheral area PA. For example, the second fan-out line FL2 and the data lines RDL, GDL, and BDL disposed in the second display area AA2 can be disposed on different layers and can contact each other through contact holes CNT. For example, the third fan-out line FL3 and the data lines RDL, GDL, and BDL disposed in the third display area AA3 can be disposed on different layers and can contact each other through contact holes CNT.

[0117] The data driver 400b may include a plurality of source channels CHR, CHG, and CHB. The first source channel CHR may provide a first data voltage corresponding to a first color to the first data line RDL, the second source channel CHG may provide a second data voltage corresponding to a second color to the second data line GDL, and the third source channel CHB may provide a third data voltage corresponding to a third color to the third data line BDL.

[0118] The data driver 400b may include a first output pad OP1 and a second output pad OP2. The first output pad OP1 may output a data voltage to the first and second fan-out lines FL1 and FL2, and the second output pad OP2 may output a data voltage to the third fan-out line FL3.

[0119] When the display panel 100b has the above structure, the data lines RDL, GDL, and BDL and the plurality of source channels CHR, CHG, and CHB in the first display area AA1 may be connected to each other through the first fan-out line FL1, thereby reducing a useless space (eg, the peripheral area PA).

[0120] In an example embodiment, source output remapping may be performed on at least some of the plurality of source channels CHR, CHG, and CHB. In other words, the output image data DAT may be generated by remapping the input image data IDAT so that the arrangement of data voltages based on the output image data DAT may differ from the arrangement of data voltages based on the input image data IDAT. For example, depending on the structure of the subpixels PX, the arrangement of the data lines RDL, GDL, and BDL, and the arrangement of the fan-out lines FL1, FL2, and FL3, the data driver 400b may output the remapped data voltages to the remapped source channels on which source output remapping is performed. For example, the remapped source channels may be at least some of the plurality of source channels CHR, CHG, and CHB.

[0121] For example, the first and second fan-out lines FL1 and FL2 may be repeatedly connected to the data lines RDL, GDL, and BDL in a first arrangement, and the third fan-out line FL3 may be repeatedly connected to the data lines RDL, GDL, and BDL in a second arrangement different from the first arrangement. The data driver 400b may output data voltages to the first and second fan-out lines FL1 and FL2 according to the first arrangement, and may output data voltages to the third fan-out line FL3 according to the second arrangement. For example, the first arrangement may be GGRRGGBB, and the second arrangement may be GRGB, but example embodiments are not limited thereto. Since the first fan-out lines FL1 and the data lines RDL, GDL, and BDL are arranged on different layers, and since the first fan-out lines FL1 are connected to the data lines RDL, GDL, and BDL via the display area AA, the first and second fan-out lines FL1 and FL2 may be alternately arranged, and the first fan-out lines FL1 may intersect the data lines RDL, GDL, and BDL in the display area AA. Therefore, although the subpixels have an RGBG structure, the first arrangement may consist of eight colors of GGRRGGBB. Here, eight colors do not refer to eight colors. The timing controller 200 may remap the input image data IDAT based on the first and second arrangements to generate output image data DAT, and may control the data driver 400b to output a remapped data voltage for remapping the source channel.

[0122] Figure 9 、 Figure 10A and Figure 10B is used to describe Figure 6 、 Figure 7 and Figure 8 FIG. 1 is a diagram illustrating the operation of the display panel 100 b and the data driver 400 b.

[0123] Reference Figure 9 , an example in which source output remapping is not performed is shown as case 1 (CASE1), and an example in which source output remapping is performed is shown as case 2 (CASE2).

[0124] In example CASE1 where source output remapping is not performed, all outputs S1, S2, S3, ..., S80, S81, S82, S83, S84, ..., S877, S878, S879, S880, S881, ..., S1078, S1079 and S1080 of the first source channel to the 1080th source channel can be unchanged and can be maintained.

[0125] In the example case 2 where source output remapping is performed, the outputs of some source channels may not be changed and may be maintained, while the outputs of other source channels may be changed. For example, in case 1 and case 2, the arrangement of the outputs S1 to S80 from the first to the 80th source channels and the arrangement of the outputs S881 to S1080 from the 881st to the 1080th source channels may be the same. For example, the arrangement of the outputs S81 to S880 from the 81st to the 880th source channels may be different in case 1 and case 2. In other words, in case 2, the 81st to the 880th source channels may be the remapped source channels for which source output remapping is performed.

[0126] However, example embodiments are not limited thereto. For example, the total number of source channels, the number of remapped source channels, the arrangement of outputs when source output remapping is performed, etc. may be determined differently according to example embodiments.

[0127] Reference Figure 1 and Figure 10A , also refer to Figure 6 and Figure 7 , shows an example of the change of the data voltage during the time intervals t1, t2, t3 and t4. For the sake of brevity, the Figure 5A 、 Figure 5B and Figure 5C Description of duplicate description.

[0128] When the display panel 100b has Figure 6 、 Figure 7 and Figure 8, the channel controller 500 may select a remapping source channel (eg, a source channel) on which source output remapping is to be performed among a plurality of source channels CHR, CHG, and CHB. Figure 9 The 81st source channel to the 880th source channel in the remapped source channel are configured, and the channel controller 500 may generate an offset signal OFS including an offset value OV21 applied to the remapped source channel. The data driver 400b may adjust the voltage level of the remapped data voltage by applying the offset value OV21 to the remapped data voltage output by the remapped source channel.

[0129] Figure 10A An example of a difference in data voltage depending on whether an offset value OV21 is applied (eg, whether source output remapping is performed) when an image having the same grayscale is displayed in the display panel 100 b is shown.

[0130] The data voltage DV@DLRX supplied to the data line connected to the source channel on which source output remapping is not performed may have the second voltage level VL2. In contrast, the remapped data voltage DV@DLRO supplied to the data line connected to the remapped source channel may have a voltage level applied to the second voltage level VL2 by an offset value OV21.

[0131] Reference Figure 1 and Figure 10B , also refer to Figure 6 , shows an example of remapping changes in the data voltages DV@DLRO1 , DV@DLRO2 , and DV@DLRO3 during time intervals t1 , t2 , t3 , and t4 .

[0132] In example embodiments, the offset values ​​OV21, OV22, and OV23 applied to the remapped source channels may vary depending on the positions of the remapped source channels. For example, the offset value OV21 applied to the first remapped data voltage DV@DLRO1 provided by the first remapped source channel, the offset value OV22 applied to the second remapped data voltage DV@DLRO2 provided by the second remapped source channel, and the offset value OV23 applied to the third remapped data voltage DV@DLRO3 provided by the third remapped source channel may be different from each other. The offset values ​​OV21, OV22, and OV23 may be determined differently according to example embodiments. In example embodiments, as shown in FIG. Figure 5C As described, the offset values ​​OV21 , OV22 , and OV23 may vary depending on the position, time interval, and / or horizon.

[0133] As described above, when the display panel 100b has Figure 6 、 Figure 7 and Figure 8 When the structure shown in is used, and when offset values ​​are applied to the remapped source channels (eg, when offset values ​​are applied differently for channels and / or lines), loading deviations can be efficiently compensated for.

[0134] However, example embodiments are not limited thereto. For example, another offset value may be additionally applied to at least one of the source channels other than the remapped source channel. For example, the another offset value applied to the other source channel may be different from or substantially the same as the offset value applied to the remapped source channel.

[0135] Figure 11 and Figure 12 4 is a diagram showing an example of a display panel and a data driver 400c included in a display device according to an example embodiment. Figure 6 、 Figure 7 and Figure 8 Description of duplicate description.

[0136] Reference Figure 11 and Figure 12 , also refer to Figure 1 ,Apart from Figure 11 and Figure 12 The display panel further includes an additional data line DLA in the first display area AA1' and a fourth fan-out line FL4 connected to the additional data line DLA, and in addition to Figure 11 The data driver 400c further includes an additional source channel CHA connected to the additional data line DLA, the fourth fan-out line FL4 and the first dummy pad DP1. Figure 11 and Figure 12 The structure can be Figure 6 、 Figure 7 and Figure 8 The additional data line DLA and the additional source channel CHA can be connected to the reference Figure 3A 、 Figure 3B and Figure 4 The additional data line DLA and the additional source channel CHA described are substantially identical.

[0137] Figure 11 and Figure 12 The structure can be combined Figure 3A 、 Figure 3B and Figure 4 The structure and Figure 6 、 Figure 7 and Figure 8 Therefore, each source channel can generate and output a data voltage corresponding to a single color, thereby reducing power consumption. In addition, the data line in the first display area AA1' and the multiple source channels can be connected to each other through the first fan-out line FL1, thereby reducing useless space.

[0138] When the display panel has Figure 11 and Figure 12 When the structure shown in FIG. 5 is used, the channel controller 500 can select additional source channels CHA and remap source channels (e.g., Figure 9 The data driver 400c may adjust the voltage level of the data voltage by applying the offset value to the data voltage output by the additional source channel CHA and the remapped source channel.

[0139] Figure 13 is a block diagram illustrating a display apparatus 10 a according to an example embodiment. Figure 14A and Figure 14B is used to describe Figure 13 FIG. 1 shows an operation of the display device 10 a.

[0140] Reference Figure 13 The display device 10a includes a display panel 100, a data driver 400, and a channel controller 500a. The display device 10a may further include a timing controller 200, a gate driver 300, and a temperature sensor 600.

[0141] Except that the display device 10a further includes the temperature sensor 600 and the operation of the channel controller 500a is partially changed, Figure 13 The display device 10a can be used with Figure 1 The display devices 10 are substantially the same.

[0142] The temperature sensor 600 may detect or sense an operating temperature and may generate temperature information TINF representing or indicating the operating temperature.

[0143] The channel controller 500a may also select at least one selected source channel based on the temperature information TINF, and the channel controller 500a may also generate a second offset value for the at least one selected source channel. For example, the at least one selected source channel may be a second offset value other than the reference channel. Figure 4 The additional source channel CHA described and / or reference Figure 9 The data driver 400 may also adjust the voltage level of the selected data voltage by applying a second offset value to the selected data voltage provided by at least one selected source channel.

[0144] Reference Figure 14A and Figure 14B , showing an example of a change in the offset value according to the operating temperature.

[0145] In an example embodiment, Figure 14A As shown in , as the operating temperature increases, the second offset value applied to at least one selected source channel may increase. In an example embodiment, as Figure 14B As shown in , as the operating temperature increases, the second offset value applied to at least one selected source channel may decrease. However, example embodiments are not limited thereto, and the relationship between the operating temperature and the second offset value may be determined differently according to example embodiments.

[0146] Figure 15 is a block diagram illustrating a display device 10b according to an example embodiment. Figure 16A and Figure 16B is used to describe Figure 15 FIG. 10B shows an operation of the display device 10 b.

[0147] Reference Figure 15 The display device 10b includes a display panel 100, a data driver 400, and a channel controller 500b. The display device 10b may further include a timing controller 200b and a gate driver 300.

[0148] Except that the operations of the timing controller 200b and the channel controller 500b are partially changed, Figure 15 The display device 10b can be used with Figure 1 The display devices 10 are substantially the same.

[0149] The timing controller 200 b may also provide brightness information DBVINF indicating the brightness of an image displayed in the display panel 100 .

[0150] The channel controller 500b may also select at least one selected source channel based on the brightness information DBVINF, and may also generate a second offset value for the at least one selected source channel. For example, the at least one selected source channel may be a second offset value other than the reference channel. Figure 4 The additional source channel CHA described and / or reference Figure 9 The data driver 400 may also adjust the voltage level of the selected data voltage by applying a second offset value to the selected data voltage provided by at least one selected source channel.

[0151] Reference Figure 16A and Figure 16B , showing an example of a change in an offset value according to brightness.

[0152] In an example embodiment, Figure 16A As shown in , as the brightness of the image increases, the second offset value applied to at least one selected source channel may increase. In an example embodiment, as shown in Figure 16BAs shown in , as the brightness of the image increases, the second offset value applied to at least one selected source channel may decrease. However, example embodiments are not limited thereto, and the relationship between the brightness of the image and the second offset value may be determined differently according to example embodiments.

[0153] Figure 17 is a block diagram illustrating a display device 10 c according to an example embodiment. Figure 18A 、 Figure 18B 、 Figure 18C and Figure 18D is used to describe Figure 17 FIG. 10A shows an operation of the display device 10c.

[0154] Reference Figure 17 The display device 10c includes a display panel 100, a data driver 400, and a channel controller 500c. The display device 10c may further include a timing controller 200c and a gate driver 300.

[0155] Except that the operations of the timing controller 200c and the channel controller 500c are partially changed, Figure 17 The display device 10c can be used with Figure 1 The display devices 10 are substantially the same.

[0156] The timing controller 200 c may provide position information PINF associated with or related to the positions of the plurality of source channels.

[0157] The channel controller 500c may also select at least one selected source channel based on the position information PINF, and the channel controller 500c may also generate a second offset value for the at least one selected source channel. For example, the at least one selected source channel may be a second offset value other than the reference channel. Figure 4 The additional source channel CHA described and / or reference Figure 9 The data driver 400 may also adjust the voltage level of the selected data voltage by applying a second offset value to the selected data voltage provided by at least one selected source channel.

[0158] Reference Figure 18A and Figure 18B , shows the display panel 100 (see Figure 17 ) in FIG. 1 . An example of the change in resistance and offset value at a position in FIG. 1 .

[0159] In an example embodiment, Figure 18A As shown in , as the position approaches the center CENT of the display panel 100, the resistance can be reduced due to the characteristics of the manufacturing process. Figure 18BAs shown in , a relatively large offset value may be applied to a source channel relatively close to the center CENT of the display panel 100, and a relatively small offset value may be applied to a source channel relatively far from the center CENT of the display panel 100 (e.g., relatively close to an edge of the display panel 100). For example, among a plurality of source channels, a source channel connected to a sub-pixel disposed at the center CENT of the display panel 100 may be selected as at least one selected source channel, and a second offset value may be applied with respect to the at least one selected source channel.

[0160] Reference Figure 18C and Figure 18D , showing an example of a change in the offset value according to the length of the fan-out line.

[0161] As reference Figure 7 As described above, the length of the fan-out line connected to the data line can be based on the display panel 100 (see Figure 17 ) changes depending on the position in the fan-out line. Therefore, the operation of selecting at least one selected source channel based on the positions of the plurality of source channels can be described as the operation of selecting at least one selected source channel based on the length of the fan-out line.

[0162] In an example embodiment, Figure 18C As shown in , as the length of the fan-out line increases, the second offset value applied to at least one selected source channel may increase. In an example embodiment, as shown in Figure 18D As shown in , as the length of the fan-out line increases, the second offset value applied to at least one selected source channel may decrease. However, example embodiments are not limited thereto, and the relationship between the length of the fan-out line and the second offset value may be determined differently according to example embodiments.

[0163] In an exemplary embodiment, a display device according to an exemplary embodiment may be configured by combining Figure 13 、 Figure 15 and Figure 17 can be implemented by two or more of the examples.

[0164] Figure 19 is a block diagram illustrating an electronic system 1000 including a display device 1040 according to example embodiments.

[0165] Reference Figure 19 , the electronic system 1000 includes a processor 1010 , a memory 1020 , a storage device 1030 , a display device 1040 , an input / output (I / O) device 1050 , and a power supply device 1060 .

[0166] The processor 1010 may perform various computing functions such as specific calculations and tasks. For example, the processor 1010 may be a central processing unit (CPU), a microprocessor, an application processor (AP), or the like.

[0167] The memory 1020 and the storage device 1030 may store data required for operating the electronic system 1000 and / or data processed by the processor 1010. For example, the memory 1020 may include a volatile memory such as a dynamic random access memory (DRAM), a static random access memory (SRAM), and / or a non-volatile memory such as an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), a nano-floating gate memory (NFGM), or a polymer random access memory (PoRAM). The storage device 1030 may include a compact disc read-only memory (CD-ROM), a hard disk drive (HDD), a solid-state drive (SSD), and the like.

[0168] The I / O device 1050 may include at least one input device such as a keyboard, buttons, a microphone, or a touch screen, and / or at least one output device such as a speaker or a printer, etc. The power supply device 1060 may provide power to the electronic system 1000 .

[0169] The display device 1040 may be a display device according to an example embodiment. Figures 1 to 12 As described, the offset values ​​may be applied differently for channels and / or lines in the display device 1040. For example, as described with reference to Figure 13 to Figure 1 8, the offset value may be further applied differently with respect to temperature, brightness, and / or position in the display device 1040. Therefore, load deviation may be efficiently compensated, and degradation of display quality may be prevented.

[0170] Example embodiments may be applied to various devices and / or systems including display devices. For example, example embodiments may be applied to devices or systems such as personal computers (PCs) (such as tablet computers or laptop computers), workstations, mobile phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, video cameras, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, and the like.

[0171] The foregoing is illustrative of example embodiments and is not to be construed as limiting the same. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the example embodiments. Therefore, all such modifications are intended to be included within the scope of the example embodiments as defined in the claims. Therefore, it will be understood that the foregoing is illustrative of various example embodiments and is not to be construed as limiting the specific example embodiments disclosed, and that modifications of the disclosed example embodiments and other example embodiments are intended to be included within the scope of the appended claims.

Claims

1. A display device, wherein: The display device comprises: A display panel, the display panel comprising: A plurality of sub-pixels, each of the plurality of sub-pixels comprising a pixel circuit and a light-emitting element, the plurality of sub-pixels comprising: a plurality of first sub-pixels configured to display a first color; a plurality of second sub-pixels configured to display a second color; and a plurality of third sub-pixels configured to display a third color; A plurality of pixel columns, the plurality of pixel columns comprising: a first pixel column, in which first subpixels among the plurality of first subpixels and third subpixels among the plurality of third subpixels are alternately arranged; a second pixel column, in which a second sub-pixel among the plurality of second sub-pixels is arranged; a third pixel column in which third subpixels among the plurality of third subpixels and first subpixels among the plurality of first subpixels are alternately arranged; and a fourth pixel column, in which the second sub-pixels among the plurality of second sub-pixels are arranged; and A plurality of data lines, the plurality of data lines comprising: a first data line connected to the third sub-pixel in the first pixel column and the third sub-pixel in the third pixel column; a second data line connected to the second sub-pixel in the second pixel column; a third data line connected to the first sub-pixel in the third pixel column; a fourth data line connected to the second sub-pixel in the fourth pixel column; and an additional data line connected to the first sub-pixel in the first pixel column; and a data driver configured to adjust a voltage level of the additional data voltage by applying an offset value to the additional data voltage, the data driver comprising: A plurality of source channels, the plurality of source channels comprising: a first source channel configured to provide a first data voltage corresponding to the third color to the first data line; a second source channel configured to provide a second data voltage corresponding to the second color to the second data line; a third source channel configured to provide a third data voltage corresponding to the first color to the third data line; a fourth source channel configured to provide a fourth data voltage corresponding to the second color to the fourth data line; and an additional source channel configured to provide the additional data voltage corresponding to the first color to the additional data line; and A channel controller is configured to select the additional source channel among the plurality of source channels and generate the offset value for the additional source channel.

2. The display device according to claim 1, wherein The offset value can be changed.

3. The display device according to claim 2, wherein The channel controller is configured to change the offset value applied to the additional data voltage according to a position of the first sub-pixel connected to the additional data line in the first pixel column. The display device according to claim 1 , wherein: The channel controller is configured to select at least one selected source channel other than the additional source channel among the plurality of source channels and generate a second offset value for the at least one selected source channel, and The data driver is configured to adjust a voltage level of the selected data voltage by applying the second offset value to the selected data voltage provided by the at least one selected source channel.

5. The display device according to claim 4, wherein The display device further includes: a temperature sensor configured to detect an operating temperature, and The channel controller is configured to select the at least one selected source channel based on the operating temperature detected by the temperature sensor. The display device according to claim 4 , wherein: The channel controller is configured to select the at least one selected source channel based on brightness of an image displayed in the display panel.

7. The display device according to claim 4, wherein The channel controller is configured to select the at least one selected source channel based on a plurality of positions of the plurality of source channels.

8. The display device according to claim 7, wherein Among the plurality of source channels, a source channel connected to a sub-pixel disposed at the center of the display panel among the plurality of sub-pixels is selected as the at least one selected source channel.

9. The display device according to claim 1, in, The plurality of pixel columns further include: a fifth pixel column, in which first subpixels among the plurality of first subpixels and third subpixels among the plurality of third subpixels are alternately arranged; a sixth pixel column, in which a second sub-pixel among the plurality of second sub-pixels is arranged; a seventh pixel column in which third subpixels among the plurality of third subpixels and first subpixels among the plurality of first subpixels are alternately arranged; and an eighth pixel column, in which a second sub-pixel among the plurality of second sub-pixels is arranged, Wherein, the plurality of data lines further include: a fifth data line connected to the third sub-pixel in the fifth pixel column and the third sub-pixel in the seventh pixel column; a sixth data line connected to the second sub-pixel in the sixth pixel column; a seventh data line connected to the first sub-pixel in the seventh pixel column; and an eighth data line connected to the second sub-pixel in the eighth pixel column, wherein the display panel further includes: a plurality of first fan-out lines connected to the first data line, the second data line, the third data line, and the fourth data line; and a plurality of second fan-out lines connected to the fifth data line, the sixth data line, the seventh data line and the eighth data line, and The plurality of first fan-out lines and the plurality of second fan-out lines are alternately arranged in a peripheral area of ​​the display panel.

10. The display device according to claim 9, in, The plurality of source channels further include: a fifth source channel configured to provide a fifth data voltage corresponding to the third color to the fifth data line; a sixth source channel configured to provide a sixth data voltage corresponding to the second color to the sixth data line; a seventh source channel configured to provide a seventh data voltage corresponding to the first color to the seventh data line; and an eighth source channel configured to provide an eighth data voltage corresponding to the second color to the eighth data line, wherein source output remapping is performed on at least some of the first source channel, the second source channel, the third source channel, the fourth source channel, the fifth source channel, the sixth source channel, the seventh source channel, and the eighth source channel, wherein the channel controller is configured to select a plurality of remapped source channels on which the source output remapping is performed from among the first source channel, the second source channel, the third source channel, the fourth source channel, the fifth source channel, the sixth source channel, the seventh source channel, and the eighth source channel and generate second offset values ​​for the plurality of remapped source channels, and The data driver is configured to apply the second offset value to a plurality of data voltages provided by the plurality of remapped source channels.

11. A display device, wherein: The display device comprises: A display panel, the display panel comprising: A plurality of sub-pixels, each of the plurality of sub-pixels comprising a pixel circuit and a light-emitting element, the plurality of sub-pixels comprising: a plurality of first sub-pixels configured to display a first color; a plurality of second sub-pixels configured to display a second color; and a plurality of third sub-pixels configured to display a third color; A plurality of data lines, the plurality of data lines comprising: a plurality of first data lines connected to the plurality of first sub-pixels; a plurality of second data lines connected to the plurality of second sub-pixels; and a plurality of third data lines connected to the plurality of third sub-pixels; A plurality of fan-out lines, the plurality of fan-out lines comprising: a plurality of first fan-out lines connected to data lines among the plurality of data lines connected to sub-pixels among the plurality of sub-pixels disposed in a first display area of ​​the display panel; a plurality of second fan-out lines connected to data lines among the plurality of data lines connected to sub-pixels among the plurality of sub-pixels disposed in a second display area of ​​the display panel, the second display area being adjacent to the first display area, the plurality of first fan-out lines and the plurality of second fan-out lines being alternately disposed in a peripheral area of ​​the display panel; and a plurality of third fan-out lines connected to data lines among the plurality of data lines connected to sub-pixels among the plurality of sub-pixels disposed in a third display area of ​​the display panel, the third display area being adjacent to the second display area; A data driver configured to output a plurality of remapped data voltages to a plurality of remapped source channels on which source output remapping is performed and to adjust a plurality of voltage levels of the plurality of remapped data voltages by applying offset values ​​to the plurality of remapped data voltages, the data driver comprising: A plurality of source channels, the plurality of source channels comprising: a plurality of first source channels configured to provide a plurality of first data voltages corresponding to the first colors to the plurality of first data lines; a plurality of second source channels configured to provide a plurality of second data voltages corresponding to the second color to the plurality of second data lines; and a plurality of third source channels configured to provide a plurality of third data voltages corresponding to the third color to the plurality of third data lines; and A channel controller is configured to select the plurality of remapped source channels as some of the plurality of source channels and generate the offset values ​​for the plurality of remapped source channels.

12. The display device according to claim 11, wherein The offset value can be changed.

13. The display device according to claim 12, wherein The channel controller is configured to change the offset values ​​applied to the plurality of remapped data voltages according to a plurality of positions of the plurality of remapped source channels.

14. The display device according to claim 11, wherein The channel controller is configured to select at least one selected source channel other than the plurality of remapped source channels among the plurality of source channels and generate a second offset value for the at least one selected source channel, and The data driver is configured to adjust a voltage level of the selected data voltage by applying the second offset value to the selected data voltage provided by the at least one selected source channel.

15. The display device according to claim 14, wherein The display device further includes: a temperature sensor configured to detect an operating temperature, and The channel controller is configured to select the at least one selected source channel based on the operating temperature detected by the temperature sensor.

16. The display device according to claim 14, wherein The channel controller is configured to select the at least one selected source channel based on brightness of an image displayed in the display panel.

17. The display device according to claim 14, wherein: The channel controller is configured to select the at least one selected source channel based on a plurality of positions of the plurality of source channels.

18. The display device according to claim 17, wherein Among the plurality of source channels, a source channel connected to a sub-pixel disposed at the center of the display panel among the plurality of sub-pixels is selected as the at least one selected source channel.

19. The display device according to claim 11, in, The display panel further includes a plurality of pixel columns, The plurality of pixel columns include: a first pixel column, in which first subpixels among the plurality of first subpixels and third subpixels among the plurality of third subpixels are alternately arranged; a second pixel column, in which a second sub-pixel among the plurality of second sub-pixels is arranged; a third pixel column in which third subpixels among the plurality of third subpixels and first subpixels among the plurality of first subpixels are alternately arranged; and a fourth pixel column, in which a second sub-pixel among the plurality of second sub-pixels is arranged; wherein one of the plurality of third data lines is connected to the third sub-pixel in the first pixel column and the third sub-pixel in the third pixel column; wherein one of the plurality of second data lines is connected to the second sub-pixel in the second pixel column, wherein one of the plurality of first data lines is connected to the first sub-pixel in the third pixel column, Another one of the plurality of second data lines is connected to the second sub-pixel in the fourth pixel column. Wherein, the plurality of data lines further include: an additional data line connected to the first sub-pixel in the first pixel column, and Wherein, the plurality of fan-out lines further include: A fourth fan-out line is connected to the additional data line.

20. The display device according to claim 19, in, The plurality of source channels further include: an additional source channel configured to provide an additional data voltage corresponding to the first color to the additional data line, wherein the channel controller is configured to select the additional source channel and generate a second offset value for the additional source channel, and The data driver is configured to apply the second offset value to the additional data voltage provided by the additional source channel.

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