Display device and driving method thereof

Abstract

A display device and a driving method of the display device are provided. The display device includes: a sub-pixel including a driving transistor and at least two light emitting devices; a display panel including a first display area and a second display area, each display area displaying an image based on sub-pixels; and a display panel driving circuit configured to drive the display panel, in which the display panel driving circuit drives the display panel to operate such that only one of the at least two light emitting devices emits light in a first driving mode, and the at least two light emitting devices emit light in a second driving mode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0028330, filed on February 27, 2024, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0003] The present disclosure relates to a display device and a driving method thereof. Background Art

[0004] With the advancement of information technology, the market for display devices, which serve as a medium connecting users to information, is growing. As a result, the use of display devices such as light-emitting display devices, quantum dot display (QDD) devices, and liquid crystal display (LCD) devices is increasing.

[0005] The display device described above includes a display panel including a plurality of sub-pixels, a driver outputting a driving signal for driving the display panel, and a power supply generating power to be supplied to the display panel or the driver.

[0006] In such a display device, when a driving signal (eg, a scan signal and a data signal) is supplied to each subpixel provided in a display panel, the selected subpixel may transmit light or may emit light by itself, and thus an image may be displayed. Summary of the Invention

[0007] In order to overcome the above-mentioned problems of the related art, the present disclosure can provide a display device and a driving method thereof, which can divert the driving current when at least two light-emitting devices emit light, and thus can achieve high brightness, and can reduce the stress applied to the device to reduce degradation and reduce the recognition of afterimages, thereby achieving long life.

[0008] To achieve these objectives and other advantages, and in accordance with the purposes of the present disclosure, as embodied and broadly described herein, a display device includes: a sub-pixel, which includes a driving transistor and at least two light-emitting devices; a display panel, which includes a first display area and a second display area, each display area displaying an image based on the sub-pixel; and a display panel driving circuit, which is configured to drive the display panel, wherein the display panel driving circuit drives the display panel to operate so that only one of the at least two light-emitting devices emits light in a first driving mode, and at least two light-emitting devices emit light in a second driving mode.

[0009] In the second driving mode, the driving current generated from the driving transistor may be distributed to the at least two light emitting devices.

[0010] The second driving mode may be started based on a shared signal applied through a shared signal line and a private signal applied through a private signal line, the shared signal line and the private signal line being connected to sub-pixels, respectively.

[0011] The display panel driving circuit may include a level shifter that outputs the shared signal and the private signal.

[0012] The sub-pixel may include a plurality of mode selection transistors for selectively driving one or two of the at least two light emitting devices.

[0013] The plurality of mode selection transistors may include: a first direction sharing mode selection transistor, which is turned on based on a first direction sharing signal applied through a first direction sharing signal line to apply a driving current generated from a driving transistor to an anode electrode of a first light-emitting device among at least two light-emitting devices; a second direction sharing mode selection transistor, which is turned on based on a second direction sharing signal applied through a second direction sharing signal line to apply a driving current generated from the driving transistor to an anode electrode of the first light-emitting device; a second direction private mode selection transistor, which is turned on based on a second direction private signal applied through a second direction private signal line to output a driving current generated from the driving transistor; and a first direction private mode selection transistor, which is turned on based on a first direction private signal applied through a first direction private signal line to apply a driving current output from the second direction private mode selection transistor to an anode electrode of a second light-emitting device among at least two light-emitting devices.

[0014] The second driving mode may start when the first direction share signal, the second direction share signal, the second direction private signal, and the first direction private signal are applied under the same voltage condition.

[0015] The driving transistor may include a gate electrode connected to a first node; a first electrode connected to a second node connected to a high-level voltage line; and a second electrode connected to a third node. The subpixel may also include: a first switching transistor including a gate electrode connected to a first scan line and a first electrode connected to a data line; a capacitor including a first electrode connected to the second electrode of the first switching transistor and a second electrode connected to the first node; a second switching transistor including a gate electrode connected to a second scan line, a first electrode connected to the first node, and a second electrode connected to the third node; a third switching transistor including a gate electrode connected to an emission control line, a first electrode connected to a reference voltage line, and a second electrode connected to the first electrode of the capacitor; a fourth switching transistor including a gate electrode connected to the emission control line, a first electrode connected to the third node; a fifth switching transistor including a gate electrode connected to a second scan line, a first electrode connected to a reference voltage line, and a second electrode connected to an anode electrode of a first light-emitting device among at least two light-emitting devices; a sixth switching transistor including a gate electrode connected to the first a gate electrode of the second scanning line, a first electrode connected to the reference voltage line, and a second electrode connected to the anode electrode of the second light-emitting device among the at least two light-emitting devices; a seventh switching transistor, which includes a gate electrode connected to the first direction shared signal line, a first electrode connected to the second electrode of the fourth switching transistor, and a second electrode connected to the anode electrode of the first light-emitting device; an eighth switching transistor, which includes a gate electrode connected to the second direction shared signal line, a first electrode connected to the second electrode of the fourth switching transistor, and a second electrode connected to the anode electrode of the first light-emitting device; a ninth switching transistor, which includes a gate electrode connected to the second direction private signal line and a first electrode connected to the second electrode of the fourth switching transistor; and a tenth switching transistor, which includes a gate electrode connected to the first direction private signal line, a first electrode connected to the second electrode of the ninth switching transistor, and a second electrode connected to the anode electrode of the second light-emitting device.

[0016] The display panel driving circuit may include a controller that generates a signal for driving the display panel in at least one of a first driving mode and a second driving mode based on a signal applied from the outside, and the controller may include: a pixel position calculator configured to calculate a position value of a boosted pixel so as to set an area for applying the second driving mode; a boost mode data generator configured to generate a boost data signal corresponding to an area to be operated in a boost mode based on the position value of the boosted pixel; and a pixel position selection signal generator configured to generate a pixel position selection signal for selecting a position of the boosted pixel based on the position value of the boosted pixel.

[0017] The display panel driving circuit may include a level shifter that outputs a shared signal and a private signal to be applied through a shared signal line and a private signal line respectively connected to the sub-pixels based on the pixel position selection signal.

[0018] The first light emitting device is defined as a shared light emitting device, which enables both the user of the first viewpoint and the user of the second viewpoint to see the light emitted therefrom, and the second light emitting device is defined as a private light emitting device, which enables only the user of the first viewpoint to see the light emitted therefrom.

[0019] The boosted data signal is generated to have increased brightness compared to the normal data signal generated in the first driving mode.

[0020] In another aspect of the present disclosure, a driving method for a display device includes: a first driving mode step of operating a display panel based on a first driving mode so that only one of two light-emitting devices included in a sub-pixel of the display device emits light; and a second driving mode step of operating the display panel based on a second driving mode different from the first driving mode so that the two light-emitting devices included in the sub-pixel emit light, wherein the second driving mode step starts based on a shared signal applied through a shared signal line and a private signal applied through a private signal line, and the shared signal line and the private signal line are respectively connected to the sub-pixels.

[0021] When the shared signal and the private signal are applied under the same voltage condition, the second driving mode step may begin. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0023] Figure 1 is a block diagram schematically illustrating a display device according to a first embodiment of the present disclosure;

[0024] Figure 2 is a cross-sectional view illustrating a stacking type of a display panel according to a first embodiment of the present disclosure;

[0025] Figure 3 is a first diagram illustrating a portion of a device included in a sub-pixel according to a first embodiment of the present disclosure, Figure 4 is a second diagram illustrating a portion of a device included in a sub-pixel according to the first embodiment of the present disclosure, and Figure 5 and Figure 6 is a graph showing operational characteristics of a sub-pixel according to the first embodiment of the present disclosure;

[0026] Figure 7 The first embodiment of the present disclosure is shown in FIG. Figure 5 or Figure 6 Cross-sectional view of the sub-pixel stacking type seen in;

[0027] Figure 8 is a diagram showing a portion of a device included in a sub-pixel according to a second embodiment of the present disclosure, and Figure 9 is a graph showing operational characteristics of a sub-pixel according to a second embodiment of the present disclosure;

[0028] Figure 10 This is a diagram showing the use of the second embodiment according to the present disclosure. Figure 8 FIG is a diagram of an application example of a display device implemented with a sub-pixel, and Figure 11 It shows the settings Figure 10 a diagram illustrating the operational characteristics of a display panel in the vehicle shown;

[0029] Figure 12 is a diagram showing a circuit configuration of a device included in a sub-pixel according to a third embodiment of the present disclosure, and Figure 13 Is to show the use of Figure 12 A diagram of a display panel implemented with sub-pixels and a gate driver for driving the display panel;

[0030] Figure 14 is a diagram for describing the arrangement of shared signal lines and private signal lines and a region selection method based on signals applied through the lines according to a third embodiment of the present disclosure, and Figure 15 and Figure 16 is a diagram for describing an area-based driving mode of a display panel; and

[0031] Figure 17 is a first diagram showing a portion of an internal configuration of a controller for generating a signal based on a pattern according to a third embodiment of the present disclosure, Figure 18 is a second diagram showing a portion of an internal configuration of a controller for generating a signal based on a pattern according to a third embodiment of the present disclosure, and Figure 19 is a waveform diagram for describing the overall operation of the display device according to the third embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are shown. However, the present disclosure can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the present disclosure to those skilled in the art.

[0033] The display device according to the present disclosure may be implemented as a light-emitting display device or a quantum dot display (QDD) device. Hereinafter, for example, for ease of description, a light-emitting display device based on self-luminescence of an inorganic light-emitting diode or an organic light-emitting diode will be described.

[0034] In addition, the thin film transistor (TFT) described below can be implemented using an n-type TFT, a p-type TFT, or a combination of an n-type TFT and a p-type TFT. A TFT can be a three-electrode element including a gate, a source, and a drain. The source electrode can be an electrode that provides carriers to the transistor. In a TFT, carriers can flow from the source electrode. The drain electrode can be an electrode through which carriers flow from the TFT to the outside. That is, in a TFT, carriers flow from the source electrode to the drain electrode.

[0035] In a p-type TFT, since the carriers are holes, the source voltage can be higher than the drain voltage, causing holes to flow from the source to the drain. In a p-type TFT, since holes flow from the source to the drain, current can flow from the source to the drain. On the other hand, in an n-type TFT, since the carriers are electrons, the source voltage can be lower than the drain voltage, causing electrons to flow from the source to the drain. In an n-type TFT, since electrons flow from the source to the drain, current can flow from the drain to the source. However, the source and drain of a TFT can switch between them based on the voltage applied to them. Based on this, in the following description, one of the source and drain is described as a first electrode, and the other of the source and drain is described as a second electrode.

[0036] Figure 1 is a block diagram schematically showing a display device 10 according to a first embodiment of the present disclosure.

[0037] like Figure 1As shown, the display device 10 may include: a display panel 100 including a plurality of sub-pixels SP; a controller 200; a gate driver 300 that supplies gate signals to the plurality of sub-pixels SP; a data driver 400 that supplies data signals (or data voltages) to the plurality of sub-pixels SP; and a power supply 500 that supplies power to the plurality of sub-pixels SP. The controller 200, the gate driver 300, the data driver 400, and the power supply 500 may be defined as a display panel driving circuit for driving the display panel 100. At least one of the devices included in the display panel driving circuit may be integrated into an integrated circuit (IC).

[0038] The display panel 100 may include a display area provided with a plurality of sub-pixels SP (see Figure 2 AA) and a non-display area (see FIG. 1 ) provided to surround the display area AA and provided with a gate driver 300 and a data driver 400 Figure 2 NA). In the display panel 100, a plurality of gate lines GL and a plurality of data lines DL may intersect each other, and each of a plurality of sub-pixels SP may be connected to the gate line GL and the data line DL. In detail, one sub-pixel SP may be supplied with a gate signal from the gate driver 300 through the gate line GL, may be supplied with a data signal from the data driver 400 through the data line DL, and may be supplied with a high-level voltage EVDD and a low-level voltage EVSS from the power supply 500.

[0039] The gate lines GL may transmit scan signals SC and emission control signals EM to the plurality of sub-pixels SP, and the data lines DL may transmit data voltages Vdata to the plurality of sub-pixels SP. According to various embodiments, the gate lines GL may include a plurality of scan lines SCL for supplying the scan signals SC and a plurality of emission control lines EML for supplying the emission control signals EM. The plurality of sub-pixels SP may be supplied with a reference voltage Vref via a reference line VRE.

[0040] Each of the plurality of sub-pixels SP may include a sub-pixel driving circuit. The sub-pixel driving circuit may include a plurality of switching elements, a driving element, and a capacitor. The switching elements and the driving element may each be configured as a TFT. The switching transistor may be turned on based on a scan signal SC supplied via a scan line SCL and an emission control signal EM supplied via an emission control line EML. The driving transistor may control the amount of current supplied to the light-emitting device OLED based on a data voltage Vdata to adjust the amount of light emitted.

[0041] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel can be applied to a transparent display device that displays an image on its screen and allows real objects in the background to be seen. The display panel 100 can be implemented as a flexible display panel. The flexible display panel can use a plastic substrate. Each of the multiple sub-pixels SP can be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color realization. Each of the multiple sub-pixels SP can also include a white sub-pixel.

[0042] A touch sensor may be provided in the display panel 100. Touch input may be sensed using a separate touch sensor or may be sensed by a plurality of sub-pixels SP. The touch sensor may be arranged in the screen of the display panel 100 as an on-cell type or an attached type, or may be implemented as an in-cell type touch sensor embedded in the display panel 100.

[0043] The controller 200 may process the image data signal DATA input from the outside based on the size and resolution of the display panel 100 to supply it to the data driver 400. The controller 200 may generate a gate control signal GDC and a data control signal DDC by using synchronization signals (e.g., a dot clock signal CLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync) input from the outside. The controller 200 may supply the gate control signal GCS to the gate driver 300 to control the operation timing of the gate driver 300. The controller 200 may supply the data control signal DCS to the data driver 400 to control the operation timing of the data driver 400. The controller 200 may synchronize the operation timing of the gate driver 300 with the operation timing of the data driver 400 by using the gate control signal GCS and the data control signal DCS.

[0044] The controller 200 can be configured to be coupled to various processors (e.g., microprocessors, mobile processors, and application processors) based on the devices installed thereon. The host system provided at the front end relative to the controller 200 can be one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, and an automotive system.

[0045] The controller 200 may multiply the input frame frequency by i (where i may be a natural number) to control the operation timing of the display panel driver based on the frame frequency of the input frame frequency Xi Hz. The input frame frequency may be approximately 60 Hz in the National Television Standards Committee (NTSC) scheme and approximately 50 Hz in the Phase Alternation Line (PAL) scheme.

[0046] The controller 200 can drive the display panel 100 at various refresh rates. The controller 200 can drive the display panel 100 in a variable refresh rate (VRR) mode, that is, between a first refresh rate and a second refresh rate, in a switchable manner. For example, the controller 200 can simply change the speed of the clock signal, or can generate a synchronization signal to cause horizontal blanking or vertical blanking, or can drive the gate driver 300 in a mask mode to drive the display panel 100 at various refresh rates.

[0047] The voltage level of the gate control signal GCS output from the controller 200 can be shifted to a gate-on voltage VGL (VEL) and a gate-off voltage VGH (VEH) by a level shifter (not shown), and can be supplied to the gate driver 300. The level shifter can shift the low-level voltage of the gate control signal GCS to the gate low voltage VGL, and can shift the high-level voltage of the gate control signal GCS to the gate high voltage VGH. The gate control signal GCS may include a start signal and a clock signal.

[0048] The gate driver 300 may supply a gate signal to the gate line GL based on a gate control signal GCS supplied from the controller 200. The gate driver 300 may be disposed on one side or both sides of the display panel 100 in a gate-in-panel (GIP) type.

[0049] The gate driver 300 may sequentially output gate signals to the plurality of gate lines GL based on the control of the controller 200. The gate driver 300 may shift the gate signals by using a shift register and thus may sequentially supply the signals to the gate lines GL.

[0050] In an organic light-emitting display device, gate signals may include a scan signal SC and an emission control signal EM. The scan signal SC may include a scan pulse that swings between a gate-on voltage VGL and a gate-off voltage VGH. The emission control signal EM may include an emission control signal pulse that swings between a gate-on voltage VEL and a gate-off voltage VEH. The scan pulse may select a subpixel SP of a line into which a data voltage Vdata is to be written. The emission control signal EM may define the emission time of each subpixel SP.

[0051] The gate driver 300 may include an emission control signal driver 310 and one or more scan drivers 320. The emission control signal driver 310 may output an emission control signal pulse in response to a start signal and a clock signal from the controller 200, and may sequentially shift the emission control signal pulse according to the clock signal. The one or more scan drivers 320 may output a scan pulse in response to a start signal (or start pulse) and a clock signal (or shift clock) from the controller 200, and may shift the scan pulse based on the clock signal timing.

[0052] The data driver 400 may convert the image data signal DATA into a data voltage Vdata based on the data control signal DCS supplied from the controller 200 and may output the data voltage Vdata through the data line DL.

[0053] exist Figure 1 , the data driver 400 is shown as one type disposed on one side of the display panel 100, but the number and arrangement position of the data driver 400 are not limited thereto. That is, the data driver 400 may be configured with a plurality of integrated circuits (ICs) and may be provided in plural, and the plurality of data drivers 400 may be divided and disposed on one side of the display panel 100.

[0054] The power supply 500 can generate the direct current (DC) power required to drive the display panel driver and the pixel array of the display panel 100 by using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, and a boost converter. The power supply 500 can receive a DC input voltage applied from a host system (not shown) to generate a gate-on voltage VGL (VEL). The power supply 500 can generate DC voltages such as a gate-off voltage VGH (VEH), a high-level voltage EVDD, and a low-level voltage EVSS. The gate-on voltage VGL (VEL) and the gate-off voltage VGH (VEH) can be supplied to a level shifter (not shown) and the gate driver 300. The high-level voltage EVDD and the low-level voltage EVSS can be supplied to a plurality of sub-pixels SP in common.

[0055] Figure 2 is a cross-sectional view illustrating a stacking type of a display panel according to a first embodiment of the present disclosure.

[0056] like Figure 2As shown, a driving transistor DT for driving the light-emitting device OLED provided in the display area AA may be provided on the substrate 101 of the display panel 100. The driving transistor DT may include a semiconductor layer 115, a gate electrode 125, and source and drain electrodes 140. For ease of description, only the driving transistor DT is shown among the various TFTs included in the sub-pixel driving circuit, but other TFTs such as switching transistors may also be included in the sub-pixel driving circuit. In addition, in the present disclosure, the driving transistor DT may be described as having a coplanar structure, but the TFT may be implemented in another structure, such as a staggered structure. Therefore, the embodiment is not limited thereto.

[0057] At least a portion of the driving transistors (DT) and switching transistors included in the sub-pixel driving circuit may use an oxide semiconductor as an active layer. Compared to TFTs using polycrystalline semiconductor materials as active layers, TFTs using oxide semiconductor materials as active layers can have a good leakage current cutoff effect and can be relatively cheaper. Therefore, to reduce power consumption and manufacturing costs, the sub-pixel driving circuit may include at least one switching transistor and a driving transistor (DT) using oxide semiconductor materials.

[0058] All TFTs configuring the sub-pixel driving circuit may be implemented using oxide semiconductor materials, or only some switching transistors may be implemented using oxide semiconductor materials. However, TFTs using oxide semiconductor materials may have difficulty ensuring reliability, while TFTs using polycrystalline semiconductor materials may have high speed and good reliability. Therefore, embodiments of the present disclosure may include both switching TFTs using oxide semiconductor materials and switching transistors using polycrystalline semiconductor materials.

[0059] In response to the data signal supplied to the gate electrode 125 of the driving transistor DT, the driving transistor DT can receive a high-level voltage EVDD to control the current supplied to the light-emitting device OLED, and can thus adjust the amount of light emitted from the light-emitting device OLED, and further, can provide a constant current based on the voltage charged in the storage capacitor (not shown) until the data signal of the next frame is supplied, thereby allowing the light-emitting device OLED to maintain light emission. The high-level supply line can be formed in parallel with the data line.

[0060] The driving transistor DT may include a semiconductor layer 115 disposed on the first insulating layer 110 , a gate electrode 125 overlapping the semiconductor layer 115 with the second insulating layer 120 therebetween, and source and drain electrodes 140 formed on the third insulating layer 135 and in contact with the semiconductor layer 115 .

[0061] The semiconductor layer 115 may be a region in which the channel of the drive transistor DT is formed. The semiconductor layer 115 may include an oxide semiconductor, or may include various organic semiconductors such as amorphous silicon (a-Si), polycrystalline silicon (poly-Si) or pentacene, but the embodiment is not limited thereto. The semiconductor layer 115 may be formed on the first insulating layer 110. The semiconductor layer 115 may include a channel region, a source region, and a drain region. The channel region may overlap with the gate electrode 125 to form a channel region between the source electrode 140 and the drain electrode 140, wherein the second insulating layer 120 is located between the channel region and the gate electrode 125. The source region may be electrically connected to the source electrode 140 through a contact hole passing through the second insulating layer 120 and the third insulating layer 135. The drain region may be electrically connected to the drain electrode 140 through a contact hole passing through the second insulating layer 120 and the third insulating layer 135. The buffer layer 105 and the first insulating layer 110 may be disposed between the semiconductor layer 115 and the substrate 101. The buffer layer 105 may delay diffusion of water and / or oxygen penetrating into the substrate 101. The first insulating layer 110 may protect the semiconductor layer 115 and may prevent various defects from occurring in the substrate 101.

[0062] The uppermost layer of the buffer layer 105 that contacts the first insulating layer 110 may include a material having etching characteristics that is different from the material of each of the other layers of the buffer layer 105, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 135. The uppermost layer of the buffer layer 105 that contacts the first insulating layer 110 may include one of silicon nitride (SiNx) and silicon oxide (SiOx). The other layers of the buffer layer 105, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 135 may include the other of SiNx and SiOx. For example, the uppermost layer of the buffer layer 105 that contacts the first insulating layer 110 may include SiNx, and the other layers of the buffer layer 105, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 135 may include SiOx, but embodiments are not limited thereto.

[0063] The gate electrode 125 may be formed on the second insulating layer 120 and may overlap the channel region of the semiconductor layer 115, wherein the second insulating layer 120 is located between the semiconductor layer 115 and the gate electrode 125. The gate electrode 125 may include a single layer or multiple layers of a first conductive material including one of magnesium (Mg), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but the embodiment is not limited thereto.

[0064] The source electrode 140 may be connected to the source region of the semiconductor layer 115 exposed through a contact hole passing through the second insulating layer 120 and the third insulating layer 135. The drain electrode 140 may face the source electrode 140 and may be connected to the drain region of the semiconductor layer 115 exposed through a contact hole passing through the second insulating layer 120 and the third insulating layer 135.

[0065] The source region and the drain region may be regions made conductive by doping a certain concentration of Group 5 or Group 3 impurity ions (e.g., phosphorus (P) or boron (B)) on an intrinsic polycrystalline semiconductor material. The channel region may allow the polycrystalline semiconductor material or the oxide semiconductor material to maintain an intrinsic state and may provide a path for electrons or holes to move through.

[0066] The source and drain electrodes 140 may include a single layer or multiple layers of a second conductive material including one of Mg, Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu or an alloy thereof, but the embodiment is not limited thereto.

[0067] The connection electrode 155 may be disposed between the first intermediate layer 150 and the second intermediate layer 160. The connection electrode 155 may be exposed through a connection electrode contact hole 156 that passes through the protective layer 145 and the first intermediate layer 150. The connection electrode 155 may include a material having a low resistivity that is the same as or similar to that of the drain electrode 140, but the embodiment is not limited thereto.

[0068] A light emitting device OLED including a light emitting layer 172 may be disposed on the second intermediate layer 160 and the bank layer 165. The light emitting device OLED may include an anode electrode 171, at least one light emitting layer 172 formed on the anode electrode 171, and a cathode electrode 173 formed on the light emitting layer 172.

[0069] The anode electrode 171 may be disposed on the first intermediate layer 150 through a contact hole passing through the second intermediate layer 160 , and may be electrically connected to the connection electrode 155 exposed at a portion on the second intermediate layer 160 .

[0070] The anode electrode 171 may be formed to be exposed through the bank layer 165. The bank layer 165 may include an opaque material (e.g., black) to prevent optical interference between adjacent sub-pixels. In this case, the bank layer 165 may include a light-blocking material including at least one of a color pigment, organic black, and carbon, but the embodiment is not limited thereto.

[0071] At least one light-emitting layer 172 may be formed on the anode electrode 171 of the emission region provided by the bank layer 165. The at least one light-emitting layer 172 may include a hole transport layer, a hole injection layer, a hole blocking layer, a light-emitting layer, an electron injection layer, an electron blocking layer, and an electron transport layer on the anode electrode 171, and may be stacked and formed sequentially or in reverse order in the emission direction. In addition, the light-emitting layer 172 may include a first emission stack and a second emission stack facing each other, with a charge generation layer located therebetween. In this case, one of the light-emitting layers in the first emission stack and the second emission stack may generate blue light, and the other light-emitting layer in the first emission stack and the second emission stack may generate yellow-green light, thereby generating white light by the first emission stack and the second emission stack. The white light generated by the emission stack may be incident on a color filter provided on or under the light-emitting layer 172, and thus a color image may be realized. As another example, each light-emitting layer 172 may generate colored light corresponding to each pixel to realize a color image without the need for a separate color filter. For example, the red sub-pixel's light emitting layer 172 may generate red light, the green sub-pixel's light emitting layer 172 may generate green light, and the blue sub-pixel's light emitting layer 172 may generate blue light.

[0072] Encapsulation layer 180 can prevent or at least reduce the penetration of external water or oxygen into the light-emitting device OLED. To this end, encapsulation layer 180 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer, but embodiments are not limited thereto. In the present disclosure, for example, a structure of encapsulation layer 180 in which first encapsulation layer 181, second encapsulation layer 182, and third encapsulation layer 183 are sequentially stacked may be described.

[0073] The first encapsulation layer 181 may be formed on the substrate 101 on which the cathode electrode 173 is formed. The third encapsulation layer 183 may be formed on the substrate 101 on which the second encapsulation layer 182 is formed, and may be formed to surround the upper surface, lower surface and side surface of the second encapsulation layer 182 together with the first encapsulation layer 181. The first encapsulation layer 181 and the third encapsulation layer 183 may minimize or prevent external water or oxygen from penetrating into the light-emitting device OLED. The first encapsulation layer 181 and the third encapsulation layer 183 may include an inorganic insulating material capable of low-temperature deposition, such as SiNx, SiOx, silicon oxynitride (SiON) or aluminum oxide (Al2O3). The first encapsulation layer 181 and the third encapsulation layer 183 may be deposited in a low-temperature atmosphere, and therefore, when the deposition process of the first encapsulation layer 181 and the third encapsulation layer 183 is performed, damage to the light-emitting device OLED that is susceptible to a high-temperature atmosphere may be prevented or at least reduced.

[0074] The second encapsulation layer 182 can perform a buffering function of reducing the stress between layers caused by the bending of the display device, and can flatten the step height between the layers. The second encapsulation layer 182 can be formed on the substrate 101 on which the first encapsulation layer 181 is formed, and can include acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin and polyethylene, or a non-photosensitive organic insulating material such as silicon oxycarbon (SiOC), or a photosensitive organic insulating material such as photoacrylic, but the embodiment is not limited thereto. In the case where the second encapsulation layer 182 is formed by inkjet processing, a dam DAM can be provided to prevent the second encapsulation layer 182 from diffusing to the edge of the substrate 101. The dam DAM can be provided closer to the edge of the substrate 101 than the second encapsulation layer 182. The dam DAM can prevent the second encapsulation layer 182 from diffusing to the pad area, in which a conductive pad provided at the outermost part of the substrate 101 is provided.

[0075] The dam DAM can be designed to prevent or at least reduce the diffusion of the second encapsulation layer 182. However, if the second encapsulation layer 182 is formed to a height that flows over the dam DAM during processing, the second encapsulation layer 182, which is an organic layer, may be exposed to the outside. As a result, water may penetrate into the light-emitting device OLED. Therefore, to solve this problem, 11 or more dams DAM can be provided to overlap each other.

[0076] The dam DAM may be provided on the protective layer 145 in the non-display area NA. Furthermore, the dam DAM may be formed simultaneously with the first and second intermediate layers 150 and 160. The lower layer of the dam DAM may be formed when the first intermediate layer 150 is formed, and the upper layer of the dam DAM may be formed when the second intermediate layer 160 is formed. Thus, the dam DAM may be stacked and formed into a double-layer structure. Therefore, the dam DAM may include the same insulating material as that of the first and second intermediate layers 150 and 160, but embodiments are not limited thereto.

[0077] The dam DAM may be formed to overlap the low-level driving power line EVSS. For example, the low-level driving power line EVSS may be formed in a lower layer of the non-display area NA where the dam DAM is provided.

[0078] The low-level driving power line EVSS and the gate driver 300 configured as a gate-in-panel (GIP) type may be formed to surround an outer portion of the display panel 100, and the low-level driving power line EVSS may be disposed further outward than the gate driver 300. The gate driver 300 is shown only in the drawings such as plan views and cross-sectional views, but is not limited thereto, and may be configured in the same structure as that of the driving transistor DT of the display area AA.

[0079] The low-level driving power line EVSS may be disposed outside the gate driver 300. The low-level driving power line EVSS may be disposed further outward than the gate driver 300 and may be disposed to surround the display area AA. The low-level driving power line EVSS may include the same material as the source electrode and the drain electrode 140 of the TFT, but embodiments are not limited thereto. For example, the low-level driving power line EVSS may include the same material as the gate electrode 125. Furthermore, the low-level driving power line EVSS may be electrically connected to the anode electrode 171. The low-level driving power line EVSS may supply a low-level voltage EVSS to the plurality of pixels in the display area AA.

[0080] The touch layer 190 may be disposed on the encapsulation layer 180. In the touch layer 190, a touch buffer layer 191 may be disposed between the cathode electrode 173 of the light emitting device OLED and a touch sensor metal including touch electrodes 195 and 196 and touch electrode connection lines 192 and 194.

[0081] The touch buffer layer 191 can prevent external water or chemical solutions (e.g., developer or etchant) used in the manufacturing process of the touch sensor metal provided on the touch buffer layer 191 from penetrating into the light emitting layer 172 including the organic material. Therefore, the touch buffer layer 191 can prevent damage to the light emitting layer 172, which is susceptible to chemical solutions or water.

[0082] Touch buffer layer 191 may include an organic insulating material having a low dielectric constant of 1 to 3 and capable of being formed at a certain temperature (e.g., 100°C) or lower to prevent damage to light-emitting layer 172, which includes organic materials susceptible to high temperatures. For example, touch buffer layer 191 may include an acrylic material, an epoxy material, or a siloxane material. Touch buffer layer 191, comprising an organic insulating material and having planarization properties, can prevent damage to encapsulation layer 180 caused by bending of the organic light-emitting display device and breakage of the touch sensor metal formed on touch buffer layer 191.

[0083] According to a mutual capacitance-based touch sensor structure, the touch electrodes 195 and 196 may be disposed on the touch buffer layer 191 , and the touch electrodes 195 and 196 may be disposed to intersect each other.

[0084] Touch electrode connection lines 192 and 194 can electrically connect touch electrodes 195 and 196 to each other. Touch electrode connection lines 192 and 194 and touch electrodes 195 and 196 can be provided in different layers with a touch insulating layer 193 therebetween. Touch electrode connection lines 192 and 194 can be provided to overlap with bank layer 165, thereby preventing a reduction in aperture ratio.

[0085] In addition, in the touch electrodes 195 and 196, a portion of the touch electrode connection line 192 can pass through the upper and side surfaces of the encapsulation layer 180 and the upper and side surfaces of the dam DAM, and can be electrically connected to the touch driving circuit (not shown) through the touch pad 198.

[0086] A portion of the touch electrode connection line 192 may be supplied with a touch driving signal from a touch driving circuit and may transmit the touch driving signal to the touch electrodes 195 and 196 , or may transmit touch sensing signals of the touch electrodes 195 and 196 to the touch driving circuit.

[0087] A touch protection layer 197 may be provided on the touch electrodes 195 and 196. In the drawings, the touch protection layer 197 is shown as being provided only on the touch electrodes 195 and 196, but embodiments are not limited thereto, and the touch protection layer 197 may extend to a previous portion or a next portion relative to the dam DAM and may be provided on the touch electrode connection line 192.

[0088] In addition, a color filter (not shown) may be further disposed on the encapsulation layer 180 , and the color filter may be disposed on the touch layer 190 or may be disposed between the encapsulation layer 180 and the touch layer 190 .

[0089] Figure 3 is a first diagram illustrating a portion of a device included in a sub-pixel according to a first embodiment of the present disclosure, Figure 4 is a second diagram illustrating a portion of a device included in a sub-pixel according to the first embodiment of the present disclosure, and Figure 5 and Figure 6 is a graph showing operational characteristics of sub-pixels according to the first embodiment of the present disclosure.

[0090] like Figure 3 As shown, the subpixel SP according to the first embodiment may include a driving transistor DT and at least two light-emitting devices OLED1 and OLED2. The driving transistor DT may be implemented as a p-type. The p-type driving transistor DT may operate in response to a low voltage. The at least two light-emitting devices OLED1 and OLED2 may emit light using a driving current generated based on the operation of the driving transistor DT.

[0091] like Figure 4As shown, the subpixel SP may include a first transistor T1, a driving transistor DT, and at least two light-emitting devices OLED1 and OLED2. The first transistor T1 may be implemented as an n-type transistor, and the driving transistor DT may be implemented as a p-type transistor. The n-type first transistor T1 may operate in response to a high voltage, and the p-type driving transistor DT may operate in response to a low voltage. The at least two light-emitting devices OLED1 and OLED2 may emit light using a driving current generated by the operation of the first transistor T1 and the driving transistor DT.

[0092] like Figure 3 and Figure 4 As shown, the sub-pixel SP may be implemented based on one type of transistor, or may be implemented based on two types of transistors. In addition, the sub-pixel SP may further include a circuit for compensating the driving transistor DT and the light-emitting devices OLED1 and OLED2. Therefore, the circuit included in the sub-pixel SP may be implemented differently and should be referred to. Figure 3 and Figure 4 In the following, reference will be made to Figure 3 The operational characteristics of the sub-pixel SP according to the first embodiment are described.

[0093] like Figure 5 and Figure 6 As shown, the sub-pixel SP according to the first embodiment can be operated so that only the first light-emitting device OLED1 of the at least two light-emitting devices OLED1 and OLED2 emits light in the first driving mode. Here, only the first light-emitting device OLED1 emits light, which is merely an example, and only the second light-emitting device OLED2 emits light. In addition, the sub-pixel SP according to the first embodiment can be operated so that at least the two light-emitting devices OLED1 and OLED2 emit light in the second driving mode.

[0094] In addition, the sub-pixel SP according to the first embodiment can prevent the driving current from being concentrated on at least two light emitting devices OLED1 and OLED2 when operating in the second driving mode. This will be described below.

[0095] Figure 7 The first embodiment of the present disclosure is shown in FIG. Figure 5 or Figure 6 A cross-sectional diagram of the sub-pixel stacking type seen in Figure 5.

[0096] like Figure 7 As shown, it is possible to Figure 5 or Figure 6The sub-pixel shown in FIG. 1 may be implemented as a structure including two emission areas EA1 and EA2 in one pixel area PA. Each of the two emission areas EA1 and EA2 may include a light emitting device OLED and a transistor TR for transmitting a driving current to the light emitting device OLED. The two transistors TR are shown to be connected to the Figure 2 The driving transistors DT shown and described in the accompanying drawings are implemented in a similar / same structure and each transistor TR includes an example of a semiconductor layer 115 , a gate electrode 125 , and source and drain electrodes 140 , but embodiments are not limited thereto.

[0097] Each of the two emission areas EA1 and EA2 may include a pixel lens 700 for collecting light emitted from the two light-emitting devices OLED. The two pixel lenses 700 may be arranged to overlap with the two light-emitting devices OLED. The pixel lens 700 may be arranged on the encapsulation layer 180, and the lens protection layer 800 may protect the pixel lens 700 from external impact, but the embodiment is not limited thereto.

[0098] Figure 8 is a diagram showing a portion of a device included in a sub-pixel according to a second embodiment of the present disclosure, and Figure 9 is a graph showing operational characteristics of a sub-pixel according to the second embodiment of the present disclosure.

[0099] like Figure 8 As shown, the subpixel SP according to the second embodiment may include a pixel circuit PC including a driving transistor DT, a plurality of switching transistors (eg, fifth to tenth switching transistors) T5 to T10, and at least two light emitting devices OLED1 and OLED2.

[0100] The pixel circuit PC can operate based on a circuit connected to the first node N1, the second node N2, and the third node N3 of the driving transistor DT to generate a driving current. The switching transistors T5 to T10 can perform an operation of applying a reference voltage to the pixel circuit PC and the nodes of the light-emitting devices OLED1 and OLED2, and an operation of preventing the driving current from being concentrated on at least two light-emitting devices OLED1 and OLED2.

[0101] For example, the fifth switching transistor T5 and the sixth switching transistor T6 may perform an operation of applying a reference voltage applied via a reference line VRE to a node between the pixel circuit PC and the light-emitting devices OLED1 and OLED2. Furthermore, the seventh to tenth switching transistors T7 to T10 may perform an operation of preventing or at least reducing a driving current from being concentrated on at least two light-emitting devices OLED1 and OLED2. The seventh to tenth switching transistors T7 to T10 may each be defined as a mode selection transistor.

[0102] The seventh switching transistor T7 may be turned on based on the first direction sharing signal applied through the first direction sharing signal line S_V and may apply the driving current generated by the driving transistor DT to the anode electrode of the first light emitting device OLED1. The seventh switching transistor T7 may be defined as a first direction sharing mode selection transistor.

[0103] The eighth switching transistor T8 may be turned on based on the second direction sharing signal applied through the second direction sharing signal line S_H and may apply the driving current generated by the driving transistor DT to the anode electrode of the first light emitting device OLED1. The eighth switching transistor T8 may be defined as a second direction sharing mode selection transistor.

[0104] The ninth switching transistor T9 may be turned on based on the second direction private signal applied through the second direction private signal line P_H and may transfer the driving current generated from the driving transistor DT to the tenth switching transistor T10. The ninth switching transistor T9 may be defined as a second direction private mode selection transistor.

[0105] The tenth switching transistor T10 may be turned on based on the first direction privacy signal applied through the first direction privacy signal line P_V and may transmit the driving current generated by the driving transistor DT to the anode electrode of the second light emitting device OLED2. The tenth switching transistor T10 may be defined as a first direction privacy mode selection transistor.

[0106] The sub-pixel SP according to the second embodiment can operate so that only the first light-emitting device OLED1 of the at least two light-emitting devices OLED1 and OLED2 emits light in the first driving mode. In addition, the sub-pixel SP according to the second embodiment can operate so that the at least two light-emitting devices OLED1 and OLED2 emit light in the second driving mode.

[0107] like Figure 9 As shown, the first driving mode can be defined as a normal mode (single emission mode), and the second driving mode can be defined as a boost mode (dual emission mode). The first light-emitting device OLED1 can be defined as a shared light-emitting device that enables both the user at the first viewpoint and the user at the second viewpoint to see the light emitted therefrom, and the second light-emitting device OLED2 can be defined as a private light-emitting device that enables only the user at the first viewpoint to see the light emitted therefrom.

[0108] In the normal mode, which is the first driving mode, the area where the first light-emitting device OLED1 emits light and the area where the second light-emitting device OLED2 emits light can be set. In the boost mode, which is the second driving mode, the area where the first light-emitting device OLED1 and the second light-emitting device OLED2 emit light can be set. The first driving mode and the second driving mode will be described below.

[0109] like Figure 8 and Figure 9 As shown, the first light emitting device OLED1 can emit light during the first driving mode (normal mode). To this end, the seventh switching transistor T7 and the eighth switching transistor T8 can be turned on during the first driving mode (normal mode).

[0110] The first light emitting device OLED1 and the second light emitting device OLED2 may emit light during the second driving mode (boosting mode). To this end, the ninth switching transistor T9 and the tenth switching transistor T10 may be turned on during the second driving mode (boosting mode).

[0111] Figure 10 This is a diagram showing the use of the second embodiment according to the present disclosure. Figure 8 FIG is a diagram of an application example of a display device implemented with a sub-pixel, and Figure 11 It shows the settings Figure 10 A diagram illustrating the operating characteristics of a display panel in a vehicle is shown.

[0112] like Figure 10 As shown, using Figure 8 The display device 10 implemented with the sub-pixels (hereinafter referred to as the automobile display device) can be provided in the vehicle 1000. For example, the automobile display device 10 can also be provided in a position such that a driver sitting on a driver's seat and an occupant sitting on a passenger seat can see the automobile display device 10.

[0113] like Figure 10 and Figure 11 As shown, the second driving mode (boost mode) can be applied to the display panel to display information related to vehicle safety (safety information, risk information, etc.) (for example, displaying a warning light ( Figure 11 On the other hand, the first driving mode (normal mode) can be applied to the display panel to display normal information not related to the safety of the vehicle (for example, displaying normal lights ( Figure 11 Part of a thermometer)) is shown.

[0114] According to the second embodiment, while the vehicle is traveling, the automotive display device 10 can simultaneously drive the two light-emitting devices OLED1 and OLED2 included in the sub-pixel (or pixel) provided at the position corresponding to the warning light, and can allow the drive current to be divided (concentrated current dispersion) to achieve high brightness, thereby reducing the stress applied to the device (reducing current acceleration). Therefore, it is possible to reduce degradation in the two light-emitting devices OLED1 and OLED2 (preventing accelerated degradation), and thus, it is possible to reduce the visibility of the afterimage displayed on the entire screen of the display panel.

[0115] According to the second embodiment, the automotive display device 10 can simultaneously drive the two light-emitting devices OLED1 and OLED2 at peak brightness to split the drive current, thereby achieving high brightness and reducing stress on the devices. In addition, according to the second embodiment, when operating in the second drive mode (boost mode) compared to the first drive mode (normal mode), the automotive display device 10 can achieve higher brightness, thereby improving visibility in certain situations such as displaying a warning light.

[0116] In the following, we can describe more specifically Figure 8 The circuit configuration of the sub-pixel shown in FIG will be described, and a driving method thereof will be described. However, the embodiments of the present disclosure are not limited thereto.

[0117] Figure 12 is a diagram showing a circuit configuration of a device included in a sub-pixel according to a third embodiment of the present disclosure, and Figure 13 Is to show the use of Figure 12 A diagram of a display panel implemented with sub-pixels and a gate driver for driving the display panel is shown.

[0118] like Figure 12 As shown, the sub-pixel SP may include a driving transistor DT, first to tenth switching transistors T1 to T10 , a capacitor CST, and at least two light emitting devices OLED1 and OLED2 .

[0119] The driving transistor DT may include a gate electrode connected to a first node N1, a first electrode connected to a second node N2 connected to a high-level voltage line transmitting a high-level voltage EVDD, and a second electrode connected to a third node N3. The driving transistor DT may generate a driving current based on a data voltage stored in the capacitor CST.

[0120] The first switching transistor T1 may include a gate electrode connected to the first scan line SCL1[n], a first electrode connected to the data line DL, and a second electrode connected to the first electrode of the capacitor CST. The first switching transistor T1 may be turned on based on a first scan signal applied through the first scan line SCL1[n] and may transmit a data voltage applied through the data line DL to the first electrode of the capacitor CST.

[0121] The second switching transistor T2 may include a gate electrode connected to the second scan line SCL2[n], a first electrode connected to the first node N1, and a second electrode connected to the third node N3. The second switching transistor T2 may be turned on based on a second scan signal applied via the second scan line SCL2[n] and may form a diode connection state of the driving transistor DT. The second transistor T2 may be turned on during a threshold voltage sampling period (or compensation period) of the driving transistor DT.

[0122] The third switching transistor T3 may include a gate electrode connected to the emission control line EML[n], a first electrode connected to the reference voltage line VRE, and a second electrode connected to the first electrode of the capacitor CST. The third switching transistor T3 may be turned on based on an emission control signal applied via the emission control line EML[n] and may transmit a reference voltage applied via the reference voltage line VRE to the first electrode of the capacitor CST. The capacitor CST may be initialized (discharged of residual charge) based on the reference voltage applied via the reference voltage line VRE.

[0123] The fourth switching transistor T4 may include a gate electrode connected to the emission control line EML[n], a first electrode connected to the third node N3, and a second electrode connected to the first electrode of each of the seventh switching transistor T7, the eighth switching transistor T8, and the ninth switching transistor T9. The fourth switching transistor T4 may be turned on based on an emission control signal applied through the emission control line EML[n] and may transmit a driving current generated by the driving transistor DT to the first electrode of each of the seventh switching transistor T7, the eighth switching transistor T8, and the ninth switching transistor T9.

[0124] The fifth switching transistor T5 may include a gate electrode connected to the second scan line SCL2[n], a first electrode connected to the reference voltage line VRE, and a second electrode connected to the second electrode of the seventh switching transistor T7 and the anode electrode of the first light-emitting device OLED1. The fifth switching transistor T5 may be turned on based on the second scan signal applied via the second scan line SCL2[n] and may transmit a reference voltage applied via the reference voltage line VRE to the anode electrode of the first light-emitting device OLED1. The first light-emitting device OLED1 may be initialized (discharged of residual charge) based on the reference voltage applied via the reference voltage line VRE.

[0125] The sixth switching transistor T6 may include a gate electrode connected to the second scan line SCL2[n], a first electrode connected to the reference voltage line VRE, and a second electrode connected to the second electrode of the tenth switching transistor T10 and the anode electrode of the second light-emitting device OLED2. The sixth switching transistor T6 may be turned on based on a second scan signal applied via the second scan line SCL2[n] and may transmit a reference voltage applied via the reference voltage line VRE to the anode electrode of the second light-emitting device OLED2. The second light-emitting device OLED2 may be initialized (discharged of residual charge) based on the reference voltage applied via the reference voltage line VRE.

[0126] The seventh switching transistor T7 may include a gate electrode connected to the first direction sharing signal line S_V, a first electrode connected to the second electrode of the fourth switching transistor T4, and a second electrode connected to the anode electrode of the first light-emitting device OLED1. The seventh switching transistor T7 may be turned on based on the first direction sharing signal applied via the first direction sharing signal line S_V, and may apply the driving current generated by the driving transistor DT to the anode electrode of the first light-emitting device OLED1.

[0127] The eighth switching transistor T8 may include a gate electrode connected to the second direction sharing signal line S_H, a first electrode connected to the second electrode of the fourth switching transistor T4, and a second electrode connected to the anode electrode of the first light-emitting device OLED1. The eighth switching transistor T8 may be turned on based on the second direction sharing signal applied via the second direction sharing signal line S_H, and may apply the driving current generated by the driving transistor DT to the anode electrode of the first light-emitting device OLED1.

[0128] The ninth switching transistor T9 may include a gate electrode connected to the second direction privacy signal line P_H, a first electrode connected to the second electrode of the fourth switching transistor T4, and a second electrode connected to the first electrode of the tenth switching transistor T10. The ninth switching transistor T9 may be turned on based on the second direction privacy signal applied via the second direction privacy signal line P_H, and may apply the driving current generated by the driving transistor DT to the tenth switching transistor T10.

[0129] The tenth switching transistor T10 may include a gate electrode connected to the first direction privacy signal line P_V, a first electrode connected to the second electrode of the ninth switching transistor T9, and a second electrode connected to the anode electrode of the second light-emitting device OLED 2. The tenth switching transistor T10 may be turned on based on the first direction privacy signal applied via the first direction privacy signal line P_V, and may apply a driving current transmitted from the ninth switching transistor T9 to the anode electrode of the second light-emitting device OLED 2.

[0130] like Figure 13 As shown, the gate driver 300 may include an emission control signal driver 310, a first scan driver 321, and a second scan driver 322. The shift registers configuring the gate driver 300 may be symmetrically arranged on both sides of the display area AA.

[0131] However, the gate driver 300 may be different based on the circuit configuration and driving scheme of the sub-pixels arranged in the display area AA. For example, the emission control signal driver 310 may be arranged between the first scan driver 321 and the second scan driver 322, or may be arranged between the first scan driver 321 and the display area AA. Therefore, it can be understood that, for example Figure 12 The layout structure.

[0132] The stages STG1 to STGn of the shift register may include first scan signal generators SC1(1) to SC1(n), second scan signal generators SC2(1) to SC2(n), and emission control signal generators EM(1) to EM(n), respectively. Figure 13 , the Nth stage STGn of the shift register is shown as the last stage. However, at least one dummy stage may be provided at a preceding end relative to the first stage STG1, and at least one dummy stage may be provided at a subsequent end relative to the first stage STG1.

[0133] The first scan signal generators SC1(1) to SC1(n) may output first scan signals through first scan lines of the display panel 100. The second scan signal generators SC2(1) to SC2(n) may output second scan signals through second scan lines of the display panel 100. The emission control signal generators EM(1) to EM(n) may output emission control signals through emission control lines of the display panel 100.

[0134] exist Figure 13 In FIG, only one reference voltage line VRE is shown to be provided on the left side of the display area AA, but the embodiment is not limited thereto, and the reference voltage line VRE may be provided on both sides or may be provided in plurality. Figure 13 Although not shown in FIG. 1 , a line for applying a signal or voltage to the shift register may be provided adjacent to the signal generator, but this may vary based on the material of the line or an arrangement relationship with a different line.

[0135] Figure 14 is a diagram for describing the arrangement of shared signal lines and private signal lines and a region selection method based on signals applied through the lines according to a third embodiment of the present disclosure, and Figure 15 and Figure 16 is a diagram for describing an area-based driving mode of a display panel.

[0136] like Figure 14 As shown, in the display panel 100 of the automotive display device, the selection area SELA, to which the first direction share signal S_VS, the second direction share signal S_HS, the first direction privacy signal P_VS, and the second direction privacy signal P_HS are applied, can operate in the second driving mode. The display panel 100 of the automotive display device can select the upper / lower area for operation in the second driving mode based on the first direction share signal S_VS and the first direction privacy signal P_VS, and can select the left / right area for operation in the second driving mode based on the second direction share signal S_HS and the second direction privacy signal P_HS.

[0137] like Figure 12 and Figure 14 As shown, the first direction share signal S_VS can be transmitted through the first direction share signal line S_V, the second direction share signal S_HS can be transmitted through the second direction share signal line S_H, the first direction private signal P_VS can be transmitted through the first direction private signal line P_V, and the second direction private signal P_HS can be transmitted through the second direction private signal line P_H.

[0138] Here, the first direction shared signal line S_V and the first direction private signal line P_V may be identically arranged in the first direction and may be separated from each other, and the second direction shared signal line S_H and the second direction private signal line P_H may be identically arranged in a second direction intersecting the first direction and may be separated from each other.

[0139] In addition, the first direction shared signal line S_V and the first direction private signal line P_V may include a metal layer configuring a scan line (see Figure 2 The gate electrode 125 of the second direction shared signal line S_H and the second direction private signal line P_H may include a metal layer configuring a data line (see Figure 2 However, this may be only an embodiment, but is not limited thereto.

[0140] like Figure 14 and Figure 15 As shown, the display panel 100 may include a shared area (shared mode) (first display area) driven in a shared mode and a private area (private mode) (first display area) driven in a private mode. The shared area (shared mode) driven in the shared mode may be defined as an area in which a driver sitting on a driver's seat and a passenger sitting on a passenger seat can see an image displayed on the display panel 100. The private area (private mode) driven in the private mode may be defined as an area in which only a passenger sitting on a passenger seat can see an image displayed on the display panel 100.

[0141] The shared area (shared mode) may include a first area A (shared only) that is only in the shared mode and a second area B (boost mode) that is only in the second driving mode. For example, the first area A in the shared mode may be defined as an area where information related to vehicle safety is not displayed (no warning signal), and the second area B in the second driving mode may be defined as an area where information related to vehicle safety is displayed (warning signal).

[0142] The privacy zone (private mode) may include a third zone C (boost mode) that is only in the second driving mode and a fourth zone D (private only) that is only in the private mode. For example, the third zone C that is only in the second driving mode may be defined as a zone that displays information related to vehicle safety (warning signal), and the fourth zone D that is only in the private mode may be defined as a zone that does not display information related to vehicle safety (no warning signal).

[0143] The first area A of the shared area (sharing mode) and the fourth area D of the private area (private mode) can be defined as areas capable of operating in the first driving mode, and the second area B of the shared area (sharing mode) and the third area C of the private area (private mode) can be defined as areas capable of operating in the second driving mode.

[0144] exist Figure 15 In the method of applying a signal for selecting at least one of the first area A and the second area B of the shared area (shared mode) and the third area C and the fourth area D of the private area (private mode), reference may be made to Figure 16 In the table. Figure 16 In the embodiment, the low voltage L may represent a gate-on voltage for turning on a switching transistor connected to the shared signal line and the private signal line, and the high voltage H may represent a gate-off voltage for turning off a switching transistor connected to the shared signal line and the private signal line. Figure 16 The table of may be shown with respect to a p-type switching transistor, and thus when is selected as an n-type switching transistor, its operating condition may be opposite thereto.

[0145] In addition, Figure 15 In the above description, an example has been described in which an area capable of operating in the second driving mode is included in all shared areas (shared mode) and private areas (private mode). However, this may be merely an embodiment, and the area capable of operating in the second driving mode may be provided only in the shared area (shared mode).

[0146] Figure 17 is a first diagram showing a portion of an internal configuration of a controller for generating a signal based on a pattern according to a third embodiment of the present disclosure, Figure 18 is a second diagram showing a portion of an internal configuration of a controller for generating a signal based on a pattern according to a third embodiment of the present disclosure, and Figure 19 is a waveform diagram for describing the overall operation of the display device according to the third embodiment of the present disclosure.

[0147] like Figure 17 and Figure 18 As shown, the controller may include a boost signal detector 210, a pixel position calculator 220, a boost mode data generator 230, a data generator 240, a data output unit 250, and a pixel position selection signal generator 260. Hereinafter, in order to help understand the description, an example in which the second driving mode is defined as the boost mode will be described.

[0148] The boost signal detector 210 may detect the boost signal BES applied from the outside to determine whether there is a boost mode activation state or a boost mode deactivation state. Figure 18As shown, the boost signal detector 210 may be omitted. In this case, the boost signal BES may be directly transmitted to the boost mode data generator 230.

[0149] Pixel position calculator 220 can calculate the position value of the boost pixel based on the externally applied boost area signal BMA to set the area where the boost mode is applied (the boost mode application area). In a display panel, the location of the area capable of operating in boost mode can vary depending on the vehicle. Therefore, the area where the boost mode is applied can be set based on the boost area signal BMA, thereby increasing universality.

[0150] When the boost mode is activated, the boost mode data generator 230 can operate. When the boost mode is activated, the boost mode data generator 230 can generate a boost data signal corresponding to the area to be operated in the boost mode (the area where OLED1 and OLED2 are driven simultaneously in the sub-pixel included in the boost pixel) based on the position value of the boost pixel transmitted from the pixel position calculator 220. The boost data signal can be generated so that the brightness is increased compared to the normal data signal generated in the normal mode (the data signal to which the boost mode is not applied). However, the boost mode data generator 230 can also operate in a manner that further increases the visibility of the area to be operated in the boost mode.

[0151] The data generator 240 may add the boosted data signal transmitted from the boost mode data generator 230 to the data signal DATA applied from the outside (the data signal applied under the normal mode condition) to generate a new data signal (including the data signals of the normal mode and the boost mode). The new data signal (including the data signals of the normal mode and the boost mode) may include a normal data signal applied to a region operating in the normal mode and a boosted data signal applied to a region operating in the boost mode.

[0152] The data output unit 250 may output the new data signal generated by the data generator 240. The data output unit 250 may include a circuit for outputting or transmitting the new data signal to the data driver 400. The data driver 400 may apply the new data signal through the data line of the display panel 100.

[0153] The pixel position selection signal generator 260 may generate a pixel position selection signal for selecting the position of the boosted pixel based on the position value of the boosted pixel transmitted from the pixel position calculator 220. The pixel position selection signal generator 260 may include a circuit for outputting or transmitting the pixel position selection signal to the level shifter 350.

[0154] The level shifter 350 may generate a shared signal and a private signal to be applied to the display panel 100 based on the pixel position selection signal transmitted from the pixel position selection signal generator 260. The level shifter 350 may shift the level to a gate-on voltage and a gate-off voltage for turning on or off the switching transistors connected to the shared signal line and the private signal line, and may thus output the shared signal and the private signal.

[0155] In the following, reference will be made to Figure 19 An example of an automobile display device operating in a boost mode is described. However, Figure 19 This may be merely an embodiment to help understand the boost mode operation, and the embodiment is not limited thereto.

[0156] like Figure 1 、 Figure 10 and Figures 12 to 19 As shown, when the power of the vehicle is applied, the car display device 10 can generate a vertical synchronization signal Vsync and can start driving. In this case, the vertical synchronization signal Vsync can be generated by the controller 200.

[0157] When the mode selection signal (MODE SELECT) applied from the outside is logic low L, the automobile display device 10 can operate (control) the shared area (shared mode), and when the mode selection signal (MODE SELECT) applied from the outside is logic high H, the automobile display device 10 can operate (control) the private area (private mode).

[0158] The automotive display device 10 may operate in the boost mode when the externally applied boost signal BES shifts from logic low L to logic high H. When operating in the boost mode, the automotive display device 10 may operate based on the new data signal DATAP and the pixel position selection signal PIXP.

[0159] The automotive display device 10 can display an image on the display panel 100 based on signals applied through the gate lines, such as the first scan signal SCAN1, the second scan signal SCAN2, and the emission control signal EM, and signals applied through the signal lines, such as the first direction privacy signal P_VS, the second direction privacy signal P_HS, the first direction share signal S_VS, and the second direction share signal S_HS.

[0160] The automotive display device 10 may operate the selected area in the boost mode when the boost signal BES is applied to a logic low L, the first scan signal SCAN1, the second scan signal SCAN2, and the emission control signal EM are applied to a low voltage L, and the first direction privacy signal P_VS, the second direction privacy signal P_HS, the first direction share signal S_VS, and the second direction share signal S_HS are applied to a low voltage L. That is, the boost mode may be initiated when the first direction privacy signal P_VS, the second direction privacy signal P_HS, the first direction share signal S_VS, and the second direction share signal S_HS are applied under the same voltage condition.

[0161] As described above, the present disclosure can allow one or more light-emitting devices selected from at least two light-emitting devices to emit light based on a driving mode, thereby increasing visibility in certain situations. Furthermore, the present disclosure can split the driving current when at least two light-emitting devices emit light, thereby achieving high brightness and reducing stress applied to the devices, thereby reducing degradation and reducing the visibility of afterimages. Furthermore, the present disclosure can increase visibility and reduce degradation when displaying information related to vehicle safety, thereby providing an automotive display device that can be implemented to achieve a long life.

[0162] The effects according to the present disclosure are not limited to the above-described examples, and other various effects may be included in the specification.

[0163] While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A display device comprising: a sub-pixel comprising a driving transistor and at least two light-emitting devices; A display panel comprising a first display area and a second display area, each display area displaying an image based on the sub-pixels; as well as a display panel driving circuit configured to drive the display panel, The display panel driving circuit drives the display panel to operate so that only one of the at least two light-emitting devices emits light in a first driving mode, and the at least two light-emitting devices emit light in a second driving mode.

2. The display device according to claim 1, wherein In the second driving mode, the driving current generated from the driving transistor is distributed to the at least two light emitting devices.

3. The display device according to claim 2, wherein: The second driving mode is started based on a shared signal applied through a shared signal line connected to the sub-pixel and a private signal applied through a private signal line connected to the sub-pixel.

4. The display device according to claim 3, wherein The display panel driving circuit includes a level shifter that outputs the shared signal and the private signal.

5. The display device according to any one of claims 1 to 4, wherein: The sub-pixel includes a plurality of mode selection transistors for selectively driving one or two of the at least two light emitting devices. The display device according to claim 5 , wherein: The plurality of mode selection transistors include: a first direction sharing mode selection transistor that is turned on based on a first direction sharing signal applied through a first direction sharing signal line to apply a driving current generated from the driving transistor to an anode electrode of a first light emitting device among the at least two light emitting devices; a second direction sharing mode selection transistor that is turned on based on a second direction sharing signal applied through a second direction sharing signal line to apply a driving current generated from the driving transistor to an anode electrode of the first light emitting device; a second direction private mode selection transistor that is turned on based on a second direction private signal applied through a second direction private signal line to output the driving current generated from the driving transistor; and a first direction privacy mode selection transistor that is turned on based on a first direction privacy signal applied through a first direction privacy signal line to apply a driving current output from the second direction privacy mode selection transistor to an anode electrode of a second light emitting device among the at least two light emitting devices.

7. The display device according to claim 6, wherein: The second driving mode starts when the first direction share signal, the second direction share signal, the second direction private signal, and the first direction private signal are applied under the same voltage condition.

8. The display device according to any one of claims 1 to 4, wherein: The driving transistor includes a gate electrode connected to a first node, a first electrode connected to a second node connected to a high-level voltage line, and a second electrode connected to a third node; Wherein, the sub-pixel further includes: a first switching transistor including a gate electrode connected to the first scan line and a first electrode connected to the data line; a capacitor including a first electrode connected to the second electrode of the first switching transistor and a second electrode connected to the first node; a second switching transistor including a gate electrode connected to the second scan line, a first electrode connected to the first node, and a second electrode connected to the third node; a third switching transistor including a gate electrode connected to the emission control line, a first electrode connected to the reference voltage line, and a second electrode connected to the first electrode of the capacitor; a fourth switch transistor comprising a gate electrode connected to the emission control line and a first electrode connected to the third node; a fifth switching transistor comprising a gate electrode connected to the second scan line, a first electrode connected to the reference voltage line, and a second electrode connected to an anode electrode of a first light emitting device of the at least two light emitting devices; a sixth switching transistor comprising a gate electrode connected to the second scan line, a first electrode connected to the reference voltage line, and a second electrode connected to an anode electrode of a second light emitting device among the at least two light emitting devices; a seventh switching transistor including a gate electrode connected to the first direction shared signal line, a first electrode connected to the second electrode of the fourth switching transistor, and a second electrode connected to the anode electrode of the first light emitting device; an eighth switching transistor including a gate electrode connected to the second direction shared signal line, a first electrode connected to the second electrode of the fourth switching transistor, and a second electrode connected to the anode electrode of the first light emitting device; a ninth switching transistor including a gate electrode connected to the second direction privacy signal line and a first electrode connected to the second electrode of the fourth switching transistor; and a tenth switching transistor including a gate electrode connected to the first direction privacy signal line, a first electrode connected to the second electrode of the ninth switching transistor, and a second electrode connected to the anode electrode of the second light emitting device.

9. The display device according to any one of claims 1 to 4, wherein: The display panel driving circuit includes a controller that generates a signal for driving the display panel in at least one of the first driving mode and the second driving mode based on a signal applied from the outside, and The controller includes: a pixel position calculator configured to calculate a position value of a boosted pixel so as to set an area to which the second driving mode is applied; a boosting mode data generator configured to generate a boosting data signal corresponding to an area to be operated in the second driving mode based on a position value of the boosting pixel; and A pixel position selection signal generator is configured to generate a pixel position selection signal for selecting a position of a boosted pixel based on the position value of the boosted pixel.

10. The display device according to claim 9, wherein The display panel driving circuit includes a level shifter that outputs a shared signal applied through a shared signal line connected to the sub-pixels and a private signal applied through a private signal line connected to the sub-pixels based on the pixel position selection signal.

11. The display device according to claim 6, wherein The first light-emitting device is defined as a shared light-emitting device, which enables both the user of the first viewpoint and the user of the second viewpoint to see the light emitted therefrom, and the second light-emitting device is defined as a private light-emitting device, which enables only the user of the first viewpoint to see the light emitted therefrom.

12. The display device according to claim 9, wherein The boosted data signal is generated to have increased brightness compared to a normal data signal generated in the first driving mode.

13. A method for driving a display device, the method comprising: a first driving mode step of operating the display panel based on a first driving mode so that only one of two light emitting devices included in a sub-pixel of the display device emits light; as well as a second driving mode step of operating the display panel based on a second driving mode different from the first driving mode so that the two light emitting devices included in the sub-pixel emit light; The second driving mode step is started based on a shared signal applied through a shared signal line and a private signal applied through a private signal line, wherein the shared signal line and the private signal line are respectively connected to the sub-pixels.

14. The driving method according to claim 13, wherein: The second driving mode step starts when the shared signal and the private signal are applied under the same voltage condition.

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