Display device

Abstract

The display device includes: a display panel including a plurality of data lines and a plurality of pixels; a first data driving portion and a second data driving portion including a plurality of first data ICs and a plurality of second data ICs; a timing control section providing an input first lock signal and an input second lock signal to the first data driving section and the second data driving section, respectively; and a comparison circuit that receives an output first lock signal and an output second lock signal generated by the first data driving section and the second data driving section according to the input first lock signal and the input second lock signal, respectively, and compares and synchronizes the output first lock signal and the output second lock signal, and a timing control section to provide a synchronization lock signal to the timing control section, in a locked state of the synchronization lock signal, the timing control section transmits image data to the first data driving section and the second data driving section, and the first data driving section and the second data driving section output corresponding data voltages.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2024-0027786, filed on February 27, 2024, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] With the development of the information society, demands for display devices for displaying images in various forms have increased, and in recent years, various flat display devices such as organic light emitting display devices and liquid crystal display devices have been used.

[0005] Recently, organic light-emitting display devices are driven by a double-bank structure in which data driving parts are placed at both ends of a data line. In this double-bank structure, the same lock signal is simultaneously input to the upper data driving part and the lower data driving part, and in response to the lock signal, the upper data driving part and the lower data driving part each generate and output an output lock signal.

[0006] However, due to differences in electrical characteristics between the upper and lower data driving parts, the timing of outputting the lock signal may not match and may be asynchronous.

[0007] In this case, the output timings of the upper and lower data driving parts may not match and may be asynchronous, resulting in a potential difference in the data voltage between the upper and lower channels, which may cause overcurrent. This overcurrent may cause the data IC (integrated circuit) to heat up or burn out. Summary of the Invention

[0008] An advantage of the present disclosure is to provide a display device that can improve occurrence of overcurrent between an upper channel and a lower channel due to asynchronous output locking signals of upper and lower data driving parts of a double bank structure.

[0009] Additional features and advantages of the present disclosure will be set forth in the following description, and in part will become apparent from the description, or may be learned by practice of the present disclosure. These and other advantages of the present disclosure will be realized and obtained through the structures particularly pointed out in the written description and its claims and drawings.

[0010] To achieve these and other advantages and in accordance with the purposes of the present disclosure, as embodied and broadly described herein, a display device includes: a display panel including a plurality of data lines and a plurality of pixels respectively connected to the plurality of data lines; a first data driving section including a plurality of first data ICs connected to one ends of the plurality of data lines; a second data driving section including a plurality of second data ICs connected to the other ends of the plurality of data lines; a timing control section providing an input first lock signal and an input second lock signal to the first data driving section and the second data driving section, respectively; and a comparison circuit receiving an output first lock signal and an output second lock signal generated from the first data driving section and the second data driving section according to the input first lock signal and the input second lock signal, respectively, and comparing and synchronizing the output first lock signal and the output second lock signal to provide a synchronization lock signal to the timing control section, wherein in a locked state of the synchronization lock signal, the timing control section transmits image data to the first data driving section and the second data driving section, and the first data driving section and the second data driving section output corresponding data voltages.

[0011] In another embodiment, a display device includes: a display panel, the display panel including a plurality of data lines and a plurality of pixels respectively connected to the plurality of data lines; a first data driving part, the first data driving part including a plurality of first data ICs connected to one end of the plurality of data lines; a second data driving part, the second data driving part including a plurality of second data ICs connected to the other end of the plurality of data lines; a timing control part, the timing control part providing an input first locking signal and an input second locking signal to the first data driving part and the second data driving part, respectively; and a comparison circuit, the comparison circuit receiving an output first locking signal and an output second locking signal generated from the first data driving part and the second data driving part according to the input first locking signal and the input second locking signal, respectively, and comparing and synchronizing the output first locking signal and the output second locking signal to provide a synchronous locking signal to the timing control part, wherein the output of the data voltages of the first data driving part and the second data driving part are adjusted according to the synchronous locking signal.

[0012] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0014] Figure 1 is a diagram schematically illustrating a display device according to an embodiment of the present disclosure;

[0015] Figure 2 is a circuit diagram schematically illustrating an example of a pixel according to an embodiment of the present disclosure;

[0016] Figure 3 is a diagram showing a configuration of a gate driving portion of a display device according to an embodiment of the present disclosure;

[0017] Figure 4 is a timing diagram schematically showing an example of a driving signal output from a gate driving portion according to an embodiment of the present disclosure;

[0018] Figure 5 is a cross-sectional view schematically illustrating an example of a cross-sectional structure of a display panel according to an embodiment of the present disclosure;

[0019] Figure 6 is a diagram schematically illustrating a timing control portion, a data driving portion, and a comparison circuit of a display device according to an embodiment of the present disclosure;

[0020] Figure 7 is a timing diagram schematically illustrating an input lock signal and an output lock signal, a synchronization lock signal, and a data voltage according to an embodiment of the present disclosure;

[0021] Figure 8 is a timing diagram schematically illustrating an example of input and output lock signals, a synchronization lock signal, and a data voltage in a case where an output lock signal has asynchrony and a lock failure according to an embodiment of the present disclosure; and

[0022] Figure 9 is a timing diagram schematically illustrating an input lock signal, an output lock signal, and a data voltage in a case where an output lock signal has asynchrony and a lock failure according to a comparative example. DETAILED DESCRIPTION

[0023] The advantages and features of the present disclosure and methods for achieving these advantages and features will be apparent from the embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below, but can be implemented in a variety of different forms, and only these embodiments make the present disclosure complete. This disclosure is provided to fully inform those skilled in the art of the present disclosure of its scope, and the present disclosure may be limited by the scope of the claims.

[0024] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for illustrating the embodiments of the present disclosure are illustrative, and the present disclosure is not limited to those shown. Throughout the specification, the same reference numerals refer to the same components.

[0025] In addition, when describing the present disclosure, if it is determined that a detailed description of a related known technology unnecessarily obscures the subject matter of the present disclosure, the detailed description thereof may be omitted. When the words "including," "comprising," and "having" are used in the present disclosure, other parts may be added unless "only" is used. When a component is expressed in the singular, the plural form is included unless a specific statement is described.

[0026] When interpreting a component, it is interpreted as including a margin range even if there is no separate explicit description.

[0027] In the case of describing positional relationships, for example, when the positional relationship of two parts is described as "on...", "above...", "over...", "under...", "beside...", "under...", etc., unless "exactly" or "directly" is used, one or more other parts may be located between such two parts.

[0028] In the case of describing a temporal relationship, for example, when a temporal sequence is described as "after," "subsequently," "before," etc., discontinuous cases may be included unless "directly" or "immediately" is used.

[0029] When describing the components of the present disclosure, terms such as first, second, etc. may be used. These terms are only used to distinguish a component from other components, and the nature, order, sequence, or number of the components are not limited by the terms.

[0030] The various features of the various embodiments of the present disclosure may be partially or completely connected or combined with each other, and may be technically interlocked and driven in various ways, and the various embodiments may be implemented independently of each other, or may be implemented together with related relationships.

[0031] Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. Meanwhile, in the following embodiments, the same and similar reference numerals are assigned to the same and similar components, and detailed description thereof may be omitted.

[0032] Figure 1 is a diagram schematically illustrating a display device according to an embodiment of the present disclosure. Figure 2 is a circuit diagram schematically illustrating an example of a pixel according to an embodiment of the present disclosure. Figure 3is a diagram illustrating a configuration of a gate driving portion of a display device according to an embodiment of the present disclosure. Figure 4 is a timing diagram schematically showing an example of a driving signal output from a gate driving portion according to an embodiment of the present disclosure.

[0033] Before detailed description, the display device 10 according to the present embodiment may include one of all types of display devices, including a light-emitting display device having a light-emitting diode to which data driving having a double-bank structure is applied.

[0034] Meanwhile, for convenience of explanation, in this embodiment, an organic light emitting display device is described as an example of the display device 10 .

[0035] Reference Figures 1 to 4 The display device 10 of this embodiment may include a display panel 100 and a driving circuit portion for driving the display panel 100. Here, the driving circuit portion may include, for example, a gate driving portion (or gate driving circuit) 210, a data driving portion (or data driving circuit) 220, and a timing control portion (or timing control circuit) 240. In addition, the driving circuit portion may include a power supply portion (or power supply circuit) 280 for supplying power required to drive the display panel 100, the gate driving portion 210, the data driving portion 220, and the timing control portion 240.

[0036] In addition, the driving circuit portion may include a comparison circuit 250 that compares the lock signals output from the data driving portion 220 of the double-bank structure, that is, outputs lock signals (LCK_out: LCK_out1 and LCK_out2), synchronizes the output lock signals to generate a synchronization lock signal LCKS, and provides the generated synchronization lock signal LCKS to the timing control portion 240. Here, the potential of the lock signal may be, for example, lower than the gate high voltage VGH and VEH, and lower than the source drive voltage ( Figure 6 SVDD), but is not limited thereto.

[0037] The display panel 100 may include a display area AA displaying an image, and a non-display area NA disposed outside the display area AA (or surrounding the display area AA).

[0038] In the display area AA, a plurality of pixels P may be arranged in a matrix form along a plurality of horizontal lines (or row lines) and a plurality of vertical lines (or column lines).

[0039] Here, the plurality of pixels P may include pixels displaying different colors, for example, a red pixel, a green pixel, and a blue pixel displaying red, green, and blue, respectively, but is not limited thereto.

[0040] In the display panel 100 , various signal lines transmitting driving signals for driving the pixels P may be formed on a substrate.

[0041] In this regard, for example, a plurality of data lines DL transmitting data signals (or data voltages) as image signals may extend in a vertical direction and be connected to pixels P of corresponding vertical lines.

[0042] In addition, the gate line GL transmitting a gate signal (or a gate voltage) may extend in a horizontal direction and be connected to the pixels P of a corresponding horizontal line.

[0043] In this embodiment, multiple gate signals may be used to drive each pixel P. For example, first to fourth scan signals SC1 to SC4 and a light emission control signal EM may be used. Therefore, multiple gate lines GL may be used to transmit the multiple gate signals, for example, first to fourth scan lines SCL1 to SCL4 and a light emission control line EML.

[0044] Thus, a plurality of pixels P may be defined by a plurality of data lines DL and gate lines GL intersecting each other.

[0045] Each pixel P may include a light emitting diode OD as a light emitting element, and a plurality of transistors and at least one capacitor for driving the light emitting diode OD.

[0046] Meanwhile, in this embodiment, for the sake of convenience of explanation, Figure 2 The pixel P shown is provided with an 8-transistor and 1-capacitor (8T1C) structure of eight transistors T1 to T7 and DT and one capacitor Cst as an example.

[0047] Reference Figure 2 , the pixel P may include a plurality of switching transistors such as first to seventh transistors T1 to T7 , a driving transistor DT, a storage capacitor Cst, and a light emitting diode OD.

[0048] Each of the first to seventh transistors T1 to T7 and the driving transistor DT may include a first electrode, a second electrode, and a gate electrode. One of the first and second electrodes may be a source electrode, and the other may be a drain electrode.

[0049] Each of the first to seventh transistors T1 to T7 and the driving transistor DT may be a P-type transistor or an N-type transistor. Figure 2In the embodiment of the present invention, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are configured as P-type transistors, the first transistor T1 and the seventh transistor T7 are configured as N-type transistors, and the driving transistor DT is configured as a P-type transistor, but is not limited thereto. Alternatively, the driving transistor DT may be configured as an N-type transistor.

[0050] The first to seventh transistors T1 to T7 and the driving transistor DT may include semiconductors of the same material or may include semiconductors of different materials. In this regard, for example, some of the first to seventh transistors T1 to T7 and the driving transistor DT may include one semiconductor layer among a polycrystalline silicon layer, an oxide semiconductor layer, and an amorphous silicon layer, and the other of the first to seventh transistors T1 to T7 and the driving transistor DT may include the other semiconductor layer among a polycrystalline silicon layer, an oxide semiconductor layer, and an amorphous silicon layer.

[0051] At the same time, since oxide semiconductors have excellent off-current characteristics and have characteristics suitable for switching transistors, at least one of the first to seventh transistors T1 to T7 may include an oxide semiconductor layer. In addition, since polysilicon has excellent mobility, the drive transistor DT may include a polysilicon layer. In another embodiment, the first to seventh transistors T1 to T7 and the drive transistor DT may be configured, for example, the drive transistor DT may include an oxide semiconductor layer.

[0052] Meanwhile, in this embodiment, a case in which the first transistor T1 and the seventh transistor T7 include an oxide semiconductor layer and the remaining transistors T2 to T6 and DT include a polysilicon layer is taken as an example.

[0053] Provide to Figure 2The gate signal for the n-th horizontal line (more specifically, at least one of the odd-numbered horizontal lines and the even-numbered horizontal lines constituting the n-th horizontal line) can be provided from the corresponding n-th stage of the gate driving portion 210. For example, four scan signals, namely, first to fourth scan signals (SC1 to SC4: SC1(n) to SC4(n)) and two emission control signals, namely, first and second emission control signals (EM: EM1(n), EM2(n)) can be provided. In this case, in the display area AA, first to fourth scan lines SCL1 to SCL4 and first and second emission control lines EML1 and EML2 connected to the n-th stage and transmitting the first to fourth scan signals SC1(n) to SC4(n) and the first and second emission control signals EM1(n) and EM2(n) to the pixels P can be arranged. Alternatively, the gate driving portion 210 can be configured to provide one emission control signal instead of the two emission control signals EM1(n) and EM2(n).

[0054] The first transistor T1 may be used as a sampling transistor, the second transistor T2 may be used as a data supply transistor, the third transistor T3 and the fourth transistor T4 may be used as light emission control transistors, the fifth transistor T5 may be used as a bias transistor, the sixth transistor T6 may be used as a reset transistor (or a first initialization transistor), and the seventh transistor T7 may be used as an initialization transistor (or a second initialization transistor).

[0055] The light emitting diode OD may include an anode electrode and a cathode electrode. The anode electrode of the light emitting diode OD may be connected to the fifth node N5, and the cathode electrode of the light emitting diode OD may be applied with the low potential driving voltage EVSS.

[0056] The driving transistor DT may include a first electrode connected to the second node N2, a second electrode connected to the third node N3, and a gate electrode connected to the first node N1. The driving transistor DT may provide a driving current to the light emitting diode OD based on the voltage of the first node N1 (i.e., the data voltage Vdata stored in the storage capacitor Cst).

[0057] The first transistor T1 may include a first electrode connected to the first node N1, a second electrode connected to the third node N3, and a gate electrode receiving a first scan signal SC1(n). The first transistor T1 may be turned on in response to the first scan signal SC1(n), and a data voltage Vdata may be applied (or written or sampled) to the gate electrode of the driving transistor DT.

[0058] The storage capacitor Cst may be connected between the first node N1 and the fourth node N4 and may store or maintain the high-potential driving voltage EVDD.

[0059] The second transistor T2 may include a first electrode connected to the data line DL (or receiving the data voltage Vdata), a second electrode connected to the second node N2, and a gate electrode receiving the second scan signal SC2(n). The second transistor T2 may be turned on in response to the second scan signal SC2(n) and transmit the data voltage Vdata to the second node N2.

[0060] The third transistor T3 and the fourth transistor T4 (or the first and second light emission control transistors) may be connected between the power line of the high potential driving voltage EVDD and the light emitting diode OD and may form a current path along which the driving current generated by the driving transistor DT moves.

[0061] The third transistor T3 may include a first electrode connected to the fourth node N4 and receiving the high potential driving voltage EVDD, a second electrode connected to the second node N2, and a gate electrode receiving the first light emitting control signal EM1(n).

[0062] The fourth transistor T4 may include a first electrode connected to the third node N3 , a second electrode connected to the fifth node N5 (or the anode electrode of the light emitting diode OD), and a gate electrode receiving the second light emitting control signal EM2 (n).

[0063] The third transistor T3 and the fourth transistor T4 may be turned on in response to the first and second emission control signals EM1(n) and EM2(n), and a driving current may be supplied to the light emitting diode OD, and the light emitting diode OD may emit light having brightness corresponding to the driving current.

[0064] The fifth transistor T5 may include a first electrode connected to a bias voltage line VobsL transmitting a bias voltage Vobs, a second electrode connected to the second node N2, and a gate electrode receiving the third scan signal SC3(n).

[0065] The sixth transistor T6 may include a first electrode connected to a reset voltage line (or first initialization voltage line) VarL transmitting an anode reset voltage (or first initialization voltage) Var, a second electrode connected to the fifth node N5, and a gate electrode receiving the third scan signal SC3(n).

[0066] The fifth and sixth transistors T5 and T6 may be turned on in response to the third scan signal SC3 (n), the bias voltage Vobs may be applied to the second node N2 , and the anode reset voltage Var may be applied to the fifth node N5 (ie, the anode electrode of the light emitting diode OD).

[0067] The seventh transistor T7 may include a first electrode connected to an initialization voltage line ViniL transmitting an initialization voltage Vini, a second electrode connected to a first node N1, and a gate electrode receiving a fourth scan signal SC4(n). The seventh transistor T7 may be turned on in response to the fourth scan signal SC4(n) and may apply the initialization voltage Vini to initialize the gate electrode of the drive transistor DT. Due to the high potential drive voltage EVDD applied to the storage capacitor Cst, unnecessary charge may remain in the gate electrode of the drive transistor DT. Therefore, by applying the initialization voltage Vini to the gate electrode of the drive transistor DT via the seventh transistor T7, the remaining charge may be initialized.

[0068] The 8T1C structure of the pixel P described above is an example, and the pixel P of this embodiment may be configured with a different structure.

[0069] Reference Figure 1 The timing control section 240 can process the image data Do input from the host system to be suitable for the size and resolution of the display panel 100 and supply it to the data driving section 220. The timing control section 240 can use the synchronization signals input from the host system, such as the dot clock signal CLK, the data enable signal DE, the horizontal synchronization signal HSY, and the vertical synchronization signal VSY, to generate the gate control signal GCS and the data control signal DCS. By supplying the gate control signal GCS and the data control signal DCS generated in this manner to the gate driving section 210 and the data driving section 220, respectively, the gate driving section 210 and the data driving section 220 can be controlled.

[0070] The timing control part 240 may be configured by combining with various processors (eg, a microprocessor, a mobile processor, an application processor, etc.) according to a device to be installed.

[0071] Meanwhile, the host system may be, for example, a driving system that drives an electronic device to which the display apparatus 10 is applied. The electronic device may be, for example, one of a TV (television), a navigation system, a monitor, a mobile device, and a wearable device.

[0072] The gate driving part 210 may receive the gate control signal GCS from the timing control part 240, generate gate signals, and sequentially apply the gate signals to the gate lines GL. For example, the gate signals may be sequentially output from top to bottom in a vertical direction.

[0073] The gate driving portion 210 may be disposed on at least one side of the display area AA, for example. In this embodiment, the gate driving portion 210 is configured to include a first gate driving portion 211 and a second gate driving portion 212 disposed on both sides of the display area AA (for example, on the left and right sides of the display area AA) as an example.

[0074] The gate driving part 210 may be directly formed in the non-display area NA on the substrate of the display panel 100, for example, in a GIP (Gate In Panel) structure. In this case, the gate driving part 210 may be formed during a process of forming elements of the display panel 100.

[0075] The gate driving portion 210 configured with a GIP structure may include, for example, a first scan driving circuit that sequentially outputs a first scan signal SC1, a second scan driving circuit that sequentially outputs a second scan signal SC2, a third scan driving circuit that sequentially outputs a third scan signal SC3, a fourth scan driving circuit that sequentially outputs a fourth scan signal SC4, a first light emitting driving circuit that sequentially outputs a first light emitting control signal EM1, and a second light emitting driving circuit that sequentially outputs a second light emitting control signal EM2.

[0076] Each of the first to fourth scan driving circuits and the first and second light emitting driving circuits may be configured with a shift register including a plurality of stages that output corresponding signals.

[0077] Further references Figure 3 The gate driving portion 210 is described. Figure 3 A portion of the gate driving portion 210 is shown, and for ease of explanation, the configuration of a portion of the gate driving portion 210 that drives the nth horizontal line of the display area AA (the nth horizontal line is configured with the nth odd horizontal line (or the 2n-1th horizontal line) and the nth even horizontal line (or the 2nth horizontal line)) is shown.

[0078] In the first gate driving part 211 of the gate driving part 210, for example, a first scanning stage SSC1(n), a third scanning stage SSC3(n), and a fourth scanning stage SSC4(n) respectively constituting a first scanning driving circuit, a third scanning driving circuit, and a fourth scanning driving circuit, a first light-emitting stage SEM1(n) and a second light-emitting stage SEM2(n) respectively constituting a first light-emitting driving circuit and a second light-emitting driving circuit, and an odd-numbered second scanning stage SSC2_O(n) and an even-numbered second scanning stage SSC2_E(n) constituting a second scanning driving circuit may be arranged.

[0079] In addition, in the second gate driving part 212 of the gate driving part 210, for example, a first scanning level SSC1(n), a third scanning level SSC3(n) and a fourth scanning level SSC4(n) respectively constituting a first scanning driving circuit, a third scanning driving circuit and a fourth scanning driving circuit, a first light-emitting level SEM1(n) and a second light-emitting level SEM2(n) respectively constituting a first light-emitting driving circuit and a second light-emitting driving circuit, and an odd-numbered second scanning level SSC2_O(n) and an even-numbered second scanning level SSC2_E(n) constituting a second scanning driving circuit may be arranged.

[0080] Figure 3 The illustrated arrangements of the first to fourth scanning stages SSC1(n) to SSC4(n) and the first and second light emitting stages SEM1(n) and SEM2(n) are examples, and they may be arranged in various combinations in the first and second gate driving parts 211 and 212.

[0081] The first scanning stage SSC1(n) may generate a first scanning signal SC1(n) and output it to the corresponding first scanning line SCL1. Thus, the pixels P_O(n) of the nth odd horizontal line and the pixels P_E(n) of the nth even horizontal line may be commonly supplied with the first scanning signal SC1(n).

[0082] The odd second scan stage SSC2_O(n) can generate an odd second scan signal SC2_O(n) and output it to the corresponding odd second scan line SCL2, and the even second scan stage SSC2_E(n) can generate an even second scan signal SC2_E(n) and output it to the corresponding even second scan line (SCL2). Therefore, the pixel P_O(n) of the nth odd horizontal line can be applied with the odd second scan signal SC2_O(n), and the pixel P_E(n) of the nth even horizontal line can be applied with the even second scan signal SC2_E(n). Here, the odd second scan signal SC2_O(n) and the even second scan signal SC2_E(n) can have different timings. For example, the odd second scan signal SC2_O(n) and the even second scan signal SC2_E(n) can be applied to the data write period of the nth odd horizontal line and the data write period of the nth even horizontal line immediately thereafter, respectively.

[0083] The third scanning stage SSC3(n) may generate a third scanning signal SC3(n) and output it to the corresponding third scanning line SCL3. Thus, the pixels P_O(n) and P_E(n) of the nth odd horizontal line and the nth even horizontal line may be commonly applied with the third scanning signal SC3(n).

[0084] The fourth scanning stage SSC4(n) may generate a fourth scanning signal SC4(n) and output it to the corresponding fourth scanning line SCL4. Thus, the pixels P_O(n) and P_E(n) of the nth odd-numbered horizontal line and the nth even-numbered horizontal line may be commonly applied with the fourth scanning signal SC4(n).

[0085] The first light emitting stage SEM1(n) may generate a first light emitting control signal EM1(n) and output it to the corresponding first light emitting control line EML1. Thus, the pixels P_O(n) and P_E(n) of the nth odd horizontal line and the nth even horizontal line may be commonly applied with the first light emitting control signal EM1(n).

[0086] The second light emitting stage SEM2(n) may generate a second light emitting control signal EM2(n) and output it to the corresponding second light emitting control line EML2. Thus, the pixels P_O(n) and P_E(n) of the nth odd-numbered horizontal line and the nth even-numbered horizontal line may be commonly applied with the second light emitting control signal EM2(n).

[0087] At the same time, refer to Figure 3 , a bias voltage line VobsL, a reset voltage line VarL, and an initialization voltage line ViniL may be disposed between the gate driving part 210 and the display area AA.

[0088] The bias voltage line VobsL, the reset voltage line VarL, and the initialization voltage line ViniL may supply the bias voltage Vobs, the anode reset voltage Var, and the initialization voltage Vini, respectively, from the power supply portion 280 to the pixels P in the display area AA.

[0089] exist Figure 3 , each of the bias voltage line VobsL, the reset voltage line VarL, and the initialization voltage line ViniL is shown as being located only on the left or right side of the display area AA, but is not limited thereto, and each of the bias voltage line VobsL, the reset voltage line VarL, and the initialization voltage line ViniL can be located on both sides, and even if located on one side, the position on the left or right side is not limited.

[0090] In addition, refer to Figure 3 , one or more optical areas OA1 and OA2 may be set in the display area AA.

[0091] One or more optical areas OA1 and OA2 may be arranged to overlap with one or more optical electronic devices, such as a camera (or image sensor) and / or a detection sensor such as a proximity sensor and an illumination sensor. For the operation of the optical electronic devices, one or more optical areas OA1 and OA2 may have a light-transmitting structure formed therein and may have a certain level of transmittance or higher. In other words, the number of pixels P per unit area in the one or more optical areas OA1 and OA2 may be smaller than the number of pixels P per unit area in the regular areas of the display area AA excluding the optical areas OA1 and OA2. In other words, the resolution of the one or more optical areas OA1 and OA2 may be lower than the resolution of the regular areas within the display area AA.

[0092] Return to reference Figure 1 The data driving part 220 may receive the image data Do and the data control signal DCS from the timing control part 240, and in response to the data control signal DCS, the data driving part 220 may convert the image data Do into analog image data, i.e., a data voltage Vdata, and output it to the corresponding data line DL.

[0093] The data driving part 220 may be configured as a double-bank structure to output the data voltage Vdata to both ends of the data line DL.

[0094] In this regard, the data driving portion 220 may be configured with a first data driving portion 221 disposed on (or connected to) one side (e.g., the upper side (or top)) of the display panel 100 (or the display area AA), and a second data driving portion 222 disposed on (or connected to) the other side (e.g., the lower side (or bottom)) of the display panel 100.

[0095] Each of the first data driving section 221 and the second data driving section 222 may be configured to include at least one data IC. In this case, the data IC may be connected to the non-display area NA of the corresponding side of the display panel 100 while being mounted on a flexible circuit film, or may be directly mounted on the non-display area NA.

[0096] The first data driving section 221 and the second data driving section 222 may be formed to have channels (or output channels) connected to, for example, a plurality of data lines DL provided in the display panel 100. In this regard, the first data driving section 221 may be provided with a channel for outputting a data voltage Vdata to the top of each data line DL. In addition, the second data driving section 222 may be provided with a channel for outputting a data voltage Vdata to the bottom of each data line DL.

[0097] Therefore, the image data Do output from the timing controlling part 240 may be commonly (or identically) provided to the first and second data driving parts 221 and 222 respectively provided at the upper and lower sides of the display panel 100 .

[0098] Therefore, the same data voltage Vdata output from the first data driving part 221 and the second data driving part 222 may be applied to the top and bottom of each data line DL.

[0099] Therefore, in the double-bank structure, since the data line DL may receive the same data voltage Vdata at both ends, the data voltage Vdata may be stably supplied into the display area AA.

[0100] The power supply portion 280 may use, for example, a DC-DC converter to generate DC power required to drive the pixel array and driving circuit portion of the display panel 100. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, and the like.

[0101] The power supply section 280 may receive a power voltage Vcc as a driving voltage for driving the display device (10) from a host system, and generate DC voltages such as gate low voltages VGL and VEL, gate high voltages VGH and VEH, a high potential driving voltage EVDD, a low potential driving voltage EVSS, and a source driving voltage ( Figure 6 The gate low voltages VGL and VEL and the gate high voltages VGH and VEH may be supplied to the gate driving portion 210. The high potential driving voltage EVDD and the low potential driving voltage EVSS may be commonly supplied to the pixels P in the display panel 100. The source driving voltage SVDD may be supplied to the first data driving portion 221 and the second data driving portion 222 constituting the data driving portion 220.

[0102] Here, the source driving voltage SVDD may have a potential higher than the high potential driving voltage EVDD and lower than the gate high voltages VGH and VEH, but is not limited thereto. In addition, the low potential driving voltage EVSS may have a potential lower than, equal to, or higher than the gate low voltages VGL and VEL, for example.

[0103] Further references Figure 4 Describes the gate signal applied to the pixel P of the display panel 100. Figure 4 In the figure, for the convenience of explanation, the first light emitting control signal and the second light emitting control signal EM(n) are not shown separately, but one light emitting control signal EM(n) representing them is shown as an example.

[0104] A frame (or refresh frame) in which data is written and an image is refreshed may be divided into a non-light emitting period Tne and a light emitting period Te.

[0105] The non-light-emitting period Tne and the light-emitting period Te may be defined by the light-emitting control signal EM(n). In this regard, a high-level scanning pulse section of the light-emitting control signal EM(n) (e.g., the first light-emitting control signal EM1(n) and the second light-emitting control signal EM2(n)) as an off-level may correspond to the non-light-emitting period Tne, and a low-level section of the light-emitting control signal EM(n) (e.g., the first light-emitting control signal EM1(n) and the second light-emitting control signal EM2(n)) as an on-level may correspond to the light-emitting period Te.

[0106] In the non-light emitting period Tne, an operation of applying and writing the data voltage Vdata may be performed.

[0107] In this regard, for example, during the data writing period (or sampling period) Ts, when each of the odd second scan signal SC2_O(n) and the even second scan signal SC2_E(n) is applied, more specifically, when a low-level scan pulse of each of the odd second scan signal SC2_O(n) and the even second scan signal SC2_E(n) is applied as a turn-on level, the data voltage Vdata of each of the odd pixel P_O(n) and the even pixel P_E(n) may be applied and written to the gate electrode of the driving transistor DT. At the same time, in the data writing period Ts, the threshold voltage of the driving transistor DT may be sampled and reflected to the gate electrode of the driving transistor DT.

[0108] In the data writing period Ts, the first scan signal SC1 (n) may have a scan pulse of a high level as a turn-on level, so that the first transistor T1 may have a turn-on state.

[0109] At the same time, in the non-luminous period Tne, at least one bias period (or anode reset period) Tobs when the bias voltage Vobs and the anode reset voltage Var are applied can be positioned. In this embodiment, the case where the bias period Tobs is set before and after the data writing period Ts is taken as an example. In this case, for ease of explanation, the bias period Tobs set before data writing can be referred to as a first bias period Tobs1, and the bias period Tobs set after data writing can be referred to as a second bias period Tobs2.

[0110] In each of the first bias period Tobs1 and the second bias period Tobs2 , the third scan signal SC3 ( n ) may have a scan pulse of a low level as a turn-on level.

[0111] In this case, the fifth transistor T5 may be turned on so that the bias voltage Vobs may be applied to the second node N2 and the third node N3 , thereby performing a turn-on bias stress operation on the driving transistor DT.

[0112] In addition, the sixth transistor T6 may be turned on so that the anode reset voltage Var may be applied to the fifth node N5. Thus, an anode reset operation with respect to the anode electrode of the light emitting diode OD may be performed.

[0113] At the same time, an operation of applying the initialization voltage Vini can be performed between the data writing period Ts and the first bias period Tobs1. In this initialization section Ti, the fourth scan signal SC4(n) can have a high-level scan pulse as a conduction level. Therefore, the seventh transistor T7 can be turned on, so that the initialization voltage Vini can be applied to the first node N1, that is, the gate electrode of the drive transistor DT. Thus, an initialization operation on the drive transistor DT can be performed.

[0114] In the following, further reference is made to Figure 5 An example of a cross-sectional structure of the display panel 100 of this embodiment is described. Figure 5 is a cross-sectional view schematically illustrating an example of a cross-sectional structure of a display panel according to an embodiment of the present disclosure.

[0115] exist Figure 5 For ease of illustration, two thin-film transistors, TFT1 and TFT2, are shown in a pixel P within the display area AA. Here, the thin-film transistor TFT1, located relatively lower and closer to the substrate 101, is referred to as the first thin-film transistor TFT1 and may be a polysilicon thin-film transistor. The thin-film transistor TFT2, located relatively higher and further from the substrate 101, is referred to as the second thin-film transistor TFT2 and may be an oxide thin-film transistor.

[0116] Meanwhile, the first thin film transistor TFT1 may be a driving transistor ( Figure 2 DT), but not limited thereto, and in Figure 5 In the figure, for the sake of convenience, the first thin film transistor TFT1 is shown to be connected to the light emitting diode OD. In addition, the second thin film transistor TFT2 can be the first transistor to the seventh transistor ( Figure 2 1 to T7), and more particularly, the first transistor T1 connected to the storage capacitor Cst, but is not limited thereto.

[0117] The substrate 101 may be configured as, for example, a thin glass substrate (or glass film) or a plastic substrate (or plastic film) to achieve flexible characteristics of the display panel 100 .

[0118] Here, in the case where the substrate 101 is configured as a glass substrate, for example, the substrate 101 may have a thickness of about 0.2 mm.

[0119] Meanwhile, in the case where the substrate 101 is configured as a plastic substrate, for example, the substrate 101 may include at least one polyimide layer.

[0120] The first thin film transistor TFT1 may include a first semiconductor layer 105 provided on a substrate 101, a first gate electrode 115 overlapping the semiconductor layer 105 with a first insulating layer 110 interposed therebetween, and a first source electrode 151 and a first drain electrode 152 located on a fourth insulating layer 145 above the first gate electrode 115. Here, the first semiconductor layer 105 may be formed of polycrystalline silicon, but is not limited thereto.

[0121] The first semiconductor layer 105 may include a central channel region and source and drain regions on both sides thereof. A first source electrode 151 and a first drain electrode 152 may be connected to the source and drain regions of the first semiconductor layer 105 through first and second contact holes 156 and 157 formed in the insulating layers 110, 120, 125, 135, and 145 below the first source electrode 151 and the first drain electrode 152.

[0122] A second insulating layer 120 may be formed on the first gate electrode 115 of the first thin film transistor TFT1 .

[0123] A first interlayer insulating layer 125 may be formed on the second insulating layer 120. A second thin film transistor TFT2 may be formed on the first interlayer insulating layer 125.

[0124] The second thin film transistor TFT2 may include a second semiconductor layer 130 on the first interlayer insulating layer 125, a second gate electrode 140 overlapping the second semiconductor layer 130 with a third insulating layer 135 interposed therebetween, and a second source electrode 153 and a second drain electrode 154 on a fourth insulating layer 145 above the second gate electrode 140. Here, the second semiconductor layer 130 may be formed of an oxide semiconductor, but is not limited thereto.

[0125] The second semiconductor layer 130 may include a central channel region and source and drain regions on both sides thereof. A second source electrode 153 and a second drain electrode 154 may be connected to the source and drain regions of the second semiconductor layer 130 through third and fourth contact holes 158 and 159 formed in the insulating layers 135 and 145 below the second source and drain electrodes 153 and 154.

[0126] A second interlayer insulating layer (or a first planarization layer) ( 160 ) may be formed on the second thin film transistor TFT2 .

[0127] Here, the first insulating layer 110 , the second insulating layer 120 , the third insulating layer 135 , and the fourth insulating layer 145 may be formed of an inorganic insulating material such as silicon nitride or silicon oxide, but are not limited thereto.

[0128] In addition, the first interlayer insulating layer 125 and the second interlayer insulating layer 160 may be formed of an organic insulating material such as photo acrylic or benzocyclobutene, but are not limited thereto.

[0129] A connection electrode 162 may be formed on the second interlayer insulating layer 160 . The connection electrode 162 may be connected to the first drain electrode 152 through a contact hole 161 formed in the second interlayer insulating layer 160 .

[0130] A third interlayer insulating layer (or a second planarization layer) 163 may be formed on the connection electrode 162. The third interlayer insulating layer 163 may be formed of an organic insulating material such as photoacryl or benzocyclobutene, but is not limited thereto.

[0131] A light emitting diode OD and a bank 165 may be formed on the third interlayer insulating layer 163 .

[0132] The light emitting diode OD may include an anode electrode (or first electrode) 171 , a light emitting layer 172 , and a cathode electrode (or second electrode) 173 .

[0133] The anode electrode 171 may be connected to the connection electrode 162 through a contact hole 164 formed in the third interlayer insulating layer 163 .

[0134] The bank 165 may be provided along a boundary of the pixel P and may be formed to cover an edge of the anode electrode 171. The light emitting layer 172 may be formed on the anode electrode 171 exposed through the opening of the bank 165.

[0135] The cathode electrode 173 may be formed on the light emitting layer 172 and may be applied with a low potential driving voltage ( Figure 2 of EVSS).

[0136] An encapsulation layer 180 may be formed on the cathode electrode 173. The encapsulation layer 180 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer, but is not limited thereto. In the present disclosure, as an example, a structure of the encapsulation layer 180 in which the first encapsulation layer 181, the second encapsulation layer 182, and the third encapsulation layer 183 are sequentially stacked is described.

[0137] The first encapsulation layer 181 may be formed on the substrate 101 on which the cathode electrode 173 is formed. The third encapsulation layer 183 may be formed on the substrate 101 on which the second encapsulation layer 182 is formed, and may be formed to surround the upper surface, lower surface, and side surface of the second encapsulation layer 182 together with the first encapsulation layer 181. The first encapsulation layer 181 and the third encapsulation layer 183 may minimize or prevent external moisture or oxygen from penetrating into the light-emitting diode OD. The first encapsulation layer 181 and the third encapsulation layer 183 may be formed of an inorganic insulating material capable of low-temperature deposition, such as silicon nitride, silicon oxide, silicon oxynitride, or aluminum oxide.

[0138] The second encapsulation layer 182 can be used as a buffer to reduce the stress between layers caused by the bending of the display device 10, and can flatten the steps between the layers. The second encapsulation layer 182 can be formed on the substrate 101 on which the first encapsulation layer 181 is formed using a non-photosensitive organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyethylene or silicon oxycarbon (SiOC), or a photosensitive organic insulating material such as photo acrylic, but is not limited thereto. When the second encapsulation layer 182 is formed by an inkjet method, a dam DAM can be placed in the non-display area NA to prevent the second encapsulation layer 182 in liquid form from diffusing to the edge of the substrate 101. Compared with the second encapsulation layer 182, the dam DAM can be arranged closer to the edge of the substrate 101. The dam DAM can prevent the second encapsulation layer 182 from diffusing to the pad area where the conductive pad is provided on the outermost edge of the substrate 101.

[0139] The dam DAM can be designed to prevent or at least reduce the diffusion of the second encapsulation layer 182. However, if the second encapsulation layer 182 is formed to exceed the height of the dam DAM during processing, the second encapsulation layer 182, which is an organic layer, may be exposed to the outside, allowing moisture and the like to easily penetrate into the light-emitting element. To prevent this, 10 or more dams DAM can be formed continuously, but the present invention is not limited thereto.

[0140] The dam DAM may be formed simultaneously with the first interlayer insulating layer 125, the second interlayer insulating layer 160, and the third interlayer insulating layer 163. When forming the first interlayer insulating layer 125, the lower layer of the dam DAM may be formed together, and when forming the second interlayer insulating layer 160 and the third interlayer insulating layer 163, the upper layer of the dam DAM may be formed together, so that the dam DAM may be formed into a three-layer structure. As another example, the dam DAM may be formed with one or two of the first interlayer insulating layer 125, the second interlayer insulating layer 160, and the third interlayer insulating layer 163.

[0141] Thus, the dam DAM may be formed of the same material as the first interlayer insulating layer 125 , the second interlayer insulating layer 160 , and the third interlayer insulating layer 163 , but is not limited thereto.

[0142] The dam DAM may be formed to overlap the low potential driving voltage line VSSL. For example, the low potential driving voltage line VSSL may be formed at a lower layer of the area where the dam DAM is located in the non-display area NA.

[0143] The gate driving portion 210 and the low-potential driving voltage line VSSL configured in a GIP structure can be formed along the periphery of the display panel 100, and the low-potential driving voltage line VSSL can be located outside the gate driving portion 210. In addition, the low-potential driving voltage line VSSL can be connected to the cathode electrode 173 to apply the low-potential driving voltage EVSS. In the drawings, the gate driving portion 210 is simply shown in plan and cross-sectional views, but can be configured with the same structure as the first thin film transistor TFT1 and / or the second thin film transistor TFT2 of the display area AA.

[0144] A touch layer (or touch element layer) 190 may be provided on the encapsulation layer 180. In the touch layer 190, a touch buffer layer 191 may be located between a touch sensor metal including touch electrode connection lines 192 and 194 and touch electrodes 195 and 196 and a cathode electrode 173 of the light emitting diode OD.

[0145] The touch buffer layer 191 can block chemical solutions (developers, etchants, etc.) used in the manufacturing process of the touch sensor metal provided on the touch buffer layer 191 or moisture from the outside from penetrating into the light-emitting layer 172 containing an organic material. Therefore, the touch buffer layer 191 can prevent damage to the light-emitting layer 172, which is susceptible to chemical solutions or moisture.

[0146] According to a mutual capacitance-based touch sensor structure, touch electrodes 195 and 196 may be provided on the touch buffer layer 191 , and the touch electrodes 195 and 196 may be arranged to cross each other.

[0147] The touch electrode connection lines 192 and 194 may electrically connect the touch electrodes 195 and 196. The touch electrodes 195 and 196 and one of the touch electrode connection lines 192 and 194 may be located at different layers with the touch insulation layer 193 interposed therebetween. In addition, one of the touch electrode connection lines 192 and 194 and the other of the touch electrode connection lines 192 and 194 may be located at different layers with the touch insulation layer 193 interposed therebetween.

[0148] The touch electrode connection lines 192 and 194 may be arranged to overlap the bank 165 in order to prevent a reduction in an aperture ratio, but are not limited thereto.

[0149] At the same time, a portion of the touch electrodes 195 and 196 and a portion of the touch electrode connecting line 192 can extend along the top and side surfaces of the encapsulation layer 180 and the top and side surfaces of the dam DAM, and be electrically connected to the touch driving circuit through the touch pads 198 and 199.

[0150] A portion of the touch electrodes 195 and 196 and a portion of the touch electrode connecting line 192 can receive a touch drive signal from the touch drive circuit and transmit it to the touch electrodes 195 and 196, and can transmit a touch sensing signal detected by the touch electrodes 195 and 196 to the touch drive circuit.

[0151] In this regard, for example, a driver IC (e.g., a data IC, etc.) including the data driving portion 220 of the touch driving circuit can be configured in a chip on film (COF) type and connected to the non-display area NA of the substrate 101 of the display panel 100, and in this case, the ends of the touch pads 198 and 199 can be connected to a flexible circuit film on which the driver IC is mounted, so that signals can be transmitted.

[0152] A touch protection layer 197 may be provided on the touch electrodes 195 and 196. In the drawings, the touch protection layer 197 is shown as being provided only on the touch electrodes 195 and 196, but is not limited thereto and may extend before or after the dam DAM to be provided on the touch electrode connection line 192.

[0153] In addition, a color filter may be provided on the encapsulation layer 180. The color filter may be located on the touch layer 190 or between the encapsulation layer 180 and the touch layer 190.

[0154] As described above, since the display device 10 of this embodiment can use the data driving section 220 with a double-bank structure, the same lock signal (or lock voltage), namely, the input lock signal (LCK_in: LCK_in1 and LCK_in2), can be input to each of the first data driving section 221 and the second data driving section 222 of the data driving section 220, and clock training, namely, clock recognition processing, can be performed in the first data driving section 221 and the second data driving section 222. When the clock training is completed (or successful), each of the first data driving section 221 and the second data driving section 222 can generate an output lock signal LCK_out as a feedback signal of the input lock signal LCK_in.

[0155] Here, the clock training may be, for example, a process in which the timing control part 240 provides a training clock to the first data driving part 221 and the second data driving part 222, and the first data driving part 221 and the second data driving part 222 normally recognize the training clock. For example, the clock training may be performed during the initial driving time after the display device 10 is powered on and during the blanking time between frames.

[0156] In this regard, for example, when the power voltage Vcc is input to the power supply part 280 to drive the display device 10, the power supply part 280 can generate various driving voltages for driving the display device 10, and the timing control part 240 can generate and output a locking signal, i.e., an input locking signal LCK_in, in synchronization with the input timing of the power voltage Vcc.

[0157] Therefore, the lock signal output from the timing control part 240, that is, the input lock signal LCK_in, can be simultaneously input to the first data driving part 221 and the second data driving part 222. For convenience of explanation, the lock signal input to the first data driving part 221 on the upper side, that is, the input lock signal LCK_in, can be referred to as the input first lock signal LCK_in1, and the lock signal input to the second data driving part 222 on the lower side, that is, the input lock signal LCK_in, can be referred to as the input second lock signal LCK_in2.

[0158] When the input first locking signal LCK_in1 and the input second locking signal LCK_in2 are transmitted at the same timing, the first data driving part 221 and the second data driving part 222 may perform clock training, respectively.

[0159] When the clock training is completed, the first data driving part 221 and the second data driving part 222 may generate and output an output lock signal LCK_out, respectively.

[0160] For example, each of the first data driving section 221 and the second data driving section 222 may be configured with a plurality of data ICs connected in a cascade manner and operated sequentially. In this regard, for example, with respect to each of the first data driving section 221 and the second data driving section 222, when the plurality of data ICs receive a corresponding lock signal, i.e., an input lock signal LCK_in, input thereto, the plurality of data ICs may sequentially perform a clock training operation and then generate and output a corresponding lock signal.

[0161] In this case, in the first data driving part 221, the first data IC can perform clock training according to the input first lock signal LCK_in1, and then generate a corresponding output lock signal and provide it to the second data IC, and in this way, the last data IC can perform clock training, and then generate a corresponding output lock signal LCK_out, and the output lock signal LCK_out, that is, the output first lock signal LCK_out1, can be transmitted to the comparison circuit 250. Therefore, in the first data driving part 221, a plurality of data ICs can sequentially receive the lock signal and perform the clock training operation, and finally output the output first lock signal LCK_out1.

[0162] Similarly, in the second data driving portion 222, the first data IC can perform clock training according to the input second lock signal LCK_in2, and then generate a corresponding output lock signal and provide it to the second data IC, and in this way, finally the data IC can perform clock training, and then generate a corresponding output lock signal LCK_out, and the output lock signal LCK_out, that is, the output second lock signal LCK_out2, can be transmitted to the comparison circuit 250. Therefore, in the second data driving portion 222, a plurality of data ICs can sequentially receive the lock signal and perform the clock training operation, and finally output the output second lock signal LCK_out2.

[0163] As above, the output first locking signal LCK_out1 output from the last data IC of the first data driving part 221 and the output second locking signal LCK_out2 output from the last data IC of the second data driving part 222 can be provided to the comparison circuit 250, and the comparison circuit 250 can compare the output first locking signal LCK_out1 and the output second locking signal LCK_out2.

[0164] For example, by comparing the output first lock signal LCK_out1 and the output second lock signal LCK_out2, the comparison circuit 250 can check whether the output timings of the output first lock signal LCK_out1 and the output second lock signal LCK_out2 of the first data driving part 221 and the second data driving part 222 match or are synchronized. In addition, for example, by checking whether either of the output first lock signal LCK_out1 and the output second lock signal LCK_out2 is in a lock failure state (e.g., by having an abnormal waveform), the comparison circuit 250 can check whether at least one of the first data driving part 221 and the second data driving part 222 has failed clock training and has caused a lock failure.

[0165] The comparison circuit 250 can compare the output first lock signal LCK_out1 and the output second lock signal LCK_out2 to synchronize the locking states of the output first lock signal LCK_out1 and the output second lock signal LCK_out2, and generate a synchronized locking signal, namely a synchronization lock signal LCKS, and transmit it to the timing control part 240.

[0166] In response to the synchronized lock signal, ie, the synchronization lock signal LCKS, the timing control part 240 may control transmission of the image data Do to the first and second data driving parts 221 and 222 to synchronize output timings of the first and second data driving parts 221 and 222 .

[0167] In this regard, for example, in a case where one of the output first lock signal LCK_out1 and the output second lock signal LCK_out2 is delayed compared to the other and therefore they are not synchronized with each other (i.e., they are asynchronous with each other), the transmission timing of the image data Do can be adjusted according to the synchronization lock signal LCKS generated based on the delayed output lock signal LCK_out, so that the image data Do can be provided to the first data driving part 221 and the second data driving part 222.

[0168] In addition, in the event that one of the first data driving part 221 and the second data driving part 222 has a locking failure, the transmission of the image data Do can be turned off (or stopped) according to the synchronization locking signal LCKS generated by reflecting the locking failure, so that the output operation of the data voltage Vdata of the first data driving part 221 and the second data driving part 222 can be turned off.

[0169] Therefore, the output locking signals of the first data driving part 221 and the second data driving part 222 can be monitored in real time by the comparison circuit 250, and the comparison circuit 250 synchronously outputs the locking state of the locking signal, thereby controlling the transmission of the image data Do to the first data driving part 221 and the second data driving part 222.

[0170] Therefore, the occurrence of a potential difference in the data voltage Vdata between the upper and lower ends of the asynchronous section or lock failure section of the upper and lower output lock signals, namely, the first output lock signal LCK_out1 and the second output lock signal LCK_out2, can be reduced or prevented. Consequently, overcurrent caused by the potential difference in the data voltage Vdata between the upper and lower channels can be reduced or prevented, and heating or burning of the data IC due to the overcurrent can be reduced or prevented. Furthermore, the occurrence of poor image quality, such as block blur, caused by a long delay in the output lock signal LCK_out can be reduced or prevented.

[0171] Therefore, the configuration and method of this embodiment are described in more detail below, which compares and synchronizes the output first locking signal LCK_out1 and the output second locking signal LCK_out2 of the first data driving part 221 and the second data driving part 222 at the upper end and the lower end to control the transmission of the image data Do to the first data driving part 221 and the second data driving part 222, and control the output timing of the first data driving part 221 and the second data driving part 222.

[0172] Figure 6 is a diagram schematically illustrating a timing control part, a data driving part, and a comparison circuit of a display device according to an embodiment of the present disclosure. Figure 7 is a timing diagram schematically illustrating input and output lock signals, a synchronization lock signal, and data voltages according to an embodiment of the present disclosure. Figure 8 is a timing diagram schematically illustrating an example of input and output lock signals, a synchronization lock signal, and a data voltage in a case where an output lock signal has asynchrony and a lock failure according to an embodiment of the present disclosure. Figure 9 is a timing diagram schematically illustrating an input lock signal, an output lock signal, and a data voltage in a case where an output lock signal has asynchrony and a lock failure according to a comparative example.

[0173] Reference Figure 6 as well as Figures 1 to 5 The display device 10 of this embodiment may use a double-bank structured data driving portion 220. The double-bank structured data driving portion 220 may include a first data driving portion 221 and a second data driving portion 222 connected to the top and bottom of the display panel 100, respectively.

[0174] Meanwhile, the display device 10 of this embodiment may be driven in a VRR (Variable Refresh Rate) method in which a driving frequency, ie, a refresh rate, is adjusted to reduce power consumption, thereby achieving low-power driving.

[0175] In this regard, refer to Figure 7 and Figure 8During the driving time of the display device 10 by receiving the power voltage Vcc, the frequency, i.e., the refresh rate, may vary, for example, between 60 Hz and 120 Hz. Here, VRR type driving is taken as an example, wherein when driven at a high speed of 120 Hz, the display panel 100 may be driven by dividing the frame into a refresh frame FRr (in which the image (or data voltage (Vdata: Vdata1, Vdata2)) is refreshed) and a skip frame FRs (in which the image is not refreshed and the previous image remains as it is), and when driven at a low speed of 60 Hz, the display panel 100 may be driven with the refresh frame FRr. At the same time, Figure 7 、 Figure 8 and Figure 9 In FIG. 1 , “SC” represents a scanning signal output from the gate driving portion 210 ( Figure 2 and Figure 3 SC1 to SC4).

[0176] The first data driving portion 221 and the second data driving portion 222 of the double bank structure may each include, for example, a plurality of data ICs DIC. In this regard, in this embodiment, an example is given in which the first data driving portion 221 includes three first data ICs DIC1, i.e., first first data IC DIC1(1) to third first data IC DIC1(3), and the second data driving portion 222 includes three second data ICs DIC2, i.e., first second data IC DIC2(1) to third second data IC DIC2(3).

[0177] The first and second data driving parts 221 and 222 of the double-bank structure may output the same data voltage Vdata of each channel to the upper and lower ends of the corresponding data lines DL.

[0178] Here, for convenience of explanation, the data voltage Vdata output from the first data driving part 221 on the upper side can be referred to as the first data voltage (or upper data voltage) Vdata1, and the data voltage Vdata output from the second data driving part 222 on the lower side can be referred to as the second data voltage (or lower data voltage) Vdata2.

[0179] In addition, in this embodiment, a case where the data IC DIC of each of the first data driving part 221 and the second data driving part 222 is mounted on the flexible circuit film FCF in a COF type is taken as an example.

[0180] Meanwhile, the first data driving part 221 may include a first source board SPCB1 to which a plurality of first data ICs DIC1 are connected. Similarly, the second data driving part 222 may include a second source board SPCB2 to which a plurality of second data ICs DIC2 are connected.

[0181] In this regard, the signal output from the timing controlling part 240 may be transmitted to the first data IC DIC1 via the first source board SPCB1 and may also be transmitted to the second data IC DIC2 via the second source board SPCB2 .

[0182] Here, a first lock signal line LCKL1 as a lock signal line LCKL transmitting a lock signal may be formed in the first source board SPCB1. A second lock signal line LCKL2 as a lock signal line LCKL transmitting a lock signal may be formed in the second source board SPCB2.

[0183] In this regard, for example, the input first lock signal LCK_in1 output from the timing control part 240 can be input to the first first data IC DIC1 (1), and the first first data IC DIC1 (1) can perform clock training to output the lock signal. Next, the lock signal (or the first output lock signal) output from the first first data IC DIC1 (1) can be input to the second first data IC DIC1 (2), and the second first data IC DIC1 (2) can perform clock training to output the lock signal. Next, the lock signal (or the second output lock signal) output from the second first data IC DIC1 (2) can be input to the third first data IC DIC1 (3), and the third first data IC DIC1 (3) can perform clock training to output the output first lock signal LCK_out1. Therefore, the output first lock signal LCK_out1 can be transmitted to the comparison circuit 250, and the output first lock signal LCK_out1 is the lock signal output from the third first data IC DIC1 (3) which is the last of the first data IC DIC1.

[0184] Therefore, in order to transmit the input first lock signal LCK_in1 provided from the timing control part 240, the output lock signal generated from the first first data IC DIC1(1) and the second first data IC DIC1(2), and the output first lock signal LCK_out1 generated from the third first data IC DIC1(3), the first lock signal line LCKL1 can be formed in the first source board SPCB1.

[0185] Furthermore, a lock signal line for inputting and outputting a lock signal may also be formed in the flexible circuit film FCF on which the first data IC DIC1 is mounted.

[0186] In addition, the input second lock signal LCK_in2 output from the timing control part 240 can be input to the first second data IC DIC2 (1), and the first second data IC DIC2 (1) can perform clock training to output the lock signal. Next, the lock signal (or first output lock signal) output from the first second data IC DIC2 (1) can be input to the second second data IC DIC2 (2), and the second second data IC DIC2 (2) can perform clock training to output the lock signal. Next, the lock signal (or second output lock signal) output from the second second data IC DIC2 (2) can be input to the third second data IC DIC2 (3), and the third second data IC DIC2 (3) can perform clock training to output the output second lock signal LCK_out2. Therefore, the output second lock signal LCK_out2 can be transmitted to the comparison circuit 250, and the output second lock signal LCK_out2 is the lock signal output from the third second data IC DIC2 (3) which is the last of the second data IC DIC2.

[0187] Therefore, in order to transmit the input second lock signal LCK_in2 provided from the timing control part 240, the output lock signal generated from the first second data IC DIC2(1) and the second second data IC DIC2(2), and the output second lock signal LCK_out2 generated from the third second data IC DIC2(3), the second lock signal line LCKL2 can be formed in the second source board SPCB2.

[0188] Furthermore, a lock signal line for inputting and outputting a lock signal may also be formed on the flexible circuit film FCF on which the second data IC DIC2 is mounted.

[0189] Meanwhile, the timing control part 240 and the comparison circuit 250 may be mounted on, for example, the control board CPCB, but are not limited thereto.

[0190] The timing control part 240 may provide an input first locking signal LCK_in1 and an input second locking signal LCK_in2 (which are the same input locking signal LCK_in) to the first data driving part 221 and the second data driving part 222 , respectively.

[0191] Regarding the input first locking signal LCK_in1 and the input second locking signal LCK_in2, refer to Figure 7, for example, the input first locking signal LCK_in1 and the input second locking signal LCK_in2 may be synchronized with each other and input to the corresponding first data driving part 221 and second data driving part 222 at the same timing.

[0192] In this regard, the input first lock signal LCK_in1 and the input second lock signal LCK_in2 may have a high level in synchronization with the time when the display device 10 is powered on and the power voltage Vcc is applied to the power supply part 280. The high-level input first lock signal LCK_in1 and the input second lock signal LCK_in2 may be continuously maintained during the driving time of the display device (10) and input to the first data driving part 221 and the second data driving part 222.

[0193] In this regard, refer to Figure 7 and Figure 8 , the input first locking signal LCK_in1 and the input second locking signal LCK_in2 may be continuously output from a power-on time of the first and second data driving parts 221 and 222 to a last output time (or last frame) before power-off.

[0194] Therefore, the input first locking signal LCK_in1 and the input second locking signal LCK_in2 output from the timing control part 240 from the power-on time can be input to the corresponding first data driving part 221 and the second data driving part 222, and the first data driving part 221 and the second data driving part 222 can perform clock training to output the corresponding output first locking signal LCK_out1 and the output second locking signal LCK_out2.

[0195] For example, in a power-on sequence performed within a specific time period immediately after powering on the display device 10, the first data driving portion 221 and the second data driving portion 222 may perform clock training and output the first and second lock signals LCK_out1 and LCK_out2. Furthermore, clock training may be performed during a blank period between adjacent frames FR, for example, during an output period of the vertical synchronization signal VSY, to output the first and second lock signals LCK_out1 and LCK_out2.

[0196] The output of the first and second locking signals LCK_out1 and LCK_out2 may be started after a certain period of time has passed since the start of the input of the first and second locking signals LCK_in1 and LCK_in2. In addition, the output of the first and second locking signals LCK_out1 and LCK_out2 may be substantially continuously maintained during the driving time of the display device 10.

[0197] In this regard, refer to Figure 7 In a normal driving state of the display device 10, the first locking signal LCK_out1 and the second locking signal LCK_out2 may be continuously output from a specific time after the power-on time of the first data driving part 221 and the second data driving part 222 to the last output time (or last frame) before the power-off time.

[0198] The comparison circuit 250 may receive the output first locking signal LCK_out1 and the output second locking signal LCK_out2 output from the first data driving part 221 and the second data driving part 222, compare the states of the output first locking signal LCK_out1 and the output second locking signal LCK_out2, synchronize their locking states, and generate a synchronization locking signal LCKS.

[0199] In this regard, for example, the comparison circuit 250 may compare the output first lock signal LCK_out1 and the output second lock signal LCK_out2 to check whether the output timings are synchronous and matched or asynchronous and mismatched, and if asynchronous, synchronize the lock state.

[0200] In this regard, refer to Figure 7 and Figure 8 For example, in a power-on sequence, the first locking signal LCK_out1 may be output first, and then the second locking signal LCK_out2 may be delayed and output. Conversely, in a power-on sequence, the second locking signal LCK_out2 may be output first, and then the first locking signal LCK_out1 may be delayed and output.

[0201] Therefore, an output delay of one of the output first lock signal LCK_out1 and the output second lock signal LCK_out2 may be caused by a resistor-capacitor (RC) component of a line transmitting the lock signal, external factors, etc. In this regard, for example, a signal transmission line between an input into which the first lock signal LCK_in1 is input and an output from which the first lock signal LCK_out1 is output and a signal transmission line between an input into which the second lock signal LCK_in2 is input and an output from which the second lock signal LCK_out2 is output may have different RC resistances, or the output first lock signal LCK_out1 and the output second lock signal LCK_out2 may have different output timings due to external factors.

[0202] In addition, refer to Figure 7, in the power-off sequence of the display device 10, the output of the first locking signal LCK_out1 may be normally terminated, and then the output of the second locking signal LCK_out2 may be delayed and terminated. Figure 8 , in the power-off sequence, the output of the first locking signal LCK_out1 may be normally terminated, and before that, the output of the second locking signal LCK_out2 may be terminated.

[0203] Therefore, when one of the output first lock signal LCK_out1 and the output second lock signal LCK_out2 has a high-level lock state and the other has a low-level unlock state, that is, when their lock states do not match and are not synchronized, the comparison circuit 250 can output the low-level synchronous lock signal LCKS having an unlock state during such an asynchronous section.

[0204] In contrast, when both the output first lock signal LCK_out1 and the output second lock signal LCK_out2 have a high-level lock state, the comparison circuit 250 may output the synchronous lock signal LCKS having a high-level lock state during such a same lock section. Figure 7 and Figure 8 , for example, after the delayed output second lock signal LCK_out2 in the power-on sequence is switched to the lock state, the comparison circuit 250 may generate a high-level synchronous lock signal LCKS.

[0205] In addition, the comparison circuit 250 can compare the output first lock signal LCK_out1 and the output second lock signal LCK_out2 to determine whether at least one of the first data driving part 221 and the second data driving part 222 is abnormally driven and whether and when a lock failure occurs, and the comparison circuit 250 can synchronize them so that they match the unlocked state.

[0206] In this regard, refer to Figure 8 For example, the second data driving part 222 is abnormally driven in the refresh frame FRr driven at 120 Hz, resulting in a lock failure. As a result, the output second lock signal LCK_out2 may not maintain a normal high level and may have an abnormal waveform. Therefore, when a lock failure occurs, the second data driving part 222 may fail clock recognition and perform an abnormal output operation, and noise may appear in the second data voltage Vdata2 output from the second data driving part 222.

[0207] Therefore, when a lock fail occurs in the second data driving part 222 and the output second lock signal LCK_out2 has an abnormal lock fail state, the comparison circuit 250 may output a low-level synchronous lock signal LCKS of an unlock state during a lock fail section.

[0208] As described above, the first output lock signal LCK_out1 and the second output lock signal LCK_out2 can be compared, and when the lock states of these signals are not synchronized with each other or at least one of them has a lock failure state, the comparison circuit 250 can set the synchronization lock signal LCKS to a low level of the unlocked state. In addition, when both the first output lock signal LCK_out1 and the second output lock signal LCK_out2 are in the locked state, the comparison circuit 250 can set the synchronization lock signal LCKS to a high level of the locked state.

[0209] Therefore, the synchronization lock signal LCKS generated by the synchronization lock state in the comparison circuit 250 can be provided to the timing control part 240, and the timing control part 240 can adjust the transmission timing of the image data Do regarding the first data driving part 221 and the second data driving part 222 according to the synchronization lock signal LCKS.

[0210] In this regard, refer to Figure 8 For example, when the locking states of the output first locking signal LCK_out1 and the output second locking signal LCK_out2 are not synchronized with each other or at least one of them is in a locking failure state, the synchronization locking signal LCKS may become a low level in an unlocked state, and in response to the unlocked state of the synchronization locking signal LCKS, the timing control part 240 may turn off the transmission of the image data Do to the first data driving part 221 and the second data driving part 222.

[0211] In this regard, when the output of the first locking signal LCK_out1 and the output of the second locking signal LCK_out2 are asynchronous, the timing control part 240 can turn off the transmission of the image data Do during the asynchronous section, and therefore, the output of the data voltages Vdata1 and Vdata2 of the first data driving part 221 and the second data driving part 222 can be turned off during the asynchronous section.

[0212] For example, Figure 8As shown, in the power-on sequence, with respect to outputting the second locking signal LCK_out2 which is delayed compared to outputting the first locking signal LCK_out1, when the output of the second locking signal LCK_out2 is delayed until the initial segment of the 60Hz-driven refresh frame FRr at which the output of the first data driving part 221 and the second data driving part 222 starts, the synchronization locking signal LCKS can be maintained at a low level until the initial segment of the refresh frame FRr which is a delayed time point, and then switched to a high level.

[0213] In addition, if Figure 8 As shown, in the power-off sequence, with respect to the output of the second locking signal LCK_out2 that terminates before the output of the first locking signal LCK_out1, when the output of the second locking signal LCK_out2 terminates before the end section of the 60 Hz driven refresh frame FRr at which the outputs of the first data driving part 221 and the second data driving part 222 terminate, the synchronization locking signal LCKS may have a high level until the end section of the refresh frame FRr that is the earlier termination time point, and then switch to a low level.

[0214] Therefore, when the output of the second lock signal LCK_out2 is delayed compared to the output of the first lock signal LCK_out1 or terminates earlier than the output of the first lock signal LCK_out1 and thus the output of the first lock signal LCK_out1 and the output of the second lock signal LCK_out2 are asynchronous with each other, the timing control part 240 can shut down the transmission of the image data Do during the asynchronous section. In addition, in a section when the output of the second lock signal LCK_out2 has a high-level lock state and thus the synchronization lock signal LCKS has a high-level lock state, the timing control part 240 can transmit the image data Do in response to the lock state of the synchronization lock signal LCKS.

[0215] Therefore, during the section when the output of the first locking signal LCK_out1 and the output of the second locking signal LCK_out2 are asynchronous, the transmission of the image data Do can be turned off to turn off the output of the first data voltage Vdata1 and the second data voltage Vdata2 at the top and bottom, and during the section when the output of the first locking signal LCK_out1 and the output of the second locking signal LCK_out2 are both in the locked state, the transmission of the image data Do can be performed to synchronize and output the first data voltage Vdata1 and the second data voltage Vdata2 that are equal to each other.

[0216] Therefore, the phenomenon in which the output timing of the first data driver 221 at the top and the second data driver 222 at the bottom may be asynchronous during the asynchronous section in which the first and second lock signals LCK_out1 and LCK_out2 are output can be reduced or prevented, thereby causing a potential difference in the output voltage between the top and bottom channels and, as a result, an overcurrent. Consequently, heating or burning of the data IC DIC due to the overcurrent that occurs when the top and bottom outputs are asynchronous can be reduced or prevented. Furthermore, poor image quality, such as block blur, can be reduced or prevented when the asynchronous section is long.

[0217] In this regard, refer to Figure 9 In the display device of the comparative example, the power supply part 280 provides a single input lock signal LCK_in to the first data driving part 221 and the second data driving part 222, and the timing control part 240 receives the output first lock signal LCK_out1 and the output second lock signal LCK_out2 from the first data driving part 221 and the second data driving part 222. When any one of the output first lock signal LCK_out1 and the output second lock signal LCK_out2 is in a locked state, the image data Do is transmitted to the first data driving part 221 and the second data driving part 222 regardless of whether they are synchronized, and the first data driving part 221 and the second data driving part 222 output corresponding data voltages Vdata1 and Vdata2.

[0218] In the driving of the comparative example, the image data Do is transmitted even in the asynchronous section between the output of the first lock signal LCK_out1 and the output of the second lock signal LCK_out2, so that in the asynchronous section, for example, in the asynchronous section of the power-on sequence or the power-off sequence, the first data driving part 221 outputs the first data voltage Vdata1, but the second data driving part 222 cannot output the second data voltage Vdata2 that is the same as the first data voltage Vdata1. Therefore, a potential difference in the output voltage occurs between the top channel and the bottom channel, which may cause overcurrent.

[0219] In contrast, in this embodiment, as mentioned above, the output of the first lock signal LCK_out1 and the output of the second lock signal LCK_out2 are synchronized to generate the synchronized lock signal LCKS. Therefore, during the asynchronous section between the output of the first lock signal LCK_out1 and the output of the second lock signal LCK_out2, the output of the first data driving part 221 and the second data driving part 222 can be turned off, and during the section where both are in the locked state, the output of the first data driving part 221 and the second data driving part 222 can be performed. Therefore, during the asynchronous section, the potential difference of the output voltage between the top channel and the bottom channel can be alleviated or reduced, so that overcurrent caused by the potential difference can be improved.

[0220] In addition, when at least one of the output first lock signal LCK_out1 and the output second lock signal LCK_out2 is in a lock failure state, the timing control part 240 can turn off the transmission of the image data Do during the lock failure section, and therefore, the output of the data voltages Vdata1 and Vdata2 of the first data driving part 221 and the second data driving part 222 can be turned off during this section.

[0221] For example, Figure 8 As shown, in the 120 Hz driven refresh frame FRr, when the output second lock signal LCK_out2 is in a lock fail state (ie, when the second data driving part 222 has a lock fail), the synchronization lock signal LCKS may have a low level during the lock fail refresh frame FRr.

[0222] Therefore, when the output second lock signal LCK_out2 is in the lock failure state, the timing control part 240 can shut down the transmission of the image data Do during the lock failure section. In addition, in the section when the output second lock signal LCK_out2 is switched to the lock state of the high level and the synchronization lock signal LCKS has the lock state of the high level, the timing control part 240 can transmit the image data Do in response to the lock state of the synchronization lock signal LCKS.

[0223] Therefore, during the section when the output second locking signal LCK_out2 is in an abnormal locking failure state, the transmission of the image data Do can be turned off to turn off the output of the first data voltage Vdata1 and the second data voltage Vdata2 at the top and bottom, and during the section when both are in a normal locking state, the transmission of the image data Do can be performed, and thus the same first data voltage Vdata1 and the second data voltage Vdata2 can be synchronized and output.

[0224] Therefore, the phenomenon in which, in a lock failure section, the first data driving section 221 at the top performs normal output and the second data driving section 222 at the bottom performs abnormal output, resulting in a potential difference in output voltage between the top channel and the bottom channel and thus an overcurrent, can be reduced or prevented. Therefore, heating or burning of the data IC DIC due to the overcurrent that occurs when the lock fails can be reduced or prevented.

[0225] In this regard, refer to Figure 9 In the comparative example, in the display device of the comparative example, when one of the output first lock signal and the output second lock signal (LCK_out1, LCK_out2) is in the locked state, the image data Do is transmitted to the first data driving part 221 and the second data driving part 222 regardless of whether the locking fails, and the first data driving part 221 and the second data driving part 222 output corresponding data voltages Vdata1 and Vdata2.

[0226] In the driving of the comparative example, the image data Do is transmitted even in the lock failure section, so that the first data driving part 221 normally outputs the first data voltage Vdata1, and the second data driving part 222 does not normally output the second data voltage Vdata2 that is the same as the first data voltage Vdata1, but abnormally outputs the second data voltage Vdata2. For example, due to the lock failure, the output voltage of the second data driving part 222 has noise.

[0227] Therefore, a potential difference in the output voltage between the top channel and the bottom channel occurs, which may cause overcurrent. For example, the output voltage of the second data driving part 222 is fixed to the source driving voltage SVDD, which may cause overcurrent to appear in the first data driving part 221.

[0228] In contrast, in this embodiment, as mentioned above, the output of the first lock signal LCK_out1 and the output of the second lock signal LCK_out2 are synchronized to generate the synchronized lock signal LCKS. Therefore, during the lock failure section in which the second lock signal LCK_out2 is output, the outputs of the first data driving part 221 and the second data driving part 222 can be turned off. Therefore, during the lock failure section, the potential difference in the output voltage between the top channel and the bottom channel can be alleviated or reduced, so that overcurrent caused by the potential difference can be improved.

[0229] As described above, in an embodiment of the present disclosure, the input first locking signal and the input second locking signal can be input to the upper data driving part and the lower data driving part of the double-bank structure, respectively, and the output first locking signal and the output second locking signal output from the upper data driving part and the lower data driving part can be compared and synchronized in a comparison circuit to generate a synchronization locking signal, and the synchronization locking signal can be provided to the timing control part, and the timing control part can adjust the transmission timing of the image data according to the synchronization locking signal to synchronize the output of the data voltage from the upper data driving part and the lower data driving part.

[0230] Therefore, a phenomenon in which an overcurrent occurs due to a potential difference in output voltage between an upper channel and a lower channel in an asynchronous section or a lock failure section can be improved.

[0231] Therefore, heating or burning of the data ICs of the upper and lower data driving parts due to overcurrent can be improved. In addition, occurrence of poor image quality such as block blur when the asynchronous section is long can be improved.

[0232] It will be apparent to those skilled in the art that various modifications and variations can be made in the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is intended to cover modifications and variations of the present disclosure as long as they fall within the scope of the appended claims and their equivalents.

Claims

1. A display device comprising: a display panel comprising a plurality of data lines and a plurality of pixels respectively connected to the plurality of data lines; a first data driving part including a plurality of first data ICs connected to one ends of the plurality of data lines; a second data driving part including a plurality of second data ICs connected to the other ends of the plurality of data lines; a timing control part, the timing control part providing an input first locking signal and an input second locking signal to the first data driving part and the second data driving part respectively; as well as a comparison circuit that receives an output first lock signal and an output second lock signal generated from the first data driving part and the second data driving part according to the input first lock signal and the input second lock signal, respectively, and compares and synchronizes the output first lock signal and the output second lock signal to provide a synchronization lock signal to the timing control part, Wherein, in a locked state of the synchronization lock signal, the timing control part transmits image data to the first data driving part and the second data driving part, and the first data driving part and the second data driving part output corresponding data voltages.

2. The display device according to claim 1, wherein During a section when the lock states of the output first lock signal and the output second lock signal are asynchronous with each other, the synchronous lock signal has an unlocked state, and Wherein, in the unlocked state of the synchronization lock signal, the timing control part turns off the transmission of the image data, and the outputs of the first data driving part and the second data driving part are turned off.

3. The display device according to claim 1, wherein During a section when at least one of the output first lock signal and the output second lock signal is in a lock failure state, the synchronization lock signal has an unlock state, and Wherein, in the unlocked state of the synchronization lock signal, the timing control part turns off the transmission of the image data, and the outputs of the first data driving part and the second data driving part are turned off.

4. The display device according to claim 2, wherein In the section when the locking states of the output first locking signal and the output second locking signal are asynchronous with each other, one of the output first locking signal and the output second locking signal is in the locking state, and the other of the output first locking signal and the output second locking signal is in the unlocking state.

5. The display device according to claim 3, wherein The at least one of the output first lock signal and the output second lock signal has an abnormal waveform in the lock failure state. The display device according to claim 1 , wherein: When the input first lock signal is input, the plurality of first data ICs sequentially operate to output corresponding lock signals, and a lock signal output from one first data IC among the plurality of first data ICs is input to a first data IC next to the one first data IC among the plurality of first data ICs, and a lock signal output from a last first data IC of the plurality of first data ICs is the output first lock signal, and When the input second lock signal is input, the plurality of second data ICs operate sequentially to output corresponding lock signals, and the lock signal output from one second data IC among the plurality of second data ICs is input to the next second data IC of the one second data IC among the plurality of second data ICs, and the lock signal output from the last second data IC of the plurality of second data ICs is the output second lock signal.

7. The display device according to claim 6, wherein: The first data driving part includes a first source board to which the plurality of first data ICs are connected, wherein the second data driving part includes a second source board to which the plurality of second data ICs are connected, wherein the first source board includes a first lock signal line for transmitting a lock signal input and output to the plurality of first data ICs, and The second source board includes a second lock signal line for transmitting a lock signal input and output to the plurality of second data ICs.

8. The display device according to claim 1, wherein One of the plurality of pixels includes a light emitting diode.

9. The display device according to claim 1, wherein In the locked state of the sync lock signal, outputs of the data voltages of the first data driving part and the second data driving part are synchronized.

10. A display device comprising: a display panel comprising a plurality of data lines and a plurality of pixels respectively connected to the plurality of data lines; a first data driving part including a plurality of first data ICs connected to one ends of the plurality of data lines; a second data driving part including a plurality of second data ICs connected to the other ends of the plurality of data lines; a timing control part, the timing control part providing an input first locking signal and an input second locking signal to the first data driving part and the second data driving part respectively; as well as a comparison circuit that receives an output first lock signal and an output second lock signal generated from the first data driving part and the second data driving part according to the input first lock signal and the input second lock signal, respectively, compares and synchronizes the output first lock signal and the output second lock signal, and provides a synchronization lock signal to the timing control part, The output of the data voltages of the first data driving part and the second data driving part is adjusted according to the synchronization locking signal.

11. The display device according to claim 10, wherein: In a locked state of the sync lock signal, outputs of the data voltages of the first data driving part and the second data driving part are synchronized.

12. The display device according to claim 10, wherein: During a section when the lock states of the output first lock signal and the output second lock signal are asynchronous with each other, the synchronous lock signal has an unlocked state, and Wherein, in the unlocked state of the synchronization lock signal, the outputs of the first data driving part and the second data driving part are turned off.

13. The display device according to claim 10, wherein: During a section when at least one of the output first lock signal and the output second lock signal is in a lock failure state, the synchronization lock signal has an unlock state, and Wherein, in the unlocked state of the synchronization lock signal, the outputs of the first data driving part and the second data driving part are turned off.

14. The display device according to claim 12, wherein: In the section when the locking states of the output first locking signal and the output second locking signal are asynchronous with each other, one of the output first locking signal and the output second locking signal is in the locking state, and the other of the output first locking signal and the output second locking signal is in the unlocking state.

15. The display device according to claim 13, wherein The at least one of the output first lock signal and the output second lock signal has an abnormal waveform in the lock failure state.

16. The display device according to claim 10, wherein The first data driving part includes a first source board to which the plurality of first data ICs are connected, wherein the second data driving part includes a second source board to which the plurality of second data ICs are connected, wherein the first source board includes a first lock signal line for transmitting a lock signal input and output to the plurality of first data ICs, and The second source board includes a second lock signal line for transmitting a lock signal input and output to the plurality of second data ICs.

17. The display device according to claim 10, wherein: One of the plurality of pixels includes a light emitting diode.

18. The display device according to claim 10, wherein: The data voltages output from the first data driving part and the second data driving part are equal to each other.

Images