Transparent display device

Abstract

There is provided a transparent display device including: a display area in which a plurality of sub-pixels are provided to display an image; a plurality of transmissive regions disposed within the display region and transmitting external light; a first non-transmissive region that is disposed between the transmissive regions disposed adjacent to each other in the first direction and that does not transmit external light; a second non-transmissive region that is disposed between the transmissive regions disposed adjacent to each other in the second direction and that does not transmit external light; a first circuit portion disposed in the first non-transmissive region to drive a sub-pixel disposed in the first non-transmissive region; and a second circuit portion disposed in the second non-transmissive region to drive a sub-pixel disposed in the second non-transmissive region.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly, to a transparent display device. Background Art

[0002] Recently, research on a transparent display device, in which a user can see an object or an image located on the opposite side of the display device, is being actively conducted.

[0003] A transparent display device includes a non-display area and a display area on which an image is displayed. The display area may include a non-transmission area and a transmission area capable of transmitting external light. The transparent display device can have high light transmittance in the display area through the transmission area.

[0004] The description provided in the Background section should not be admitted to be prior art merely because it is mentioned in or related to the Background section.The Background section may include information describing one or more aspects of the subject technology. Summary of the Invention

[0005] Transparent display devices can improve transparency by increasing the transmissive area. However, when the transmissive area is increased, the non-transmissive area is reduced, and a problem arises in that a plurality of signal lines and a plurality of circuit elements should be arranged in the narrow non-transmissive area.

[0006] The present disclosure is made in view of the above problems, and an object of the present disclosure is to provide a transparent display device which can improve transparency.

[0007] Another object of the present disclosure is to provide a transparent display device that can achieve environmental / social / governance (ESG) by reducing the occurrence of greenhouse gases that may occur due to a manufacturing process.

[0008] In addition to the above-mentioned objects of the present disclosure, those skilled in the art will clearly understand other objects and features of the present disclosure from the following description of the present disclosure.

[0009] According to one aspect of the present disclosure, the above and other purposes can be achieved by providing a transparent display device, which includes: a display area in which a plurality of sub-pixels are arranged to display an image; a plurality of transmission areas, which are arranged within the display area and transmit external light; a first non-transmission area, which is arranged between the transmission areas arranged adjacent to each other along a first direction and does not transmit external light; a second non-transmission area, which is arranged between the transmission areas arranged adjacent to each other along a second direction and does not transmit external light; a first circuit portion, which is arranged in the first non-transmission area to drive the sub-pixels arranged in the first non-transmission area; and a second circuit portion, which is arranged in the second non-transmission area to drive the sub-pixels arranged in the second non-transmission area.

[0010] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the inventive concepts as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of this application. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. The above and other objects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a schematic perspective view showing a transparent display device according to an exemplary embodiment of the present disclosure;

[0013] Figure 2 is a schematic plan view showing a transparent display panel according to an exemplary embodiment of the present disclosure;

[0014] Figure 3 It is shown in Figure 2 A schematic diagram of an exemplary embodiment of a pixel arranged in area A;

[0015] Figure 4 It shows Figure 3 A circuit diagram of an example of a pixel element of a sub-pixel shown;

[0016] Figure 5 is a schematic diagram showing an example in which a plurality of signal lines and a plurality of circuit elements are provided;

[0017] Figure 6 is shown along Figure 5 An example cross-sectional view of the region along line II';

[0018] Figure 7 is a view showing a crosstalk defect;

[0019] Figure 8 is a view showing an example of a switch connection line and a sense connection line;

[0020] Figure 9 is shown along Figure 8 An example cross-sectional view of the region of line II-II'; and

[0021] Figure 10 is shown along Figure 8 An example cross-sectional view of a region taken along line III-III'.

[0022] Throughout the drawings and detailed description, unless otherwise described, the same drawing reference numerals should be understood to refer to the same elements, features, and structures. The relative sizes and descriptions of these elements may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0023] Reference will now be made in detail to embodiments of the present disclosure, examples of which may be shown in the accompanying drawings. In the following description, detailed descriptions of known functions or configurations associated with this document will be omitted when it is determined that such detailed descriptions unnecessarily obscure the main points of the inventive concept. The described progression of processing steps and / or operations are examples; however, the order of the steps and / or operations is not limited to the order set forth herein and may be changed as is known in the art, except for steps and / or operations that must occur in a specific order. The names of the various elements used in the following description may have been selected solely for ease of writing the specification and may therefore differ from the names used in the actual product.

[0024] The advantages and features of the present disclosure and their implementation methods will be clarified by the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Instead, these embodiments are provided to make the present disclosure thorough and complete and to fully convey the scope of the present disclosure to those skilled in the art.

[0025] The shapes (e.g., size, length, width, height, thickness, position, radius, diameter, and area), ratios, angles, and quantities disclosed in the drawings for describing the embodiments of the present disclosure are merely examples, and therefore, the present disclosure is not limited to the details shown. The same reference numerals denote the same elements throughout the disclosure. In the following description, when a detailed description of a related known function or configuration is determined to unnecessarily obscure the main points of the present disclosure, the detailed description will be omitted. In the case of using "including," "having," and "comprising" described in the present disclosure, another part may be added unless "only to" is used. Unless otherwise specified, terms in the singular may include plural forms.

[0026] The word "exemplary" is used to mean serving as an example or illustration. Each aspect is an exemplary aspect. "Implementation," "example," "aspect," etc. should not be construed as preferred or advantageous over other implementations. Unless otherwise specified, implementations, examples, exemplary implementations, aspects, etc. may refer to one or more implementations, one or more examples, one or more exemplary implementations, one or more aspects, etc. Furthermore, the term "may" encompasses all meanings of the term "can."

[0027] The term "or" means "inclusive or" rather than "exclusive or." That is, unless otherwise specified or clear from the context, the statement "x uses a or b" means any of the natural inclusive permutations. For example, "a or b" can mean "a," "b," or "a and b." For example, "a, b, or c" can mean "a," "b," "c," "a and b," "b and c," "a and c," or "a, b, and c."

[0028] When explaining an element, even if not explicitly described, the element is to be interpreted as including a margin of error.Any implementation described herein as "example" is not necessarily to be construed as preferred or advantageous over other implementations.

[0029] When describing a positional relationship, for example, when the positional relationship is described as "on," "above," "below," and "beside," one or more parts may be disposed between two other parts unless "just" or "directly" is used.

[0030] Terms such as "below," "lower," "above," "upper," etc. may be used herein to describe the relationship between elements as shown in the drawings. It should be understood that these terms are spatially relative and based on the orientation depicted in the drawings.

[0031] When describing a temporal relationship, for example, when a time sequence is described as "after," "subsequently," "next," and "before," discontinuous cases may be included unless "just" or "directly" is used.

[0032] It should be understood that although the terms "first," "second," "A," "B," "(a)," and "(b)" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of this disclosure.

[0033] It should be understood that the term "at least one" includes all combinations related to any one item. For example, "at least one of the first element, the second element, and the third element" can include all combinations of two or more elements selected from the first element, the second element, and the third element, as well as each of the first element, the second element, and the third element. In addition, the term "may" fully encompasses the full meaning and coverage of the term "can."

[0034] As will be fully understood by those skilled in the art, the features of the various embodiments of the present disclosure may be coupled or combined with each other in part or in whole, and may interoperate and be technically driven in various ways. The embodiments of the present disclosure may be implemented independently of each other, or may be implemented together in a mutually dependent relationship.

[0035] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by those skilled in the art to which the exemplary embodiments belong. It should also be understood that terms (e.g., terms defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, for example, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein. For example, as will be understood by those skilled in the art, the term "component" or "unit" may apply to, for example, a separate circuit or structure, an integrated circuit, a computing block of a circuit device, or any structure configured to perform the described function.

[0036] Hereinafter, preferred embodiments of the transparent display device according to the present disclosure will be described in detail with reference to the accompanying drawings. Throughout the drawings, the same reference numerals will be used to designate the same or similar components whenever possible. Furthermore, in the following description, if a detailed description of a related known technology is determined to unnecessarily obscure the subject matter of the present disclosure, such detailed description will be omitted.

[0037] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. All components of each display device according to all embodiments of the present disclosure are operatively coupled and configured.

[0038] Figure 1 is a schematic perspective view illustrating a transparent display device according to an exemplary embodiment of the present disclosure. Figure 2 is a schematic plan view illustrating a transparent display panel according to an exemplary embodiment of the present disclosure.

[0039] Hereinafter, the X-axis represents a direction parallel to the gate line, the Y-axis represents a direction parallel to the data line, and the Z-axis represents a height direction of the transparent display device 100 .

[0040] Although the transparent display device 100 according to an exemplary embodiment of the present disclosure will be described as being implemented as an organic light emitting display (OLED), it may also be implemented as a liquid crystal display (LCD), a plasma display panel (PDP), a quantum dot light emitting display (QLED), a light emitting display (LED), a micro LED display, or an electrophoretic display, etc.

[0041] Reference Figure 1 and Figure 2, a transparent display device 100 according to an exemplary embodiment of the present disclosure may include a transparent display panel 110 , a source driver integrated circuit (hereinafter referred to as “IC”) 210 , a flexible film 220 , a circuit board 230 , and a timing controller 240 .

[0042] The transparent display panel 110 includes a first substrate 111 and a second substrate 112 facing each other. The second substrate 112 may be an encapsulation substrate. The first substrate 111 may be, but is not limited to, a plastic film, a glass substrate, or a silicon wafer substrate formed using a semiconductor process. As an example, the first substrate 111 may be a rigid substrate or a flexible substrate. The second substrate 112 may be a plastic film, a glass substrate, or an encapsulation film. The first substrate 111 and the second substrate 112 may be formed of transparent or opaque materials.

[0043] The transparent display panel 110 may be divided into a display area DA (or active area) in which pixels P are formed to display an image and a non-display area NDA (or inactive area) not used to display an image.

[0044] The first signal line SL1, the second signal line SL2, and the pixels P may be disposed in the display area DA, and a pad area PA where pads are disposed and at least one scan driver 205 may be disposed in the non-display area NDA.

[0045] The first signal line SL1 may extend along the second direction (e.g., the Y-axis direction) and may intersect the second signal line SL2 in the display area DA. The second signal line SL2 may extend along the first direction (or the X-axis direction). Pixels may be provided in an area where the first signal line SL1 is provided, an area where the second signal line SL2 is provided, or an area where the first signal line SL1 and the second signal line SL2 intersect each other, and may emit predetermined light to display an image.

[0046] A plurality of pads may be provided in the pad area PA. As an example, the size of the first substrate 111 may be larger than the size of the second substrate 112, and thus a portion of the first substrate 111 may be exposed without being covered by the second substrate 112, but the present invention is not limited thereto. Pads such as power pads and data pads may be provided in the portion of the first substrate 111 that is exposed and not covered by the second substrate 112.

[0047] The scan driver 205 is connected to the scan line to provide a scan signal. In the gate-in-panel (GIP) mode, the scan driver 205 can be formed in the non-display area NDA outside one or both sides of the display area DA of the transparent display panel 110. Alternatively, the scan driver 205 can be manufactured as a driver chip, encapsulated on a flexible film, and attached to the non-display area NDA outside one or both sides of the display area DA of the transparent display panel 110 in a tape automated bonding (TAB) mode, or can be attached to the non-display area NDA using a chip on glass (COG) or chip on board (COP) method, or can be implemented using a chip on film (COF) method and connected to the transparent display panel 110, but is not limited thereto.

[0048] The source driver IC 210 receives digital video data and a data control signal from the timing controller 240. The source driver IC 210 converts the digital video data into an analog data voltage according to the data control signal and supplies the analog data voltage to the data line. When the source driver IC 210 is manufactured as a driver chip, the source driver IC 210 can be packaged on the flexible film 220 using a chip on film (COF) mode or a chip on plastic (COP) mode, but is not limited thereto.

[0049] Wires for connecting the pads to the source driver IC 210 and wires for connecting the pads to the circuit board 230 may be formed in the flexible film 220. The flexible film 220 is attached to the pads, for example, by using an anisotropic conductive film, so that the pads and the wires of the flexible film 220 can be connected to each other.

[0050] The circuit board 230 may be attached to the flexible film 220. A plurality of circuits implemented with a driving chip may be packaged on the circuit board 230. For example, the timing controller 240 may be packaged on the circuit board 230. The circuit board 230 may be a printed circuit board or a flexible printed circuit board.

[0051] The timing controller 240 receives digital video data and timing signals from an external system board (not shown). Based on the timing signals, the timing controller 240 generates a scan control signal for controlling the operation timing of the scan driver and a data control signal for controlling the source driver IC 210. The timing controller 240 provides the scan control signal to the scan driver 205 and provides the data control signal to the source driver IC 210.

[0052] Figure 3 It is shown in Figure 2 A schematic diagram of an exemplary embodiment of pixels arranged in region A, Figure 4 It shows Figure 3 A circuit diagram of an example of a pixel element of a sub-pixel is shown, Figure 5is a schematic diagram showing an example in which a plurality of signal lines and a plurality of circuit elements are provided, and Figure 6 is shown along Figure 5 An example cross-sectional view of a region taken along line II'.

[0053] The transparent display panel 110 according to an exemplary embodiment of the present disclosure may be divided into a display area DA and a non-display area NDA ( Figure 2 ), pixels P are formed in the display area DA to display images, and the non-display area DA is not used to display images.

[0054] like Figure 3 As shown, the display area DA may include a first area NTA having a plurality of sub-pixels SP1, SP2, SP3, and SP4, and a second area TA having no sub-pixels SP1, SP2, SP3, and SP4. The first area NTA may be a non-transmissive area that does not transmit most of the light incident from the outside. The second area TA may be a transmissive area through which most of the light incident from the outside passes. For example, the transmissive area TA may be an area having a transmittance greater than α%, and the non-transmissive area NTA may be an area having a transmittance less than β%. In this case, α may be a value greater than β. Due to the presence of the transmissive area TA, a user can view an object or background located on the rear surface of the transparent display panel 110.

[0055] The non-transmission area NTA may include first and second non-transmission areas NTA1 and NTA2 , and a plurality of pixels P and a plurality of first and second signal lines SL1 and SL2 for supplying signals to each of the plurality of pixels P may be disposed in the non-transmission area NTA.

[0056] As an example, Figure 3As shown, the first non-transmission area NTA1 may be disposed between the transmission areas TA disposed adjacent to each other along a first direction (e.g., the X-axis direction). The first non-transmission area NTA1 may extend in a second direction (e.g., the Y-axis direction) between the transmission areas TA disposed adjacent to each other along the first direction (e.g., the X-axis direction) and may be disposed so as to overlap at least a portion of the emission areas EA1, EA2, EA3, and EA4. A plurality of first non-transmission areas NTA1 may be disposed so as to be spaced apart from each other in the transparent display panel 110, and the transmission area TA may be disposed between two adjacent first non-transmission areas NTA1. Embodiments are not limited thereto. As an example, the first non-transmission area NTA1 may be disposed between the transmission areas TA disposed adjacent to each other along a second direction (e.g., the Y-axis direction) or along a direction other than the first and second directions. Furthermore, although the plurality of sub-pixels SP1, SP2, SP3, and SP4 are arranged in a row along the second direction (e.g., the Y-axis direction) in the first non-transmission area NTA1, embodiments are not limited thereto. As an example, the plurality of sub-pixels SP1, SP2, SP3, and SP4 may be arranged in a row along the first direction (e.g., the X-axis direction) or along a direction other than the first and second directions in the first non-transmission area NTA1. As an example, the plurality of sub-pixels SP1, SP2, SP3, and SP4 may be arranged in two or more rows along the first direction or the second direction or in a direction other than the first and second directions in the first non-transmission area NTA1. As an example, two or more sub-pixels may be arranged in the first non-transmission area NTA1 in one pixel, but are not limited thereto.

[0057] like Figure 3 As shown, the second non-transmission area NTA2 may be disposed between the transmission areas TA disposed adjacent to each other along the second direction (e.g., the Y-axis direction). The second non-transmission area NTA2 may extend in the first direction (e.g., the X-axis direction) between the transmission areas TA disposed adjacent to each other along the second direction (e.g., the Y-axis direction), and may be disposed to overlap at least a portion of the light-emitting areas EA1, EA2, EA3, and EA4. A plurality of second non-transmission areas NTA2 may be disposed to be spaced apart from each other in the transparent display panel 110, and the transmission area TA may be disposed between two adjacent second non-transmission areas NTA2.

[0058] As an example, the transmission area TA may be surrounded by two first non-transmission areas NTA1 and two second non-transmission areas NTA2 , but is not limited thereto.

[0059] A plurality of pixels P may be disposed in the first non-transmission area NTA1 and the second non-transmission area NTA2. Each pixel P may include at least two sub-pixels. For example, each pixel P may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3, but is not limited thereto. Each pixel P may also include a fourth sub-pixel SP4.

[0060] The first subpixel SP1 may include a first light emitting area EA1 that emits light of a first color, and the second subpixel SP2 may include a second light emitting area EA2 that emits light of a second color. The third subpixel SP3 may include a third light emitting area EA3 that emits light of a third color, and the fourth subpixel SP4 may include a fourth light emitting area EA4 that emits light of a fourth color. As an example, the first to fourth colors may be different from each other, or at least two of the first to fourth colors may be the same color.

[0061] The first to fourth light-emitting areas EA1, EA2, EA3, and EA4 can emit light of different colors. For example, the first light-emitting area EA1 can emit red light, and the second light-emitting area EA2 can emit green light. The third light-emitting area EA3 can emit blue light, and the fourth light-emitting area EA4 can emit white light. However, the present disclosure is not limited to the above examples. In addition, various modifications can be made to the arrangement order of the sub-pixels SP1, SP2, SP3, and SP4.

[0062] A plurality of sub-pixels SP1 , SP2 , SP3 , and SP4 may be disposed in the first and second non-transmission areas NTA1 and NTA2 to display an image.

[0063] like Figure 4 As shown, each of the plurality of sub-pixels SP1, SP2, SP3, and SP4 may include a light-emitting element ED for emitting light and a circuit element. Specifically, each of the plurality of sub-pixels SP1, SP2, SP3, and SP4 may include a circuit element having a 3T (transistor) 1C (capacitor) structure and a light-emitting element ED. The 3T (transistor) 1C (capacitor) structure includes a switching transistor SWT, a sensing transistor SET, a driving transistor DT, and a capacitor Cst, but is not limited thereto. Each of the sub-pixels SP1, SP2, SP3, and SP4 may further include a compensation circuit, and in this case, may have various structures such as 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, and 7T2C.

[0064] Each of the transistors DT, SWT, and SET of each of the sub-pixels SP1, SP2, SP3, and SP4 may include a gate, a source, and a drain. Since the source and drain are not fixed but can change according to the voltage applied to the gate and the direction of the current, one of the source and drain can be represented as a first electrode and the other can be represented as a second electrode. The transistors DT, SWT, and SET of each of the sub-pixels SP1, SP2, SP3, and SP4 can use at least one of a polycrystalline silicon semiconductor, an amorphous silicon semiconductor, a compound semiconductor, an organic material, or an oxide semiconductor, but are not limited thereto. The transistors DT, SWT, and SET can be P-type transistors or N-type transistors, or P-type transistors and N-type transistors can be used interchangeably.

[0065] The switching transistor SWT can be used to provide a data voltage Vdata provided from the data line DL to the driving transistor DT. Specifically, the switching transistor SWT can charge the capacitor Cst with the data voltage Vdata provided from the data line DL. To this end, the switching transistor SWT can have a gate connected to the scan line SCANL and a first electrode connected to the data line DL. In addition, the first switching transistor SWT can have a second electrode connected to one end of the capacitor Cst and the gate of the driving transistor DT.

[0066] The switching transistor SWT may be turned on in response to a scan signal Scan applied through the scan line SCANL. When the switching transistor SWT is turned on, a data voltage Vdata applied through the data line DL may be transmitted to one end of the capacitor Cst.

[0067] The sensing transistor SET can be used to provide a reference voltage Vref provided from the reference line REFL to the driving transistor DT. Specifically, the sensing transistor SET can have a gate connected to the scan line SCANL and a first electrode connected to the reference line REFL. In addition, the sensing transistor SET can have a second electrode connected to the first electrode of the driving transistor DT and the other end of the capacitor Cst.

[0068] The sensing transistor SET can be turned on in response to a scan signal Scan applied through a scan line SCANL. When the sensing transistor SET is turned on, a reference voltage Vref (or initialization voltage) applied through a reference line REFL can be transmitted to the other end of the capacitor Cst. In addition, the reference voltage Vref can be applied to the first electrode of the driving transistor DT. Although the gate of the sensing transistor SET and the gate of the switching transistor SWT are shown to be connected to the same scan line SCANL, so that the sensing transistor SET and the switching transistor SWT can be turned on in response to the same scan signal Scan, the embodiment is not limited thereto. As an example, the gate of the sensing transistor SET and the gate of the switching transistor SWT can be connected to different scan lines so that the sensing transistor SET and the switching transistor SWT can be independently controlled, but it is not limited thereto.

[0069] The capacitor Cst can be used to maintain the data voltage Vdata supplied to the driving transistor DT during a specific period (e.g., one frame). Specifically, the capacitor Cst can have a first electrode connected to the gate of the driving transistor DT and a second electrode connected to the first electrode of the driving transistor DT. The capacitor Cst can charge a driving voltage Vgs corresponding to the data voltage Vdata transmitted through the switching transistor SWT and supply the charged driving voltage Vgs to the driving transistor DT.

[0070] The driving transistor DT may be configured to generate a driving current Ids based on a first power source EVDD supplied from a pixel power source line VDDL and supply the driving current Ids to the anode of the light-emitting element ED. The driving transistor DT may have a gate electrode connected to one end of the capacitor Cst and a second electrode connected to the pixel power source line VDDL. The driving transistor DT may also have a first electrode connected to the anode of the light-emitting element ED.

[0071] The driving transistor DT can be turned on according to the driving voltage Vgs charged in the capacitor Cst. When the driving transistor DT is turned on, the first power EVDD applied through the pixel power line VDDL can be transmitted to the anode of the light-emitting element ED. The driving transistor DT can control the luminous intensity of the light-emitting element ED by controlling the driving current Ids according to the driving voltage Vgs charged in the capacitor Cst.

[0072] The light-emitting element ED may include an anode connected to the driving transistor DT, a cathode receiving a second power supply EVSS from a common power supply line VSSL, and a light-emitting layer located between the anode and the cathode. As an example, the anode is an independent electrode for each light-emitting element, but the cathode may be a common electrode shared by at least some or all of the light-emitting elements. The embodiment is not limited to this. As an example, the cathode may also be an independent electrode for each light-emitting element. When a driving current Ids is provided from the driving transistor DT, electrons from the cathode may be injected into the light-emitting layer, and holes from the anode may be injected into the light-emitting layer, so that the light-emitting element ED can allow the fluorescent or phosphorescent material to emit light through the recombination of electrons and holes in the light-emitting layer, thereby generating light with a brightness proportional to the current value of the driving current.

[0073] An anode of the light emitting element ED may be connected to the first electrode of the driving transistor DT, and a cathode thereof may be connected to the common power line VSSL. The light emitting element ED may emit light corresponding to the driving current Ids generated by the driving transistor DT.

[0074] As an example, in the transparent display panel 110, Figure 4 The circuit elements DT, SWT, SET and Cst and the plurality of signal lines DL, VDDL, VSSL, REFL and SCANL shown may be arranged to overlap with the light emitting areas EA1, EA2, EA3 and EA4 (see FIG. Figure 3 ), in order to increase the aperture ratio, but not limited thereto.

[0075] Reference Figure 5 , the first signal line SL1 may be disposed in the first non-transmission area NTA1. The first signal line SL1 may extend along the second direction (eg, the Y-axis direction) in the first non-transmission area NTA1.

[0076] The first signal line SL1 may include a plurality of lines, and in this case, one first signal line SL1 may represent a signal line group formed by the plurality of lines. For example, one first signal line SL1 may represent a signal line group formed by four data lines DL1, DL2, DL3, and DL4, a pixel power line VDDL, a reference line REFL, and a common power line VSSL.

[0077] The first signal line SL1 may include, for example, at least one of a pixel power line VDDL, a common power line VSSL, a reference line REFL, or a data line DL.

[0078] The pixel power line VDDL may supply a first power source to the driving transistor DT of each of the sub-pixels SP1 , SP2 , SP3 , and SP4 disposed in the first and second non-transmission areas NTA1 and NTA2 .

[0079] The common power line VSSL may supply a second power source to cathode electrodes of the sub-pixels SP1, SP2, SP3, and SP4 disposed in the first and second non-transmission areas NTA1 and NTA2. In this case, the second power source may be a common power source commonly supplied to the sub-pixels SP1, SP2, SP3, and SP4.

[0080] The reference line REFL can provide an initialization voltage (or reference voltage) to the driving transistor DT of each of the sub-pixels SP1, SP2, SP3, and SP4 arranged in the first non-transmission area NTA1 and the second non-transmission area NTA2. As an example, the reference line REFL can be arranged between the multiple data lines DL1, DL2, DL3, and DL4. For example, the reference line REFL can be arranged at the center of the multiple data lines DL1, DL2, DL3, and DL4, for example, between the second data line DL2 and the third data line DL3. Embodiments are not limited to this. As an example, the reference line REFL can be arranged between any one of the multiple data lines DL1, DL2, DL3, and DL4 and the remaining data lines in the multiple data lines DL1, DL2, DL3, and DL4. As an example, the reference line REFL can be arranged on one side of all the multiple data lines DL1, DL2, DL3, and DL4.

[0081] Each of the data lines DL1, DL2, DL3, and DL4 may provide a data voltage to each of the sub-pixels SP1, SP2, SP3, and SP4 disposed in the first non-transmission area NTA1 and the second non-transmission area NTA2. For example, the first data line DL1 may provide a first data voltage to the first sub-pixel SP1 disposed in the first non-transmission area NTA1, the second data line DL2 may provide a second data voltage to the second sub-pixel SP2 disposed in the first non-transmission area NTA1, the third data line DL3 may provide a third data voltage to the third sub-pixel SP3 disposed in the first non-transmission area NTA1, and the fourth data line DL4 may provide a fourth data voltage to the fourth sub-pixel SP4 disposed in the second non-transmission area NTA2.

[0082] The second signal line SL2 may be disposed in the second non-transmission area NTA2. The second signal line SL2 may extend in the first direction (eg, X-axis direction) in the second non-transmission area NTA2.

[0083] The second signal line SL2 may include a plurality of lines, and in this case, one second signal line SL2 may represent a signal line group formed of the plurality of lines.

[0084] The second signal line SL2 may include, for example, a scan line SCANL. The scan line SCANL may provide a scan signal to the sub-pixels SP1, SP2, SP3, and SP4 disposed in the first and second non-transmission areas NTA1 and NTA2.

[0085] The circuit elements DT, SWT, SET, and Cst for the plurality of sub-pixels SP1, SP2, SP3, and SP4 may be divided into a first circuit portion C1 disposed in the first non-transmission area NTA1 and a second circuit portion C2 disposed in the second non-transmission area NTA2.

[0086] The first circuit portion C1 may include a plurality of circuit elements for driving each of the plurality of sub-pixels disposed in the first non-transmission area NTA1. Figure 3 As shown, three sub-pixels SP1, SP2, and SP3 may be disposed in the first non-transmission area NTA1. Figure 5 As shown, the first circuit portion C1 may include three circuit elements CE1, CE2, and CE3 for driving the three sub-pixels SP1, SP2, and SP3, respectively. More specifically, the first circuit portion C1 may include a first circuit element CE1 for driving the first sub-pixel SP1, a second circuit element CE2 for driving the second sub-pixel SP2, and a third circuit element CE3 for driving the third sub-pixel SP3, but the present disclosure is not limited thereto. For ease of description, the following description will be based on the first circuit portion C1 including the first to third circuit elements CE1, CE2, and CE3 for driving the first to third sub-pixels SP1, SP2, and SP3, respectively.

[0087] The first circuit section C1 may be disposed on one side of the first signal line SL1. In the transparent display panel 110 according to an exemplary embodiment of the present disclosure, the multiple circuit elements CE1, CE2, and CE3 included in the first circuit section C1 may be disposed so as to be concentrated on one side of the first signal line SL1. As an example, the first signal line region in which the first signal line SL1 is disposed may be disposed between the first circuit section C1 and the transmissive area TA. As an example, the first circuit section C1 may be disposed in an edge region on one side of the sub-pixels SP1, SP2, and SP3. The first circuit section C1 may be formed along an edge region on one side of the first non-transmissive area NTA1. Specifically, the first circuit section C1 may be formed along an edge region on one side of the first non-transmissive area NTA1. Although the first circuit section C1 is shown as being disposed on the left side of the first signal line SL1, embodiments are not limited thereto. As an example, the first circuit section C1 may be disposed on the right side of the first signal line SL1, or the first circuit section C1 may be disposed between signal lines within the first signal line SL1, but the present invention is not limited thereto. As another example, the first circuit portion C1 may at least partially overlap the first signal line SL1 , but is not limited thereto.

[0088] The circuit elements may include a switch transistor SWT, a sense transistor SET (see Figure 4 ), a driving transistor DT and a capacitor Cst, and may be provided for each of the sub-pixels SP1, SP2 and SP3. The first circuit element CE1 connected to the first sub-pixel SP1 may include a first driving transistor DT1, a first switching transistor SWT1, a first sensing transistor SET (see Figure 4 ) and a first capacitor Cst1. The second circuit element CE2 connected to the second sub-pixel SP2 may include a second driving transistor DT2, a second switching transistor SWT2, a second sensing transistor SET (see Figure 4 ) and a second capacitor Cst2. The third circuit element CE3 connected to the third sub-pixel SP3 may include a third driving transistor DT3, a third switching transistor SWT3, a third sensing transistor SET (see Figure 4 and a third capacitor Cst3.

[0089] In the transparent display panel 110 according to an exemplary embodiment of the present disclosure, the first signal line SL1 and the first circuit portion C1 may be arranged so as not to overlap each other, thereby reducing or minimizing the size of the area where the plurality of signal lines DL, VDDL, VSSL, and REFL included in the first circuit portion C1 and the circuit elements CE1, CE2, and CE3 included in the first circuit portion C1 are formed. When the circuit elements CE1, CE2, and CE3 are arranged between the plurality of signal lines DL, VDDL, VSSL, and REFL included in one first signal line SL1, the circuit elements CE1, CE2, and CE3 may require space to ensure a minimum gap distance from the plurality of signal lines DL, VDDL, VSSL, and REFL on at least one or each of the upper side, lower side, left side, and right side. For this reason, the size of the area where the plurality of signal lines DL, VDDL, VSSL, and REFL and the circuit elements CE1, CE2, and CE3 are formed may increase.

[0090] In the transparent display panel 110 according to an exemplary embodiment of the present disclosure, the circuit elements CE1, CE2, and CE3 may be disposed to be concentrated on one side of the first signal line SL1, so that the space for separating the circuit elements CE1, CE2, and CE3 from the plurality of signal lines DL, VDDL, VSSL, and REFL may be reduced or minimized.

[0091] like Figure 3 As shown, the first to third sub-pixels SP1, SP2, and SP3 may be arranged in a row along the second direction (e.g., the Y-axis direction) in the first non-transmission area NTA1. The first to third circuit elements CE1, CE2, and CE3 for each of the first to third sub-pixels SP1, SP2, and SP3 may be arranged along one edge region of each of the plurality of sub-pixels SP1, SP2, and SP3 in the second direction (e.g., the Y-axis direction). For example, Figure 5 As shown, the first to third circuit elements CE1, CE2, and CE3 may be arranged in a row along the second direction (e.g., the Y-axis direction). In addition, the switching transistors SWT1, SWT2, and SWT3, the driving transistors DT1, DT2, and DT3, and the capacitors Cst1, Cst2, and Cst3 included in the first to third circuit elements CE1, CE2, and CE3, respectively, may also be arranged in a row along the second direction (e.g., the Y-axis direction).

[0092] The second circuit portion C2 may include at least one circuit element for driving at least one sub-pixel disposed in the second non-transmission area NTA2. Figure 3 As shown, one sub-pixel SP4 may be disposed in the second non-transmission area NTA2. Figure 5As shown, the second circuit portion C2 may include a circuit element CE4 for driving a sub-pixel SP4. Specifically, the second circuit portion C2 may include a fourth circuit element CE4 for driving a fourth sub-pixel SP4, but the present invention is not limited thereto. For ease of description, the following description will be based on the second circuit portion C2 including the fourth circuit element CE4 for driving the fourth sub-pixel SP4.

[0093] The second circuit portion C2 may be provided on one side of the second signal line SL2. In the transparent display panel 110 according to an exemplary embodiment of the present disclosure, the circuit element CE4 included in the second circuit portion C2 may be provided on one side of the second signal line SL2. The second circuit portion C2 may be provided between the second signal line region where the second signal line SL2 is provided and the transmission region TA. The second circuit portion C2 may be provided in an edge region on one side of the sub-pixel SP4. The second circuit portion C2 may be formed along an edge region on one side of the second non-transmission region NTA2. Specifically, the second circuit portion C2 may be formed along an edge region on one side of the second non-transmission region NTA2. Although the second circuit portion C2 is shown as being provided on the upper side of the second signal line SL2, the embodiment is not limited thereto. As an example, the second circuit portion C2 may be provided on the lower side of the second signal line SL2.

[0094] The fourth circuit element CE4 connected to the fourth sub-pixel SP4 may include a fourth driving transistor DT4, a fourth switching transistor SWT4, a fourth sensing transistor SET (see FIG. Figure 4 ) and a fourth capacitor Cst4.

[0095] In the transparent display panel 110 according to an exemplary embodiment of the present disclosure, the second signal line SL2 and the second circuit portion C2 can be arranged not to overlap each other, thereby reducing or minimizing the size of the area where the signal line SCANL included in the second signal line SL2 and the circuit element CE4 included in the second circuit portion C2 are formed.

[0096] like Figure 3 As shown, the fourth sub-pixel SP4 can be formed to be longer in the first direction (e.g., the X-axis direction) in the second non-transmission area NTA2. The fourth circuit element CE4 for the fourth sub-pixel SP4 can be arranged to be longer in the first direction (e.g., the X-axis direction) along an edge region of one side of the fourth sub-pixel SP4. For example, the fourth switching transistor SWT4, the fourth driving transistor DT4, and the fourth capacitor Cst4 included in the fourth circuit element CE4 can be arranged in a row along the first direction (e.g., the X-axis direction).

[0097] In the following, reference will be made to Figure 6 The switching transistor SWT, the driving transistor DT, and the capacitor Cst are described in more detail.

[0098] The switching transistor SWT, the driving transistor DT, and the capacitor Cst may be arranged in a row in an edge region of one side of at least one of the sub-pixels SP1, SP2, SP3, and SP4. Each of the driving transistors DT may include an active layer ACT1, a gate GE1, a source electrode SE1, and a drain electrode DE1, and the switching transistor SWT may include an active layer ACT2 and a gate GE2. The capacitor Cst may include a first capacitor electrode CstE1 and a second capacitor electrode CstE2. Although the switching transistor SWT and the driving transistor DT are shown as being disposed on the same layer and having similar structures, embodiments are not limited thereto. As an example, the switching transistor SWT and the driving transistor DT may be disposed on different layers and / or may have different structures.

[0099] More specifically, as an example, light shielding layers LS1 and LS2 and the first capacitor electrode CstE1 may be provided on the first substrate 111. The light shielding layer LS1 may be provided in a region where the driving transistor DT is formed to shield external light from incident on the active layer ACT1 of the driving transistor DT. Furthermore, the light shielding layer LS2 may be provided in a region where the switching transistor SWT is formed to shield external light from incident on the active layer ACT2 of the switching transistor SWT. Embodiments are not limited thereto. As an example, one or both of the light shielding layers LS1 and LS2 may be omitted or provided on different layers.

[0100] The first capacitor electrode CstE1 may be provided on the same layer as the light shielding layer LS. As an example, the first capacitor electrode CstE1 may or may not be provided between the light shielding layer LS1 provided in the region where the driving transistor DT is formed and the light shielding layer LS2 provided in the region where the switching transistor SWT is formed, but is not limited thereto.

[0101] At least one or each of the light-shielding layers LS1 and LS2 and the first capacitor electrode CstE1 may be formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or alloys thereof, but is not limited thereto.

[0102] The buffer layer BF may be provided on the light shielding layers LS1 and LS2. The buffer layer BF serves to protect the driving transistor DT, the switching transistor SWT, and the capacitor Cst, which are susceptible to moisture penetration, from impurities such as hydrogen and moisture penetrating through the first substrate 111, and may have a single-layer structure or a multi-layer structure including an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), and aluminum oxide (Al2O3). Figure 6As shown, the buffer layer BF may include not only the non-transmission area NTA but also the transmission area TA, but is not limited thereto. In another embodiment, the buffer layer BF may be provided only in the non-transmission area NTA and may not be provided in the transmission area TA.

[0103] As an example, the driving transistor DT, the switching transistor SWT and the second capacitor electrode CstE2 can be set on the buffer layer BF, but are not limited to this. As an example, the active layer ACT1 of the driving transistor DT and the active layer ACT2 of the switching transistor SWT can be set on the buffer layer BF, but are not limited to this. As an example, the active layer ACT1 of the driving transistor DT and the active layer ACT2 of the switching transistor SWT can be set on different layers. As an example, each of the active layer ACT1 of the driving transistor DT and the active layer ACT2 of the switching transistor SWT can be formed of a silicon-based semiconductor material or an oxide-based semiconductor material, but are not limited to this. As an example, each of the active layer ACT1 of the driving transistor DT and the active layer ACT2 of the switching transistor SWT can be formed of any other semiconductor material such as a compound semiconductor material, an organic semiconductor material, a germanium-based semiconductor material, etc. As an example, the active layer ACT1 of the driving transistor DT and the active layer ACT2 of the switching transistor SWT can be formed of the same material or different materials.

[0104] A gate insulating layer GI may be disposed on the active layer ACT1 of the driving transistor DT and the active layer ACT2 of the switching transistor SWT. Figure 6 As shown, the gate insulating layer GI may be formed to be patterned only in the region where the gate GE1 of the driving transistor DT, the gate GE2 of the switching transistor SWT, and the second capacitor electrode CstE2 are provided, but is not limited thereto. In another exemplary embodiment, the gate insulating layer GI may be formed to cover the active layer ACT1 of the driving transistor DT and the active layer ACT2 of the switching transistor SWT. The gate insulating layer GI may have a single-layer structure or a multi-layer structure including an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), and aluminum oxide (Al2O3), but is not limited thereto.

[0105] The gate electrode GE1 of the driving transistor DT, the gate electrode GE2 of the switching transistor SWT, and the second capacitor electrode CstE2 may be disposed on the gate insulating layer GI, or may be disposed on different layers. The gate electrode GE1 of the driving transistor DT, the gate electrode GE2 of the switching transistor SWT, and the second capacitor electrode CstE2 may be formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof, but is not limited thereto.

[0106] An interlayer insulating layer ILD may be provided on the gate electrode GE1 of the driving transistor DT, the gate electrode GE2 of the switching transistor SWT, and the second capacitor electrode CstE2. The interlayer insulating layer ILD may have a single-layer structure or a multi-layer structure including an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), and aluminum oxide (Al2O3), but is not limited thereto.

[0107] The source electrode SE1 and the drain electrode DE1 of the driving transistor DT may be disposed on the interlayer insulating layer ILD. The source electrode SE1 and the drain electrode DE1 of the driving transistor DT may be connected to the source region and the drain region of the active layer ACT1, respectively, via a first contact hole CH1 penetrating the interlayer insulating layer ILD. The source electrode SE1 and the drain electrode DE1 of the driving transistor DT may be formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof, but is not limited thereto.

[0108] At the same time, as an example, one of the source electrode SE1 and drain electrode DE1 of the driving transistor DT may be connected to the light shielding layer LS1 via a contact hole passing through the interlayer insulating layer ILD and the buffer layer BF. The light shielding layer LS1 may be electrically connected to one of the source electrode SE1 and drain electrode DE1 of the driving transistor DT, thereby not operating as a floating gate. When the light shielding layer LS1 is floating and not connected to other electrodes, the threshold voltage of the driving transistor DT may be changed by the floating light shielding layer LS1. In the transparent display panel 110 according to an exemplary embodiment of the present disclosure, the light shielding layer LS1 may be electrically connected to one of the source electrode SE1 and drain electrode DE1 of the driving transistor DT, thereby reducing or minimizing the change in the threshold voltage of the driving transistor DT. Embodiments are not limited to this. As an example, the light shielding layer LS1 may not be electrically connected to the source electrode SE1 or drain electrode DE1 of the driving transistor DT, but may be electrically connected to another electrode, signal line, or pad, or may be floating, but is not limited to this. As an example, the light shielding layer LS1 may be omitted depending on the design.

[0109] The insulating layer PAS may be disposed on the driving transistor DT, the switching transistor SWT, and the capacitor Cst. The insulating layer PAS may be disposed in the non-transmission area NTA and may not be disposed in at least a portion of the transmission area TA. As an example, the insulating layer PAS may include an opening area that overlaps with at least a portion or the entirety of the transmission area TA. The insulating layer PAS may reduce transparency by causing refraction of light when light is transmitted. Therefore, the transparent display panel 110 according to an exemplary embodiment of the present disclosure may increase transparency by removing a portion of the insulating layer PAS from the transmission area TA. The insulating layer PAS may have a single-layer structure or a multi-layer structure including an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), and aluminum oxide (Al2O3), but is not limited thereto.

[0110] A planarization layer PLN may be provided on the insulating layer PAS, which is used to planarize the step difference caused by the driving transistor DT, the switching transistor SWT, and the capacitor Cst. The planarization layer PLN may be provided in the non-transmission area NTA and may not be provided in at least a portion of the transmission area TA. As an example, the planarization layer PLN may include an opening area that overlaps with at least a portion or the entirety of the transmission area TA. The planarization layer PLN may reduce transparency by causing refraction of light when light is transmitted. Therefore, the transparent display panel 110 according to an exemplary embodiment of the present disclosure may increase transparency by removing a portion of the planarization layer PLN from the transmission area TA. The planarization layer PLN may be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin, but is not limited thereto.

[0111] The light emitting element ED including the first electrode 120 , the light emitting layer 130 , and the second electrode 140 and the bank BN may be disposed on the planarization layer PLN.

[0112] The first electrode 120 may be disposed in the non-transmission area NTA. The first electrode 120 may be disposed on the planarization layer PLN for each of the sub-pixels SP1, SP2, SP3, and SP4. The first electrodes 120 disposed for each of the sub-pixels SP1, SP2, SP3, and SP4 may be electrically insulated from each other by being spaced apart from each other.

[0113] The first electrode 120 may be electrically connected to the driving transistor DT. As an example, the first electrode 120 may be connected to one of the source SE1 and the drain DE1 of the driving transistor DT through a second contact hole CH2 passing through the planarization layer PLN and the insulating layer PAS.

[0114] The first electrode 120 may be formed of a conductive material. As an example, the first electrode 120 may be formed of a metal material. As an example, the first electrode 120 may be formed of a metal material with high reflectivity, such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an Ag alloy, a stacked structure of an Ag alloy and ITO (ITO / Ag alloy / ITO), a MoTi alloy, and a stacked structure of a MoTi alloy and ITO (ITO / MoTi alloy / ITO), but is not limited thereto. The Ag alloy may be an alloy of silver (Ag), palladium (Pd), copper (Cu), etc. The MoTi alloy may be an alloy of molybdenum (Mo) and titanium (Ti). The first electrode 120 may be the anode of the light-emitting element ED.

[0115] The bank BN may be provided on the planarization layer PLN in the non-transmission area NTA. By way of example, the bank BN may be formed to cover the edge of each of the first electrodes 120 and expose a portion of each of the first electrodes 120, but is not limited thereto. Thus, the bank BN can mitigate or prevent the degradation of luminous efficiency caused by current concentration at the ends of the first electrodes 120. Embodiments are not limited thereto. By way of example, the bank BN may be formed adjacent to and in contact with the edge of each of the first electrodes 120, but is not limited thereto.

[0116] The bank BN may define the emission area EA of each of the sub-pixels SP1, SP2, SP3, and SP4. The emission area EA of each of the sub-pixels SP1, SP2, SP3, and SP4 refers to a region where the first electrode 120, the light-emitting layer 130, and the second electrode 140 are sequentially stacked to emit light by combining holes from the first electrode 120 and electrons from the second electrode 140 in the light-emitting layer 130. In this case, the region where the bank BN is formed does not emit light, thereby becoming the non-emission area NEA, while the region where the bank BN is not formed and the first electrode 120 is exposed may become the emission area EA.

[0117] The bank BN may be provided in the non-transmission area NTA and may not be provided in at least a portion of the transmission area TA. That is, the bank BN may include an open area that overlaps at least a portion or the entirety of the transmission area TA. The bank BN may reduce transparency by causing light refraction when light is transmitted. Therefore, the transparent display panel 110 according to an exemplary embodiment of the present disclosure may increase transparency by removing a portion of the bank BN from the transmission area TA.

[0118] The bank BN may be formed of an organic layer such as acrylic resin, epoxy resin, phenol resin, polyamide resin, or polyimide resin, but is not limited thereto.

[0119] The light-emitting layer 130 may be disposed on the first electrode 120. For example, the light-emitting layer 130 may include a light-emitting material layer. For example, the light-emitting layer 130 may include a hole transport layer, a light-emitting material layer, and an electron transport layer. In this case, when a voltage is applied to the first electrode 120 and the second electrode 140, holes and electrons move through the hole transport layer and the electron transport layer, respectively, to the light-emitting layer and combine with each other in the light-emitting layer to emit light. For example, the light-emitting layer 130 may further include additional layers such as a hole injection layer and an electron injection layer.

[0120] In one exemplary embodiment, the light-emitting layer 130 may be a common layer commonly formed in the sub-pixels SP1, SP2, SP3, and SP4. In this case, the light-emitting layer may be a white light-emitting layer for emitting white light. In this case, the light-emitting layer 130 may be formed not only in the sub-pixels SP1, SP2, SP3, and SP4, but also in the non-light-emitting area NEA between the sub-pixels SP1, SP2, SP3, and SP4. The light-emitting layer 130 may be formed continuously between the sub-pixels SP1, SP2, SP3, and SP4. Furthermore, the light-emitting layer 130 may be provided in the transmission area TA and the non-light-emitting area NTA including the light-emitting area EA and the non-light-emitting area NEA, but is not limited thereto. As an example, the light-emitting layer 130 may be patterned only in the non-light-emitting area NTA including the light-emitting area EA and the non-light-emitting area NEA.

[0121] In another exemplary embodiment, the light-emitting material layer of the light-emitting layer 130 may be formed for each of the sub-pixels SP1, SP2, SP3, and SP4. For example, a red light-emitting layer for emitting red light may be formed in the first sub-pixel SP1, a green light-emitting layer for emitting green light may be formed in the second sub-pixel SP2, a blue light-emitting layer for emitting blue light may be formed in the third sub-pixel SP3, and a white light-emitting layer for emitting white light may be formed in the fourth sub-pixel SP4. In this case, the light-emitting material layer of the light-emitting layer 130 may not be formed in the transmission area TA. However, in addition to the light-emitting material layer, a hole injection layer HIL, a hole transport layer HTL, an electron transport layer ETL, and an electron injection layer EIL may be commonly formed in the sub-pixels SP1, SP2, SP3, and SP4, and may also be formed in the transmission area TA. Embodiments are not limited thereto. As an example, at least one or each of a hole injection layer HIL, a hole transport layer HTL, an electron transport layer ETL, and an electron injection layer EIL may be formed for each of the sub-pixels SP1, SP2, SP3, and SP4, but is not limited thereto.

[0122] The second electrode 140 may be provided on the light-emitting layer 130. The second electrode 140 may be a common layer commonly formed in the sub-pixels SP1, SP2, SP3, and SP4 to apply the same voltage. The second electrode 140 may be formed not only in the light-emitting area EA of the sub-pixels SP1, SP2, SP3, and SP4, but also in the non-light-emitting area NEA between the sub-pixels SP1, SP2, SP3, and SP4. The second electrode 140 may be continuously formed between the sub-pixels SP1, SP2, SP3, and SP4.

[0123] In addition, the second electrode 140 may be provided in the transmission area TA and the non-transmission area NTA including the emission area EA and the non-emission area NEA, but is not limited thereto. The second electrode 140 may be formed to be patterned only in the non-transmission area NTA including the emission area EA and the non-emission area NEA.

[0124] As an example, the second electrode 140 may be formed of a transparent conductive material (TCO) such as ITO or IZO that can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag), but is not limited thereto. As an example, when the second electrode 140 is formed of a semi-transmissive metal material, the light emitting efficiency can be improved by the microcavity. The second electrode 140 may be the cathode of the light emitting element ED.

[0125] The encapsulation layer 150 may be provided on the light-emitting element ED. The encapsulation layer 150 may be formed on the second electrode 140 to cover the second electrode 140. The encapsulation layer 150 is used to limit or prevent oxygen or moisture from penetrating into the light-emitting layer 130 and the second electrode 140. To this end, as an example, the encapsulation layer 150 may include at least one inorganic layer, and may also include at least one organic layer, but is not limited thereto.

[0126] The color filter CF may be provided on one surface of the second substrate 112 facing the first substrate 111. The color filter CF may be provided and formed to be patterned for each of the sub-pixels SP1, SP2, SP3, and SP4.

[0127] As an example, the color filter CF may include a first color filter, a second color filter, a third color filter, and a fourth color filter. The first color filter may be arranged to correspond to the emission area EA1 of the first sub-pixel SP1 and may be a red color filter for transmitting red light. The second color filter may be arranged to correspond to the emission area EA2 of the second sub-pixel SP2 and may be a green color filter for transmitting green light. The third color filter may be arranged to correspond to the emission area EA3 of the third sub-pixel SP3 and may be a blue color filter for transmitting blue light. The fourth color filter may be arranged to correspond to the emission area EA4 of the fourth sub-pixel SP4 and may be a transparent organic layer. As an example, the fourth color filter may be omitted according to the design.

[0128] Although not shown in the figure, a black matrix (not shown) can be provided between the color filters CF. A black matrix can be provided between the sub-pixels SP1, SP2, SP3, and SP4 to reduce or prevent color mixing between adjacent sub-pixels SP1, SP2, SP3, and SP4. In addition, the black matrix can reduce or prevent externally incident light from being reflected by multiple signal lines (e.g., scan lines, data lines, pixel power lines, common power lines, and reference lines) provided between the sub-pixels SP1, SP2, SP3, and SP4. For example, the black matrix can be omitted depending on the design.

[0129] In addition, as an example, a black matrix may be provided between the transmission area TA and the plurality of sub-pixels SP1, SP2, and SP3 to reduce or prevent light emitted from each of the plurality of sub-pixels SP1, SP2, and SP3 from moving to the transmission area TA. The black matrix may not be provided between a portion of the plurality of sub-pixels (e.g., the white sub-pixel) and the transmission area TA. When the fourth sub-pixel SP4 is a white sub-pixel for emitting white light, the white light generated by the fourth sub-pixel SP4 does not vary depending on the viewing angle. Therefore, since the black matrix is ​​not provided between the fourth sub-pixel SP4 and the transmission area TA, the transmittance can be improved and light loss caused by the black matrix can be reduced.

[0130] As an example, such a black matrix may include a light-absorbing material (eg, a black dye that absorbs all light in the visible wavelength band), but is not limited thereto.

[0131] The filler 160 may be provided between the first substrate 111 provided with the light-emitting element ED and the second substrate 112 provided with the color filter CF and the black matrix. In this case, a thermosetting resin or a UV curable resin may be used as the filler 160, and the filler 160 may be formed of an organic material having adhesive properties. In one exemplary embodiment, the filler 160 may include a hydrogen absorbing material, but is not limited thereto.

[0132] In the transparent display panel 110 according to an exemplary embodiment of the present disclosure, the circuit elements CE1, CE2, and CE3 can be arranged to be concentrated on one side of the first signal line SL1, thereby reducing or minimizing the space used to separate the circuit elements CE1, CE2, and CE3 from the plurality of signal lines DL, VDDL, VSSL, and REFL. Therefore, in the transparent display panel 110 according to an exemplary embodiment of the present disclosure, the size of the area where the plurality of signal lines DL, VDDL, VSSL, and REFL included in the first signal line SL1 and the circuit elements CE1, CE2, and CE3 included in the first circuit portion C1 are formed can be reduced or minimized. The transparent display panel 110 according to an exemplary embodiment of the present disclosure can reduce or minimize the width of the first non-transmissive area NTA1 along the first direction (e.g., the X-axis direction).

[0133] In addition, in the transparent display panel 110 according to an exemplary embodiment of the present disclosure, at least one of the plurality of circuit elements CE1, CE2, CE3, and CE4 may be disposed in the second non-transmission area NTA2. For example, in the transparent display panel 110, the fourth circuit element CE4 for the fourth sub-pixel SP4 may be disposed in the second non-transmission area NTA2.

[0134] Unlike the transparent display panel 110 according to an exemplary embodiment of the present disclosure, a structure in which the plurality of circuit elements CE1, CE2, CE3, and CE4 are all disposed in the first non-transmission area NTA1 may be considered. In this structure, since the plurality of signal lines DL, VDDL, VSSL, and REFL and the plurality of circuit elements CE1, CE2, CE3, and CE4 should be disposed in a limited space, the gap distance between the plurality of signal lines DL, VDDL, VSSL, and REFL and the plurality of circuit elements CE1, CE2, CE3, and CE4 is formed to be short, and thus parasitic capacitance may be generated therebetween and affect the same.

[0135] Furthermore, the capacitors Cst1, Cst2, Cst3, and Cst4 included in each of the plurality of circuit elements CE1, CE2, CE3, and CE4 may not have a sufficient area. As the area of ​​the capacitors Cst1, Cst2, Cst3, and Cst4 decreases, the driving voltage Vgs charged into the capacitors Cst1, Cst2, Cst3, and Cst4 may decrease, and thus the brightness may decrease. Figure 7 As shown, when the partial area A1 emits light with bright brightness, a crosstalk phenomenon may occur in which the upper area A21 and the lower area A22 disposed on the driving current path CP passing through the partial area A1 appear darker than the peripheral area A3.

[0136] In the transparent display panel 110 according to an exemplary embodiment of the present disclosure, at least one of the plurality of circuit elements CE1, CE2, CE3, and CE4 may be disposed in the second non-transmission area NTA2 to ensure the area of ​​the capacitors Cst1, Cst2, Cst3, and Cst4. For example, in the transparent display panel 110 according to an exemplary embodiment of the present disclosure, the fourth circuit element CE4 for the fourth subpixel SP4 may be disposed in the second non-transmission area NTA2. In addition, the first to third circuit elements CE1, CE2, and CE3 for the first to third subpixels SP1, SP2, and SP3 may be disposed in the first non-transmission area NTA1.

[0137] In the transparent display panel 110 according to an exemplary embodiment of the present disclosure, the fourth circuit element CE4 may be disposed in the second non-transmission area NTA2, thereby increasing the areas of the capacitors Cst1, Cst2, and Cst3 of the first to third circuit elements CE1, CE2, and CE3 disposed in the first non-transmission area NTA1. Therefore, the transparent display panel 110 according to an exemplary embodiment of the present disclosure can reduce or prevent a decrease in the luminance of the first to third sub-pixels SP1, SP2, and SP3.

[0138] Furthermore, in the transparent display panel 110 according to an exemplary embodiment of the present disclosure, the fourth capacitor Cst4 of the fourth circuit element CE4 disposed in the second non-transmissive area NTA2 may have a sufficient area. As an example, the fourth capacitor Cst4 of the fourth circuit element CE4 may have a larger formation area than the first to third capacitors Cst1, Cst2, and Cst3 of the first to third circuit elements CE1, CE2, and CE3. Embodiments are not limited thereto. As an example, the fourth capacitor Cst4 of the fourth circuit element CE4 may have a formation area equal to or smaller than the first to third capacitors Cst1, Cst2, and Cst3 of the first to third circuit elements CE1, CE2, and CE3.

[0139] The fourth subpixel SP4 connected to the fourth circuit element CE4 can be a white subpixel. Since the white subpixel is used to achieve brightness, the brightness reduction caused by the reduction in the capacitor area may be greater than that of a subpixel of another color, and may significantly affect the crosstalk phenomenon. In the transparent display panel 110 according to an exemplary embodiment of the present disclosure, the white subpixel can be arranged in the second non-transmission area NTA2, and the fourth circuit element CE4 connected to the white subpixel can also be arranged in the second non-transmission area NTA2 with relatively free space. Therefore, the transparent display panel 110 according to an exemplary embodiment of the present disclosure can fully ensure the area of ​​the fourth capacitor Cst4 included in the fourth circuit element CE4, thereby reducing or preventing the brightness reduction of the white subpixel. In addition, the transparent display panel 110 according to an exemplary embodiment of the present disclosure can improve crosstalk defects.

[0140] The transparent display panel 110 according to an exemplary embodiment of the present disclosure can reduce manufacturing process costs, shorten manufacturing process time, and also reduce production energy due to a reduced product defect rate. In addition, the transparent display panel 110 according to an exemplary embodiment of the present disclosure can reduce the generation of greenhouse gases that may occur due to the manufacturing process, thereby achieving environmental / social / governance (ESG).

[0141] In addition, in the transparent display panel 110 according to an exemplary embodiment of the present disclosure, the black matrix may not be provided between the white sub-pixel provided in the second non-transmission area NTA2 and the transmission area TA. Therefore, the transparent display panel 110 according to an exemplary embodiment of the present disclosure can reduce or minimize the width of the second non-transmission area NTA2 along the second direction (e.g., the Y-axis direction).

[0142] The transparent display panel 110 according to an exemplary embodiment of the present disclosure has an arrangement structure of the circuit elements CE1, CE2, CE3, and CE4 capable of reducing the sizes of the first and second non-transmission areas NTA1 and NTA2, thereby increasing the size of the transmission area TA and thereby improving light transmittance.

[0143] Figure 8 is a view showing an example of a switch connection line and a sense connection line, Figure 9 is shown along Figure 8 An example cross-sectional view of the region of line II-II', and Figure 10 is shown along Figure 8 An example cross-sectional view of a region taken along line III-III'.

[0144] In the transparent display panel 110 according to the present disclosure, capacitors Cst1, Cst2, Cst3, and Cst4 may be provided between switching transistors SWT1, SWT2, SWT3, and SWT4 and driving transistors DT1, DT2, DT3, and DT4 to ensure a maximum area of ​​the capacitors Cst1, Cst2, Cst3, and Cst4 of the plurality of circuit elements CE1, CE2, CE3, and CE4.

[0145] Reference Figure 5 In the first circuit element CE1, the first capacitor Cst1 may be disposed between the first switching transistor SWT1 and the first driving transistor DT1, such that the first driving transistor DT1, the first capacitor Cst1, and the first switching transistor SWT1 may be sequentially arranged in a row along the second direction (e.g., the Y-axis direction). In the second circuit element CE2, the second capacitor Cst2 may be disposed between the second switching transistor SWT2 and the second driving transistor DT2, such that the second switching transistor SWT2, the second capacitor Cst2, and the second driving transistor DT2 may be sequentially arranged in a row along the second direction (e.g., the Y-axis direction). In the third circuit element CE3, the third capacitor Cst3 may be disposed between the third switching transistor SWT3 and the third driving transistor DT3, such that the third switching transistor SWT3, the third capacitor Cst3, and the third driving transistor DT3 may be sequentially arranged in a row along the second direction (e.g., the Y-axis direction).

[0146] The circuit elements CE1, CE2, and CE3 included in the first circuit portion C1 may include two circuit elements spaced apart from each other and interposed between the scan line SCANL. As an example, the circuit elements CE1, CE2, and CE3 included in the first circuit portion C1 may include two circuit elements symmetrical to each other with respect to the scan line SCANL interposed therebetween, but are not limited thereto. For example, the first circuit element CE1 and the third circuit element CE3 included in the first circuit portion C1 may be arranged symmetrically with respect to the scan line SCANL. As an example, the arrangement order of the switching transistor, capacitor, and driver transistor included in each of the first circuit element CE1 and the third circuit element CE3 may be symmetrical with respect to the scan line SCANL. The first circuit element CE1 may be arranged on one side of the scan line SCANL (e.g., the first scan line) and may be arranged in the order of the first switching transistor SWT1, the first capacitor Cst1, and the first driver transistor DT1 based on the scan line SCANL. Specifically, in the first circuit element CE1, the first switching transistor SWT1, the first capacitor Cst1, and the first driver transistor DT1 may be arranged in sequence based on the scan line SCANL. The third circuit element CE3 can be arranged on the other side of the scan line SCANL (e.g., a second scan line adjacent to the first scan line), and can be provided in the order of a third switching transistor SWT3, a third capacitor Cst3, and a third driving transistor DT3 based on the scan line SCANL. Specifically, in the third circuit element CE3, the third switching transistor SWT3, the third capacitor Cst3, and the third driving transistor DT3 can be provided in the order of the scan line SCANL. In addition, in the second circuit element CE2, the second switching transistor SWT2, the second capacitor Cst2, and the second driving transistor DT2 can be provided in the order of the scan line SCANL (e.g., the second scan line).

[0147] At the same time, the first circuit element CE1 and the third circuit element CE3 may further include a first sensing transistor SET1 and a third sensing transistor SET3, respectively. Figure 8As shown, the first sensing transistor SET1 can be arranged adjacent to the first switching transistor SWT1. As an example, the first sensing transistor SET1 and the first switching transistor SWT1 can partially overlap with the scan line SCANL on one side of the scan line SCANL and can be arranged to be spaced apart from each other at a predetermined interval along the side of the scan line SCANL. The third sensing transistor SET3 and the third switching transistor SWT3 can partially overlap with the scan line SCANL on the other side of the scan line SCANL and can be arranged to be spaced apart from each other at a predetermined interval along the other side of the scan line SCANL. The first sensing transistor SET1 of the first circuit element CE1 can be arranged to face the third sensing transistor SET3 of the third circuit element CE3, and the first switching transistor SWT1 of the first circuit element CE1 can be arranged to face the third switching transistor SWT3 of the third circuit element CE3.

[0148] The fourth circuit element CE4 may include a fourth capacitor Cst4 between the fourth switching transistor SWT4 and the fourth driving transistor DT4. In this case, the fourth switching transistor SWT4 may be disposed closer to the fourth data line DL4 than the fourth driving transistor DT4 to receive the data voltage from the fourth data line DL4, but is not limited thereto.

[0149] At the same time, the fourth circuit element CE4 may further include a fourth sensing transistor SET4. Figure 8 As shown, the fourth sensing transistor SET4 can be disposed adjacent to the fourth switching transistor SWT4. The fourth sensing transistor SET4 and the fourth switching transistor SWT4 can partially overlap with the scan line SCANL and can be spaced apart from each other at a predetermined interval along the scan line SCANL. The fourth sensing transistor SET4 can be disposed closer to the reference line REFL than the fourth driving transistor DT4 to receive a reference voltage from the reference line REFL, but is not limited thereto.

[0150] The gap distance between the fourth drive transistor DT4 and the first signal line group including the fourth data line DL4 connected to the fourth switching transistor SWT4 and the reference line REFL connected to the fourth sensing transistor SET4 can be increased. Therefore, as an example, the fourth drive transistor DT4 can be connected to a pixel power line VDDL included in a first signal line group different from the first signal line group including the fourth data line DL4 connected to the fourth switching transistor SWT4 and the reference line REFL connected to the fourth sensing transistor SET4. As an example, the pixel power line VDDL can be located at the leftmost side of the first signal line group, but is not limited to this. As an example, the pixel power line VDDL in one first signal line group can be farther from the fourth drive transistor DT4 than the fourth data line DL4 and the reference line REFL in the same first signal line group, but is not limited to this. Embodiments are not limited to this. As an example, the fourth drive transistor DT4 can be connected to a pixel power line VDDL included in the same first signal line group as the first signal line group including the fourth data line DL4 connected to the fourth switching transistor SWT4 and the reference line REFL connected to the fourth sensing transistor SET4.

[0151] In this case, as an example, a first signal line group including a fourth data line DL4 connected to the fourth switching transistor SWT4 and a reference line REFL connected to the fourth sensing transistor SET4 can be provided in an area overlapping with the corresponding fourth sub-pixel SP4. On the other hand, a different first signal line group can be provided in an area overlapping with the fourth sub-pixel SP4 arranged adjacent to the corresponding fourth sub-pixel SP4 along a first direction (e.g., an X-axis direction). The pixel power line VDDL of the different first signal line group can be separated from the fourth data line DL4 connected to the fourth switching transistor SWT4 and the reference line REFL connected to the fourth sensing transistor SET4, with the transmission area TA interposed therebetween.

[0152] The fourth switching transistor SWT4, the fourth sensing transistor SET4, the fourth capacitor Cst4, and the fourth driving transistor DT4 may be disposed between a first signal line group disposed in an area overlapping with the corresponding fourth sub-pixel SP4 and a first signal line group disposed in an area overlapping with the fourth sub-pixel SP4 disposed adjacent to the corresponding sub-pixel SP4 along a first direction (e.g., an X-axis direction). The fourth switching transistor SWT4 and the fourth sensing transistor SET4 may be disposed closer to the fourth data line DL4 and the reference line REFL of the first signal line group disposed in an area overlapping with the corresponding fourth sub-pixel SP4 than the fourth driving transistor DT4. At the same time, the fourth driving transistor DT4 may be disposed closer to the pixel power line VDDL of the first signal line group disposed in an area overlapping with the fourth sub-pixel SP4 disposed adjacent to the corresponding fourth sub-pixel SP4 along the first direction (e.g., an X-axis direction) than the fourth switching transistor SWT4 and the fourth sensing transistor SET4.

[0153] As a result, the fourth circuit element CE4 can be arranged in the first direction (e.g., X-axis direction) in the order of the fourth switching transistor SWT4, the fourth capacitor Cst4, and the fourth driving transistor DT4, or in the order of the fourth sensing transistor SET4, the fourth capacitor Cst4, and the fourth driving transistor DT4. Specifically, as an example, in the fourth circuit element CE4, the fourth switching transistor SWT4, the fourth capacitor Cst4, and the fourth driving transistor DT4 can be arranged in sequence, or the fourth sensing transistor SET4, the fourth capacitor Cst4, and the fourth driving transistor DT4 can be arranged in sequence.

[0154] The switching transistors SWT1, SWT2, SWT3, and SWT4 and the sensing transistors SET1, SET2, SET3, and SET4 included in the circuit elements CE1, CE2, CE3, and CE4, respectively, can be connected to the signal lines DL1, DL2, DL3, DL4, and REFL disposed in the first non-transmission area NTA1. The switching transistors SWT1, SWT2, SWT3, and SWT4 can receive data voltages from the data lines DL1, DL2, DL3, and DL4 extending in the second direction (e.g., the Y-axis direction) in the first non-transmission area NTA1. To this end, the switching transistors SWT1, SWT2, SWT3, and SWT4 can be electrically connected to the data lines DL1, DL2, DL3, and DL4 via the switch connection lines SWCL.

[0155] Reference Figure 8The first switching transistor SWT1 included in the first circuit element CE1 may be connected to the first data line DL1 through the first switching connection line SWCL1. The first switching connection line SWCL1 may be connected to the first data line DL1 through the fourth contact hole CH4 at one end and may be connected to the active layer ACT2 of the first switching transistor SWT1 at the other end.

[0156] The third switching transistor SWT3 included in the third circuit element CE3 can be connected to the third data line DL3 through the third switching connection line SWCL3. The third switching connection line SWCL3 can be connected to the third data line DL3 at one end through the fifth contact hole CH5 and can be connected to the active layer ACT2 of the third switching transistor SWT3 at the other end.

[0157] The fourth switching transistor SWT4 included in the fourth circuit element CE4 may be connected to the fourth data line DL4 through a fourth switching connection line SWCL4. Figure 10 As shown, the fourth switching link wire SWCL4 may be connected to the fourth data line DL4 through the sixth contact hole CH6 at one end and may be connected to the active layer ACT2 of the fourth switching transistor SWT4 at the other end.

[0158] although Figure 8 Although not shown in the figure, the second switching transistor SWT2 included in the second circuit element CE2 may also be connected to the second data line DL2 through a second switching connection line (not shown). The second switching connection line (not shown) may be connected to the second data line DL2 through a contact hole at one end and may be connected to the active layer ACT2 of the second switching transistor SWT2 at the other end.

[0159] In addition, the sensing transistors SET1, SET2, SET3, and SET4 can receive a reference voltage (or initialization voltage) from a reference line REFL extending in the second direction (e.g., the Y-axis direction) in the first non-transmission area NTA1. To this end, the sensing transistors SET1, SET2, SET3, and SET4 can be electrically connected to the reference line REFL through a sensing connection line SSCL.

[0160] Reference Figure 8 The first sensing transistor SET1 included in the first circuit element CE1 may be connected to the reference line REFL through the first sensing connection line SSCL1. The first sensing connection line SSCL1 may be connected to the reference line REFL through the third contact hole CH3 and may be connected at one end to the active layer ACT3 of the first sensing transistor SET1.

[0161] The third sensing transistor SET3 included in the third circuit element CE3 may be connected to the reference line REFL through the third sensing connection line SSCL3. Figure 9 As shown, the third sensing link line SSCL3 may be connected to the reference line REFL through the third contact hole CH3 and may be connected at one end to the active layer ACT3 of the third sensing transistor SET3.

[0162] The fourth sensing transistor SET4 included in the fourth circuit element CE4 may be connected to the reference line REFL through a fourth sensing connection line SSCL4. Figure 9 As shown, the fourth sensing link line SSCL4 may be connected to the reference line REFL through the third contact hole CH3 and may be connected at one end to the active layer ACT3 of the fourth sensing transistor SST4 .

[0163] although Figure 8 Although not shown in the figure, the second sensing transistor (not shown) included in the second circuit element CE2 may also be connected to the reference line REFL through a second sensing connection line (not shown). The second sensing connection line (not shown) may be connected to the reference line REFL through a contact hole at one end and may be connected to the active layer of the second sensing transistor (not shown) at the other end.

[0164] In the transparent display panel 110 according to an exemplary embodiment of the present disclosure, as an example, the switch connection line SWCL and the sensing connection line SSCL may be provided on the same layer, or may be provided on different layers. In the transparent display panel 110 according to an exemplary embodiment of the present disclosure, each of the switch connection line SWCL and the sensing connection line SSCL may be formed of a silicon-based semiconductor material or an oxide-based semiconductor material, or may be formed of any other semiconductor material or conductive material. For example, each of the switch connection line SWCL and the sensing connection line SSCL may be formed of the same material on the same layer as the active layer ACT1 of the drive transistor DT, but is not limited thereto.

[0165] like Figure 10 As shown, the transparent display panel 110 according to an exemplary embodiment of the present disclosure may include a second laser cutting area LCA2 in the switch connection line SWCL. In the transparent display panel 110 according to an exemplary embodiment of the present disclosure, when a defect occurs in the switching transistor SWT (e.g., the fourth switching transistor SWT4), the second laser cutting area LCA2 of the switch connection line SWCL (e.g., the fourth switching line SWCL4) connected to the defective switching transistor SWT (e.g., the fourth switching transistor SWT4) may be cut using a laser.

[0166] In addition, if Figure 9 As shown, the transparent display panel 110 according to an exemplary embodiment of the present disclosure may include a first laser cutting area LCA1 located in the sensing connection line SSCL. In the transparent display panel 110 according to an exemplary embodiment of the present disclosure, when a defect occurs in the sensing transistor SET (e.g., the fourth sensing transistor SET4), the first laser cutting area LCA1 of the sensing connection line SSCL (e.g., the fourth sensing connection line SSCL4) connected to the sensing transistor SET (e.g., the fourth sensing transistor SET4) in which the defect has occurred may be cut using a laser.

[0167] In the transparent display panel 110 according to an exemplary embodiment of the present disclosure, as an example, each of the switch connection line SWCL and the sensing connection line SSCL can be formed of a silicon-based semiconductor material or an oxide-based semiconductor material. During laser irradiation, the silicon-based semiconductor material or the oxide-based semiconductor material may be more thermally condensed than a metal material such as Cu, thereby generating high heat. Therefore, the silicon-based semiconductor material or the oxide-based semiconductor material may be more easily broken than other metal materials. That is, as an example, in the transparent display panel 110 according to an exemplary embodiment of the present disclosure, each of the switch connection line SWCL and the sensing connection line SSCL can be formed of a silicon-based semiconductor material or an oxide-based semiconductor material, thereby ensuring electrical separation from a defective switching transistor SWT or a defective sensing transistor SET during laser cutting. The embodiment is not limited thereto. As an example, at least one of the first laser cutting area LCA1 and the second laser cutting area LCA2 can be omitted according to the design.

[0168] In addition, in the transparent display panel 110 according to an exemplary embodiment of the present disclosure, the switching connection line SWCL and the sensing connection line SSCL disposed on the same layer as the active layer ACT1 of the driving transistor DT may be laser cut so that the light emitting element ED disposed on the upper portion may be repaired without damage.

[0169] At the same time, in the transparent display panel 110 according to an exemplary embodiment of the present disclosure, a plurality of sensing connection lines SSCL, each connected to a plurality of sensing transistors SET, may be connected to a reference line REFL via a single third contact hole CH3. In the transparent display panel 110 according to an exemplary embodiment of the present disclosure, the first sensing connection line SSCL1 and the third sensing connection line SSCL3 connected to the first sensing transistor SET1 and the third sensing transistor SET3 of the first circuit portion C1, and the fourth sensing connection line SSCL4 connected to the fourth sensing transistor SET4 of the second circuit portion C2 may be connected to each other on the same layer. Furthermore, the first sensing connection line SSCL1 and the third sensing connection line SSCL3 connected to the first sensing transistor SET1 and the third sensing transistor SET3 of the first circuit portion C1 and the fourth sensing transistor SET4 of the second circuit portion C2 may be connected to the reference line REFL via a single third contact hole CH3.

[0170] As a result, in the transparent display panel 110 according to an exemplary embodiment of the present disclosure, the number of contact holes can be reduced. Therefore, the area increased by forming the contact holes can be reduced or minimized, and the size of the non-transmission area NTA can also be reduced or minimized.

[0171] According to the present disclosure, the following advantageous effects can be obtained.

[0172] In the present disclosure, the circuit elements of the first circuit portion can be arranged to be concentrated on one side of the first signal line in the first non-transmissive region, thereby reducing or minimizing the space used to separate the circuit elements from the plurality of signal lines. Therefore, the size of the area in which the plurality of signal lines included in the first signal line and the circuit elements included in the first circuit portion are formed can be reduced or minimized.

[0173] In addition, at least one (e.g., one, two, three, or more) of the plurality of circuit elements can be disposed in the second non-transmissive region, thereby increasing the area of ​​the capacitor included in each of the plurality of circuit elements. Thus, the brightness reduction of the sub-pixel can be reduced, and crosstalk defects can be resolved.

[0174] In addition, in the present disclosure, the product defect rate can be reduced, thereby reducing the manufacturing process cost and shortening the manufacturing process time, and also reducing production energy. In addition, the present disclosure can reduce the occurrence of greenhouse gases that may occur due to the manufacturing process, thereby achieving environmental / social / governance (ESG).

[0175] Furthermore, in the present disclosure, each of the switch connection line and the sense connection line may be formed of a silicon-based semiconductor material or an oxide-based semiconductor material, thereby ensuring electrical separation from a defective switch transistor or a defective sense transistor during laser cutting.

[0176] Furthermore, in the present disclosure, the switch connection line and the sense connection line are disposed on the same layer as the active layer of the driving transistor, so that the light emitting element disposed on the upper portion can be repaired without being damaged during laser cutting.

[0177] In addition, in the present disclosure, multiple sensing connection lines respectively connected to multiple sensing transistors are connected to the reference line through a single contact hole, thereby reducing the number of contact holes. Therefore, the area increased by forming the contact holes can be reduced or minimized, and the size of the non-transmission area NTA can also be reduced or minimized.

[0178] It will be apparent to those skilled in the art that the present disclosure is not limited to the above embodiments and drawings, and that various substitutions, modifications, and variations may be made in the present disclosure without departing from the spirit or scope of the present disclosure.

[0179] CROSS-REFERENCE TO RELATED APPLICATIONS

[0180] This application claims the benefit of and priority to Korean Patent Application No. 10-2024-0030120, filed on February 29, 2024, which is hereby incorporated by reference in its entirety for all purposes as if fully set forth herein.

Claims

1. A transparent display device, comprising: a display area in which a plurality of sub-pixels are arranged to display an image; a plurality of transmission areas disposed within the display area and transmitting external light; a first non-transmission region that is disposed between the transmission regions disposed adjacent to each other along the first direction and does not transmit external light; a second non-transmission area that is disposed between the transmission areas disposed adjacent to each other along the second direction and does not transmit external light; a first circuit portion disposed in the first non-transmitting region to drive a sub-pixel; as well as A second circuit portion is provided in the second non-transmitting area to drive the sub-pixel.

2. The transparent display device according to claim 1 , further comprising a first signal line extending along the second direction in the first non-transmitting area, in, The region where the first signal line is provided is provided between the first circuit portion and the transmissive region.

3. The transparent display device according to claim 2, wherein: The first circuit part is formed along an edge region of one side of the first non-transmission region.

4. The transparent display device according to claim 2, wherein: The first signal line includes: a first data line for providing a data voltage to a sub-pixel disposed in the first non-transmitting area; a second data line for providing a data voltage to a sub-pixel disposed in the second non-transmission area; and A reference line is provided for providing a reference voltage to the sub-pixel disposed in the first non-transmission area and the sub-pixel disposed in the second non-transmission area.

5. The transparent display device according to claim 2, wherein: The first circuit portion and the second circuit portion are provided on opposite sides of the region where the first signal line is provided.

6. The transparent display device according to claim 5, wherein: The region where the first signal line is provided is provided between the first circuit portion and the transmission region adjacent to the second circuit portion along the second direction.

7. The transparent display device according to claim 2, wherein: Each of the first signal lines includes: a first data line for providing a data voltage to a sub-pixel disposed in the first non-transmitting area; a second data line for providing a data voltage to a sub-pixel disposed in a second non-transmission area located on one side of the first non-transmission area; and A power supply line is configured to supply power to sub-pixels disposed in a second non-transmission region located on the other side of the first non-transmission region opposite to the one side.

8. The transparent display device according to claim 7, wherein: The first data line and the second data line are closer to a sub-pixel disposed in the second non-transmission area located at the one side of the first non-transmission area than the power line.

9. The transparent display device according to claim 1, wherein: The first circuit section is configured to drive a sub-pixel provided in the first non-transmission area, and The second circuit section is configured to drive a sub-pixel provided in the second non-transmission area.

10. The transparent display device according to claim 1, further comprising a second signal line extending along the first direction in the second non-transmitting area, in, The second signal lines include scan lines for providing scan signals to the sub-pixels disposed in the first non-transmission area and the sub-pixels disposed in the second non-transmission area.

11. The transparent display device according to claim 2, further comprising a second signal line extending along the first direction in the second non-transmitting area, in, The second signal line includes a scan line for providing a scan signal to the sub-pixel disposed in the first non-transmission area and the sub-pixel disposed in the second non-transmission area. wherein the first signal line and the first circuit portion are arranged so as not to overlap each other, and The second signal line and the second circuit portion are disposed so as not to overlap each other.

12. The transparent display device according to claim 1, wherein: A plurality of sub-pixels are provided in the first non-transmitting area, and The first circuit part includes a plurality of circuit elements for the plurality of sub-pixels disposed in the first non-transmission area.

13. The transparent display device according to claim 12, wherein: The plurality of circuit elements of the first circuit portion are arranged in a row along the second direction.

14. The transparent display device according to claim 1, wherein: One sub-pixel is disposed in the second non-transmitting area, The second circuit portion includes one circuit element for the one sub-pixel provided in the second non-transmission area.

15. The transparent display device according to claim 14, wherein: The one circuit element includes a capacitor and at least one transistor.

16. The transparent display device according to claim 15, wherein: The at least one transistor includes a driving transistor for supplying a driving current to the one sub-pixel and a switching transistor for supplying a data voltage supplied from a data line to the driving transistor, and The capacitor is provided between the driving transistor and the switching transistor.

17. The transparent display device according to claim 16, wherein: The switching transistor is disposed closer to the data line than the driving transistor.

18. The transparent display device according to claim 1, further comprising: a data line extending in the first non-transmission area along the second direction and providing a data voltage to a sub-pixel disposed in the second non-transmission area; as well as a reference line extending in the second direction in the first non-transmission area and providing a reference voltage to a sub-pixel disposed in the second non-transmission area, The second circuit portion includes a switching transistor connected to the data line and a sensing transistor connected to the reference line.

19. The transparent display device according to claim 18, further comprising: a switch connection line, the switch connection line connecting the data line and the switch transistor; as well as a sensing connection line connecting the reference line and the sensing transistor, Wherein, the switch connection line and the sensing connection line are arranged on the same layer.

20. The transparent display device according to claim 18, further comprising a power line, the power line being spaced apart from the data line and the reference line with a transmissive region interposed therebetween, and the power line extending along the second direction. in, The power supply line is configured to supply power to the sub-pixels disposed in the second non-transmission area, The second circuit unit further includes a driving transistor connected to the power line.

21. The transparent display device according to claim 20, wherein: The sensing transistor is disposed closer to the reference line than the driving transistor, and the driving transistor is disposed closer to the power supply line than the sensing transistor.

22. The transparent display device according to claim 20, wherein: The driving transistor includes an active layer, a drain electrode, a source electrode, and a gate electrode, and The switch connection line and the sensing connection line are formed on the same layer and of the same material as the active layer of the driving transistor.

23. The transparent display device according to claim 19, wherein: Each of the switch connection line and the sensing connection line is made of a silicon-based semiconductor material or an oxide-based semiconductor material.

24. The transparent display device according to claim 1, further comprising a scan line extending along the first direction in the second non-transmitting area, in, The first circuit portion includes two circuit elements that are symmetrically arranged with respect to each other based on the scanning line.

25. The transparent display device according to claim 24, wherein: The first circuit portion includes a first circuit element provided on one side of the scan line and a second circuit element provided on an opposite side of the scan line. Each of the first circuit element and the second circuit element includes a switching transistor, a capacitor, and a driving transistor, and In each of the first circuit element and the second circuit element, the switching transistor, the capacitor, and the driving transistor are sequentially provided based on the scanning line.

26. The transparent display device according to claim 1, further comprising: a reference line for providing a reference voltage to a sensing transistor of the first circuit portion disposed in the first non-transmission region and a sensing transistor of the second circuit portion disposed in the second non-transmission region; a first sensing connection line connecting the reference line to the sensing transistor of the first circuit portion; as well as a second sensing connection line connecting the reference line and the sensing transistor of the second circuit portion; The first sensing connection line and the second sensing connection line are connected to each other on the same layer.

27. The transparent display device according to claim 26, wherein: The first sensing connection line and the second sensing connection line are connected to the reference line through the same contact hole.

28. The transparent display device according to claim 1, wherein: Each of the first circuit portion and the second circuit portion includes a capacitor, and The capacitor of the second circuit portion has a larger formation area than the capacitor of the first circuit portion.

29. The transparent display device according to claim 1, wherein: The sub-pixel disposed in the second non-transmission area is a white sub-pixel.

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