Method and apparatus for handling frame collisions of power line carrier signals

Abstract

This invention discloses a method and apparatus for handling frame collisions in power line carrier signals, belonging to the field of power line carrier communication technology. The method includes: after the baseband module completes the reception of the current signal frame and transmits the data to the memory module, it sets a reception completion signal to indicate the reception completion status; while the reception completion signal is set, if the baseband module detects a frame synchronization completion signal, it sets an overflow flag signal; according to the frame collision handling strategy, it performs frame collision handling operations related to the current signal frame or the next signal frame based on the overflow flag signal. This invention, by introducing a frame collision detection and handling mechanism based on the reception completion signal and the overflow flag signal, can quickly respond to frame data processing collisions during continuous frame reception, avoid data corruption or loss, and improve the reception stability and data integrity of the communication system.

Description

Technical Field

[0001] This invention belongs to the field of power line carrier communication technology, and particularly relates to a method and apparatus for handling frame collisions of power line carrier signals. Background Technology

[0002] With the development of High-speed Power Line Communication (HPLC) technology, it has been widely used in smart grids, smart meters, and distribution automation. This type of communication system uses power lines as the transmission medium, resulting in a complex channel environment susceptible to transient interference, narrowband interference, and background noise. To improve communication stability and data throughput, more and more HPLC systems are adopting higher bandwidth and higher frequency signal frame transmission methods to meet the high-speed or low-latency communication requirements for real-time reporting, power grid status monitoring, and control command issuance. In such systems, upper-layer software frequently interacts with the HPLC chip for subsequent networking or channel estimation processing. Because signal frames are transmitted continuously with short intervals between frames, the signal receiving device must complete the reception, parsing, transfer, and notification processing of the previous frame within a very short timeframe to ensure the communication system smoothly transitions to the next frame.

[0003] However, related technologies still have significant shortcomings when handling such high-density continuous frame structures: if the CPU, due to heavy workload or scheduling lag, fails to complete the reading and state clearing of the previous frame in time, the next frame may have already entered synchronization and completed part of the reception process. At this point, the system will face a typical conflict state of "the previous frame not yet processed, the next frame has already started," which can easily lead to problems such as buffer data misalignment, frame feature information overwriting, or control state chaos. Some traditional systems rely solely on interrupts for software-based conflict handling, but the timeliness of interrupt services is limited by the CPU's current load and response capabilities, often failing to effectively guarantee data consistency under continuous frame reception. Summary of the Invention

[0004] This invention aims to at least solve one of the technical problems existing in related technologies. To this end, this invention proposes a method and apparatus for handling frame collisions of power line carrier signals, so as to achieve rapid identification and strategic handling of collisions during continuous frame reception, thereby improving data integrity and processing efficiency in high-speed communication scenarios.

[0005] In a first aspect, the present invention provides a method for handling frame collisions of a power line carrier signal, the method being applied to a signal receiving device, the signal receiving device including a baseband module and a memory module; the method comprising:

[0006] After the baseband module completes the reception of the current signal frame and transmits the current signal frame to the memory module, it sets up the reception completion signal to indicate the reception completion status.

[0007] During the period when the reception completion signal is in the enabled state, if the baseband module detects the frame synchronization completion signal, it enables the overflow flag signal; the overflow flag signal is used to indicate that the processing state of the current signal frame conflicts with the reception behavior of the next signal frame.

[0008] According to the frame conflict handling strategy, frame conflict handling operations related to the current signal frame or the next signal frame are performed based on the overflow flag signal.

[0009] According to the frame collision handling method for power line carrier signals provided by this invention, after the baseband module completes the reception of the current signal frame and transmits the data of the current signal frame to the memory module, it sets the reception completion signal, thereby clearly defining the state between frame reception and processing, which facilitates the processing module in determining the timing of data reading. While the reception completion signal is in the set-up state, if the baseband module detects a frame synchronization completion signal, it sets the overflow flag signal, enabling timely detection of the next frame's access behavior and generating a flag signal for alarm. This achieves rapid and automatic identification of collision states without waiting for processor intervention or polling, eliminating reliance on interrupt responses or software scheduling mechanisms. Furthermore, according to the frame collision... The overflow handling strategy performs frame collision handling operations related to the current or next signal frame based on the overflow flag signal. The baseband module automatically triggers the collision strategy, supporting automatic frame collision handling within the hardware without the need for processor intervention in judgment and control signal initiation. This reduces control path latency, improves robustness and overall processing efficiency in high-speed reception scenarios, and by introducing configurable or dynamically selectable collision handling strategies, it supports flexible handling of conflicts between current frame retention and next frame reception according to application requirements, improving system adaptability and processing efficiency. It can effectively reduce the risk of data loss and state disorder caused by frame collisions, and improve the reliability and processing efficiency of the system in high-density reception scenarios.

[0010] According to an embodiment of the present invention, the step of performing frame collision handling operations related to the current signal frame or the next signal frame based on the overflow flag signal according to the frame collision handling strategy includes:

[0011] When the overflow flag signal is enabled, the baseband module generates an overflow reset signal to trigger an interrupt;

[0012] In response to the overflow reset signal, the baseband module performs a reset operation to stop processing the next frame of data;

[0013] The baseband module sets the receive completion signal and the overflow reset signal to zero to end the conflict state between the current signal frame and the next signal frame.

[0014] In the above embodiments, by actively generating an overflow reset signal after a conflict is detected by the baseband module, and performing buffer clearing and reception termination operations based on this signal, and coordinating the synchronous zeroing of the reception completion signal and the overflow reset signal, a fast closed-loop processing of frame conflict states is achieved. This avoids uncontrollable delays caused by relying on CPU response, ensuring timely handling of conflict states. Furthermore, by clearing the next frame of data and terminating reception, overlapping or overwriting of consecutive frames is avoided, ensuring the integrity of each frame of data. In addition, the entire process is completed independently by the baseband module, without CPU participation, resulting in no response delay. It also completely avoids the problem of delayed conflict response caused by software busyness or scheduling delays. This ensures both the real-time performance of the communication process and the continuity and stability of CPU software tasks. Even when consecutive frames arrive in close succession or the CPU is under high load, the system can still operate stably, achieving efficient and reliable data protection in frame conflict scenarios.

[0015] According to an embodiment of the present invention, the signal receiving device further includes a processing module; the step of performing frame collision processing operations related to the current signal frame or the next signal frame based on the overflow flag signal according to the frame collision processing strategy further includes:

[0016] Upon detecting the overflow flag signal, the processing module suspends the reading operation of the current signal frame;

[0017] The processing module sets the received signal to zero in order to read the next signal frame.

[0018] In the above embodiments, by interrupting the continued reading of the current frame through the processing module, invalid data is not extracted after the frame data is partially covered, thus improving the effectiveness of the frame data. Furthermore, by actively setting the receiving completion signal to zero, the conflict handling time is shortened, the preparation for processing the next frame data is accelerated, and the overall system processing speed is improved.

[0019] In a second aspect, the present invention provides a frame collision processing apparatus applied to a signal receiving device, the apparatus comprising:

[0020] The signal triggering module is used to set up a reception completion signal to indicate the reception completion status after the baseband module has completed receiving the current signal frame and transmitting the current signal frame data to the memory module.

[0021] The conflict triggering module is used to set up the overflow flag signal if the baseband module detects the frame synchronization completion signal while the reception completion signal is in the set state; the overflow flag signal is used to indicate that the processing state of the current signal frame conflicts with the reception behavior of the next signal frame.

[0022] The conflict handling module is used to perform frame conflict handling operations related to the current signal frame or the next signal frame based on the overflow flag signal, according to the frame conflict handling strategy.

[0023] The frame conflict handling apparatus provided by this invention, after the baseband module completes the reception of the current signal frame and transmits the data of the current signal frame to the memory module, sets the reception completion signal, thereby clearly defining the state between frame reception and processing, facilitating the processing module's determination of data reading timing. While the reception completion signal is in the set-up state, if the baseband module detects a frame synchronization completion signal, it sets the overflow flag signal, enabling timely detection of the next frame's access behavior and generating a flag signal for alarm. This achieves rapid and automatic identification of conflict states without waiting for processor intervention or polling, eliminating reliance on interrupt responses or software scheduling mechanisms. Furthermore, according to the frame conflict handling strategy... The system performs frame conflict handling operations related to the current or next signal frame based on the overflow flag signal. The baseband module automatically triggers the conflict strategy, supporting automatic frame conflict handling within the hardware without the need for the processor to participate in judgment and control signal initiation. This reduces control path latency, improves robustness and overall processing efficiency in high-speed reception scenarios, and by introducing configurable or dynamically selectable conflict handling strategies, it supports flexible handling of conflicts between current frame retention and next frame reception according to application requirements, improving system adaptability and processing efficiency. This effectively reduces the risk of data loss and state disorder caused by frame conflicts, and improves the reliability and processing efficiency of the system in high-density reception scenarios.

[0024] Thirdly, the present invention provides a signal receiving device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the frame collision handling method for power line carrier signals as described in the first aspect above.

[0025] Fourthly, the present invention provides a non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the frame collision handling method for power line carrier signals as described in the first aspect above.

[0026] Fifthly, the present invention provides a chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run computer programs or instructions to implement the frame collision handling method for power line carrier signals as described in the first aspect above.

[0027] In a sixth aspect, the present invention provides a computer program product, including a computer program that, when executed by a processor, implements the frame collision handling method for power line carrier signals as described in the first aspect above.

[0028] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0029] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments with reference to the accompanying drawings, in which:

[0030] Figure 1 This is a schematic diagram illustrating an application scenario of the frame collision handling method for power line carrier signals provided in some embodiments of the present invention;

[0031] Figure 2 This is a schematic diagram of the power line carrier communication signal processing procedure provided in some embodiments of the present invention;

[0032] Figure 3 This is a schematic diagram illustrating the underlying data interaction principle provided in some embodiments of the present invention;

[0033] Figure 4 This is a schematic diagram of the signal under normal conditions provided in some embodiments of the present invention;

[0034] Figure 5 This is a schematic diagram of the signal under delay conditions provided in some embodiments of the present invention;

[0035] Figure 6 This is a flowchart illustrating a method for handling frame collisions of power line carrier signals provided in some embodiments of the present invention.

[0036] Figure 7 This is a signal schematic diagram of a frame collision handling strategy provided in some embodiments of the present invention;

[0037] Figure 8 This is a signal schematic diagram of another frame collision handling strategy provided in some embodiments of the present invention;

[0038] Figure 9 This is a schematic diagram of the feature information synchronization process provided in some embodiments of the present invention;

[0039] Figure 10 This is a signal diagram illustrating the feature information synchronization process provided in some embodiments of the present invention;

[0040] Figure 11 This is an overall schematic diagram of the feature information synchronization process provided in some embodiments of the present invention;

[0041] Figure 12 This is a schematic diagram of the frame collision processing device provided in some embodiments of the present invention;

[0042] Figure 13 This is a schematic diagram of the structure of a signal receiving device provided in some embodiments of the present invention. Detailed Implementation

[0043] The technical solutions of the embodiments of the present invention will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention are within the scope of protection of the present invention.

[0044] Unless otherwise defined, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains; the terminology used in the specification of this application is for the purpose of describing particular embodiments only and is not intended to limit the invention; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings are used to distinguish different objects, not to describe a particular order or hierarchy.

[0045] In this invention, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this invention can be combined with other embodiments.

[0046] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "attachment" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0047] In this invention, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, in this invention, the character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0048] In this invention, "multiple" refers to two or more (including two), similarly, "multiple groups" refers to two or more (including two groups), and "multiple pieces" refers to two or more (including two pieces).

[0049] The following description, in conjunction with the accompanying drawings, details the frame collision handling method for power line carrier signals provided by the present invention through specific embodiments and application scenarios.

[0050] Figure 1 This is a schematic diagram illustrating an application scenario of the frame collision handling method for power line carrier signals provided in some embodiments of the present invention. The frame collision handling method for power line carrier signals provided in the embodiments of the present invention can be applied to, for example... Figure 1 The diagram illustrates the application environment of a power line communication system. This system includes signal transmitting equipment and signal receiving equipment. The signal transmitting equipment sends power line communication signals, while the signal receiving equipment receives these signals and performs subsequent processing such as channel estimation.

[0051] The signal transmitting and receiving devices can be, for example, computer devices, such as power line communication terminals, concentrator devices, smart meters, communication module embedded devices, or communication test terminals. Alternatively, the computer devices can also be devices with computing capabilities or intelligent robots, used to perform signal reception, processing, and subsequent possible processing tasks in this invention.

[0052] Based on the above application scenarios, this invention can be applied to power line carrier communication signal processing scenarios. Figure 2 This is a schematic diagram of the power line carrier communication signal processing procedure provided in some embodiments of the present invention. For example... Figure 2As illustrated, exemplarily, the transmitting end (i.e., the signal transmitting device) encodes the frame control data and payload data accordingly, then adds a preamble to the frame signal through Inverse Fast Fourier Transform (IFFT) and cyclic prefix sum windowing, and transmits it to the power line channel through an analog front-end. The receiving end (i.e., the signal receiving device) receives the signal through the analog front-end and completes initial signal alignment through automatic gain control in conjunction with a clock mechanism or frame synchronization mechanism. Subsequently, the receiving end converts the signal to the frequency domain through a Fast Fourier Transform (FFT) module, and then completes symbol restoration through demodulation. The demodulated frame control data and payload data are then decoded accordingly to finally restore the frame control data and data payload. All of the above processes are completed within the baseband of the receiving end. In addition, the receiving end also uses a buffering mechanism to temporarily store relevant frame data of the current signal frame to ensure that data consistency and system stability can be maintained even when multiple frames arrive consecutively.

[0053] Figure 3 This is a schematic diagram illustrating the underlying data interaction principle provided in some embodiments of the present invention. For example... Figure 3 As shown, frame data (including preamble, frame control data, and data payload) is first received by the baseband module, which then demodulates and parses the data. After processing the frame data, the baseband module writes the frame control data and data payload into the memory module (i.e., system memory) and, through its internal hardware logic, sets the receive completion signal (rx-end-flag) at time t1, switching it from a default low level to a high level to indicate that the reception and transmission of the frame data for that signal frame has been completed. Upon detecting the high level of the receive completion signal, the processing module (i.e., the CPU) begins reading the corresponding frame data from the system memory. After reading is complete, the processing module sets the receive completion signal to zero at time t2, restoring it from a high level to a low level to indicate the completion status. This establishes a handshake mechanism jointly implemented by the baseband module and the processing module, ensuring reliable setting and release of the receive completion flag and improving the reliability of frame data reading.

[0054] The following further describes the normal timing process of the handshake mechanism under the condition of consecutive frame arrivals. Figure 4 This is a schematic diagram of signals under normal conditions provided in some embodiments of the present invention. For example... Figure 4As shown, in the context of the system continuously receiving multiple frames of data, after the baseband module completes the reception and processing of frame 1, it writes the frame control data and data payload into the system memory at time t1 and sets the reception completion signal (rx-end-flag) to indicate that the data for frame 1 has been written. Subsequently, the processing module detects that the reception completion signal is in a high-level state, confirming that the current frame data is ready to be read, and initiates the reading operation. After the processing module completes the reading of frame 1 data, at time t2, it uses software control to set the reception completion signal to zero, i.e., it transitions from a high level to a low level, to notify the baseband module that the processing of the current frame data has ended and the reception process for the next frame data can begin.

[0055] exist Figure 4 In the normal data flow scenario shown, the timely setting and resetting of the receive completion signal effectively synchronizes the frame data reception status between the baseband module and the processing module, helping to ensure data integrity and read timing when the system continuously receives multiple signal frames. However, in actual operation, the CPU often undertakes multiple parallel tasks simultaneously, posing a risk of response delay. Especially in scenarios with short frame intervals and high processing pressure, the resetting of the receive completion signal may not be completed within the expected time window, thus affecting the normal reception and storage of subsequent frames. To illustrate the potential data conflict problem caused by this type of response delay, the following shows the overwriting and misreading phenomena caused by continuously receiving frame data when the CPU fails to reset the receive completion signal in a timely manner.

[0056] Figure 5 This is a schematic diagram of the signal under delay conditions provided in some embodiments of the present invention. For example... Figure 5 As shown, at time t1, the baseband module transmits frame 1 data to system memory and sets the receive completion signal (rx-end-flag), which should normally be set to zero at time t2. However, because the CPU is currently processing other tasks and cannot respond in time, the receive completion signal is not set to zero at time t2 and remains at a high level. Assuming the receive completion signal is set to zero at time t2', and the baseband module has already started receiving frame 2 data, the data extracted by the CPU between t1 and t2' will contain a mixture of frame 1 and frame 2 data. This will cause errors in the upper-layer application processing, and subsequent frame 2 data will also be missing, leading to errors in subsequent processing as well.

[0057] It should be noted that although system designs typically reserve frame intervals for the CPU to complete read and flag-setting operations, the CPU response process is software-controlled and inevitably involves latency fluctuations. Delayed responses will directly affect the correctness of the cached data, especially in scenarios with dense, continuous frame reception, where overlay conflicts are more likely to occur.

[0058] Therefore, it is evident that the traditional method of handling receive conflicts in the intermediate buffer using CPU interrupts has inherent timing disadvantages. It not only easily leads to delays in conflict identification but also increases CPU load, reducing overall system efficiency and stability. Furthermore, frequent interrupt triggering increases CPU burden and impacts overall system processing efficiency.

[0059] In view of this, the present invention provides a general frame collision handling method applicable to continuous signal frame structures, which realizes collision detection and response control of frame reception status and new frame access behavior, significantly improves the processing stability, response speed and module decoupling capability of signal receiving equipment in high-density data stream environment, and provides a solid foundation for subsequent strategies such as reception path management and channel feature protection.

[0060] The frame collision handling method for power line carrier signals provided in this embodiment of the invention can be executed by a signal receiving device or a functional module or functional entity in the signal receiving device that can implement the frame collision handling method for power line carrier signals.

[0061] The following describes the frame collision handling method for power line carrier signals provided in this embodiment of the invention, using a signal receiving device as the execution subject as an example.

[0062] The signal receiving device includes a baseband module, a memory module, and a processing module. The baseband module is responsible for demodulating and performing preliminary processing of the signal frames, while the memory module is used to store the received signal frame data.

[0063] For example, a baseband module refers to a hardware or hardware / software combination unit used to perform low-level communication operations such as wireless signal demodulation, channel estimation, field identification, and physical layer processing. For instance, a baseband module can be a hardware processing unit composed of FPGA (Field Programmable Gate Array), DSP (Digital Signal Processor), or ASIC (Application Specific Integrated Circuit).

[0064] A memory module refers to a system storage resource used to store complete signal frame data transmitted by the baseband module. It can be on-chip RAM (Random Access Memory), DDR (Double Data Rate) memory, or an embedded cache module.

[0065] The processing module can include an embedded processor (such as an ARM (Advanced RISC Machines) core), an MCU (Microcontroller Unit), or a main control CPU (Central Processing Unit) that runs in conjunction with an operating system. It is used to read frame data from the memory module and combine it with feature information to complete further upper-level business processing, conflict decision-making, control signal issuance, and flag signal clearing operations.

[0066] Figure 6 This is a flowchart illustrating a method for handling frame collisions of power line carrier signals provided in some embodiments of the present invention. For example... Figure 6 As shown, the frame collision handling method for the power line carrier signal includes steps 610 to 630.

[0067] Step 610: After the baseband module completes the reception of the current signal frame and transmits the current signal frame data to the memory module, it sets up the reception completion signal to indicate the reception completion status.

[0068] The receive completion signal is a status indication signal set by the baseband module. It indicates that the reception operation of the current signal frame has been completed and the process can proceed to the next stage. This signal helps coordinate read / write synchronization between the baseband and subsequent processing modules, preventing overlapping of inter-frame operations.

[0069] The baseband module receives the current signal frame (e.g., frame 1) and completes data parsing and demodulation operations. After data processing is complete, the baseband module writes the FC field (Frame Control) and PL field (Payload) of frame 1 into the memory module and sets the receive completion signal rx-end-flag. The default state of this signal is low; setting it indicates that the current frame has been transmitted and the system is ready for subsequent read operations.

[0070] The baseband module receives the current signal frame and transmits it to the memory module. This process includes not only the direct transmission of the FC (Frame Control) and PL (Payload) fields in the signal frame, but also complete support for the preceding reception processing. Specifically, when constructing a power line carrier signal data frame, the signal transmitting device typically first performs general channel coding on the raw byte data to be transmitted (e.g., hexadecimal 0x12) to improve error resilience. Then, the coding result is interleaved to combat sudden interference or narrowband noise. Afterward, the signal transmitting device inserts multiple preamble symbols before the coded data. These preamble symbols typically consist of multiple synchronization training symbols or pilots, used by the receiver to perform frame synchronization and channel estimation. For example, the raw data 0x12, after coding and interleaving, can be mapped to "110011". Then, a preamble sequence "010101" is inserted, ultimately forming the complete transmitted bit string "010101110011" as a complete physical layer signal frame.

[0071] The baseband module of the signal receiving device first receives the bit string (i.e., a composite frame containing a preamble, FC, and PL). Within the synchronization window, it performs frame synchronization by detecting multiple consecutive synchronization peaks or matching the local frame preamble sequence, triggering the generation of corresponding frame synchronization start signals (sync-begin) and frame synchronization completion signals (frame-synced). Furthermore, the baseband module performs channel estimation and equalization, using the preamble symbol to calculate CE and estimate the channel response. The signal receiving device also performs deinterleaving and decoding, deinterleaving, soft-decision decoding, or maximum likelihood decoding of the payload portions of the FC and PL fields in the received bitstream to restore the original data bytes (e.g., recovering 0x12). Additionally, the receiver can perform verification and field parsing, such as performing CRC checks on the frame control field and parsing the length / address field. Finally, when the decoding result is valid, the baseband module writes the decoding result corresponding to the signal frame (i.e., 0x12) into the system memory module and simultaneously sets the receive completion signal Rx-end-flag to notify the processing module (e.g., the CPU) that the data is readable.

[0072] Step 620: During the period when the reception completion signal is in the enabled state, if the baseband module detects the frame synchronization completion signal, it enables the overflow flag signal; the overflow flag signal is used to indicate that the processing state of the current signal frame conflicts with the reception behavior of the next signal frame.

[0073] The overflow flag signal is a collision indication signal used to indicate an abnormal state where the previous frame has not been processed but the next frame has already begun entering the reception path. This signal serves as a trigger condition for collision management, enabling the signal receiving device to switch processing strategies in a timely manner, i.e., switching between normal processing and frame collision handling, to avoid data loss or state confusion.

[0074] While the receive completion signal rx-end-flag is still in the enabled state (high level), if the baseband module detects a frame synchronization completion signal, it indicates that the frame synchronization processing of the next signal frame (e.g., frame 2) has been completed. In this case, the communication system faces a conflict scenario, i.e., the previous frame has not yet been released, and the next frame has already begun to be received. At this time, the baseband module generates an overflow flag signal overflow-flag to explicitly indicate that the current signal frame has not been processed but a new reception action has occurred, which is a potential data conflict state.

[0075] Step 630: In accordance with the frame conflict handling strategy, perform frame conflict handling operations related to the current signal frame or the next signal frame based on the overflow flag signal.

[0076] The frame collision handling strategy refers to the predefined collision response scheme of the signal receiving device to deal with the overlap of received signal frames. This collision response scheme includes the strategy for retaining and discarding signal frames, as well as corresponding behavior control logic, state initiation / clearing order, and other parameters. A reasonable setting of this strategy helps ensure system processing stability in continuous frame reception scenarios and improves overall communication quality.

[0077] When a collision is detected and an overflow flag signal is generated, the baseband module executes frame collision handling operations according to a preset frame collision handling strategy. This strategy can determine whether to retain the previous frame or the current frame based on factors such as different system loads and processing priorities.

[0078] For example, frame collision handling strategies may include, but are not limited to: interrupting the current reception, discarding the new frame, latching the old frame, enabling double buffering, and clearing the next frame. The baseband module will select to perform differentiated collision clearing actions for the current frame or the next frame based on the state characteristics at the time of the collision, thereby ensuring stable system operation.

[0079] Taking a wireless communication system based on OFDM (Orthogonal Frequency Division Multiplexing) signal structure as an example, after the baseband module completes the reception of all symbols of frame 1 and transfers them to memory via DMA, it sets a reception completion signal. At this time, since the upper-layer CPU has not yet completed data reading, if frame 2 has started reception through synchronization symbol detection, the baseband module will generate an overflow flag signal and then process it according to the preset frame conflict handling strategy. For example, if the system prioritizes retaining frame 1 data, the frame 2 reception process is discarded and its buffer area is cleared; if frame 2 needs to be retained, the frame 1 reception state is cleared and its reading path is released for use by new frames, and so on.

[0080] The frame collision handling method for power line carrier signals provided in this invention, after the baseband module completes the reception of the current signal frame and transmits the data of the current signal frame to the memory module, sets up the reception completion signal, thus clearly defining the state between frame reception and processing, facilitating the processing module's determination of data reading timing. While the reception completion signal is in the set-up state, if the baseband module detects a frame synchronization completion signal, it sets up the overflow flag signal, enabling timely detection of the next frame's access behavior and generating a flag signal for alarm. This achieves rapid and automatic identification of collision states without waiting for processor intervention or polling, eliminating reliance on interrupt responses or software scheduling mechanisms. Furthermore, according to frame collision... The overflow handling strategy performs frame collision handling operations related to the current or next signal frame based on the overflow flag signal. The baseband module automatically triggers the collision strategy, supporting automatic frame collision handling within the hardware without the need for processor intervention in judgment and control signal initiation. This reduces control path latency, improves robustness and overall processing efficiency in high-speed reception scenarios, and by introducing configurable or dynamically selectable collision handling strategies, it supports flexible handling of conflicts between current frame retention and next frame reception according to application requirements, improving system adaptability and processing efficiency. It can effectively reduce the risk of data loss and state disorder caused by frame collisions, and improve the reliability and processing efficiency of the system in high-density reception scenarios.

[0081] In actual communication, frames may arrive consecutively. Signal receiving devices need to accurately determine when to enter the next frame reception process in order to achieve pre-triggering for frame collision identification and control.

[0082] Therefore, in some embodiments, the baseband module detects the frame synchronization completion signal by: monitoring the synchronization sequence in the input signal, and when a synchronization sequence matching the preset frame format is detected, generating a frame synchronization start signal to indicate that frame synchronization detection for the next signal frame has been initiated; after confirming the frame synchronization position, the baseband module generates a frame synchronization completion signal to indicate that the currently received next signal frame has completed the synchronization process.

[0083] Specifically, during signal reception, the baseband module first continuously monitors the synchronization sequence in the input signal. For example, a sliding window can be set to perform matching operations on the preamble region of the received signal to identify whether a sequence pattern matching a preset frame structure exists. If a continuous correlation peak or feature template that meets the conditions is detected, a frame synchronization start signal (sync-begin) can be triggered to indicate that the synchronization detection phase of the next signal frame has started.

[0084] Subsequently, the baseband module continues to perform frame synchronization processing on the input signal, such as locating the boundary point between the synchronization symbols SYNCP (Synchronization Pattern) and SYNCM (Synchronization Channel Midpoint), or determining the frame header position through the maximum correlation value. Once the frame synchronization position is successfully confirmed, the baseband module generates a frame-synced signal to indicate the end of the current synchronization process, and the reception process can proceed to the frame control segment and data payload segment reception processing.

[0085] Taking a typical OFDM frame structure as an example, its frame header usually contains multiple preamble symbols used for frame synchronization, frequency offset estimation, and channel estimation. The communication system pre-configures a preset frame format and decision threshold. At time t0, the baseband module detects more than three similar synchronization peaks in the input signal, thus generating a frame synchronization start signal (sync-begin), indicating that synchronization detection for frame 2 has started. Next, the baseband module confirms the synchronization position based on a sliding window matching mechanism, for example, determining the intersection of SYNCP and SYNCM, and generates a frame synchronization completion signal (frame-synced), indicating that synchronization of frame 2 is complete and its FC and PL fields can be received. If the previous frame, frame 1, has not yet been read, the baseband module will combine the frame synchronization completion signal with the reception completion signal (Rx-end-flag) to trigger subsequent frame collision handling procedures.

[0086] In the above embodiments, by introducing a synchronization sequence matching and frame synchronization signal generation mechanism into the baseband module, the arrival of the next frame signal can be quickly and accurately identified without CPU intervention. This helps improve the boundary detection accuracy during frame reception and ensures that the frame collision handling process has an accurate starting judgment basis. Simultaneously, this mechanism can effectively reduce system response latency, avoid data misreading or overwriting problems caused by hardware and software asynchrony, and enhance the robustness and real-time performance of the overall communication system.

[0087] It should be noted that the frame collision handling method for power line carrier signals provided by this invention can be applied to communication systems with continuous frame structures. In a communication system, one scenario is that multiple signal frames are arranged sequentially, and the inter-frame interval between adjacent signal frames is less than the minimum reading period of the processing module. That is, when the previous frame has not yet completed data extraction, the next frame has already begun to arrive and enter the synchronization stage.

[0088] Such systems are common in high-density, high-speed data communication scenarios, such as power line carrier communication (HPLC), OFDM systems, or point-to-point communication in specific embedded devices. Due to the lack of inter-frame buffer redundancy, the processing cycle of frame 1 easily overlaps with the reception cycle of frame 2, leading to frame collisions. Against this backdrop, the frame collision handling strategy proposed in this invention can significantly improve system stability.

[0089] The following sections will describe the three frame collision handling strategies proposed in this invention to more clearly illustrate the specific response methods under different collision conditions.

[0090] It should be noted that the classification and implementation methods of frame conflict handling strategies are merely illustrative and do not constitute a limitation on the scope of protection of this invention. Without departing from the core ideas of this invention, the processing flow of the relevant strategies can be adapted and extended according to the actual system design.

[0091] In some embodiments, according to the frame conflict handling strategy, a frame conflict handling operation related to the current signal frame or the next signal frame is performed based on the overflow flag signal, including: when the overflow flag signal is in an enabled state, the baseband module generates an overflow reset signal for triggering an interrupt; in response to the overflow reset signal, the baseband module performs a reset operation to stop processing the next frame data; the baseband module sets the receive completion signal and the overflow reset signal to zero to end the conflict state between the current signal frame and the next signal frame.

[0092] When the baseband module detects that the data of the current signal frame has been transmitted to the memory module and the reception completion signal is in the enabled state, and then starts receiving the next frame of data, it will enable the overflow flag signal to indicate the occurrence of a frame collision.

[0093] Under the current frame collision handling strategy, if the overflow flag signal is in the enabled state, the baseband module will automatically generate an overflow reset signal (overflow-rst). This signal serves as a trigger mechanism, prompting the baseband module to actively perform a reset operation based on this signal. The reset operation refers to the baseband module actively suspending the currently executing processing of the next frame during a frame collision. For example, it can reset baseband deinterleaving, decoding, and other modules. It should be noted that the reset operation does not mean terminating the processing of the next signal frame; its purpose is to stop the current data writing operation to avoid problems such as frame aliasing, frame header misalignment, or control signal lag caused by writing data for the next frame. After collision handling is completed, the baseband module simultaneously sets the previously enabled receive completion signal and overflow reset signal to zero, clearly indicating the end of the collision state, thereby allowing the system to re-enter the synchronized receiving state.

[0094] Figure 7 This is a signal diagram illustrating a frame collision handling strategy provided in some embodiments of the present invention. For example... Figure 7 As shown, if the baseband module does not set the receive completion signal (rx-end-flag) to zero after processing frame 1, and the baseband module detects the frame synchronization signal (frame-synced) of frame 2 at time t1', then the baseband module generates an overflow flag signal (overflow-flag). Based on this overflow flag signal, under the current frame conflict handling strategy, the baseband module also generates an overflow reset signal (overflow-rst). Furthermore, the baseband module performs a reset operation based on this overflow reset signal. Therefore, the baseband module will not perform decoding or other parsing processing on frame 2 data after time t1', and thus will not transmit frame 2 data to the memory module for writing into system memory. The current strategy is a frame conflict handling strategy that discards frame 2 data. Therefore, based on this overflow flag and reset mechanism, the baseband module will not write frame data into system memory, thereby ensuring that frame 1 data is not overwritten by frame 2 data, guaranteeing the integrity of frame 1 data.

[0095] It should be noted that when the baseband module performs frame synchronization detection, the frame 2 data consists of the frame preamble, FC field, and PL field. The frame synchronization position is in the preamble position. Therefore, when the baseband module detects the frame synchronization signal, it has not yet started to move the frame 2 data to the system memory, so there will be no data overwriting.

[0096] In the above embodiments, by actively generating an overflow reset signal after a conflict is detected by the baseband module, and performing buffer clearing and reception termination operations based on this signal, and coordinating the synchronous zeroing of the reception completion signal and the overflow reset signal, a fast closed-loop processing of frame conflict states is achieved. This avoids uncontrollable delays caused by relying on CPU response, ensuring timely handling of conflict states. Furthermore, by clearing the next frame of data and terminating reception, overlapping or overwriting of consecutive frames is avoided, ensuring the integrity of each frame of data. In addition, the entire process is completed independently by the baseband module, without CPU participation, resulting in no response delay. It also completely avoids the problem of delayed conflict response caused by software busyness or scheduling delays. This ensures both the real-time performance of the communication process and the continuity and stability of CPU software tasks. Even when consecutive frames arrive in close succession or the CPU is under high load, the system can still operate stably, achieving efficient and reliable data protection in frame conflict scenarios.

[0097] In other embodiments, the signal receiving device further includes a processing module. The following embodiments further propose a frame collision handling strategy that is collaboratively processed by the processing module.

[0098] Accordingly, in accordance with the frame conflict handling strategy, the frame conflict handling operation related to the current signal frame or the next signal frame is performed based on the overflow flag signal, and further includes: when the overflow flag signal is detected, the processing module stops reading the current signal frame; the processing module sets the receive completion signal to zero in order to read the next signal frame.

[0099] When the processing module detects an overflow flag signal set by the baseband module, it determines that there is a risk of reading the current signal frame and immediately stops reading the current signal frame to prevent the data being extracted from being mixed with subsequent data. At the same time, the processing module can actively set the receive completion signal to zero to release the current frame state and enter the read preparation process for the next signal frame.

[0100] For example, in a scenario involving the reception of a series of consecutive OFDM signal frames, when the baseband module detects the start of frame 2 reception, it has not yet set the reception completion signal corresponding to frame 1 to zero, thus setting the overflow flag. At this point, the CPU, as the processing module, reads this overflow flag in the interrupt response and immediately stops retrieving frame 1 data from system memory to avoid reading the data content of frame 2. Afterwards, the CPU sends a zero-setting instruction to the baseband module, instructing it to set the reception completion signal (Rx-end-flag) to zero, allowing the system to quickly enter the frame 2 data processing flow and avoiding communication backlog.

[0101] Figure 8 This is a signal diagram illustrating another frame collision handling strategy provided in some embodiments of the present invention. For example... Figure 8As shown, if the baseband module does not set the receive completion signal (rx-end-flag) to zero after processing frame 1, and the baseband module detects the frame synchronization signal (frame-synced) of frame 2 at time t1', then the baseband module generates an overflow flag. Based on this overflow flag, under the current frame collision handling strategy, the processing module (such as the CPU) actively terminates the reading operation of frame 1 to avoid extracting invalid data that may have been partially overwritten; subsequently, the processing module sets the receive completion signal to zero to release the read flag of the current frame 1. On this basis, the baseband module continues to complete the receiving processing of frame 2 and writes the data of frame 2 into system memory. After the transmission of frame 2 is completed, the baseband module sets the receive completion signal again at time t3 to indicate that the data of frame 2 is ready. Finally, after the CPU detects that the receive completion signal is high, it switches to reading the data of frame 2 from system memory, completing the data recovery and normal processing flow after the inter-frame collision. In other words, the current strategy is a frame collision handling strategy that discards the data of frame 1.

[0102] Compared to relying entirely on the baseband module to handle conflicts, the mechanism of suspending reading and clearing flags through the processing module effectively solves the problem of misreading conflicting data caused by frame interruption, enhancing the accuracy and scalability of data reception while maintaining the original system architecture.

[0103] In the above embodiments, by interrupting the continued reading of the current frame through the processing module, invalid data is not extracted after the frame data is partially covered, thus improving the effectiveness of the frame data. Furthermore, by actively setting the receiving completion signal to zero, the conflict handling time is shortened, the preparation for processing the next frame data is accelerated, and the overall system processing speed is improved.

[0104] To further improve the reliability of signal reception and data quality in the event of frame collisions, this invention proposes a frame selection mechanism based on channel quality assessment, building upon the aforementioned frame collision handling strategy. This mechanism enables the signal receiving device to automatically determine and retain the frame with better quality between two conflicting frames, avoiding the misselection of low-quality data under channel degradation and improving the overall robustness of the system.

[0105] Therefore, in some other embodiments, according to the frame collision handling strategy, the frame collision handling operation related to the current signal frame or the next signal frame is performed based on the overflow flag signal, which further includes: the baseband module at least completes the reception of the preamble symbol of the next signal frame to evaluate the channel quality corresponding to the next signal frame based on the preamble symbol; the baseband module compares the channel quality corresponding to the next signal frame with the channel quality corresponding to the current signal frame, retains the signal frame with higher channel quality based on the comparison result, and discards the other signal frame.

[0106] Specifically, after detecting a next signal frame that conflicts with the current signal frame, the baseband module in the signal receiving device first receives and parses the preamble symbol in the next signal frame. The preamble symbol, as a channel estimation reference field, possesses strong stability and representativeness. The baseband module can use it to calculate the channel characteristic indicators of the corresponding frame, including but not limited to signal-to-noise ratio (SNR), received signal strength indicator (RSSI), or channel estimation (CE).

[0107] After obtaining the channel quality information of the next signal frame, the baseband module compares and analyzes it with the channel quality of the current signal frame. Based on preset criteria, such as prioritizing maximum SNR and RSSI exceeding a threshold, it determines which frame has better reception conditions. Based on this determination, the frame with higher channel quality is automatically retained for subsequent processing, while the frame with degraded channel quality is discarded to avoid invalid data interference or resource waste.

[0108] In the above embodiments, by introducing a channel quality assessment mechanism into the conflict handling strategy, the signal receiving device can effectively distinguish and select frame data with better reception conditions in high frame density or continuous communication scenarios, avoiding data misuse caused by channel condition fluctuations; at the same time, it reduces the resource burden caused by redundant data processing and improves the overall system's communication reliability and robustness.

[0109] In practical communication systems, the operating load of signal receiving devices is often affected by factors such as upper-layer processing tasks, system buffer usage, and external interrupt frequency. If a fixed frame collision handling strategy is still used under high load conditions, it may be impossible to simultaneously ensure system real-time performance and data integrity. This invention further proposes a load-aware adaptive strategy mechanism, enabling signal receiving devices to dynamically adjust their frame collision handling logic, thereby flexibly balancing data retention strategies and feature information extraction strategies under different operating loads.

[0110] Therefore, in some embodiments, the above method further includes: detecting the load state; automatically selecting different frame collision handling strategies based on the load state to retain the current signal frame or the next signal frame; and determining the reading strategy of the feature information of the current signal frame or the next signal frame based on the selected frame collision handling strategy.

[0111] Specifically, the signal receiving device continuously monitors its load status during operation, which may include indicators such as CPU processing utilization, frame buffer queue depth, and task scheduling latency.

[0112] The signal receiving device determines whether the system is currently under light, medium, or heavy load based on these indicators, and selects the most suitable one from several preset frame collision handling strategies accordingly. For example, under low load, a frame collision handling strategy that retains the current signal frame and discards the next signal frame is preferred. Under high load, a frame collision handling strategy that retains the next signal frame and discards the current signal frame is preferred to reduce congestion and improve processing throughput. If the load is critical or medium, a channel quality optimization strategy can be used to selectively retain the current frame from the next frame.

[0113] In the above embodiments, by introducing a load status perception and processing strategy adaptive mechanism, the signal receiving device's ability to respond flexibly to complex operating environments is enhanced. It can improve the overall processing efficiency and stability of the system while ensuring the integrity of frame data, and is particularly suitable for communication scenarios with dense frame arrivals, high-frequency switching, or frequent interference.

[0114] While the aforementioned frame collision handling strategies can effectively alleviate data coverage issues caused by continuous frame reception, in the normal data reception process, the signal receiving device still needs to extract and retain characteristic information corresponding to each signal frame, such as channel estimates, received signal strength indicators, or signal-to-noise ratios. This characteristic information does not directly participate in the real-time frame collision handling process, but it has important reference value for subsequent tasks such as link quality assessment, communication optimization, and fault analysis performed by upper-layer software. Therefore, in some embodiments, the signal receiving device extracts the characteristic information of the current signal frame while performing frame synchronization, and completes stable latching through a shadow register mechanism to ensure that subsequent tasks can still obtain complete and accurate channel status information under timing uncertainty conditions.

[0115] Figure 9 This is a schematic diagram illustrating the feature information synchronization process provided in some embodiments of the present invention. For example... Figure 9 As shown, after receiving frame data (including preamble, frame control data, and data payload), the baseband module first completes the reception and field parsing of the frame data. During the period from frame synchronization start (sync-begin) to frame synchronization completion (frame-synced), it extracts corresponding feature information, such as channel estimation, received signal strength indication, and signal-to-noise ratio, and writes it into the baseband buffer. Simultaneously, the frame control data and data payload frame data are transferred to the memory module for writing into system memory. For example, the baseband module first performs synchronization detection on the received signal. When three synchronization peaks are detected consecutively, the baseband module generates a sync-begin signal to mark the start of the current frame synchronization process. After the frame synchronization process ends, the baseband module generates a frame-synced signal to indicate the completion of frame synchronization.

[0116] Subsequently, the baseband module sets the receive completion signal (rx-end-flag), transitioning from a low level to a high level, to indicate that the reception and transmission of the current frame data has been completed. Upon detecting this high-level flag, the processing module (i.e., the CPU) begins reading the corresponding frame data from system memory and simultaneously retrieves feature information from the baseband buffer for upper-layer applications to perform network analysis, link evaluation, and other operations. This mechanism ensures the temporal and structural consistency between frame data and feature information, and achieves data synchronization and release control between the baseband and CPU through the receive completion signal, contributing to improved accuracy of upper-layer service processing and overall stability of the communication system.

[0117] During the continuous reception of multiple frames, the baseband module continuously updates the feature information in the baseband buffer, triggered by the frame synchronization start signal. For example, when the baseband module completes feature extraction between sync-begin and frame-synced during the reception of frame 1, the corresponding feature information for frame 1 is written into the buffer. When the baseband module starts receiving frame 2 and detects the sync-begin signal for frame 2, the baseband buffer will begin updating the feature information corresponding to frame 2. Thus, the contents of the baseband buffer are dynamically refreshed as each frame synchronization progresses, achieving real-time maintenance of the feature data of the currently valid frames.

[0118] Figure 10 This is a signal diagram illustrating the feature information synchronization process provided in some embodiments of the present invention. For example... Figure 10 As shown, at time t0, the baseband module begins frame synchronization processing for frame 1. Between the sync-begin and frame-synced states of frame 1 (i.e., time t0 to t0'), it calculates the feature information of frame 1 and writes it into the baseband buffer. Subsequently, at time t1, the data for frame 1 is written to system memory, and the baseband module sets the receive completion signal (rx-end-flag) to notify the processing module (such as the CPU) that the current frame data reception is complete. Ideally, the CPU should respond to the receive completion signal promptly at time t2 and complete the synchronous extraction of the frame 1 data from system memory and the frame 1 feature information from the baseband buffer, thus ensuring a one-to-one correspondence between frame data and feature information. However, in some scenarios, due to delays in CPU or upper-layer software processing, the data extraction operation may not be completed until time t2'. Simultaneously, if the baseband module has already started receiving frame 2 and detects the sync-begin signal of frame 2 at time T1, the frame 1 feature information originally stored in the baseband buffer will be overwritten by the new feature information of frame 2.

[0119] At this point, even if the frame data extracted by the CPU is the complete content of frame 1, its corresponding feature information has already been updated to the content of frame 2, resulting in a mismatch between the frame data and the feature information. If the application processing stage relies on this feature information (e.g., for network topology selection based on signal-to-noise ratio), it may lead to subsequent decision-making errors.

[0120] Therefore, while relying solely on the received completion signal can resolve frame collisions, it cannot guarantee the correct binding of frame data and feature information, and data mismatch is particularly prone to occur in high-concurrency scenarios. Therefore, this invention, based on the aforementioned frame collision handling method for power line carrier signals, introduces a shadow register latching mechanism to further improve the synchronization reliability of feature information.

[0121] Therefore, in some embodiments, the above method further includes: when a frame synchronization start signal is detected, the baseband module calculates the feature information of the current signal frame and writes the calculated feature information of the current signal frame into the baseband buffer; when a frame synchronization completion signal is detected, the baseband module moves the feature information of the current signal frame stored in the baseband buffer to the shadow register for latching, so that subsequent processing modules can read it.

[0122] When the baseband module detects the frame synchronization start signal, it begins to execute the frame feature calculation logic. It extracts key features such as demodulation, energy statistics, signal-to-noise ratio estimation, received power, initial carrier frequency offset, and channel estimation of the received data corresponding to the frame, and writes these feature information into the baseband buffer.

[0123] The baseband cache is a high-speed RAM area in the baseband module used to temporarily store frame-level features that have not yet been latched.

[0124] When a frame synchronization completion signal is detected, indicating that frame synchronization is complete, the baseband module confirms that the synchronization position of the current frame has been determined. The baseband module then immediately moves the calculated feature information from the baseband buffer to the shadow register and performs a latching operation. This shadow register, as a dedicated register area for feature reading, has a write protection mechanism to prevent subsequent frame information from overwriting the data during CPU reading, thereby ensuring the integrity and consistency of the read data.

[0125] It should be noted that the update of the shadow register is not directly controlled by the baseband module, but is achieved automatically through hardware logic such as gate circuits configured within the baseband module. Specifically, the state of the shadow register is automatically triggered by the control logic circuit based on changes in the synchronization signal and the overflow flag signal. Through the state control of the gate circuits, the shadow register can autonomously choose whether to retain the feature information of the current signal frame or update it with the feature information of the next signal frame.

[0126] When the baseband module detects the frame synchronization start signal (sync-begin) for the next signal frame, the shadow register update operation is automatically executed according to a preset synchronization strategy. This update operation relies on the triggering mechanism of the hardware circuit, which controls the write and read paths of the shadow register through gate circuits to ensure that no information conflicts or loss occur during frame data processing.

[0127] Therefore, the state changes of the shadow register are completely controlled by hardware, without relying on the direct intervention of the baseband module or the intervention of external processing modules, thereby improving the response efficiency of the power communication system and ensuring the efficient storage and updating of feature information.

[0128] In the above embodiments, by combining the latching mechanism of the shadow register, data overwriting or conflicts can be prevented during the reading process, improving the stability and accuracy of feature reading. The entire process is executed independently within the baseband module, without waiting for CPU response, effectively improving the system's processing efficiency for frame features.

[0129] Based on the aforementioned feature information synchronization and transfer mechanism, this invention further constrains the update control strategy of the shadow register in overflow scenarios to ensure that the feature information of the current signal frame is not overwritten.

[0130] Therefore, in some embodiments, the above method further includes: after detecting that the next signal frame has completed frame synchronization, if the overflow flag signal is in the enabled state, the shadow register is not updated to maintain the latched feature information of the current signal frame; the processing module reads the feature information of the current signal frame in the shadow register and sets the reception completion signal to zero to complete the processing of the current signal frame and discard the next signal frame.

[0131] When the baseband module detects that the next signal frame has completed frame-syncing, if the overflow flag is enabled at this time, the shadow register will not update the currently stored data, thereby preventing the feature information of the current frame from being overwritten.

[0132] In this conflict state, the processing module directly extracts the feature information of the current signal frame from the shadow register, and sets the receive completion signal (rx-end-flag) to zero after extraction to terminate the processing flow of the current frame and discard the next frame.

[0133] In this embodiment, the update of the shadow register is controlled by the combined judgment of the overflow signal and the synchronization status. The update is only allowed when the predetermined conditions are met, thereby ensuring that the latched feature information always corresponds one-to-one with the frame data processed by the CPU and avoiding incorrect binding.

[0134] In the above embodiments, by not updating the shadow register when the overflow flag is enabled, the problem of the feature information of the next signal frame incorrectly overwriting the current feature information can be effectively avoided. This ensures that the system can still extract the feature information that correctly corresponds to the frame data in data conflict scenarios. This mechanism improves the stability and consistency of software processing, avoids abnormal processing or business judgment errors in upper-layer applications caused by feature data mismatch, and is especially suitable for scenarios with high requirements for physical layer accuracy, such as power line carrier communication, smart meter reading, and communication protocol analysis.

[0135] In other embodiments, the method further includes: after starting frame synchronization for the next signal frame, the baseband module calculates the feature information of the next signal frame and writes the calculated feature information of the next signal frame into the baseband buffer; after detecting that the next signal frame has completed frame synchronization, if the overflow flag signal is in the enabled state, the baseband module moves the feature information of the next signal frame stored in the baseband buffer to the shadow register for latching, so as to overwrite the feature information of the current signal frame; the processing module reads the feature information of the next signal frame in the shadow register and sets the receive completion signal to zero, so as to complete the processing of the next signal frame and discard the current signal frame.

[0136] When the baseband module begins performing frame synchronization for the next signal frame, it synchronously calculates the feature information of the next frame and writes this feature information into the baseband buffer. If frame synchronization for the next signal frame is detected (i.e., a frame-synced signal is detected) and the overflow flag is enabled, the baseband module performs a feature information shifting operation, writing the next feature information from the buffer into the shadow register, thereby overwriting the feature data of the current signal frame.

[0137] The processing module then reads the latest feature information (i.e. the next feature information) from the shadow register, and sets the receive completion signal (rx-end-flag) to zero after reading, thereby terminating the processing of the current frame and taking over the feature data of the next frame.

[0138] This embodiment demonstrates a proactive overlay conflict handling strategy. When the integrity or consistency of the current frame cannot be guaranteed, the synchronization feature information of the next frame is retained and the current frame is discarded, thus avoiding the impact on subsequent tasks due to processing delays or incorrect feature binding.

[0139] In the above embodiments, by actively shifting the feature information of the next frame and overwriting the original information in the overflow state, it is beneficial to reduce the frame loss rate and data mismatch probability caused by synchronization conflict, and improve the stability and processing flexibility of the system in the frame conflict scenario. It is especially suitable for high-speed communication, dense networking or bandwidth-limited power line carrier communication scenarios.

[0140] Figure 11 This is a signal diagram illustrating the feature information synchronization process provided in some embodiments of the present invention. For example... Figure 11 As shown, based on the existing baseband cache structure, this invention adds a shadow register (or shadow memory) to specifically store feature information, ensuring the correctness and readability of frame feature data in conflict states or software latency scenarios. Compared to Figure 9 As shown, the shadow register provides a stable copy of feature information for extraction and use by the CPU or upper-level processing modules.

[0141] refer to Figure 10 As shown in the timing diagram, when the baseband module detects the sync-begin signal of frame 1 (at time t0), i.e., when multiple synchronization peaks are detected consecutively, the baseband module begins processing such as channel estimation, calculates the feature information of frame 1, and writes it into the baseband buffer. This process continues until the frame-synced signal of frame 1 is detected, i.e., at time t0'. When the baseband module detects the frame-synced signal of frame 1 at time t0', the baseband module immediately controls the shadow register to read the feature information of the current frame (frame 1) from the baseband buffer and latches it. At this time, the shadow register stores consistent feature information corresponding to the frame 1 data in the system memory.

[0142] When frame 1 data is successfully transmitted to system memory (at time t1), the baseband module sets up the receive completion signal (rx-end-flag) to notify the CPU that the frame data can be read. When the baseband detects the sync-begin signal for frame 2 at time T1, it begins to recalculate and update the feature information of frame 2. If the CPU has not yet completed extracting the frame 1 data at this time, there is a risk that the frame feature data may be overwritten.

[0143] In conjunction with the above embodiments Figure 7 The provided frame conflict handling strategy detects an overflow flag being set at time t1' (i.e., when frame 2 synchronization is complete). In this case, the baseband module disables the shadow register update, preserving the characteristic information of frame 1. Even if the CPU delays data reading at time t2', the characteristic information obtained from the shadow register remains consistent with the data in frame 1.

[0144] In conjunction with the above embodiments Figure 8The proposed frame conflict handling strategy triggers a feature shift operation if an overflow flag is detected at time t1'. The baseband module then updates the shadow register with the feature information of frame 2 to align with the system's frame conflict handling strategy that preserves frame 2 data. When the CPU subsequently completes the reading of frame 2 data (e.g., at time t3), it can obtain the corresponding frame 2 feature information from the shadow register, ensuring data consistency. This effectively solves the problem of frame data and feature information mismatch caused by software latency in traditional architectures, further improving data consistency and application reliability of signal receiving devices in high-concurrency scenarios.

[0145] Unlike related technologies where the CPU directly accesses the baseband cache, in this invention, the CPU reads feature information from the shadow register to ensure that the extracted frame data and feature information correspond one-to-one, avoiding data mismatch caused by cache overwriting. After reading is complete, the CPU or upper-layer application sets the reception completion signal (rx-end-flag) to zero to end the current processing cycle.

[0146] The above mechanism is particularly suitable for scenarios that require high communication reliability, have complex meter networking, and are subject to significant power line noise interference, such as the networking application of power line carrier communication chips.

[0147] The frame collision handling method for power line carrier signals provided in this embodiment of the invention can be executed by a frame collision handling device. This embodiment of the invention uses the execution of the frame collision handling method for power line carrier signals by a frame collision handling device as an example to illustrate the frame collision handling device provided in this embodiment of the invention.

[0148] This invention also provides a frame collision processing device, applied to a signal receiving device.

[0149] Figure 12 This is a schematic diagram of the frame collision processing apparatus provided in some embodiments of the present invention. For example... Figure 12 As shown, the frame collision processing device includes a signal triggering module 1201, a collision triggering module 1202, and a collision processing module 1203. Wherein:

[0150] The signal triggering module 1201 is used to set up a reception completion signal to indicate the reception completion status after the baseband module has completed receiving the current signal frame and transmitting the current signal frame data to the memory module.

[0151] The conflict triggering module 1202 is used to set up the overflow flag signal if the baseband module detects the frame synchronization completion signal while the reception completion signal is in the set state; the overflow flag signal is used to indicate that the processing state of the current signal frame conflicts with the reception behavior of the next signal frame.

[0152] The conflict handling module 1203 is used to perform frame conflict handling operations related to the current signal frame or the next signal frame based on the overflow flag signal according to the frame conflict handling strategy.

[0153] The frame conflict handling apparatus provided in this embodiment of the invention, after the baseband module completes the reception of the current signal frame and transmits the data of the current signal frame to the memory module, sets up the reception completion signal, thereby clearly defining the state between frame reception and processing, facilitating the processing module's determination of data reading timing. While the reception completion signal is in the set-up state, if the baseband module detects a frame synchronization completion signal, it sets up the overflow flag signal, enabling timely detection of the next frame's access behavior and generating a flag signal for alarm. This achieves rapid and automatic identification of conflict states without waiting for processor intervention or polling, eliminating reliance on interrupt responses or software scheduling mechanisms. Furthermore, according to the frame conflict handling... The strategy, based on the overflow flag signal, performs frame collision handling operations related to the current signal frame or the next signal frame. The baseband module automatically triggers the collision strategy, supporting automatic frame collision handling within the hardware without the need for processor intervention in judgment and control signal initiation. This reduces control path latency, improves robustness and overall processing efficiency in high-speed reception scenarios, and by introducing configurable or dynamically selectable collision handling strategies, it supports flexible handling of conflicts between current frame retention and next frame reception according to application requirements, improving system adaptability and processing efficiency. It can effectively reduce the risk of data loss and state disorder caused by frame collisions, and improve the reliability and processing efficiency of the system in high-density reception scenarios.

[0154] In some embodiments, the conflict handling module is further configured to generate an overflow reset signal for triggering an interrupt when the overflow flag signal is in the enabled state; perform a reset operation in response to the overflow reset signal to stop processing the next frame of data; and set the receive completion signal and the overflow reset signal to zero to end the conflict state between the current signal frame and the next signal frame.

[0155] In some embodiments, the conflict handling module is further configured to, upon detecting an overflow flag signal, suspend the reading operation of the current signal frame; set the receive completion signal to zero, and read the next signal frame.

[0156] In some embodiments, the conflict handling module is further configured to at least complete the reception of the preamble symbol of the next signal frame, so as to evaluate the channel quality corresponding to the next signal frame based on the preamble symbol; compare the channel quality corresponding to the next signal frame with the channel quality corresponding to the current signal frame, retain the signal frame with higher channel quality based on the comparison result, and discard the other signal frame.

[0157] In some embodiments, the conflict triggering module is further configured to, by monitoring the synchronization sequence in the input signal, generate a frame synchronization start signal when a synchronization sequence matching a preset frame format is detected, indicating that frame synchronization detection for the next signal frame has been initiated; and after confirming the frame synchronization position, generate a frame synchronization completion signal, which indicates that the currently received next signal frame has completed the synchronization process.

[0158] In some embodiments, the above-described apparatus further includes a frame feature synchronization module, which is used to calculate the feature information of the current signal frame when a frame synchronization start signal is detected, and write the calculated feature information of the current signal frame into a baseband buffer; when a frame synchronization completion signal is detected, the feature information of the current signal frame stored in the baseband buffer is moved to a shadow register for latching, so that subsequent processing modules can read it.

[0159] In some embodiments, the frame feature synchronization module is further configured to, after detecting that the next signal frame has completed frame synchronization, if the overflow flag signal is in the enabled state, not update the shadow register so as to maintain the latched feature information of the current signal frame; read the feature information of the current signal frame in the shadow register and set the reception completion signal to zero so as to complete the processing of the current signal frame and discard the next signal frame.

[0160] In some embodiments, the frame feature synchronization module is further configured to calculate the feature information of the next signal frame after starting frame synchronization for the next signal frame, and write the calculated feature information of the next signal frame into the baseband buffer; after detecting that the next signal frame has completed frame synchronization, if the overflow flag signal is in the enabled state, the feature information of the next signal frame stored in the baseband buffer is moved to the shadow register for latching to overwrite the feature information of the current signal frame; the feature information of the next signal frame in the shadow register is read, and the reception completion signal is set to zero to complete the processing of the next signal frame and discard the current signal frame.

[0161] In some embodiments, the above-described apparatus further includes a detection module for detecting load status; automatically selecting different frame conflict handling strategies based on the load status to retain the current signal frame or the next signal frame; and determining a reading strategy for the feature information of the current signal frame or the next signal frame based on the selected frame conflict handling strategy.

[0162] The frame collision processing apparatus provided in this embodiment of the invention can implement the various processes implemented in each method embodiment. To avoid repetition, it will not be described again here.

[0163] The frame collision handling device in this embodiment of the invention can be a signal receiving device or a component within the signal receiving device, such as an integrated circuit or a chip. The signal receiving device is a computer device, such as a terminal device.

[0164] This invention also provides a signal receiving device. Figure 13 This is a schematic diagram of the structure of a signal receiving device provided in some embodiments of the present invention. For example... Figure 13 As shown, the signal receiving device 1300 includes a baseband module 1301, a memory module 1302, and a processing module 1303. Wherein:

[0165] The baseband module 1301 is used to set up a reception completion signal to indicate the reception completion status after completing the reception of the current signal frame and transmitting the current signal frame to the memory module.

[0166] The baseband module 1301 is also configured to set an overflow flag signal if the reception of the next signal frame is detected to begin while the reception completion signal is in the set state; the overflow flag signal is used to indicate that the processing state of the current signal frame conflicts with the reception behavior of the next signal frame.

[0167] The baseband module 1301 or the processing module 1303 is used to perform frame conflict processing operations related to the current frame or the next frame based on the overflow flag signal and in accordance with the frame conflict processing strategy.

[0168] The memory module 1302 is used to receive and store the data transmitted by the baseband module for subsequent reading and processing by the processing module.

[0169] The signal receiving device provided in this embodiment of the invention can implement the various processes implemented in each method embodiment. To avoid repetition, it will not be described again here.

[0170] This invention also provides a non-transitory computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the various processes of the above-described power line carrier signal frame collision handling method embodiments and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0171] The processor is the processor in the computer device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0172] This invention also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method for handling frame collisions of power line carrier signals.

[0173] The processor is the processor in the computer device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0174] This invention also provides a chip, which includes a processor and a communication interface. The communication interface and the processor are coupled. The processor is used to run programs or instructions to implement the various processes of the above-described power line carrier signal frame collision processing method embodiments and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0175] It should be understood that the chip mentioned in the embodiments of the present invention may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0176] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of the present invention is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0177] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the related technology, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0178] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of the present invention.

[0179] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0180] Unless otherwise specified, all embodiments and optional embodiments of the present invention can be combined with each other to form new technical solutions.

[0181] Unless otherwise specified, all technical features and optional technical features of this invention can be combined to form new technical solutions.

[0182] Unless otherwise specified, all steps of the present invention may be performed sequentially or randomly, preferably sequentially. For example, the method includes steps (a) and (b), indicating that the method may include steps (a) and (b) performed sequentially, or it may include steps (b) and (a) performed sequentially. For example, the mention that the method may also include step (c) indicates that step (c) may be added to the method in any order; for example, the method may include steps (a), (b), and (c), or it may include steps (a), (c), and (b), or it may include steps (c), (a), and (b), etc.

[0183] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A method for handling frame collisions in power line carrier signals, characterized in that, Applied to a signal receiving device, the signal receiving device including a baseband module and a memory module; the method includes: After the baseband module completes the reception of the current signal frame and transmits the current signal frame to the memory module, it sets up the reception completion signal to indicate the reception completion status. During the period when the reception completion signal is in the enabled state, if the baseband module detects the frame synchronization completion signal, it enables the overflow flag signal; the overflow flag signal is used to indicate that the processing state of the current signal frame conflicts with the reception behavior of the next signal frame. According to the frame conflict handling strategy, frame conflict handling operations related to the current signal frame or the next signal frame are performed based on the overflow flag signal.

2. The frame collision handling method for power line carrier signals according to claim 1, characterized in that, The step of performing frame collision handling operations related to the current signal frame or the next signal frame based on the overflow flag signal according to the frame collision handling strategy includes: When the overflow flag signal is enabled, the baseband module generates an overflow reset signal to trigger an interrupt; In response to the overflow reset signal, the baseband module performs a reset operation to stop processing the next frame of data; The baseband module sets the receive completion signal and the overflow reset signal to zero to end the conflict state between the current signal frame and the next signal frame.

3. The frame collision handling method for power line carrier signals according to claim 1, characterized in that, The signal receiving device further includes a processing module; the step of performing frame collision processing operations related to the current signal frame or the next signal frame based on the overflow flag signal according to the frame collision processing strategy further includes: Upon detecting the overflow flag signal, the processing module suspends the reading operation of the current signal frame; The processing module sets the received signal to zero in order to read the next signal frame.

4. The frame collision handling method for power line carrier signals according to claim 1, characterized in that, The step of performing frame collision handling operations related to the current signal frame or the next signal frame based on the overflow flag signal according to the frame collision handling strategy further includes: The baseband module at least completes the reception of the preamble symbol of the next signal frame in order to evaluate the channel quality corresponding to the next signal frame based on the preamble symbol; The baseband module compares the channel quality corresponding to the next signal frame with the channel quality corresponding to the current signal frame. Based on the comparison result, it retains the signal frame with higher channel quality and discards the other signal frame.

5. The frame collision handling method for power line carrier signals according to claim 1, characterized in that, The baseband module detects a frame synchronization completion signal, including: The baseband module monitors the synchronization sequence in the input signal. When it detects a synchronization sequence that matches the preset frame format, it generates a frame synchronization start signal to indicate that frame synchronization detection for the next signal frame has been initiated. After confirming the frame synchronization position, the baseband module generates a frame synchronization completion signal, which indicates that the next received signal frame has completed the synchronization process.

6. The method for handling frame collisions of power line carrier signals according to claim 1 or 5, characterized in that, The method further includes: When a frame synchronization start signal is detected, the baseband module calculates the feature information of the current signal frame and writes the calculated feature information of the current signal frame into the baseband buffer. When a frame synchronization completion signal is detected, the baseband module moves the feature information of the current signal frame stored in the baseband buffer to the shadow register for latching, so that subsequent processing modules can read it.

7. The frame collision handling method for power line carrier signals according to claim 6, characterized in that, The method further includes: After the next signal frame is detected to have completed frame synchronization, if the overflow flag signal is in the enabled state, the shadow register will not be updated in order to maintain the characteristic information of the current signal frame. The processing module reads the feature information of the current signal frame from the shadow register and sets the receive completion signal to zero to complete the processing of the current signal frame and discard the next signal frame.

8. The frame collision handling method for power line carrier signals according to claim 6, characterized in that, The method further includes: After starting frame synchronization for the next signal frame, the baseband module calculates the feature information of the next signal frame and writes the calculated feature information of the next signal frame into the baseband buffer. After detecting that the next signal frame has completed frame synchronization, if the overflow flag signal is in the enabled state, the baseband module will move the feature information of the next signal frame stored in the baseband buffer to the shadow register for latching, so as to overwrite the feature information of the current signal frame. The processing module reads the feature information of the next signal frame from the shadow register and sets the reception completion signal to zero to complete the processing of the next signal frame and discard the current signal frame.

9. The frame collision handling method for power line carrier signals according to claim 1, characterized in that, The method further includes: Detect load status; Based on the load status, different frame conflict handling strategies are automatically selected to retain the current signal frame or the next signal frame, and based on the selected frame conflict handling strategy, the reading strategy of the feature information of the current signal frame or the next signal frame is determined.

10. A frame collision processing apparatus for power line carrier signals, characterized in that, Applied to a signal receiving device, the device includes: The signal triggering module is used to set up a reception completion signal to indicate the reception completion status after the baseband module has completed receiving the current signal frame and transmitting the current signal frame data to the memory module. The conflict triggering module is used to set up the overflow flag signal if the baseband module detects the frame synchronization completion signal while the reception completion signal is in the set state; the overflow flag signal is used to indicate that the processing state of the current signal frame conflicts with the reception behavior of the next signal frame. The conflict handling module is used to perform frame conflict handling operations related to the current signal frame or the next signal frame based on the overflow flag signal, according to the frame conflict handling strategy.

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