High-linearity switch low-noise amplifier with logic control

Abstract

The invention relates to the technical field of low-noise amplifiers, and discloses a high-linearity switch low-noise amplifier with logic control, which comprises an LNA channel circuit, a Bypass channel circuit, a TX channel circuit and a logic control circuit, the LNA channel circuit comprises a serial-parallel switch unit, an amplifier adopting a Cascode combined nonlinear cancellation structure, and a biasing circuit; the Bypass channel circuit comprises two paths of switching tubes which are connected in series and are used for variable gain switching, and a pi-type attenuator; the TX channel circuit comprises double-gate switch tubes connected in series and double-gate switch tube groups stacked in parallel; and the logic control circuit controls the states of switching tubes in the LNA channel circuit, the Bypass channel circuit and the TX channel circuit through the first logic level and the second logic level so as to perform channel switching. According to the invention, by adopting a specific switch architecture in each channel, the isolation among the three channels is improved, so that the three channels have better linearity and radio frequency performance in an LNA mode, a Bypass mode and a TX mode respectively.

Description

Technical Field

[0001] The present invention relates to the technical field of low noise amplifiers, and in particular to a high linearity switching low noise amplifier with logic control. Background Art

[0002] High-performance switching low-noise amplifiers (LNAs) are an inevitable product of the development of wireless communications towards high frequency, high speed, and high integration. Their core is to achieve high linearity, low noise, and fast-switching RF front-end performance through advanced semiconductor processes and circuit design. Current wireless communication systems are increasingly demanding data rates and bandwidths. Higher-order modulation schemes are more sensitive to signal purity, and any nonlinear distortion reduces modulation accuracy and increases bit error rates. Furthermore, the application of Multiple-Input Multiple-Output (MIMO) technology requires independent LNAs and switches for each antenna channel, driving demand for highly integrated components and, consequently, the need for even higher performance from switching LNAs.

[0003] The LNA mode amplifies weak signals while minimizing noise and avoiding signal distortion. However, with today's high-order modulation signals, the linearity requirements for low-noise amplifiers are extremely high. Conventional cascodes cannot meet the linearity requirements for higher-order modulation signals. Summary of the Invention

[0004] To address the above-mentioned deficiencies in the prior art, the present invention provides a high-linearity switching low-noise amplifier with logic control. By adopting a specific switching architecture in each channel, the isolation between the three channels is improved, resulting in good linearity and RF performance in LNA mode, Bypass mode, and TX mode. Furthermore, a specific logic circuit is used to switch between the three modes by controlling two logic levels.

[0005] In order to achieve the above-mentioned object of the invention, the technical solution adopted by the present invention is: A high-linearity switching low-noise amplifier with logic control, comprising: LNA channel circuit, Bypass channel circuit, TX channel circuit and logic control circuit; The LNA channel circuit includes a serial-parallel switch unit, an amplifier using a cascode combined with a nonlinear cancellation structure, and a bias circuit; The Bypass channel circuit includes two series-connected switching tubes for variable gain switching and a π-type attenuator; The TX channel circuit includes a series-connected dual-gate switch tube and a parallel-connected stacked dual-gate switch tube group; The logic control circuit controls the states of the switch tubes in the LNA channel circuit, the Bypass channel circuit and the TX channel circuit through the first logic level and the second logic level to perform channel switching.

[0006] Furthermore, the amplifier using the Cascode combined with the nonlinear cancellation structure includes: a first amplifying tube, a second amplifying tube, and a third amplifying tube; The gate of the first amplifier tube is connected to the bias voltage terminal and is connected to the gate of the third amplifier tube via a sixth capacitor; the drain of the first amplifier tube is connected to the source of the second amplifier tube and the drain of the third amplifier tube respectively; the source of the first amplifier tube is connected to the source of the third amplifier tube and is grounded via a first inductor; The gate of the second amplifier tube is connected to the bias voltage terminal and is grounded via the first resistor and the eighth capacitor connected in series; the drain of the second amplifier tube is grounded via the second inductor and the seventh capacitor connected in series; The grid of the third amplifier tube is connected to the bias voltage terminal.

[0007] Furthermore, the series-parallel switch unit includes: a fifth switching tube, a sixth switching tube, and a seventh switching tube; The control terminals of the fifth switch tube, the sixth switch tube and the seventh switch tube are respectively connected to the logic control circuit; The output end of the fifth switching tube is connected to the input end of the sixth switching tube, and is connected to the gate of the first amplifier tube through the fifth capacitor; The output end of the sixth switch tube is grounded via a fourth capacitor; The input end of the seventh switch tube is connected to the drain of the second amplifier tube via a ninth capacitor; the output end of the seventh switch tube is connected to the RX output end via a tenth capacitor.

[0008] Furthermore, the bypass channel circuit includes: an eighth switching tube, a ninth switching tube, a tenth switching tube, and an eleventh switching tube; The control terminals of the eighth switch tube, the ninth switch tube, the tenth switch tube and the eleventh switch tube are respectively connected to the logic control circuit; The output end of the eighth switching tube is connected to the input end of the tenth switching tube and the input end of the eleventh switching tube respectively; The output end of the tenth switching tube is connected to one end of the second resistor; the other end of the second resistor is connected to the input end of the ninth switching tube and is grounded via the third resistor and the eleventh capacitor connected in series; The output end of the eleventh switching tube is connected to the input end of the ninth switching tube; The output end of the ninth switch tube is connected to the RX output end via the twelfth capacitor.

[0009] Furthermore, the TX channel circuit includes: a second switching tube, a third switching tube, and a fourth switching tube; The control terminal of the second switch tube and the parallel control terminals of the third switch tube and the fourth switch tube are respectively connected to the logic control circuit; The output end of the second switch tube is connected to the input end of the third switch tube and one end of the second capacitor respectively; the other end of the second capacitor is connected to the TX input end; The output end of the third switch tube is connected to the input end of the fourth switch tube; The output end of the fourth switch tube is grounded via the third capacitor.

[0010] Furthermore, it also includes a first switching tube; The control end of the first switch tube is connected to the logic control circuit; The input end of the first switch tube is connected to the input end of the second switch tube, and is connected to the ANT signal end through the first capacitor; the output end of the first switch tube is respectively connected to the input end of the fifth switch tube and the input end of the eighth switch tube.

[0011] Furthermore, the logic control circuit includes: a first transistor and a second transistor; The drain of the first transistor is connected to the drain of the second transistor, and is connected to the control terminals of the eighth and ninth switching transistors, and the source and gate of the ninth transistor; the sources of the first and second transistors are both grounded; the gate of the second transistor is connected to the LNA enable input terminal; the gate of the first transistor is connected to the TX enable input terminal, and is connected to the gates of the fourth, sixth, and sixteenth transistors, respectively; The source of the fourth transistor is grounded; the drain of the fourth transistor is connected to the control terminal of the first switch tube and the parallel control terminal of the third switch tube and the fourth switch tube, and is respectively connected to the source and gate of the third transistor; The source of the sixth transistor is grounded; the drain of the sixth transistor is connected to the source and gate of the fifth transistor respectively, and is connected to the gate of the eighth transistor; The source of the eighth transistor is grounded; the drain of the eighth transistor is connected to the source and gate of the seventh transistor respectively, and is connected to the control terminal of the second switch tube; The drain of the sixteenth transistor is connected to the drain of the seventeenth transistor, the gates of the twelfth transistor and the fourteenth transistor, and is respectively connected to the source and gate of the eighteenth transistor; The source of the twelfth transistor is grounded; the drain of the twelfth transistor is connected to the source and gate of the thirteenth transistor respectively, and is connected to the gate of the tenth transistor; The source of the tenth transistor is grounded; the drain of the tenth transistor is connected to the source and gate of the eleventh transistor respectively, and is connected to the parallel control terminals of the fifth switch tube and the seventh switch tube; The source of the fourteenth transistor is grounded; the drain of the fourteenth transistor is connected to the source and gate of the fifteenth transistor respectively, and is connected to the bias voltage terminal; The source of the sixteenth transistor is grounded; the drain of the sixteenth transistor is connected to the source and gate of the eighteenth transistor respectively, and is connected to the gate of the seventeenth transistor; The source of the seventeenth transistor is grounded; the gate of the seventeenth transistor is connected to the drain of the nineteenth transistor and to the source and gate of the twentieth transistor; The source of the nineteenth transistor is grounded; the gate of the nineteenth transistor is connected to the LNA enable input terminal.

[0012] Furthermore, the logic control circuit includes: a twenty-first transistor and a twenty-second transistor; The source of the twenty-first transistor is grounded; the gate of the twenty-first transistor is connected to the bypass selection terminal and to the gate of the twenty-second transistor; the drain of the twenty-first transistor is connected to the control terminal of the tenth switch tube and to the source and gate of the twenty-fourth transistor respectively; The source of the twenty-second transistor is grounded; the drain of the twenty-second transistor is connected to the gate of the twenty-third transistor, and is connected to the source and gate of the twenty-fifth transistor respectively; The source of the twenty-third transistor is grounded; the drain of the twenty-third transistor is connected to the control end of the eleventh switch tube, and is respectively connected to the source and gate of the twenty-sixth transistor.

[0013] The present invention has the following beneficial effects: The present invention's LNA Mode and TX Mode both utilize serial-parallel switching, while the Bypass Mode employs two series-connected switching transistors for variable gain switching. This structure provides high isolation between the three modes, ensuring that when operating in any mode, other paths do not significantly impact the performance of the current mode, improving linearity and RF performance in each mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a functional block diagram of a high-linearity switching low-noise amplifier provided by an embodiment of the present invention.

[0015] Figure 2 This is a schematic diagram of a logic control circuit provided by an embodiment of the present invention.

[0016] Figure 3 This is a schematic diagram of the logic control circuit for switching the bypass attenuation channels provided by an embodiment of the present invention.

[0017] Figure 4This is an AMAM curve diagram of the LNA channel provided by an embodiment of the present invention.

[0018] Figure 5 This is an AMPM curve diagram of the LNA channel provided by an embodiment of the present invention.

[0019] Figure 6 This is an AMAM curve diagram of the Bypass large and small attenuation channels provided by an embodiment of the present invention.

[0020] Figure 7 This is an AMPM curve diagram of the Bypass large and small attenuation channels provided by an embodiment of the present invention.

[0021] Figure 8 This is a TX channel amplitude distortion AMAM curve diagram provided by an embodiment of the present invention.

[0022] Figure 9 This is an AMPM curve diagram of the TX channel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The specific embodiments of the present invention are described below to facilitate understanding of the present invention by those skilled in the art. However, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, these changes are obvious, and all inventions and creations utilizing the concepts of the present invention are protected.

[0024] like Figure 1 As shown, an embodiment of the present invention provides a high-linearity switching low-noise amplifier with logic control, comprising: LNA channel circuit, Bypass channel circuit, TX channel circuit and logic control circuit; The LNA channel circuit includes a serial-parallel switch unit, an amplifier using a cascode combined with a nonlinear cancellation structure, and a bias circuit; The Bypass channel circuit includes two series-connected switching tubes for variable gain switching and a π-type attenuator; The TX channel circuit includes a series-connected dual-gate switch tube and a parallel-connected stacked dual-gate switch tube group; The logic control circuit controls the states of the switch tubes in the LNA channel circuit, the Bypass channel circuit and the TX channel circuit through the first logic level and the second logic level to perform channel switching.

[0025] This embodiment includes three modes: LNA mode, Bypass mode, and TX mode. The LNA channel consists of a switch, a cascode combined with a cancellation structure, and its bias circuit; the Bypass mode consists of two channels, a low attenuation mode and a high attenuation mode, switched by a switch; the TX channel consists of a series-connected dual-gate switch and a parallel-stacked dual-gate switch. Switching between the three modes is achieved by a specific logic circuit using two logic control levels. By adopting a specific series-parallel switch structure for each channel, the present invention achieves high isolation between the three channels, enabling optimal linearity and RF characteristics in each mode.

[0026] In an optional embodiment of the present invention, an amplifier using a cascode combined with a nonlinear cancellation structure includes: a first amplifying tube, a second amplifying tube, and a third amplifying tube; The gate of the first amplifier tube is connected to the bias voltage terminal and is connected to the gate of the third amplifier tube via a sixth capacitor; the drain of the first amplifier tube is connected to the source of the second amplifier tube and the drain of the third amplifier tube respectively; the source of the first amplifier tube is connected to the source of the third amplifier tube and is grounded via a first inductor; The gate of the second amplifier tube is connected to the bias voltage terminal and is grounded via the first resistor and the eighth capacitor connected in series; the drain of the second amplifier tube is grounded via the second inductor and the seventh capacitor connected in series; The grid of the third amplifier tube is connected to the bias voltage terminal.

[0027] The series-parallel switch unit includes: a fifth switching tube, a sixth switching tube, and a seventh switching tube; The control terminals of the fifth switch tube, the sixth switch tube and the seventh switch tube are respectively connected to the logic control circuit; The output end of the fifth switching tube is connected to the input end of the sixth switching tube, and is connected to the gate of the first amplifier tube through the fifth capacitor; The output end of the sixth switch tube is grounded via a fourth capacitor; The input end of the seventh switch tube is connected to the drain of the second amplifier tube via a ninth capacitor; the output end of the seventh switch tube is connected to the RX output end via a tenth capacitor.

[0028] In this embodiment, the LNA channel utilizes a cascode amplifier and nonlinear cancellation architecture. The main and auxiliary amplifiers work in tandem, leveraging the phase opposition of their third-order nonlinear components to achieve active distortion cancellation. The cascode architecture improves gain stability through cascaded amplification, while the auxiliary tube bias is independently adjusted to dynamically balance nonlinear terms. This allows weak signal amplification to maintain a low noise figure while significantly suppressing phase and amplitude distortion. The channel switch and physical isolation design ensure no signal leakage when other modes are disabled, achieving highly linear and low-noise RF signal amplification.

[0029] In this embodiment, both LNA Mode and TX Mode utilize serial-parallel switching, while Bypass Mode employs two series-connected switching transistors for variable gain switching. This architecture provides high isolation between the three modes, ensuring that when operating in any mode, the other paths do not significantly impact the performance of the current mode, thereby improving linearity and RF performance in each mode.

[0030] In an optional embodiment of the present invention, the bypass channel circuit includes: an eighth switching tube, a ninth switching tube, a tenth switching tube, and an eleventh switching tube; The control terminals of the eighth switch tube, the ninth switch tube, the tenth switch tube and the eleventh switch tube are respectively connected to the logic control circuit; The output end of the eighth switching tube is connected to the input end of the tenth switching tube and the input end of the eleventh switching tube respectively; The output end of the tenth switching tube is connected to one end of the second resistor; the other end of the second resistor is connected to the input end of the ninth switching tube and is grounded via the third resistor and the eleventh capacitor connected in series; The output end of the eleventh switching tube is connected to the input end of the ninth switching tube; The output end of the ninth switch tube is connected to the RX output end via the twelfth capacitor.

[0031] In this embodiment, the bypass channel includes two paths: low-attenuation and high-attenuation. Variable signal attenuation is achieved through a π-type attenuation network combined with a switch. The low-attenuation path uses a low-insertion-loss switch for direct signal transmission, while the high-attenuation path uses a resistor network to reduce signal strength. Independent switches control the switching between the two paths. The isolation between the channel switch and the LNA stage prevents parasitic capacitance coupling between the amplifiers, ensuring low-distortion transmission even when strong input signals bypass the LNA, preventing amplitude compression and phase distortion caused by signal saturation.

[0032] In an optional embodiment of the present invention, the TX channel circuit includes: a second switching tube, a third switching tube, and a fourth switching tube; The control terminal of the second switch tube and the parallel control terminals of the third switch tube and the fourth switch tube are respectively connected to the logic control circuit; The output end of the second switch tube is connected to the input end of the third switch tube and one end of the second capacitor respectively; the other end of the second capacitor is connected to the TX input end; The output end of the third switch tube is connected to the input end of the fourth switch tube; The output end of the fourth switch tube is grounded via the third capacitor.

[0033] In an optional embodiment of the present invention, this embodiment further includes a first switching tube; The control end of the first switch tube is connected to the logic control circuit; The input end of the first switch tube is connected to the input end of the second switch tube, and is connected to the ANT signal end through the first capacitor; the output end of the first switch tube is respectively connected to the input end of the fifth switch tube and the input end of the eighth switch tube.

[0034] In this embodiment, the TX channel utilizes a combination of series dual-gate switches and parallel stacked switches. The series switches provide a low-impedance main path, while the parallel stacked switches form a distributed grounding network. When the transmit signal is transmitted through the series switches, the stacked switches reduce the voltage stress on individual transistors through multi-stage voltage division, suppressing gate breakdown or parasitic conduction caused by high-power signals. This structure efficiently transmits high-power signals in the transmit state while preventing reverse leakage to the receiver through physical isolation, thus ensuring the linearity and power integrity of the transmit link.

[0035] In an optional embodiment of the present invention, Figure 2 As shown, the logic control circuit includes: a first transistor and a second transistor; The drain of the first transistor is connected to the drain of the second transistor, and is connected to the control terminals of the eighth and ninth switching transistors, and the source and gate of the ninth transistor; the sources of the first and second transistors are both grounded; the gate of the second transistor is connected to the LNA enable input terminal; the gate of the first transistor is connected to the TX enable input terminal, and is connected to the gates of the fourth, sixth, and sixteenth transistors, respectively; The source of the fourth transistor is grounded; the drain of the fourth transistor is connected to the control terminal of the first switch tube and the parallel control terminal of the third switch tube and the fourth switch tube, and is respectively connected to the source and gate of the third transistor; The source of the sixth transistor is grounded; the drain of the sixth transistor is connected to the source and gate of the fifth transistor respectively, and is connected to the gate of the eighth transistor; The source of the eighth transistor is grounded; the drain of the eighth transistor is connected to the source and gate of the seventh transistor respectively, and is connected to the control terminal of the second switch tube; The drain of the sixteenth transistor is connected to the drain of the seventeenth transistor, the gates of the twelfth transistor and the fourteenth transistor, and is respectively connected to the source and gate of the eighteenth transistor; The source of the twelfth transistor is grounded; the drain of the twelfth transistor is connected to the source and gate of the thirteenth transistor respectively, and is connected to the gate of the tenth transistor; The source of the tenth transistor is grounded; the drain of the tenth transistor is connected to the source and gate of the eleventh transistor respectively, and is connected to the parallel control terminals of the fifth switch tube and the seventh switch tube; The source of the fourteenth transistor is grounded; the drain of the fourteenth transistor is connected to the source and gate of the fifteenth transistor respectively, and is connected to the bias voltage terminal; The source of the sixteenth transistor is grounded; the drain of the sixteenth transistor is connected to the source and gate of the eighteenth transistor respectively, and is connected to the gate of the seventeenth transistor; The source of the seventeenth transistor is grounded; the gate of the seventeenth transistor is connected to the drain of the nineteenth transistor and to the source and gate of the twentieth transistor; The source of the nineteenth transistor is grounded; the gate of the nineteenth transistor is connected to the LNA enable input terminal.

[0036] like Figure 3 As shown, the logic control circuit in this embodiment includes: a twenty-first transistor and a twenty-second transistor; The source of the twenty-first transistor is grounded; the gate of the twenty-first transistor is connected to the bypass selection terminal and to the gate of the twenty-second transistor; the drain of the twenty-first transistor is connected to the control terminal of the tenth switch tube and to the source and gate of the twenty-fourth transistor respectively; The source of the twenty-second transistor is grounded; the drain of the twenty-second transistor is connected to the gate of the twenty-third transistor, and is connected to the source and gate of the twenty-fifth transistor respectively; The source of the twenty-third transistor is grounded; the drain of the twenty-third transistor is connected to the control end of the eleventh switch tube, and is respectively connected to the source and gate of the twenty-sixth transistor.

[0037] Among them, LEF is an enhancement logic tube and LDF is a depletion logic tube.

[0038] In this embodiment, the logic control circuit generates tri-state control logic from a combination of two-level signals, driving the complementary conduction of each channel switch. By synchronously adjusting the bias voltages of the amplifier and switches during mode switching, the leakage paths of the non-operating channels are completely shut off, achieving high isolation and fast switching between modes, ensuring optimal performance when each channel operates independently.

[0039] The present invention has three working modes, namely LNA mode, Bypass mode and TX mode.

[0040] When working in LNA mode, the received RF signal is input from the ANT port and output from the RXout port. The LNA is enabled to a high level and the TX is enabled to a low level, so that the switches corresponding to the M1 and M3 nodes are turned on, and the switches corresponding to the M2 and M4~M6 nodes are turned off. Bias1~bias3 provide the required operating voltage for the Cascode. At this time, the TX path and the Bypass path are in a disconnected state, so that the LNA channel has a high degree of isolation from other channels, so that its performance will not deteriorate. In addition, the LNA adopts a cancellation structure and designs the bias points of the amplifier main and auxiliary tubes to reduce the third-order nonlinear term of the main tube, achieving the effect of nonlinear cancellation, thereby improving the linearity of the amplifier. Figure 4 and Figure 5 It can be seen that when the input power is less than -10dBm, the linearity indicator AMAM is flat and the AMPM variation is less than 0.1°.

[0041] When the Bypass channel works in high attenuation mode, TX enable, LNA enable and Bypass channel selection enable are all set to low level, so that the switches corresponding to the M1, M4 and M5 nodes are turned on, and the switches corresponding to the M2, M3 and M6 nodes are turned off, and bias1 and bias2 are set to low level to turn off the Cascode. If working in low attenuation mode, the Bypass channel selection enable is set to high level, so that SW11 is turned on and SW10 is turned off. The high attenuation channel achieves greater insertion loss by adding π attenuation. Due to the presence of switches SW5 and SW6 in the LNA channel, the Cascode part of the LNA channel is well isolated from the Bypass, so it will not cause the linearity of the Bypass to deteriorate. Figure 6 and Figure 7 It can be seen that in Bypass mode, when the input power is less than IP1dB, the linearity indicator AMAM is flat and the AMPM variation is less than 0.1°.

[0042] When working in TX mode, the transmit signal is input from the TX port and output from the ANT port. TX is enabled to a high level and LNA is enabled to a low level, so that the switch corresponding to the M2 node is turned on and the switches corresponding to the M1, M3 and M4 nodes are all turned off. Since the TX mode is used to transmit high-power signals, the TX mode must not only focus on isolation, but also prevent power leakage of large signals. Therefore, in TX mode, other channels need to decide how many switches to stack based on the output power corresponding to the TX path to prevent power leakage caused by the switch opening due to the voltage swing of the high-power signal, thereby improving the linearity of the TX switch mode. Figure 8 and Figure 9It can be seen that in TX mode, when the output P is -0.1dB, the linearity indicator AMAM is flat and the AMPM variation is less than 0.5°.

[0043] Specific embodiments are used in the present invention to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

[0044] Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the principles of the present invention, and it should be understood that the scope of protection of the present invention is not limited to such specific descriptions and embodiments. Those skilled in the art can make various other specific variations and combinations based on the technical teachings disclosed in the present invention without departing from the essence of the present invention, and such variations and combinations are still within the scope of protection of the present invention.

Claims

1. A high linearity switching low noise amplifier with logic control, characterized in that: include: LNA channel circuit, Bypass channel circuit, TX channel circuit and logic control circuit; The LNA channel circuit includes a serial-parallel switch unit, an amplifier using a cascode combined with a nonlinear cancellation structure, and a bias circuit; The Bypass channel circuit includes two series-connected switching tubes for variable gain switching and a π-type attenuator; The TX channel circuit includes a series-connected dual-gate switch tube and a parallel-connected stacked dual-gate switch tube group; The logic control circuit controls the states of the switch tubes in the LNA channel circuit, the Bypass channel circuit and the TX channel circuit through the first logic level and the second logic level to perform channel switching.

2. The high linearity switching low noise amplifier with logic control according to claim 1, characterized in that: Amplifiers that use Cascode combined with nonlinear cancellation structure include: a first amplifying tube, a second amplifying tube, and a third amplifying tube; The gate of the first amplifier tube is connected to the bias voltage terminal and is connected to the gate of the third amplifier tube via a sixth capacitor; the drain of the first amplifier tube is connected to the source of the second amplifier tube and the drain of the third amplifier tube respectively; the source of the first amplifier tube is connected to the source of the third amplifier tube and is grounded via a first inductor; The gate of the second amplifier tube is connected to the bias voltage terminal and is grounded via the first resistor and the eighth capacitor connected in series; the drain of the second amplifier tube is grounded via the second inductor and the seventh capacitor connected in series; The grid of the third amplifier tube is connected to the bias voltage terminal.

3. The high linearity switching low noise amplifier with logic control according to claim 2, characterized in that: The serial-parallel switching unit includes: a fifth switching tube, a sixth switching tube, and a seventh switching tube; The control terminals of the fifth switch tube, the sixth switch tube and the seventh switch tube are respectively connected to the logic control circuit; The output end of the fifth switching tube is connected to the input end of the sixth switching tube, and is connected to the gate of the first amplifier tube through the fifth capacitor; The output end of the sixth switch tube is grounded via a fourth capacitor; The input end of the seventh switch tube is connected to the drain of the second amplifier tube via a ninth capacitor; the output end of the seventh switch tube is connected to the RX output end via a tenth capacitor.

4. The high linearity switching low noise amplifier with logic control according to claim 3, characterized in that: Bypass channel circuit includes: an eighth switching tube, a ninth switching tube, a tenth switching tube, and an eleventh switching tube; The control terminals of the eighth switch tube, the ninth switch tube, the tenth switch tube and the eleventh switch tube are respectively connected to the logic control circuit; The output end of the eighth switching tube is connected to the input end of the tenth switching tube and the input end of the eleventh switching tube respectively; The output end of the tenth switching tube is connected to one end of the second resistor; the other end of the second resistor is connected to the input end of the ninth switching tube and is grounded via the third resistor and the eleventh capacitor connected in series; The output end of the eleventh switching tube is connected to the input end of the ninth switching tube; The output end of the ninth switch tube is connected to the RX output end via the twelfth capacitor.

5. The high linearity switching low noise amplifier with logic control according to claim 4, characterized in that: The TX channel circuit includes: a second switching tube, a third switching tube, and a fourth switching tube; The control terminal of the second switch tube and the parallel control terminals of the third switch tube and the fourth switch tube are respectively connected to the logic control circuit; The output end of the second switch tube is connected to the input end of the third switch tube and one end of the second capacitor respectively; the other end of the second capacitor is connected to the TX input end; The output end of the third switch tube is connected to the input end of the fourth switch tube; The output end of the fourth switch tube is grounded via the third capacitor.

6. The high linearity switching low noise amplifier with logic control according to claim 5, characterized in that: Also includes a first switching tube; The control end of the first switch tube is connected to the logic control circuit; The input end of the first switch tube is connected to the input end of the second switch tube, and is connected to the ANT signal end through the first capacitor; the output end of the first switch tube is respectively connected to the input end of the fifth switch tube and the input end of the eighth switch tube.

7. The high linearity switching low noise amplifier with logic control according to claim 6, characterized in that: The logic control circuit includes: a first transistor and a second transistor; The drain of the first transistor is connected to the drain of the second transistor, and is connected to the control terminals of the eighth and ninth switching transistors, and the source and gate of the ninth transistor; the sources of the first and second transistors are both grounded; the gate of the second transistor is connected to the LNA enable input terminal; the gate of the first transistor is connected to the TX enable input terminal, and is connected to the gates of the fourth, sixth, and sixteenth transistors, respectively; The source of the fourth transistor is grounded; the drain of the fourth transistor is connected to the control terminal of the first switch tube and the parallel control terminal of the third switch tube and the fourth switch tube, and is respectively connected to the source and gate of the third transistor; The source of the sixth transistor is grounded; the drain of the sixth transistor is connected to the source and gate of the fifth transistor respectively, and is connected to the gate of the eighth transistor; The source of the eighth transistor is grounded; the drain of the eighth transistor is connected to the source and gate of the seventh transistor respectively, and is connected to the control terminal of the second switch tube; The drain of the sixteenth transistor is connected to the drain of the seventeenth transistor, the gates of the twelfth transistor and the fourteenth transistor, and is respectively connected to the source and gate of the eighteenth transistor; The source of the twelfth transistor is grounded; the drain of the twelfth transistor is connected to the source and gate of the thirteenth transistor respectively, and is connected to the gate of the tenth transistor; The source of the tenth transistor is grounded; the drain of the tenth transistor is connected to the source and gate of the eleventh transistor respectively, and is connected to the parallel control terminals of the fifth switch tube and the seventh switch tube; The source of the fourteenth transistor is grounded; the drain of the fourteenth transistor is connected to the source and gate of the fifteenth transistor respectively, and is connected to the bias voltage terminal; The source of the sixteenth transistor is grounded; the drain of the sixteenth transistor is connected to the source and gate of the eighteenth transistor respectively, and is connected to the gate of the seventeenth transistor; The source of the seventeenth transistor is grounded; the gate of the seventeenth transistor is connected to the drain of the nineteenth transistor and to the source and gate of the twentieth transistor; The source of the nineteenth transistor is grounded; the gate of the nineteenth transistor is connected to the LNA enable input terminal.

8. The high linearity switching low noise amplifier with logic control according to claim 7, characterized in that: The logic control circuit includes: a twenty-first transistor and a twenty-second transistor; The source of the twenty-first transistor is grounded; the gate of the twenty-first transistor is connected to the bypass selection terminal and to the gate of the twenty-second transistor; the drain of the twenty-first transistor is connected to the control terminal of the tenth switch tube and to the source and gate of the twenty-fourth transistor respectively; The source of the twenty-second transistor is grounded; the drain of the twenty-second transistor is connected to the gate of the twenty-third transistor, and is connected to the source and gate of the twenty-fifth transistor respectively; The source of the twenty-third transistor is grounded; the drain of the twenty-third transistor is connected to the control end of the eleventh switch tube, and is respectively connected to the source and gate of the twenty-sixth transistor.

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