Storage array access device and equipment and storage medium

Abstract

The invention discloses a storage array access device and system and a storage medium, and relates to the technical field of electric digital data processing, in the device, each main equipment interface is provided with a corresponding data cache unit, a corresponding command cache unit and a corresponding response cache unit; the routing arbitration module is used for connecting the command cache unit of at least one main equipment interface and selecting a command with the highest priority according to the priority of the main equipment interface; if the target storage unit corresponding to the command with the highest priority is idle, issuing the command with the highest priority to a storage unit arbitration module corresponding to the target storage unit; and the storage unit arbitration module is used for arbitrating the command issued by the route arbitration module, reading data according to the arbitrated command and writing the data into a corresponding storage interface. According to the scheme, the possibility that the commands which can be executed later are blocked due to the fact that the previous commands cannot be executed is avoided as far as possible, and the data processing efficiency is greatly improved.

Description

Technical Field

[0001] The present application relates to the field of electronic digital data processing technology, and in particular to a storage array access device, system and storage medium. Background Art

[0002] With the rapid development of emerging technologies such as artificial intelligence and multi-core, the amount of data and computing power that integrated circuit chips need to carry are increasing rapidly. The computing units inside the chip will generate a large amount of temporary data during the calculation process.

[0003] Traditional SoCs typically integrate a block of SRAM on-chip for temporary data storage and exchange within a subsystem or between several Master Devices (MSTs). However, the access bandwidth of an SRAM is limited by the interface's bit width and clock frequency. When multiple cores or multiple Master Devices access the SRAM in parallel, the SRAM's bandwidth cannot meet the requirements, leading to frequent access conflicts. To improve SRAM access bandwidth and reduce conflicts, a single SRAM can be split into multiple smaller SRAMs. Furthermore, to prevent a write operation from blocking the SRAM due to a conflict, which would block subsequent operations on that core or IP, a FIFO can be added to the path as a buffer to buffer data and smooth the impact of access conflicts on overall bandwidth.

[0004] However, in the above solution, the buffers in the channel are managed according to the first-in-first-out (FIFO) principle. Therefore, although the congestion can be temporarily alleviated by buffering, the subsequent executable commands cannot be queued up for priority execution, and the buffer is still prone to being full. Summary of the Invention

[0005] The present application provides a storage array access device, system, and storage medium, which reduce the impact of a full buffer on other executable commands.

[0006] The present application provides a storage array access device, comprising: a plurality of master device interfaces, a plurality of storage interfaces, a routing arbitration module, a storage unit arbitration module, and a response buffer control module; wherein each master device interface has a corresponding data cache unit, a command cache unit, and a response cache unit;

[0007] The routing arbitration module is used to connect to the command cache unit of at least one of the master device interfaces and select the command with the highest priority according to the priority of the master device interface; if the target storage unit corresponding to the command with the highest priority is idle, the command with the highest priority is sent to the storage unit arbitration module corresponding to the target storage unit;

[0008] The storage unit arbitration module is used to arbitrate the commands issued by the routing arbitration module, and read the data and write it into the corresponding storage interface according to the arbitration command;

[0009] The response buffer control module is used to collect all response commands replied by the response buffer control module, classify the commands according to the main device interface, and then forward the classified commands to the response buffer unit of the corresponding main device interface.

[0010] The present application also provides an electronic device, including a memory, a processor, and the above-mentioned storage array access device.

[0011] The present application also provides a computer-readable storage medium, which is used to access data through the above-mentioned storage array access device.

[0012] The technical solution provided by this application may have the following beneficial effects:

[0013] In a storage array access device, each master device interface has a corresponding data cache unit, a command cache unit, and a response cache unit; a routing arbitration module is used to connect to the command cache unit of at least one master device interface and select the command with the highest priority according to the priority of the master device interface; if the target storage unit corresponding to the command with the highest priority is idle, the command with the highest priority is sent to the storage unit arbitration module corresponding to the target storage unit; the storage unit arbitration module is used to arbitrate the commands sent by the routing arbitration module and, based on the arbitrated command, read the data and write it to the corresponding storage interface; the response buffer control module is used to collect all the response commands replied by the response buffer control module, classify the commands according to the master device interface, and then forward the classified commands to the response cache unit of the corresponding master device interface. The above scheme first sorts the commands according to priority, and then screens out the commands that can be executed directly through multiple rounds of arbitration and processes them first. Under the premise of ensuring the priority of command processing, the possibility of the previous command being unable to be executed, which causes the subsequent executable commands to be blocked, is avoided as much as possible, thereby greatly improving data processing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0015] Figure 1 Shows a 2-master 2-memory bank interconnection solution structure diagram;

[0016] Figure 2This is a schematic diagram of the structure of a storage array access device provided by an embodiment of the present invention;

[0017] Figure 3 is a structural diagram of another storage array access device provided by an embodiment of the present invention;

[0018] Figure 4 A single-route arbitration command data flow diagram according to an embodiment of the present application is shown;

[0019] Figure 5 A multi-route arbitration command data flow diagram according to an embodiment of the present application is shown;

[0020] Figure 6 Schematic diagram of the hardware structure of the electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0021] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0022] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0023] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0024] With breakthroughs in cutting-edge technologies like AI and multi-core computing, the data throughput and computational intensity of integrated circuit chips are increasing exponentially. In intensive computing scenarios, the intermediate data generated by computing units requires ultra-low latency access channels. However, while external storage devices like DDR increase capacity, their inherent protocol mechanisms cause access latency to increase rather than decrease. Especially when multi-core processors or computing units execute large-scale data interactions concurrently, the memory wall effect becomes a key bottleneck restricting system performance. This makes the construction of high-bandwidth, low-latency on-chip temporary storage systems a top priority.

[0025] Traditional on-chip systems usually configure dedicated SRAM modules as subsystem caches. With their streamlined timing structure and efficient access characteristics, they can complete data interaction in nanoseconds. However, the bandwidth of a single SRAM is limited by the product of the physical interface bit width and the clock frequency, and there is a theoretical performance ceiling at a given process node. When a multi-core system or main control unit accesses concurrently, the bandwidth bottleneck of a single memory bank will cause serious resource contention. To this end, the industry uses memory bank cutting technology to decouple a single SRAM into multiple homogeneous sub-memory modules and build a distributed storage architecture through an on-chip network. Figure 1 In the 2-master 2-memory bank interconnection scheme shown in the diagram, each computing unit can achieve parallel access to storage resources through a bus arbitration mechanism, theoretically increasing the system bandwidth to N times that of the original design (N is the number of memory banks).

[0026] However, this decoupled architecture introduces a new timing challenge: when the master unit initiates continuous write operations across memory banks, if a particular access encounters a memory bank conflict, the entire instruction sequence will be blocked, even if the subsequent target memory bank is idle. This serial blocking effect severely reduces the bandwidth advantage of the distributed architecture. A conventional solution is to insert FIFO cache queues into the data transmission path (such as the command / data queues between the Mst0_Interface and the switch node, and between the switch node and the SRAM interface in the figure) to reduce performance fluctuations during conflicts through data buffering. However, this solution has two limitations: First, each channel requires independent cache resources. In high-bandwidth scenarios, the large amount of redundant cache leads to exponentially increasing hardware overhead. Moreover, the caches of each channel cannot be dynamically shared, which can easily lead to inefficient situations where local cache overflows coexist with global resource idleness. Second, the inherent first-in-first-out mechanism of the FIFO lacks priority scheduling capabilities. Even if a subsequent instruction is immediately executable, it must still wait for the previous blocking operation. This mechanical scheduling not only wastes cache resources but also increases transmission latency. When the system expands to a multi-master multi-memory architecture, these issues will become core obstacles that restrict performance improvement.

[0027] In order to solve the above problems, an embodiment of the present application provides a storage array access device. Figure 2 FIG. 1 is a schematic diagram of a storage array access device provided by an embodiment of the present invention. Figure 2 As shown, the device includes: a plurality of master device interfaces, a plurality of storage interfaces, a routing arbitration module, a storage unit arbitration module and a response buffer control module; wherein each master device interface has a corresponding data cache unit, a command cache unit and a response cache unit;

[0028] The routing arbitration module is used to connect to at least one command buffer unit of the master device interface and select the command with the highest priority according to the priority of the master device interface; if the target storage unit corresponding to the command with the highest priority is idle, the command with the highest priority is sent to the storage unit arbitration module corresponding to the target storage unit;

[0029] The storage unit arbitration module is used to arbitrate the commands issued by the routing arbitration module, and read the data and write it into the corresponding storage interface according to the arbitration command;

[0030] The response buffer control module is used to collect all response commands replied by the response buffer control module, classify the commands according to the main device interface, and then forward the classified commands to the response buffer unit of the corresponding main device interface.

[0031] In this embodiment of the present application, each master device interface in the system is equipped with three local caches: a command cache unit, a data cache unit, and a response cache unit. When a master device (such as a CPU core or IP unit) initiates a read or write request to the system, the command is written to the command cache, and the data (if it is a write operation) is written to the data cache.

[0032] The routing arbitration module is responsible for the system's first-level scheduling. It continuously monitors the command caches of all master device interfaces, arbitrates based on the priority settings of each master device interface, and selects the command with the highest current priority. When deciding whether to issue a command, the routing arbitration module not only considers the priority of the command itself, but also determines whether the target storage unit is idle. If the target storage unit corresponding to the command is being accessed, the system can forward the command to the next round of arbitration, skipping the current command and processing the next appropriate command. If the target storage unit is not being accessed, the command can be directly forwarded to the corresponding storage unit arbitration module for arbitration and processing. This skip scheduling method effectively avoids the problem of "first-arriving commands blocking later-arriving but executable commands" in the FIFO structure, thereby improving overall bandwidth utilization.

[0033] Next, the command selected by the routing arbitration module is sent to its corresponding storage unit arbitration module. Arbitration here is performed at a more granular, local level. A storage unit may typically receive commands from multiple master devices, so these commands need to be arbitrated again to determine which one has priority access to storage resources. This ensures that different master devices can share the storage interface fairly and efficiently, minimizing resource contention and access conflicts. After successful arbitration, the command is officially executed, and the read or write operation interfaces with the data cache unit to extract or write data.

[0034] After the operation is complete, the system must also return the execution result to the corresponding master device interface. This task is handled by the response buffer control module, which centrally collects the response information returned by the arbitration modules of all storage units, identifies the master device to which each response belongs, and then forwards it back to the response buffer unit of each master device according to the classification. This allows the master device to promptly determine whether its command has been completed and continue subsequent processing.

[0035] Therefore, the device design uses an arbitration mechanism to avoid the problem in traditional FIFO pipelines where subsequent commands, even if executable, cannot be queued when the previous command is blocked. Furthermore, by dynamically selecting free storage units and flexibly distributing commands, it significantly improves parallel access capabilities. Furthermore, the buffers in traditional pipelines are fixed and isolated, making it easy for one side to be full while the other side is empty. Although this solution still provides a separate cache for each master device, the centralized arbitration and command skipping scheduling mechanism significantly reduces the waste caused by uneven resource allocation.

[0036] In summary, in a storage array access device, each master device interface has a corresponding data cache unit, a command cache unit, and a response cache unit; a routing arbitration module is used to connect to the command cache unit of at least one master device interface, and select the command with the highest priority according to the priority of the master device interface; if the target storage unit corresponding to the command with the highest priority is idle, the command with the highest priority is sent to the storage unit arbitration module corresponding to the target storage unit; the storage unit arbitration module is used to arbitrate the commands sent by the routing arbitration module, and at the same time, read the data and write it to the corresponding storage interface according to the arbitrated command; the response buffer control module is used to collect all the response commands replied by the response buffer control module, and classify the commands according to the master device interface, and then forward the classified commands to the response cache unit of the corresponding master device interface. The above scheme first sorts the commands according to priority, and then screens out the commands that can be executed directly through multiple rounds of arbitration and processes them first. Under the premise of ensuring the priority of command processing, it avoids the possibility of the previous command being unable to be executed, which leads to the blocking of the subsequent commands that can be executed, thereby greatly improving data processing efficiency.

[0037] In such Figure 2 Based on the storage array access device shown in FIG, another storage array access device is provided in this embodiment. Figure 3 It is a structural diagram of another storage array access device provided by an embodiment of the present invention. Figure 3 The example adopts a scenario of 3 Msts and 3 SRAMs, and in this scenario, arbitration flow control is performed through each module to demonstrate the hierarchical relationship and command data path between each module. The solution shown in the embodiment of the present application can also be applied to other numbers of Msts and SRAMs.

[0038] like Figure 3 As shown in the figure, the architecture includes three master device interface modules, each of which is connected to the Mst interface (master device interface) of the processor core or IP to initiate commands to access the SRAM. Figure 3 As shown, each master device interface has a corresponding data cache unit, command cache unit and response cache unit. For master device interface 1, the device includes a first command cache unit 311, a first data cache unit 312 and a first response cache unit 313 corresponding thereto; for master device interface 2, the device includes a second command cache unit 321, a second data cache unit 322, a second response cache unit 323 and a first command issuing unit 324 corresponding thereto; for master device interface 3, the device includes a third command cache unit 331, a third data cache unit 332, a third response cache unit 333 and a second command issuing unit 334 corresponding thereto.

[0039] The interface protocol of the master device interface can be an on-chip bus protocol such as AXI or AHB. The master device interface implements bus protocol conversion, separates commands and data, and first stores the commands in the command cache unit, and then sends them to the routing arbitration module through the command issuing unit, and the data is stored in the temporary buffered data cache unit of the master device interface. In the present invention, in order to control the number of pending commands of each interface, command flow control is implemented within the interface. When the number of commands received but not completed by the Mst interface reaches a set value, the external bus will be back-pressured to stop writing commands and data to the command cache unit and the data cache unit. There is a command issuing module behind the command cache unit. The main function of this module is to detect commands and corresponding data. Only when the data of a command is written into the buffer of the data cache unit will the command be sent back. This can reduce the bandwidth waste of the internal data path. At the same time, functions such as QoS can be implemented in this module to achieve interface flow control.

[0040] In addition, in an embodiment of the present application, the storage interface can be an SRAM interface, which is used to directly connect the split small SRAMs. The number can be split according to needs, and the interface can be customized according to the SRAM interface timing.

[0041] The arbitration part of the entire architecture is between the req_to_sw module and the SRAM interface module. The routing arbitration module includes multiple functional units.

[0042] Optional, such as Figure 3As shown, the routing arbitration module also includes a priority circular queue module; each master device interface includes a priority register; the priority register is connected to the priority circular queue module, and the priority circular queue sorts the priorities of each master device interface according to the value in the priority register of each master device interface.

[0043] In this embodiment, the priority round-robin module further optimizes the priority control of multi-master device interfaces. Each master device interface has an internal priority register that records the scheduling weight of that device. All registers are connected to the priority round-robin module, which is responsible for dynamically rotating and sorting the master device priorities. Even if some devices have lower priorities, they will still receive scheduling opportunities in a certain round, avoiding "resource starvation."

[0044] Specifically, the priority circular queue module's main function is to implement MST priority polling queuing. This is to enable bandwidth allocation based on priority configuration for different MSTs. Each MST interface is designed with a priority register, which is directly connected to the priority circular queue module. The module internally sorts the MST interfaces based on their priorities. This allows the routing arbitration module to prioritize MST interfaces based on the queues before arbitration, reducing command arbitration time. After product production, users can also adjust the bandwidth allocation of each MST interface through software configuration of MST priorities as needed, optimizing product performance and improving adaptability in different scenarios.

[0045] like Figure 3 As shown, Figure 2 The routing arbitration module in this case may include a multi-routing arbitration module SW and a buffer management arbitration module Buf_arb;

[0046] The multi-routing arbitration module SW is connected to the command cache units of at least two of the master device interfaces, and selects the command with the highest priority according to the priority of the master device interface; if the target storage unit corresponding to the command with the highest priority is idle, the command with the highest priority is sent to the storage unit arbitration module corresponding to the target storage unit.

[0047] Optionally, the multi-route arbitration module SW is further configured to:

[0048] Acquire a plurality of commands from the command buffer units of at least two of the master device interfaces, perform priority sorting arbitration according to the priorities of the master device interfaces, and select the command with the highest priority;

[0049] Determine whether the storage unit arbitration module of the command with the highest priority is empty. If it is empty, directly execute the write request through the storage unit arbitration module;

[0050] If it is not empty, a command is selected and sent to the buffer management arbitration module Buf_arb according to the priority sorting and the number of idle data buffers, so that the buffer management arbitration module Buf_arb selects a command and sends it to the storage unit arbitration module.

[0051] In this embodiment of the present application, the multi-route arbitration module SW assumes the core global command scheduling function. It retrieves commands from the command buffer units of multiple master device interfaces, and prioritizes them based on the priority information of each master device interface, selecting the command with the highest priority for processing.

[0052] Next, the multi-routing arbitration module SW will determine whether the target storage unit of this command is currently idle: if the target is idle, the command will be directly handed over to the storage unit arbitration module for processing; if the target is busy (a command is queued or being written), the system will not block blindly, but will hand over the command to the buffer management arbitration module Buf_arb for further arrangement.

[0053] Specifically, the multi-routing arbitration module can be connected to multiple Mst interfaces. Its main function is to select the command with the highest priority based on the priority of the Mst interface, and then determine whether the storage unit arbitration module of the corresponding SRAM interface is currently executing the command. If the storage unit arbitration module is idle, the corresponding highest priority write command will be directly sent to the storage unit arbitration module. In this process, some special requirements supported by the on-chip bus must also be considered, such as order preservation. If there are commands that do not meet the requirements for direct issuance, the remaining commands will be re-prioritized and arbitrated, and then, based on the number of remaining buffers, the qualified commands will be selected and sent to the buffer management arbitration module Buf_Arb module. If there are commands that cannot be issued because the buffer is full, the back pressure will be buffered in the routing arbitration module, and arbitration will continue in the next clock cycle. This module implements the first-level arbitration, routing and flow control functions.

[0054] The buffer management arbitration module Buf_arb included in the routing arbitration module is used to allocate data buffers according to the commands of different master device interfaces sent by the routing arbitration module, and move the data corresponding to the commands of different master device interfaces from the data cache unit of the corresponding master device into the allocated data buffer.

[0055] Optionally, the buffer management arbitration module Buf_arb is also used to:

[0056] Get the residence time of the command in the buffer management arbitration module Buf_arb;

[0057] Time arbitration is performed according to the residence time of the commands in the buffer management arbitration module Buf_arb, and the command with the highest priority is selected from the commands in the buffer management arbitration module Buf_arb and sent to the storage unit arbitration module.

[0058] The buffer management arbitration module, Buf_arb, serves as a dynamic cache scheduling hub, bridging the gap between master devices and storage resources. Upon receiving commands from the routing arbitration module, it dynamically allocates available data buffers based on the command source. It then moves data from the master device's corresponding data cache unit to an intermediate buffer in preparation for subsequent write operations. This module enables shared and dynamic allocation of cache resources, improving overall system cache utilization.

[0059] In addition, in an embodiment of the present application, the residence time of each command entering the buffer is recorded; when multiple commands are waiting, the system not only considers the priority, but also considers which command has been waiting the longest, thereby preventing some low-priority commands from "starving" and achieving a balance between fair scheduling and timeliness.

[0060] Specifically, the main functions of the buffer management arbitration module include buffer management and arbitration. The first is to allocate buffers based on the commands of different Mst interfaces sent by the routing arbitration module. Because the data buffer of this module may be shared by multiple Mst interfaces, multiple commands from different Mst interfaces may be received simultaneously in each clock cycle, so many-to-many arbitration allocation of buffers is required. Because the routing arbitration module has blocked commands that exceed the current number of empty buffers inside it, the arbitration allocation of buffers here is mainly for the allocation and correspondence of Mst interface commands and current empty buffers. The second is buffer management. Management mainly realizes the control of the empty and full status of each buffer and the storage of command information such as the address, length, Mst interface number, priority, etc. corresponding to the data in the buffer. If some bus characteristics are supported, information such as ID and command arrival time may also be stored. The size of each buffer is based on the maximum packet size that the Mst interface needs to support, and the number is customized according to the actual scenario needs. Next comes the data transfer function, which requires transferring data from the corresponding Mst interface's data cache unit to the assigned data buffer according to the command. Since multiple commands may be applied for and arbitrated simultaneously, multiple DMAs are required to carry out parallel transfers. The number of DMAs depends on the number of Mst interfaces and the number of buffers. Finally, this module also arbitrates the commands buffered in the buffer. The arbitration process also first classifies the commands in the buffer according to the address. To prevent commands from staying in the buffer for too long, time arbitration is required. Ultimately, the highest priority command is selected and sent to the corresponding storage unit arbitration module.

[0061] Optional, such as Figure 3As shown, the routing arbitration module also includes a single routing arbitration module SW_S; the single routing arbitration module SW_S is connected to a command buffer unit of a target master device interface;

[0062] The single-route arbitration module SW_S is used to read the command in the command buffer unit of the target master device interface and query the empty buffer area to allocate the command in the command buffer unit of the target master device interface;

[0063] The single-route arbitration module SW_S is further used to arbitrate commands buffered in the buffer, so as to send the command with the highest priority to the storage unit arbitration module corresponding to the target master device interface.

[0064] Furthermore, the single-route arbitration module SW_S is also used for:

[0065] When reading the command in the command buffer unit of the target master device interface, determining whether the buffer in the single-route arbitration module SW_S is full;

[0066] If the buffer in the single-route arbitration module SW_S is not full, the command in the command buffer unit of the target master device interface is written into the command buffer.

[0067] Furthermore, the single routing arbitration module is also used to:

[0068] Obtaining the residence time of commands in a buffer in a single routing arbitration module;

[0069] Time arbitration is performed according to the residence time of the commands in the buffer of the single-route arbitration module, and the command with the highest priority is selected from the commands in the buffer of the single-route arbitration module and sent to the storage unit arbitration module.

[0070] Compared to multi-route arbitration, the single-route arbitration module SW_S is optimized for a single master channel. Its function is to independently read the command buffer of a specific master interface; if its own buffer is not full, it pulls commands in advance and stores them in the local cache; then, based on the priority of commands in its own buffer, it arbitrates again to determine which command proceeds to the next step. The single-route arbitration module SW_S is suitable for master interfaces with high bandwidth requirements or clear real-time requirements, providing them with a "fast channel" with lower latency and higher scheduling weight.

[0071] Specifically, the main function of the single-route arbitration module is similar to that of the buffer management arbitration module, which is also buffer management and arbitration. Since the single-route arbitration has only one Mst interface, the command buffer unit corresponding to the Mst interface is directly read (i.e., Figure 3The first command cache unit 311 shown in FIG3 is used to store commands in the buffer and query empty buffers for allocation. The second is buffer management, which mainly controls the empty and full status of each buffer and stores command information such as the address, length, and priority corresponding to the data in the buffer. If certain bus characteristics are supported, information such as the ID and command arrival time may also be stored. The size of each buffer is based on the maximum packet size required to be supported by the Mst interface, and the number is customized according to the actual scenario. Then there is the data transfer function, which needs to transfer data from the corresponding Mst interface data cache unit to the allocated designated data buffer according to the command. Finally, this module also arbitrates the commands buffered in the buffer. The arbitration process also first classifies the commands in the buffer according to the address. To prevent commands from remaining in the buffer for too long, time arbitration is required. Ultimately, the highest priority command is selected and sent to the corresponding storage unit arbitration module.

[0072] Optional, such as Figure 3 As shown, each storage interface has a corresponding storage unit arbitration module; the first end of the storage unit arbitration module is connected to its corresponding storage interface; the second end of the storage unit arbitration module is connected to the cache area in the buffer management arbitration module and the data cache unit in each master device interface.

[0073] In the embodiment of the present application, each storage interface has an independent storage unit arbitration module, thereby dispersing the pressure of resource contention and decoupling different storage interfaces from each other.

[0074] The Memory Unit Arbitration Module (MWA) is located at the front end of the SRAM interface. Each SRAM interface has one MWA Arbitration Module, responsible for arbitrating all commands issued by the Routing Arbitration Module and the Buffer Management Arbitration Module (Buf_arb). Based on the arbitrated commands, the MWA Arbitration Module reads data from the DataFifo in the Master Transceiver (Mst) interface or the small buffers in the Buffer Management Arbitration Module (Buf_arb) and writes it to the SRAM. This module's command request signals are connected to the Routing Arbitration Module and the Buffer Management Arbitration Module, while its data path directly connects to all command buffers in the Mst interface and all small buffers in the Buffer Management Arbitration Module (Buf_arb). Its other end is directly connected to the partitioned SRAM through the SRAM interface. Because the data source on one end is already fully stored in the buffer, while the other end is SRAM memory, the transfer process is free of backpressure or interruptions. Therefore, the MWA Arbitration Module simultaneously responds with a write completion command to the Response Buffer Control Module (Wrsp_Ctrl).

[0075] Optionally, in the embodiment of the present application, the main function of the response buffer control module Wrsp_ctrl is to first collect the wrsp commands replied by all the storage unit arbitration modules, classify the commands according to Mst, and then forward these commands to the corresponding Mst interface. However, because each storage unit arbitration module may reply to the wrsp command at the same time, or even all storage unit arbitration modules may reply to the wrsp command continuously for multiple clock cycles, or there may be a situation where multiple storage unit arbitration modules reply to the wrsp command to one Mst at the same time, the module needs to implement the wrsp buffer internally to ensure that the wrsp command is not lost under any circumstances. It should be noted that because the response buffer control module Wrsp_ctrl cannot be used to back pressure the command sent by the previous arbitration routing module, there needs to be a response cache unit between the response buffer control module Wrsp_ctrl and each Mst interface logic to buffer the Wrsp command, and the depth must be greater than or equal to the unfinished command setting value of the Mst interface. This buffer is independent of the buffer inside the response buffer control module Wrsp_ctrl.

[0076] In a possible implementation of an embodiment of the present application, the above-mentioned multi-route arbitration module will perform priority sorting arbitration according to the priority of the master device interface. If the priority of each master device is fixed in the arbitration strategy, it is easy to cause a low-priority master device to be unable to obtain arbitration opportunities for a long time, thereby affecting the normal operation of the master device.

[0077] Therefore, in an embodiment of the present application, a statically set initial priority value can be set for each master device interface, and the initial priority value can be stored in a priority register; then the multi-route arbitration module records a resident counter for the command cache item of each master device, which is used to count the number of cycles the command waits in the cache.

[0078] At this time, if the residence time of a command exceeds a preset threshold (for example, 100 cycles), the arbitration priority of the master device corresponding to the command is temporarily increased. Optionally, the level of this increase can be a fixed increase, for example, the priority value is increased by a fixed value each time, or the priority value is doubled every time the residence time reaches a preset threshold. Once the command is executed by the master device, the arbitration priority value of the master device is restored to the initial priority value.

[0079] In such Figure 3 In the architecture diagram shown, in order to achieve the maximum bandwidth, the master device interface 1 is configured with a single routing arbitration module and a dedicated data buffer, thus ensuring the maximum data flow bandwidth. While writing data to the SRAM, it replies to the Wrsp command to the buffer control module Wrsp_ctrl, and then forwards it to the corresponding Mst interface. Taking the above structure as an example, Figure 4FIG. 1 shows a single-route arbitration command data flow diagram related to an embodiment of the present application. Figure 4 As shown, from the command side, the single-route arbitration module SW_S reads the command in the command cache unit of the target master device interface, and queries the empty buffer area to allocate the command in the command cache unit of the target master device interface; then the single-route arbitration module SW_S is also used to arbitrate the commands buffered in the buffer to send the highest priority command to the storage unit arbitration module corresponding to the target master device interface. At this time, the storage unit arbitration module determines whether the command can be executed. If it can be executed, it will execute it accordingly and reply with a write response to the corresponding response buffer module. From the data side, the master device interface 1 caches the data in the corresponding data cache unit, and when the command arbitration is passed, the storage unit arbitration module obtains the data of the data cache unit to the data cache area corresponding to the SRAM so that it can be written to the SRAM later.

[0080] Figure 5 A multi-route arbitration command data flow diagram according to an embodiment of the present application is shown. Figure 5 As shown, the command flow and data flow of the master device interface 2 are as follows:

[0081] Figure 3Master interfaces 2 and 3 have relatively low bandwidth requirements. To conserve resources, they share buffer resources. This is slightly different from master interface 1: commands first enter the multi-route arbitration module for arbitration. After arbitration, commands enter the buffer management arbitration module, and finally reach the storage unit arbitration module. Because Mst1 and Mst2 share a buffer, two levels of arbitration are required before entering the buffer. First, the priority polling module prioritizes the two Msts. Then, commands are categorized based on the SRAM being accessed. The highest-priority Mst is arbitrated, and the SRAM idle state is determined before the command is sent to the storage unit arbitration module. If the SRAM is idle, the command is sent directly to the corresponding storage unit arbitration module. Upon receiving the command, the storage unit arbitration module reads the data directly from the data storage unit and writes it to the SRAM, then responds with a write completion signal. The remaining Mst requests are requeued according to priority, and then a second level of arbitration is performed based on the number of available buffers. The selected command is sent to the buffer management arbitration module, Buf_arb. It should be noted that the buffer management arbitration module Buf_arb of this path is functionally different from the buffer management arbitration module Buf_arb of a separate path. It is necessary to implement many-to-many arbitration of commands to the buffer and parallel DMA data transfer from multiple master device interfaces to the cache area. The specific number of DMAs needs to be consistent with the smaller of the number of master device interfaces or the number of buffers participating in the arbitration. It should be noted that because the data of the master device interface write path is temporarily buffered in the cache unit within the interface, it is necessary to ensure that the pipeline level of the buffer management arbitration module Buf_arb after arbitration and the storage unit arbitration module reading the data cache unit must be the same as the pipeline level of the storage unit arbitration module reading the data cache unit to ensure that the order of the data in the read data cache unit is not disordered.

[0082] In summary, in a storage array access device, each master device interface has a corresponding data cache unit, a command cache unit, and a response cache unit; a routing arbitration module is used to connect to the command cache unit of at least one master device interface, and select the command with the highest priority according to the priority of the master device interface; if the target storage unit corresponding to the command with the highest priority is idle, the command with the highest priority is sent to the storage unit arbitration module corresponding to the target storage unit; the storage unit arbitration module is used to arbitrate the commands sent by the routing arbitration module, and at the same time, read the data and write it to the corresponding storage interface according to the arbitrated command; the response buffer control module is used to collect all the response commands replied by the response buffer control module, and classify the commands according to the master device interface, and then forward the classified commands to the response cache unit of the corresponding master device interface. The above scheme first sorts the commands according to priority, and then screens out the commands that can be executed directly through multiple rounds of arbitration and processes them first. Under the premise of ensuring the priority of command processing, it avoids the possibility of the previous command being unable to be executed, which leads to the blocking of the subsequent commands that can be executed, thereby greatly improving data processing efficiency.

[0083] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0084] The embodiment of the present application also provides an electronic device, such as Figure 6 As shown, it includes a memory 10 and a processor 20. The memory 10 stores a computer program, and the processor 20 is configured to run the computer program to execute the logic in any of the above-mentioned storage array access device embodiments.

[0085] An embodiment of the present application also provides a computer-readable storage medium, which can be set in the above-mentioned storage array access device. Optionally, the computer-readable storage medium stores a computer program, wherein the computer program is configured to execute the logic in any of the above-mentioned storage array access devices when running.

[0086] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0087] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the logic in any of the above-mentioned storage array access device embodiments is implemented.

[0088] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the logic in any of the above-mentioned storage array access device embodiments is implemented.

[0089] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0090] The above describes in detail a storage array access device, apparatus, and storage medium provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is intended only to facilitate understanding of the method and core concepts of the present application. It should be noted that those skilled in the art may, without departing from the principles of the present application, make various improvements and modifications to the present application, and such improvements and modifications also fall within the scope of protection of the present application.

Claims

1. A storage array access device, characterized in that: The device includes: a plurality of master device interfaces, a plurality of storage interfaces, a routing arbitration module, a storage unit arbitration module and a response buffer control module; wherein each master device interface has a corresponding data cache unit, a command cache unit and a response cache unit; The routing arbitration module is used to connect to the command cache unit of at least one of the master device interfaces and select the command with the highest priority according to the priority of the master device interface; if the target storage unit corresponding to the command with the highest priority is idle, the command with the highest priority is sent to the storage unit arbitration module corresponding to the target storage unit; The storage unit arbitration module is used to arbitrate the commands issued by the routing arbitration module, and read the data and write it into the corresponding storage interface according to the arbitration command; The response buffer control module is used to collect all response commands replied by the response buffer control module, classify the commands according to the main device interface, and then forward the classified commands to the response buffer unit of the corresponding main device interface.

2. The device according to claim 1, characterized in that The routing arbitration module includes a multi-routing arbitration module and a buffer management arbitration module; The multi-route arbitration module is connected to the command buffer units of at least two of the master device interfaces and selects the command with the highest priority according to the priority of the master device interface; If the target storage unit corresponding to the command with the highest priority is idle, the command with the highest priority is sent to the storage unit arbitration module corresponding to the target storage unit; The buffer management arbitration module is used to allocate data buffers according to the commands of different master device interfaces sent by the routing arbitration module, and move the data corresponding to the commands of different master device interfaces from the data cache unit of the corresponding master device into the allocated data buffer.

3. The device according to claim 2, characterized in that The multi-route arbitration module is further used for: Acquire a plurality of commands from the command buffer units of at least two of the master device interfaces, perform priority sorting arbitration according to the priorities of the master device interfaces, and select the command with the highest priority; Determine whether the storage unit arbitration module corresponding to the command with the highest priority is empty, and if the storage unit arbitration module of the command with the highest priority is empty, directly execute the write request through the storage unit arbitration module; If the storage unit arbitration module corresponding to the command with the highest priority is not empty, then according to the priority sorting and the number of free data buffers, a command is selected and sent to the buffer management arbitration module, so that the buffer management arbitration module selects the command and sends it to the storage unit arbitration module; The buffer management arbitration module is further used for: Obtaining the residence time of the command in the buffer management arbitration module; Time arbitration is performed according to the residence time of the commands in the buffer management arbitration module, and the command with the highest priority is selected from the commands in the buffer management arbitration module and sent to the storage unit arbitration module.

4. The device according to claim 2, characterized in that The routing arbitration module also includes a priority circular queue module; each master device interface includes a priority register; the priority register is connected to the priority circular queue module, and the priority circular queue sorts the priorities of the various master device interfaces according to the values ​​in the priority register of each master device interface.

5. The device according to claim 1, characterized in that The routing arbitration module further includes a single routing arbitration module; the single routing arbitration module is connected to a command buffer unit of a target master device interface; The single-route arbitration module is used to read the command in the command buffer unit of the target master device interface and query the empty buffer area to allocate the command in the command buffer unit of the target master device interface; The single-route arbitration module is further configured to arbitrate commands buffered in the buffer, so as to send the command with the highest priority to the storage unit arbitration module corresponding to the target master device interface.

6. The device according to claim 5, characterized in that The single-route arbitration module is further configured to: When reading a command in a command buffer unit of the target master device interface, determining whether a buffer in the single-route arbitration module is full; If the buffer in the single-route arbitration module is not full, the command in the command buffer unit of the target master device interface is written into the command buffer.

7. The device according to claim 6, characterized in that The single-route arbitration module is further configured to: Obtaining the residence time of the command in the buffer of the single-route arbitration module; Time arbitration is performed according to the residence time of the commands in the buffer of the single-route arbitration module, and the command with the highest priority is selected from the commands in the buffer of the single-route arbitration module and sent to the storage unit arbitration module.

8. The device according to any one of claims 1 to 7, characterized in that Each storage interface has a corresponding storage unit arbitration module; the first end of the storage unit arbitration module is connected to its corresponding storage interface; the second end of the storage unit arbitration module is connected to the cache area in the buffer management arbitration module and the data cache unit in each master device interface.

9. An electronic device, characterized in that: The device is characterized in that it comprises: a memory, a processor, and a storage array access device as described in any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium is used to access data through the storage array access device according to any one of claims 1 to 8.

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