Target object control method and device, electronic equipment, medium and product

Abstract

The invention provides a target object control method and device, electronic equipment, a medium and a product, and relates to the technical field of intelligent robots, a target object comprises dual-core heterogeneous processors, instruction sets and / or operating systems corresponding to the dual-core heterogeneous processors are different, and the dual-core heterogeneous processors share hardware resources; the method comprises the steps that in the starting process of any subsystem in an operating system of a target object, the running state of the dual-core heterogeneous processor is detected; in the embodiment of the invention, under the condition that the running state is determined to be abnormal, the information of the currently running task of the dual-core heterogeneous processor is stored, and the operating system of the target object is restarted based on the task information, so that the task is quickly recovered when the operating system has a problem, the task can be continuously executed from an interruption point after restarting, and the downtime is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of intelligent robot technology, and in particular to a method, device, electronic device, medium, and product for controlling a target object. Background Art

[0002] In a multiprocessor system, such as one that runs both Linux and operating systems corresponding to RISC-V (Reduced Instruction Set Computer V) processors, each processor corresponding to each operating system typically runs independently. Therefore, when an operating system problem occurs, each processor is responsible for resetting its corresponding operating system.

[0003] However, the above reset process also runs independently and cannot resume tasks in time after reset, which increases the downtime of the operating system. Summary of the Invention

[0004] The present disclosure provides a method, device, electronic device, medium and product for controlling a target object. For a target object having a dual-core heterogeneous processor, the method detects the operating status of each processor in real time. When an abnormal operating status is detected, the method saves and restores task information, and then restarts the operating system. This allows for rapid task recovery when a problem occurs, ensuring that tasks continue from the interruption point after restart, thereby reducing downtime.

[0005] In a first aspect, the present disclosure provides a method for controlling a target object, wherein the target object includes a dual-core heterogeneous processor, the dual-core heterogeneous processors correspond to different instruction sets and / or operating systems, and the dual-core heterogeneous processors share hardware resources; the method includes:

[0006] During the startup of any subsystem in the target object's operating system, detecting the operating status of the dual-core heterogeneous processor;

[0007] When it is determined that the running state is abnormal, the task information currently running on the dual-core heterogeneous processor is saved, and the operating system of the target object is restarted based on the task information.

[0008] Therefore, real-time monitoring of the processor's operating status during subsystem startup can help the operating system identify potential issues early. This preventative measure reduces the probability of OS crashes. When an anomaly is detected, saving the current task information and restarting the OS ensures that task information is not lost during the reboot process. This also ensures that the OS can quickly recover to a normal state in the event of an issue, reducing OS downtime and improving OS availability and reliability.

[0009] In addition, by saving and restoring task information, the operating system can continue to execute tasks from the interruption point after restart, ensuring task continuity and data integrity, and avoiding problems such as machine loss of control.

[0010] In a second aspect, the present disclosure provides a control device for a target object, wherein the target object includes a dual-core heterogeneous processor, the dual-core heterogeneous processors correspond to different instruction sets and / or operating systems, and the dual-core heterogeneous processors share hardware resources; the device includes:

[0011] A detection module, configured to detect the operating status of the dual-core heterogeneous processor during the startup of any subsystem in the target object's operating system;

[0012] The restart module is used to save the task information currently running on the dual-core heterogeneous processor and restart the operating system of the target object based on the task information when it is determined that the running state is abnormal.

[0013] In a third aspect, the present disclosure provides an electronic device comprising: a dual-core heterogeneous processor, a controller, and a memory communicatively connected to the controller;

[0014] Memory stores computer-executable instructions;

[0015] The controller executes the computer-executable instructions stored in the memory to implement the method according to any one of the first aspects.

[0016] In a fourth aspect, the present disclosure provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, they are used to implement the method as described in any one of the first aspects.

[0017] It should be noted that the second to fourth aspects of the present disclosure correspond to the technical solutions of the first aspect of the present disclosure, and the beneficial effects achieved by each aspect and the corresponding feasible implementation methods are similar, which will not be repeated here.

[0018] In summary, the present disclosure provides a control method, device, electronic device, medium and product for a target object, wherein the target object uses a dual-core heterogeneous processor, each processor can run a different instruction set and / or operating system, and this architecture allows the target object to execute different types of tasks on different processors. In this way, during the startup process of any subsystem of the operating system, the operating status of the dual-core heterogeneous processor can be continuously detected to detect possible abnormal situations, such as deadlock, crash or upgrade abnormalities. If an abnormality is detected, the task information currently being executed by the dual-core heterogeneous processor can be saved, such as the progress of the task, the currently processed data, context information, etc. After saving the task information, the restart process of the operating system can be triggered, that is, the operating system is restarted based on these task information to quickly restore to the state before the abnormality occurs, so that the task can continue to be executed from the interruption point, reducing downtime.

[0019] Therefore, this anomaly detection and task information preservation mechanism enables the operating system to recover more quickly when encountering problems. Furthermore, by saving and restoring task status, the operating system can quickly resume normal operation after a reboot, significantly reducing operating system downtime. Furthermore, saving and restoring task status ensures task continuity, reducing task interruptions and data loss caused by operating system anomalies. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0021] Figure 1 A schematic diagram of an application scenario provided by an embodiment of the present disclosure;

[0022] Figure 2 A flow chart of a method for controlling a target object provided by an embodiment of the present disclosure;

[0023] Figure 3 A flowchart of an optional method for controlling a target object provided in an embodiment of the present disclosure;

[0024] Figure 4 A schematic structural diagram of a control device for a target object provided by an embodiment of the present disclosure;

[0025] Figure 5 A schematic structural diagram of an electronic device provided in an embodiment of the present disclosure.

[0026] The above drawings illustrate specific embodiments of the present disclosure, which will be described in more detail below. These drawings and textual descriptions are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of the present disclosure to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0027] To facilitate a clear description of the technical solutions of the embodiments of the present disclosure, in the embodiments of the present disclosure, terms such as "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. For example, the first device and the second device are merely used to distinguish between different devices and do not limit their order. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or execution order, and that terms such as "first" and "second" do not necessarily mean that they are different.

[0028] It should be noted that in this disclosure, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this disclosure as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0029] In the present disclosure, "at least one" means one or more, and "more" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or plural.

[0030] First, the professional terms involved in this disclosure are explained below.

[0031] RISC-V: is an open source instruction set architecture that uses the principles of Reduced Instruction Set Computer (RISC) and supports multiple data widths, such as 32 bits, 64 bits, and 128 bits.

[0032] A watchdog timer is a hardware or software timer used to monitor the system's operating status. Its primary function is to detect whether the system is operating properly and automatically reset or perform predefined error correction actions if the system fails or stops responding.

[0033] It's important to note that the watchdog timer has an input and an output. The input receives a "feed the watchdog" signal, while the output connects to the reset pin of the microcontroller. Under normal operation, the microcontroller periodically sends a "feed the watchdog" signal to the input to reset the timer. If the microcontroller fails to send the "feed the watchdog" signal on time, the timer overflows and generates a reset signal, resetting the microcontroller and preventing the program from entering an infinite loop or running out of control.

[0034] Among them, the "feed dog" signal can be used to indicate the reset operation of the watchdog timer. Correspondingly, the "do not feed dog" signal corresponds to the "feed dog" signal. The "do not feed dog" signal can be used to indicate not to reset the watchdog timer.

[0035] Linux system: is an open source operating system that supports 32-bit and 64-bit hardware and can run major Unix tool software, applications and network protocols.

[0036] File system: A system that organizes and allocates space on file storage devices, is responsible for file storage, and protects and retrieves stored files. It is a software organization in the operating system that is responsible for managing and storing file information and is a subsystem in the operating system.

[0037] Boot0 stage: refers to the initial stage of operating system startup. In this stage, the "dog feeding" operation can prevent operating system problems before loading and executing U-Boot.

[0038] It should be noted that the "feed the dog" operation may refer to the process of resetting the watchdog timer after receiving the "feed the dog" signal to ensure that the watchdog timer does not time out and trigger an operating system reset. Correspondingly, the "do not feed the dog" operation refers to the process of not resetting the watchdog timer after receiving the "do not feed the dog" signal.

[0039] U-Boot stage: It is a commonly used boot loader used to initialize the hardware and load the operating system kernel. At this stage, the "dog feeding" operation can ensure that U-Boot can complete its tasks normally, including initializing the hardware and loading the kernel.

[0040] Kernel stage: This is the stage when the operating system kernel starts and runs. During this stage, performing the "dog feeding" operation can prevent the kernel from crashing due to abnormal conditions during the startup process or operation.

[0041] Boot partition: refers to the partition used to store the boot loader and files related to the startup process.

[0042] Rootfs partition: refers to the partition that stores the root file system.

[0043] Active panic: refers to an emergency stop operation actively triggered by the operating system or program when it detects an unrecoverable error or abnormal state.

[0044] Currently, for multi-processor systems of robots, taking one of the processor systems as an example, when the RISC-V processor or the operating system it runs crashes, due to the lack of a self-recovery mechanism, the operating system may not be able to automatically restart or recover to a normal state, so a manual restart or shutdown is required to recover the system.

[0045] For example, if one of the processor systems is a Linux system, if the U-Boot stage crashes during Linux system startup, the Linux system will not be able to continue booting to the operating system. In this case, if the operating system is unresponsive, it may be necessary to remove power, such as removing the battery, to reset the hardware state.

[0046] It should also be noted that if the RISC-V system partition or the Boot partition or Rootfs partition of the Linux system is damaged, the operating system will not be able to find the necessary startup files and configurations, which may also cause startup failure.

[0047] Additionally, errors may occur during the software upgrade process, such as incompatible firmware, damaged upgrade packages, or interrupted upgrade processes, which may also prevent the operating system from booting properly.

[0048] Thus, during the upgrade process, if the new software version is incompatible with the hardware or existing software, or if the upgrade process is interrupted, the operating system may not start.

[0049] Therefore, when a problem occurs in the operating system, each processor can be responsible for resetting its corresponding operating system.

[0050] However, the above reset process runs independently, and during the reset process, the current state and task information of the processor will be lost, which will cause the operating system to need to reinitialize and reload tasks after the reset, increasing the downtime of the operating system.

[0051] In addition, the operating system is reset directly. Since the state cannot be saved before the reset, the task cannot be restored in time during the reset, which can easily cause problems such as machine loss of control, which in turn causes users to perceive that there is a problem.

[0052] In response to the above problems, the present disclosure provides a control method for a target object, which uses a dual-core heterogeneous processor, each processor can run a different instruction set and / or operating system, and this architecture allows the target object to execute different types of tasks on different processors. In this way, during the startup process of any subsystem of the operating system, the operating status of the dual-core heterogeneous processor can be continuously detected to detect possible abnormal situations, such as deadlock, crash or upgrade abnormalities. If an abnormality is detected, the task information currently being executed by the dual-core heterogeneous processor can be saved, such as the progress of the task, the currently processed data, context information, etc. After saving the task information, the restart process of the operating system can be triggered, that is, the operating system is restarted based on this task information to quickly restore to the state before the abnormality occurred, so that the task can continue to be executed from the interruption point, reducing downtime.

[0053] Therefore, this anomaly detection and task information preservation mechanism enables the operating system to recover more quickly when encountering problems. Furthermore, by saving and restoring task status, the operating system can quickly resume normal operation after a reboot, significantly reducing operating system downtime. Furthermore, saving and restoring task status ensures task continuity, reducing task interruptions and data loss caused by operating system anomalies.

[0054] For example, Figure 1 A schematic diagram of an application scenario provided by an embodiment of the present disclosure, such as Figure 1 As shown, taking the target object as a sweeping robot 100 as an example, the sweeping robot 100 includes a dual-core heterogeneous processor 101. Optionally, the dual-core heterogeneous processor 101 includes a first processor 11 and a second processor 12, which can effectively allocate and manage different types of tasks.

[0055] For example, the first processor 11 can be responsible for high-level decision-making and planning, such as global path planning and navigation decisions, complex environmental perception tasks such as obstacle identification, receiving instructions from mobile applications, task scheduling, resource allocation, and inter-processor communication. The second processor 12 is responsible for low-level motion control and cleaning tasks, such as motor driving, speed regulation, and direction control.

[0056] In this way, during the startup of any subsystem of the operating system of the cleaning robot 100, such as the file system, if an abnormality is detected in either the first processor 11 or the second processor 12, such as when the second processor 12 is detected to have an abnormality when starting to execute a cleaning task, the task state of the second processor 12 currently executing the cleaning task can be saved. Then, the operating system of the cleaning robot 100 is restarted so that the cleaning task can be continued after the restart.

[0057] It should be noted that when saving the task status of the second processor 12 currently executing the cleaning task, the task status corresponding to the current task executed by the first processor 11 can also be saved. In this way, restarting the operating system of the sweeping robot 100 includes restarting the operating system corresponding to the first processor 11 and the operating system corresponding to the second processor 12.

[0058] In this way, when the operating systems corresponding to both processors are reset, the robot's operating system can be restored to a known initial state or baseline configuration state, and all parts of the operating system of the cleaning robot 100 are in a consistent state. This is crucial to ensuring the reliability and stability of the operating system.

[0059] It should be noted that the embodiments of the present disclosure do not specifically limit the application scenarios of the target object control method. For example, the target object control method can also be applied to other cleaning robots, medical robots, autonomous mobile robots, underwater robots and educational robots.

[0060] The following detailed description of the technical solution of the present disclosure and how the technical solution of the present disclosure solves the above-mentioned technical problems is provided with specific embodiments. The following specific embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. The embodiments of the present disclosure will be described below in conjunction with the accompanying drawings.

[0061] Figure 2 A flow chart of a method for controlling a target object provided by an embodiment of the present disclosure is shown as follows: Figure 2 As shown, the target object includes a dual-core heterogeneous processor, the dual-core heterogeneous processors correspond to different instruction sets and / or operating systems, and the dual-core heterogeneous processors share hardware resources; the control method of the target object includes:

[0062] S201: During the startup of any subsystem in the operating system of the target object, detect the operating status of the dual-core heterogeneous processor.

[0063] In the disclosed embodiment, the dual-core heterogeneous processor includes two different types of processor cores, and the two processor cores may use different instruction set architectures. For example, one core may use a processor architecture based on RISC principles, while the other core may use a RISC-V architecture.

[0064] Or each processor core can run a different operating system. For example, one core might run a real-time operating system while another runs Linux.

[0065] The two processor cores can access a shared memory space to exchange data and task status information.

[0066] It should be noted that in the target operating system, subsystem startup refers to the process of loading and initializing specific functional modules or services. For example, this includes the startup process of the file system and algorithm modules, as well as the communication between processors, communication between processors and slave modules, and the running of daemons.

[0067] For example, during the subsystem startup process, the operating status of the dual-core heterogeneous processor can be detected, and the operating status includes a healthy state, an abnormal state, and a normal operating state, etc. The abnormal state may include system scheduling, program abnormality, overload, overheating, resource conflict, communication failure, system crash, upgrade error, system partition damage, etc. The embodiment of the present disclosure does not limit the specific state corresponding to the abnormal state, which can be determined based on the actual application scenario.

[0068] S202: When it is determined that the running state is abnormal, save the task information currently running on the dual-core heterogeneous processor, and restart the operating system of the target object based on the task information.

[0069] In the embodiment of the present disclosure, task information may refer to the record information of the current task execution progress, which may include the context information of the task, the progress of the task, the memory status of the task, the input / output status data and intermediate results of the task, etc. The embodiment of the present application does not specifically limit the content of the currently running task information, which can be determined based on the actual scenario.

[0070] For example, the operating status of the dual-core heterogeneous processor is continuously monitored to detect any anomalies. If an anomaly is detected, an exception handling process is triggered. This exception handling process includes immediately saving the currently running task information and triggering an operating system restart. After the operating system restarts, the previously saved task information is used to restore the task status, allowing the task to resume execution from the point of interruption, minimizing work interruption and data loss caused by the anomaly.

[0071] Optionally, if the operating state of any processor in the dual-core heterogeneous processors is abnormal, restarting the operating system corresponding to the dual-core heterogeneous processors at the same time can clear the inconsistent state that may cause the abnormality, thereby restoring the consistency and normal operation of the operating system.

[0072] Alternatively, in some embodiments, if a processor experiences an abnormality in its operating state, only the operating system corresponding to that processor is restarted. This restart of only the operating system corresponding to the abnormal processor is generally faster than restarting the operating system corresponding to the dual-core heterogeneous processor, allowing the affected processor to resume normal operation more quickly, but with reduced stability.

[0073] Therefore, real-time monitoring of the processor's operating status during subsystem startup can help the operating system identify potential issues early. This preventative measure reduces the probability of OS crashes. When an anomaly is detected, saving the current task information and restarting the OS ensures that task information is not lost during the reboot process. This also ensures that the OS can quickly recover to a normal state in the event of an issue, reducing OS downtime and improving OS availability and reliability.

[0074] In addition, by saving and restoring task information, the operating system can continue to execute tasks from the interruption point after restart, ensuring task continuity and data integrity, and avoiding problems such as machine loss of control.

[0075] Optionally, the dual-core heterogeneous processor includes a first processor and a second processor, the first processor is configured with at least two timers, one timer is used to detect the operating status of the first processor, and the other timer is used to detect the operating status of the second processor; detecting the operating status of the dual-core heterogeneous processor includes:

[0076] A timer is used to detect whether an abnormality occurs in the operating state of any one of the first processor and the second processor.

[0077] In the disclosed embodiments, the first processor is typically designed as the main processor of the target object, responsible for executing complex computing tasks and managing the overall operation of the target object, and for handling high-level logic and decision-making tasks. For example, the first processor may be a processor architecture using RISC principles, and is used to execute complex application and operating system tasks.

[0078] The second processor is responsible for coordinating and executing fine control tasks. For example, the second processor may be a processor using a RISC-V architecture, which is used to execute specific control tasks, such as controlling the operation of the side brush assembly, the roller brush assembly, and the motor.

[0079] It should be noted that the timer can trigger an interrupt or event at a preset time interval to check the operating status of the processor. The timer can be a watchdog timer. The embodiment of the present disclosure does not specifically limit the type of timer, and it can be used to detect the operating status of the processor.

[0080] If the timer does not receive a normal response from the processor, such as a heartbeat signal, within a predetermined period, it can be considered that the processor may be abnormal. This process is called timeout detection.

[0081] Exemplarily, at least two watchdog timers are enabled on the first processor, wherein at least one watchdog timer is used to detect the operating status of the first processor to determine whether the operating system corresponding to the first processor is running normally. At least one other watchdog timer is used to detect the operating status of the second processor to determine whether the operating system corresponding to the second processor is running normally.

[0082] It should be noted that if the first processor is configured with multiple timers, two timers can be enabled when detecting the operating status of each processor. When problems occur with these two timers, other spare timers can be enabled. Alternatively, multiple timers can be allocated to each processor to improve the accuracy of anomaly detection. The embodiment of the present disclosure does not specifically limit the number of timers configured for the first processor. The above is only an example.

[0083] Because the timer can quickly detect abnormal processor conditions and take corrective measures immediately after a failure occurs, downtime is reduced. Therefore, using the timer to monitor the operating status of any processor in real time can identify potential problems early, ensuring rapid recovery and stable operation in abnormal situations, reducing system crashes or downtime caused by processor failures.

[0084] Optionally, at least two timers are reset within a preset period, indicating that the first processor and the second processor are in a normal operating state; and determining that an abnormality occurs in the operating state includes:

[0085] If it is determined that any timer has not been reset within the preset period, it is determined that the operating state is abnormal.

[0086] In the disclosed embodiment, when operating normally, the processors will send signals, such as heartbeat signals, within a preset period to reset their corresponding timers. If any processor fails to reset its timer within the preset period, the timer will time out. The timer expiration is used to confirm that the operating status of the processor is abnormal.

[0087] It is understandable that using a timer reset as a sign of normal processor operation is a simple and effective monitoring mechanism that is easy to implement and maintain. In addition, the timer reset operation usually has low overhead and has little impact on processor performance.

[0088] It should be noted that the embodiment of the present disclosure does not specifically limit the size of the preset period, which can be determined based on the performance of the timer. For example, the preset period of the watchdog timer can be 16 seconds.

[0089] For example, consider a scenario where one watchdog timer is used to monitor the operating status of a Linux system, and another watchdog timer is used to monitor the operating system corresponding to a RISC-V processor. After the file system is started, the operating system can periodically perform a "feed the watchdog" operation to reset both watchdog timers. If either watchdog timer times out after 16 seconds (i.e., it hasn't been reset within 16 seconds), then the processor's operating status detected by that watchdog timer is considered abnormal.

[0090] At this time, the task information currently executed by the Linux system and the operating system corresponding to the RISC-V processor can be saved, and the Linux system and the operating system corresponding to the RISC-V processor can be restarted based on the task information so that the current task can be continued at the next startup.

[0091] In some embodiments, the watchdog timer on the first processor can be periodically cleared by a monitoring program. If the monitoring program fails to complete the clearing process, i.e., the watchdog timer times out and is not reset, it indicates that there is a problem with the monitoring program itself. In this case, the current task state of the entire operating system is saved, and the first processor triggers the operating system restart process.

[0092] The slave module periodically clears the watchdog timer on the second processor. The monitoring program checks the clearing results. If the clearing is normal, it indicates normal operation. If the clearing is not normal, that is, the watchdog timer has timed out and has not been reset, the current task state of the entire operating system is saved, and the second processor triggers the operating system restart process.

[0093] Among them, the slave module refers to the control module that controls the peripheral of the target object. Taking the target object as a sweeping robot as an example, the peripheral can be a side brush assembly, a roller brush assembly, etc. The embodiment of the present disclosure does not specifically limit the type of peripheral.

[0094] This periodic reset mechanism of the timer allows real-time monitoring of the processor's operating status, ensuring it operates within the expected timeframe. If the timer doesn't reset within the preset period, it indicates a possible processor problem. This mechanism enables rapid anomaly detection. Therefore, by monitoring the processor's operating status, a timely restart can be performed, minimizing the impact of the failure on the target object and enhancing security.

[0095] In addition, timer timeout can quickly indicate abnormal status of the processor. Through timer timeout detection, it is easier to diagnose and analyze the cause of the fault, discover and handle potential faults early, and prevent the problem from expanding.

[0096] Optionally, the dual-core heterogeneous processor includes a first processor and a second processor, and a communication connection is established between the first processor and the second processor; and determining that an abnormality occurs in the operating state includes:

[0097] If the second processor does not receive the heartbeat information transmitted by the first processor within the preset time period, it is determined that the operating state is abnormal.

[0098] In the embodiment of the present disclosure, a reliable communication connection is established between the first processor and the second processor, which can be achieved through shared memory, bus interface or other communication protocols, and the embodiment of the present disclosure does not specifically limit the communication method between the two.

[0099] For example, the first processor and the second processor can communicate via heartbeat packets. The first processor periodically sends heartbeat packets to the second processor. A heartbeat packet is a simple signal, a form of heartbeat information. If the second processor receives the heartbeat packet within a preset time, it indicates that the first processor is operating normally.

[0100] The preset duration is a predetermined time interval set in advance, which can also be called a heartbeat cycle. During each heartbeat cycle, the first processor can send heartbeat information at least once. The embodiment of the present disclosure does not specifically limit the size of the preset duration, which can be set based on the requirements of the application scenario.

[0101] For example, the heartbeat mechanism can adjust the preset duration according to different application needs to adapt to different system performance and response requirements.

[0102] For example, if the second processor does not receive a heartbeat packet from the program on the first processor within 15 minutes, it determines that the operating state is abnormal. At this time, the second processor can actively panic and perform a "no dog feeding" operation, save the current task state of the entire operating system, and trigger the operating system restart process.

[0103] It's important to note that the heartbeat mechanism provides a simple and effective way to monitor the operating status of processors in real time, continuously monitoring the connection status between processors. If a second processor fails to receive heartbeat information from the first processor within a preset time, it can quickly identify a possible anomaly in the first processor and promptly initiate a restart. This improves the overall reliability of the target object and reduces operating system crashes or downtime caused by processor failures.

[0104] Optionally, the running state is represented in the form of identification information; during the startup of any subsystem in the operating system of the target object, detecting the running state of the dual-core heterogeneous processor includes:

[0105] After the file system of the target object is started, the running status is represented by the change of the detected identification information of the dual-core heterogeneous processor within a preset time period.

[0106] In the embodiments of the present disclosure, the identification information may be specific data or signals that represent the operating status. For example, the identification information may be an algorithm timestamp. Alternatively, it may be the value of a specific register, such as the zero flag (ZF), the carry flag (CF), or the overflow flag (OF). Alternatively, it may be an error code or status code generated by the processor. The embodiments of the present disclosure do not limit the content of the identification information; it may simply indicate whether the operating status is normal.

[0107] In this step, the identification information of the dual-core heterogeneous processor can be regularly collected and recorded within a preset period of time after the file system is started. By analyzing the changes in the identification information within the preset period of time, it can be determined whether the processor is operating normally. If the changes in the identification information exceed the normal range, it can be determined that there may be an abnormality in the processor.

[0108] For example, after the file system is started, a monitoring program may be used to continuously detect updated algorithm timestamps. If the algorithm timestamp is not updated for a period of time, it is determined that an abnormality occurs in the running state.

[0109] Therefore, by detecting changes in identification information, the processor's operating status can be monitored in real time, allowing for rapid detection of processor anomalies. This allows for prompt implementation of the restart process at an early stage of file system startup, thereby improving startup efficiency. Furthermore, by promptly detecting abnormal changes in identification information, abnormal processor status can be quickly identified and responded to, reducing the impact of faulty operations on the system and improving the reliability of the operating system.

[0110] Optionally, the method further includes:

[0111] In response to an operating system startup failure, recording the number of restarts caused by the operating system startup failure;

[0112] After the number of restarts exceeds a preset threshold, it is determined that the firmware of the operating system is abnormal.

[0113] In the disclosed embodiments, a reboot counter or a U-Boot-based counter can be set to record the number of reboots caused by operating system boot failures. Each time the operating system fails to boot and triggers a reboot, the reboot count is incremented. Furthermore, a preset threshold for the number of reboots is set as a criterion for determining firmware anomalies. If the number of reboots exceeds this threshold, it is determined that the operating system firmware may be anomaly.

[0114] It should be noted that the embodiment of the present disclosure does not specifically limit the size of the preset threshold, which can be set based on the requirements of the application scenario. For example, the preset threshold can be 7 times.

[0115] Optionally, operating system boot failures also include failures in the Boot0, U-Boot, and Kernel stages. After the target object is powered on, it sequentially enters the Boot0, U-Boot, and Kernel stages. After these three stages, the file boot stage begins. Therefore, if a boot failure occurs during these three stages and subsequent processes, U-Boot will accumulate the number of reboots. If the U-Boot count reaches a preset threshold, the operating system firmware is determined to be abnormal.

[0116] It should be noted that if the operating system fails to boot once, the U-Boot count increases by 1, and the reboot process is initiated. If the reboot is successful, the U-Boot count decreases by 1, and this process is continuously recorded. If the U-Boot count exceeds the preset threshold, that is, the operating system reboot occurs during the preset threshold number of consecutive boots and the boot fails, it indicates that the operating system firmware is abnormal.

[0117] Therefore, by monitoring and limiting the number of reboots, we can identify potential firmware issues and prevent repeated reboots from causing further damage to the operating system. Furthermore, by limiting the number of reboots, we avoid unnecessary reboots and effectively prevent infinite reboot loops caused by firmware anomalies, saving system resources and time, reducing wear and tear on hardware, and protecting the integrity and security of the operating system.

[0118] In addition, by automatically recording and monitoring the number of restarts, the need for manual intervention is reduced and the maintainability of the operating system is improved.

[0119] Optionally, the method further includes:

[0120] When it is determined that the firmware of the operating system is abnormal and the operating system of the target object is restarted again, the target object is controlled to perform a rollback operation.

[0121] In the embodiment of the present disclosure, one or more known stable firmware versions or operating system images are pre-stored in the operating system. When a firmware anomaly is detected and the system is restarted again, a stable firmware version or operating system image can be automatically loaded and started.

[0122] A rollback operation refers to rolling back the current software, firmware, or system version to a stable version. The stable version may be the previous version compared to the current version, or a default version. The disclosed embodiments do not specifically limit the version to which the rollback operation rolls back. For example, the rollback operation may also roll back to the N previous versions compared to the current version, where N is an integer greater than 1.

[0123] For example, if the target object restarts the operating system during seven consecutive boot attempts, resulting in a boot failure, the U-Boot count reset will not be triggered. The next time the target object is booted, it is considered that there is a problem with the current operating system firmware, and the U-Boot boot process will roll back to the previous version.

[0124] It should be noted that rolling back to the previous version refers to rolling back the entire version of the operating system corresponding to the first processor and the second processor.

[0125] This rollback operation can restore the operating system to its previous stable state, ensuring that the target object can continue to operate normally. Rapid rollback can significantly reduce operating system downtime, allowing the target object to return to normal working state more quickly, reducing the impact on task execution, and avoiding repeated failures caused by abnormal firmware, thereby improving the overall stability of the operating system.

[0126] In addition, the automated fallback mechanism can reduce the need for manual intervention, simplify the fault recovery process, and improve user experience and operating system availability.

[0127] Optionally, each dual-core heterogeneous processor includes at least one spare partition, where the spare partition is used to store a specified version of firmware corresponding to the operating system and / or a specified version of an image corresponding to the operating system; controlling the target object to perform a rollback operation includes:

[0128] The control target object calls the specified version of firmware and / or the specified version of the image in the spare partition to restore the operating system.

[0129] It should be noted that a processor usually has two main partitions: an active partition and a backup partition. The active partition is the partition that stores the image of the current version of the firmware and / or the operating system, and the backup partition is the partition that stores one or more specified versions of the firmware or operating system.

[0130] The specified version may refer to a previous version compared to the current version, or a default preset version, which is not specifically limited in the embodiment of the present disclosure.

[0131] Optionally, the dual-core heterogeneous processor has a dual-partition structure, that is, each processor has an active partition and a standby partition. When a problem occurs in the operating system corresponding to any one of the processors, the operating systems corresponding to the first processor and the second processor can be controlled to roll back at the same time to restore the operating system.

[0132] It should also be noted that if the algorithm program is damaged during the update process or due to other external reasons, the operating system still has the ability to automatically recover, that is, load the backup firmware or image from the backup partition to restore to a known good state.

[0133] The backup partition provides a safe fallback option. If a problem occurs with the current version, the operating system can be quickly restored to a known stable state by invoking the specified firmware and / or image versions in the backup partition, mitigating risk and reducing downtime. Storing specific firmware and image versions also allows for better version control and management, ensuring the operating system can be restored to the correct version when needed, avoiding recurring failures caused by abnormal firmware or operating system issues and maintaining operating system stability.

[0134] Optionally, the operating system fails to start, including at least one of the following:

[0135] Communication failure between the dual-core heterogeneous processor and peripherals;

[0136] Communication failure between dual-core heterogeneous processors;

[0137] The dual-core heterogeneous processor failed to start.

[0138] Among them, the failure of the dual-core heterogeneous processor to start up may be due to power problems, firmware errors, software or hardware failures, etc. If the algorithm main program detects that the algorithm has not started successfully, the embodiment of the present disclosure does not specifically limit the cause of the failure of the dual-core heterogeneous processor to start up.

[0139] In some embodiments, the operating system may attempt to initialize and communicate with peripherals during the boot process, and if communication with the peripherals fails, a restart process may be triggered.

[0140] For example, the algorithm main program can also detect whether communication between the algorithm and the peripheral is successful, for example, by sending instructions and responding to instructions to determine whether communication between the dual-core heterogeneous processor and the peripheral is successful. Alternatively, the algorithm main program can also determine whether communication between the dual-core heterogeneous processor and the peripheral is successful by sending a heartbeat packet. The disclosed embodiments do not specifically limit the method for determining whether communication between the dual-core heterogeneous processor and the peripheral is successful; the above is merely illustrative.

[0141] In other embodiments, communication between processors can be implemented via shared memory, a bus, or other interfaces. In this way, by detecting the communication between the dual-core heterogeneous processors, it is determined whether the operating system has been successfully started. If the communication between the processors fails, it indicates that the operating system has failed to start.

[0142] Optionally, in the present disclosure, whether the operating system has been successfully started can be determined by detecting whether the daemon process is running normally. If the daemon process cannot run, it means that the operating system has failed to start. In this case, the current task state of the entire operating system can be saved, triggering the operating system restart process so that the current task can be continued at the next startup.

[0143] Therefore, by identifying and addressing the specific cause of OS boot failure, normal operations can be restored more quickly. Detailed OS boot failure detection helps quickly locate the source of the problem, more comprehensively detects and identifies various issues that may arise during the boot process, and simplifies the troubleshooting process. Furthermore, after detecting the specific failure type, appropriate recovery measures can be quickly implemented, reducing downtime.

[0144] For example, Figure 3 A flow chart of an optional target object control method provided in an embodiment of the present disclosure is shown as follows: Figure 3 As shown, the control method of the target object includes the following steps:

[0145] S301: The target device boots up, and the three phases of Boot0, U-Boot, and Kernel are initiated in sequence. During the Boot0 phase, a watchdog timer on the first processor is started, and a determination is made as to whether the watchdog timer has timed out (i.e., whether the watchdog timer has been reset within a preset period). If the watchdog timer has timed out, the operating system is restarted.

[0146] Among them, the operating system will perform the "dog feeding" operation regularly in the three stages of Boot0, U-Boot, and Kernel, and will also perform the "dog feeding" operation regularly after the subsequent file system is started. In addition, in the U-Boot stage, if the operating system fails to start, the U-Boot count will increase by 1, and it will be determined whether the restart count is greater than 7 times. If 7 consecutive restarts are unsuccessful, the entire operating system will roll back to the previous version of the operating system.

[0147] S302: In the U-Boot stage, the second processor is started, and accordingly, the watchdog timer on the second processor side is started, and the "dog feeding" operation is started regularly. Then, it is determined whether the watchdog timer has timed out, that is, whether the watchdog timer has been reset within a preset period. If it is determined that the watchdog timer has timed out, the operating system of the target object is restarted.

[0148] After the scheduled "feed the dog" operation begins, the second processor can also detect the heartbeat packet sent by the first processor to the second processor. If the second processor does not receive the heartbeat packet within a specified time, it determines that the communication between the first and second processors is abnormal. At this time, the second processor can output an abnormality message and perform the "do not feed the dog" operation. Correspondingly, it can also restart the operating system of the target object.

[0149] S303: After the file system is started, the main algorithm program starts and starts the operating system health check, such as checking whether the algorithm is started and whether the algorithm and peripheral components are communicating successfully, to determine whether the operating system is running normally. If so, the startup count is cleared to ensure normal operation of the operating system.

[0150] This way, if the second processor detects a program runaway, meaning the algorithm has entered an unexpected state, it can quickly trigger a restart. This mechanism ensures that the operating system does not remain in an abnormal state for extended periods, thereby minimizing the impact on the normal functioning of the target object. Furthermore, task information can be saved before the operating system restarts, allowing the operating system to resume the task at the last interruption after the restart.

[0151] In the aforementioned embodiments, the target object control method provided by the embodiments of the present disclosure has been introduced. To implement the various functions of the target object control method provided by the embodiments of the present disclosure, the electronic device serving as the execution subject may include a hardware structure and / or a software module, and implement the aforementioned functions in the form of a hardware structure, a software module, or a combination of a hardware structure and a software module. Whether a particular function is implemented in the form of a hardware structure, a software module, or a combination of a hardware structure and a software module depends on the specific application and design constraints of the technical solution.

[0152] For example, Figure 4 This is a schematic diagram of a control device for a target object provided by an embodiment of the present disclosure, wherein the target object includes a dual-core heterogeneous processor, the dual-core heterogeneous processors correspond to different instruction sets and / or operating systems, and the dual-core heterogeneous processors share hardware resources; Figure 4 As shown, the control device 400 of the target object includes:

[0153] The detection module 401 is used to detect the operating status of the dual-core heterogeneous processor during the startup of any subsystem in the operating system of the target object;

[0154] The restart module 402 is configured to save the task information currently running on the dual-core heterogeneous processor and restart the operating system of the target object based on the task information when determining that an abnormality occurs in the running state.

[0155] Optionally, the dual-core heterogeneous processor includes a first processor and a second processor, the first processor is configured with at least two timers, one timer is used to detect the operating status of the first processor, and the other timer is used to detect the operating status of the second processor; the detection module 401 is specifically used to:

[0156] A timer is used to detect whether an abnormality occurs in the operating state of any one of the first processor and the second processor.

[0157] Optionally, at least two timers are reset within a preset period, indicating that the first processor and the second processor are in normal operation; the restart module 402 includes a determination unit, which is configured to:

[0158] If it is determined that any timer has not been reset within the preset period, it is determined that the operating state is abnormal.

[0159] Optionally, the dual-core heterogeneous processor includes a first processor and a second processor, and a communication connection is established between the first processor and the second processor; the determining unit is configured to:

[0160] If the second processor does not receive the heartbeat information transmitted by the first processor within the preset time period, it is determined that the operating state is abnormal.

[0161] Optionally, the operating status is represented in the form of identification information; the detection module 401 is specifically configured to:

[0162] After the file system of the target object is started, the running status is represented by the change of the detected identification information of the dual-core heterogeneous processor within a preset time period.

[0163] Optionally, the target object control device 400 further includes a determination module, which is configured to:

[0164] In response to an operating system startup failure, recording the number of restarts caused by the operating system startup failure;

[0165] After the number of restarts exceeds a preset threshold, it is determined that the firmware of the operating system is abnormal.

[0166] Optionally, the control device 400 for the target object further includes a control module, which is configured to:

[0167] When it is determined that the firmware of the operating system is abnormal and the operating system of the target object is restarted again, the target object is controlled to perform a rollback operation.

[0168] Optionally, each dual-core heterogeneous processor includes at least one spare partition, and the spare partition is used to store a specified version of firmware corresponding to the operating system and / or a specified version of an image corresponding to the operating system; the control module is specifically used to:

[0169] The control target object calls the specified version of firmware and / or the specified version of the image in the spare partition to restore the operating system.

[0170] Optionally, the operating system fails to start, including at least one of the following:

[0171] Communication failure between the dual-core heterogeneous processor and peripherals;

[0172] Communication failure between dual-core heterogeneous processors;

[0173] The dual-core heterogeneous processor failed to start.

[0174] It should be noted that the specific implementation principles and effects of the control device 400 for the above-mentioned target object can be found in the relevant descriptions and effects corresponding to the above-mentioned embodiments, and will not be elaborated on here.

[0175] For example, Figure 5 A structural schematic diagram of an electronic device is provided for an embodiment of the present disclosure. The electronic device 500 may include: a dual-core heterogeneous processor 101, a controller 501, and a memory 502 communicatively connected to the controller 501; the memory 502 stores a computer program; the controller 501 executes the computer program stored in the memory 502, so that the controller 501 executes the method described in any of the above embodiments.

[0176] The memory 502 and the controller 501 may be connected via a bus 503 .

[0177] It should be noted that the specific implementation principles and effects of the above-mentioned electronic device 500 can be found in the relevant descriptions and effects corresponding to the above-mentioned embodiments, and will not be elaborated here.

[0178] An embodiment of the present disclosure further provides a computer-readable storage medium, which stores computer-executable instructions. When the computer-executable instructions are executed by a processor, they are used to implement the method described in any of the aforementioned embodiments of the present disclosure.

[0179] An embodiment of the present disclosure further provides a chip for executing instructions, wherein the chip is used to execute the method described in any of the aforementioned embodiments as executed by the processor in any of the aforementioned embodiments of the present disclosure.

[0180] An embodiment of the present disclosure further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the method described in any of the aforementioned embodiments of the present disclosure and executed by the processor can be implemented.

[0181] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways.

[0182] For example, the device embodiments described above are merely illustrative. For example, the division of modules is merely a logical function division. In actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0183] On the other hand, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or module, which may be electrical, mechanical or other forms.

[0184] Modules described as separate components may or may not be physically separate, and components displayed as modules may or may not be physical units, that is, they may be located in one place or distributed across multiple network units.

[0185] Some or all of the modules may be selected according to actual needs to implement the solution of this embodiment.

[0186] In addition, the functional modules in the various embodiments of the present disclosure may be integrated into one processing unit, or each module may exist physically separately, or two or more modules may be integrated into one unit.

[0187] The above modules can be implemented in the form of hardware or hardware plus software functional units. The above integrated modules implemented in the form of software functional modules can be stored in a computer-readable storage medium.

[0188] The above-mentioned software function module is stored in a storage medium, including a number of instructions for enabling a computer device (which may be a personal computer, server, or network device, etc.) or a processor to execute some steps of the method described in each embodiment of the present disclosure.

[0189] It should be understood that the above-mentioned processor may be a central processing unit (CPU), or other general-purpose processors, a digital signal processor (DSP), an application specific integrated circuit (ASIC), etc.

[0190] The general purpose processor may be a microprocessor or any conventional processor, etc. The steps of the method disclosed in the disclosure may be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in the processor.

[0191] The memory may include high-speed random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage, and may also be a USB flash drive, a mobile hard disk, a read-only memory, a magnetic disk, or an optical disk.

[0192] The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus.

[0193] The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, the bus in the drawings of the present disclosure is not limited to only one bus or one type of bus.

[0194] The above-mentioned storage medium can be implemented by any type of volatile or non-volatile storage device, or a combination thereof, such as static random-access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0195] An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium may be an integral part of the processor. The processor and storage medium may be located in an application-specific integrated circuit (ASIC). Alternatively, the processor and storage medium may be present as discrete components within the cleaning device or the main control device.

[0196] It should be noted that, for the sake of simplicity of description, the aforementioned method embodiments are all expressed as a series of action combinations. However, those skilled in the art should know that the present disclosure is not limited to the order of the actions described, because according to the present disclosure, certain steps can be performed in other orders or simultaneously.

[0197] Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all optional embodiments, and the actions and modules involved are not necessarily required for this disclosure. It should be further noted that although the steps in the flowchart are shown in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows.

[0198] Unless otherwise specified herein, there is no strict order restriction for the execution of these steps, and these steps may be executed in other orders. Furthermore, at least some of the steps in the flowchart may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times. The order of execution of these sub-steps or stages is not necessarily sequential, but may be executed in rotation or alternation with other steps or at least a portion of the sub-steps or stages of other steps.

[0199] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0200] The technical features of the above embodiments can be combined in any manner. To simplify the description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there are no contradictions in the combination of these technical features, they should be considered to be within the scope of this specification. Those skilled in the art will easily conceive of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein.

[0201] This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0202] The above description is merely a specific implementation of the embodiments of the present disclosure, but the scope of protection of the embodiments of the present disclosure is not limited thereto. Any changes or substitutions within the technical scope disclosed in the embodiments of the present disclosure shall be included in the scope of protection of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope of protection of the claims.

[0203] The above description is merely a specific implementation of the embodiments of the present disclosure, but the scope of protection of the embodiments of the present disclosure is not limited thereto. Any changes or substitutions within the technical scope disclosed in the embodiments of the present disclosure shall be included in the scope of protection of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope of protection of the claims.

Claims

1. A method for controlling a target object, characterized in that: The target object includes a dual-core heterogeneous processor, the dual-core heterogeneous processors correspond to different instruction sets and / or operating systems, and the dual-core heterogeneous processors share hardware resources; the method includes: During the startup of any subsystem in the operating system of the target object, detecting the operating status of the dual-core heterogeneous processor; When it is determined that the running state is abnormal, the task information currently running on the dual-core heterogeneous processor is saved, and the operating system of the target object is restarted based on the task information.

2. The method according to claim 1, characterized in that The dual-core heterogeneous processor includes a first processor and a second processor, the first processor is configured with at least two timers, one timer is used to detect the operating status of the first processor, and the other timer is used to detect the operating status of the second processor; The detecting the operating status of the dual-core heterogeneous processor includes: The timer is used to detect whether an abnormality occurs in the operating state of any one of the first processor and the second processor.

3. The method according to claim 2, characterized in that The at least two timers are reset within a preset period, which is used to indicate that the first processor and the second processor are in a normal operating state; Determining that the operating state is abnormal includes: If it is determined that any of the timers is not reset within the preset period, it is determined that the operating state is abnormal.

4. The method according to claim 1, wherein The dual-core heterogeneous processor includes a first processor and a second processor, and a communication connection is established between the first processor and the second processor; Determining that the operating state is abnormal includes: If the second processor does not receive the heartbeat information transmitted by the first processor within a preset time period, it is determined that the operating state is abnormal.

5. The method according to claim 1, characterized in that The operating state is represented by identification information; and during the startup of any subsystem in the operating system of the target object, detecting the operating state of the dual-core heterogeneous processor includes: After the file system of the target object is started, the operating state is represented by changes in the detected identification information of the dual-core heterogeneous processor within a preset time period.

6. The method according to claim 1, characterized in that The method further comprises: In response to the operating system startup failure, recording the number of restarts caused by the operating system startup failure; After the number of restarts exceeds a preset threshold, it is determined that the firmware of the operating system is abnormal.

7. The method according to claim 6, characterized in that The method further comprises: When it is determined that the firmware of the operating system is abnormal and the operating system of the target object is restarted again, the target object is controlled to perform a rollback operation.

8. The method according to claim 7, characterized in that Each of the dual-core heterogeneous processors includes at least one spare partition, and the spare partition is used to store a specified version of firmware corresponding to the operating system and / or a specified version of an image corresponding to the operating system; The controlling the target object to perform a rollback operation includes: The target object is controlled to call the specified version of the firmware and / or the specified version of the image in the spare partition to recover the operating system.

9. The method according to claim 6, characterized in that The operating system startup failure includes at least one of the following situations: Communication between the dual-core heterogeneous processor and the peripheral device fails; Communication between the dual-core heterogeneous processors fails; The dual-core heterogeneous processor failed to start.

10. A control device for a target object, characterized in that: The target object includes a dual-core heterogeneous processor, the dual-core heterogeneous processors correspond to different instruction sets and / or operating systems, and the dual-core heterogeneous processors share hardware resources; the device includes: a detection module, configured to detect the operating status of the dual-core heterogeneous processor during the startup of any subsystem in the operating system of the target object; The restart module is used to save the task information currently running on the dual-core heterogeneous processor and restart the operating system of the target object based on the task information when it is determined that the running state is abnormal.

11. An electronic device, characterized in that: include: A dual-core heterogeneous processor, a controller, and a memory in communication with the controller; The memory stores computer-executable instructions; The controller executes the computer-executable instructions stored in the memory to implement the method according to any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 9 when executed by a processor.

13. A computer program product, characterized in that The invention comprises a computer program, which implements the method according to any one of claims 1 to 9 when the computer program is executed by a processor.

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