Data stream architecture-based many-core processor system and task scheduling method

Abstract

The invention belongs to the field of many-core processor design, and particularly relates to a many-core processor system based on a data flow framework and a task scheduling method.The system comprises a system control node, computing nodes and storage nodes which are connected through an on-chip internet, and each storage node and at least one computing node form a computing cluster; the system control node sends an instruction and data to the storage node through the on-chip internet, and the storage node distributes the data to the computing nodes in the computing cluster; an initialization unit of the computing node monitors a data buffer area of the on-chip internet through a state register, data are moved to a buffer unit, and initialization of a computing core is completed; the scheduling unit is responsible for scheduling a task queue, and transferring data required by a next task to the cache unit in advance through the DMA unit to realize parallel calculation and data transferring; the computing unit executes the computing task, and the data directly flows among different computing nodes, so that the memory access requirement is reduced, and the computing resource utilization rate is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of many-core processor design, and in particular relates to a many-core processor system and a task scheduling method based on a data flow architecture. Background Art

[0002] Traditional many-core processor architectures face numerous bottlenecks that hinder performance improvements. Regarding initialization efficiency, traditional architectures employ a per-core approach to register configuration and communication link establishment. As the number of cores increases, startup time increases linearly, significantly impacting performance in real-time applications. Memory access latency is also a significant issue. During operation, computing units spend over 70% of their time waiting for data. Shared bus architectures trigger severe memory access conflicts, and remote memory access latency can be 5-10 times that of local access. Even with the use of high-bandwidth memory (HBM), data locality remains difficult to effectively address.

[0003] In terms of computing resource utilization, traditional scheduling strategies cannot efficiently dispatch computing data and instructions, resulting in long periods of idle waiting for computing units and low computing efficiency. These issues severely limit the effectiveness of many-core processors in high-performance computing scenarios such as AI training and 5G communications, and a new architecture is urgently needed to address these challenges. Summary of the Invention

[0004] In response to the above problems faced by traditional many-core processor architectures, the present invention provides a many-core processor system and a task scheduling method based on a data flow architecture to solve the above technical problems.

[0005] In a first aspect, the technical solution of the present invention provides a many-core processor system based on a data flow architecture, comprising: System control node, used to communicate with the host and receive instructions and data sent by the host; Multiple computing nodes, each integrating a dedicated computing core, the computing core including an initialization unit, a scheduling unit, a DMA unit, an operation unit, a bus matrix, and a cache unit; the bus matrix supports many-to-many parallel data transmission between multiple AXIMasters and AXI Slaves within the computing core; Multiple storage nodes, each storage node and at least one computing node form a computing cluster for storing and distributing data; An on-chip interconnection network connecting the system control nodes, computing nodes, and storage nodes for data transmission and routing; The system control node sends instructions and data to the storage node through the on-chip interconnect network, and the storage node distributes the data to the computing nodes in the computing cluster; The initialization unit of the computing node monitors the data buffer of the on-chip interconnect network through the status register, moves the data to the cache unit, and completes the initialization of the computing core; The scheduling unit is responsible for scheduling the task queue and moves the data required for the next task to the cache unit in advance through the DMA unit, thus achieving parallel calculation and data movement. The computing unit performs computing tasks, and data flows directly between different computing nodes, avoiding frequent access to external storage units.

[0006] The collaborative work of system control nodes and storage nodes reduces the time required to configure registers and establish communication links on a per-core basis, significantly improving initialization efficiency and resolving the linear growth of startup time with the number of cores in traditional architectures. The on-chip interconnect network and cache units within the compute nodes reduce reliance on the shared bus, avoiding memory access conflicts. Pre-fetching data through the DMA unit reduces the waiting time of the compute unit and effectively resolves the memory access latency issue. The scheduling unit dynamically adjusts the order of task queues and pre-fetches data, enabling parallel processing of computation and data movement, avoiding idle waiting of the computation unit and improving computing resource utilization.

[0007] As a further limitation of the technical solution of the present invention, the system control node encapsulates the instructions and data sent by the host into a data packet that complies with the on-chip interconnection network transmission standard, and the data packet format includes: The packet type field is used to identify the instruction or data type; Destination address field, used for routing in the on-chip interconnect network; Source address field, used for response data transmission; Load data field, which stores instructions or calculation data; The on-chip interconnection network selects the optimal routing path according to the destination address field in the data packet, and implements caching or forwarding of the data packet through dynamic link status monitoring until the data packet reaches the target storage node.

[0008] The system control node encapsulates instructions and data into packets in a specific format, facilitating efficient transmission and routing within the on-chip interconnect network. The packet type field specifies the instruction or data type, helping the receiving node to correctly process it. The destination and source address fields provide critical information for routing and data transmission. The on-chip interconnect network selects the optimal routing path based on the destination address and dynamically monitors link status to cache or forward packets, ensuring that data reaches its target storage node accurately and efficiently. This improves data transmission efficiency and reliability, further optimizing overall system performance.

[0009] As a further limitation of the technical solution of the present invention, after receiving the data packet, the storage node performs the following operations: If the data packet is an instruction, the instruction is parsed and a computing task queue is generated; If the data packet is computing data, the data is split into sub-data sets according to the computing task requirements; The sub-datasets or task instructions are repackaged into data packets, the destination address field is updated to the address of the corresponding computing node in the computing cluster, and distributed to each computing node through the on-chip interconnection network.

[0010] The storage nodes classify and process received data packets, parse the instructions into computational task queues, split the computational data into sub-datasets, and repackage them into data packets for distribution to the compute nodes within the compute cluster. This processing method ensures that computational tasks and data are accurately assigned to the corresponding compute nodes, improving the accuracy and efficiency of task scheduling, avoiding resource waste, and further enhancing the system's computing performance.

[0011] As a further limitation of the technical solution of the present invention, the initialization unit of the computing node has an AXI Master function, which monitors the data status of the on-chip interconnect network data buffer in real time through the status register, and triggers the DMA unit to move the data to the local cache unit when data is detected to complete data preparation.

[0012] The compute node's initialization unit features AXI Master functionality, actively monitoring the data buffer's status through status registers and promptly triggering the DMA unit to move data when it's ready. This real-time monitoring and rapid response mechanism ensures rapid completion of the initialization process, improving system startup speed and real-time performance, and providing strong support for subsequent computing tasks.

[0013] As a further limitation of the technical solution of the present invention, the scheduling unit receives the computing task queue from the system control node and assigns a priority label to each computing task; monitors the status register of the operation unit in real time to obtain the progress information of the currently executed task; and dynamically adjusts the task queue order according to the task dependency and computing resource occupancy rate.

[0014] The scheduling unit assigns priority tags to computing tasks, enabling them to be scheduled appropriately based on their importance and urgency. Real-time monitoring of the status registers of the computing units provides task progress information, enabling the scheduling unit to promptly understand task execution. Dynamically adjusting the task queue order based on task dependencies and computing resource utilization ensures efficient task execution, avoids resource conflicts and task waiting, and improves computing resource utilization and overall system performance.

[0015] As a further limitation of the technical solution of the present invention, when the computing unit executes task A, the scheduling unit performs the following parallel operations: Analyze the data requirements of the next task B to be executed in the task queue; Locate the physical address of the data required by Task B by querying the storage node address mapping table; Initiate a prefetch request to the DMA unit, which includes: source address, destination address, data volume information, and priority identifier; After receiving the prefetch request, the DMA unit initiates an AXI bus transaction through the bus matrix; During data transfer, the dispatch unit continuously monitors the DMA status register and the arithmetic unit status register; exception handling is triggered when any of the following conditions occurs: Task A completes ahead of schedule but data is not ready: insert an idle cycle or switch to a lower-priority task; Data is ready in advance but task A is not completed: update the cache unit tag to standby state.

[0016] While the arithmetic unit is executing task A, the scheduling unit prefetches data for the next task, task B, in parallel. This enables parallel computation and data movement, further improving computational efficiency. The physical address of the data is located by querying the storage node address mapping table, ensuring accurate data movement. A prefetch request is sent to the DMA unit, along with detailed information, enabling the DMA unit to efficiently complete the data movement task. The status register is continuously monitored during the data movement process, and exception handling is triggered promptly when an abnormality occurs, ensuring system stability and reliability.

[0017] As a further limitation of the technical solution of the present invention, when the computing unit completes task A: The scheduling unit checks the ready status of task B data in the cache unit; If the data is ready, immediately jump the program counter to the entry address of task B; If the data is not ready, the following options are selected based on priority: High priority task: trigger interrupt to force DMA to accelerate transmission; Low-priority task: Suspend the current thread and execute the ready task.

[0018] When the arithmetic unit completes Task A, the scheduling unit promptly checks the data readiness status of Task B and takes appropriate action based on the data's readiness. If the data is ready, the program counter immediately jumps to execute Task B, reducing task switching latency. If the data is not ready, different processing methods are selected based on task priority, ensuring that high-priority tasks are executed first and lower-priority tasks are processed at the appropriate time, improving system responsiveness and task execution flexibility.

[0019] As a further limitation of the technical solution of the present invention, when data fails to flow between computing nodes, the scheduling unit will trigger a data retransmission mechanism and select an alternative routing path through the on-chip interconnect network.

[0020] When data fails to flow between computing nodes, the scheduling unit triggers a data retransmission mechanism and selects an alternate routing path, ensuring reliable data transmission. This fault-tolerant mechanism avoids task interruptions and data loss caused by data transmission failures, improving system stability and reliability and ensuring the smooth progress of computing tasks.

[0021] In a second aspect, the technical solution of the present invention further provides a task scheduling method based on the many-core processor system described in the first aspect, comprising the following steps: The system control node receives computing tasks from the host, encapsulates the tasks into data packets, and sends them to the storage node via the on-chip interconnection network; The storage node parses the data packet. If the data packet is an instruction, a computing task queue is generated. If the data packet is computing data, the data is split into sub-data sets according to the computing task requirements, and the sub-data sets or task instructions are repackaged into data packets. The storage node distributes the data packets to the corresponding computing nodes through the on-chip interconnection network according to the addresses of the computing nodes in the computing cluster; The scheduling unit of the computing node receives the task queue and assigns a priority tag to each task. The scheduling unit dynamically adjusts the order of the task queue based on task dependencies and computing resource utilization. At the same time, the scheduling unit uses the DMA unit to move the data required for the next task to the cache unit in advance. The arithmetic unit executes the current task, and the scheduling unit monitors the status register of the arithmetic unit in real time; when the current task is completed, the scheduling unit checks the ready status of the data required for the next task. If the data is ready, it immediately switches to the next task; if the data is not ready, it performs corresponding processing according to the task priority.

[0022] This task scheduling method achieves efficient task scheduling in a many-core processor system through a series of steps. The system control node encapsulates tasks into data packets and sends them to the storage node. The storage node parses and re-encapsulates the data packets before distributing them to the compute nodes, ensuring accurate task and data allocation. The compute node's scheduling unit improves task execution efficiency and computing resource utilization by assigning priority tags, dynamically adjusting the task queue order, and preemptively moving data. The scheduling unit monitors the arithmetic unit status registers in real time and takes appropriate action based on the data readiness status and task priority, ensuring timely and rational task switching and improving overall system performance.

[0023] As a further limitation of the technical solution of the present invention, when the computing unit executes task A, the scheduling unit performs the following parallel operations: Analyze the data requirements of the next task B to be executed in the task queue; Locate the physical address of the data required by Task B by querying the storage node address mapping table; Initiate a prefetch request to the DMA unit, which includes: source address, destination address, data volume information, and priority identifier; After receiving the prefetch request, the DMA unit initiates an AXI bus transaction through the bus matrix; During data transfer, the dispatch unit continuously monitors the DMA status register and the arithmetic unit status register; exception handling is triggered when any of the following conditions occurs: Task A completes ahead of schedule but data is not ready: insert an idle cycle or switch to a lower-priority task; Data is ready in advance but task A is not completed: update the cache unit tag to standby state.

[0024] This method pre-fetches data for the next task, Task B, while the arithmetic unit is executing Task A. This enables parallel computation and data movement, improving computational efficiency. By querying the address mapping table to locate the data's physical address, initiating pre-fetch requests, and continuously monitoring the status register, this method ensures accurate and efficient data movement. It also handles exceptions promptly, ensuring system stability and reliability.

[0025] As a further limitation of the technical solution of the present invention, when the computing unit completes task A, the scheduling unit performs the following operations: The scheduling unit checks the ready status of task B data in the cache unit; If the data is ready, immediately jump the program counter to the entry address of task B; If the data is not ready, the following options are selected based on priority: High priority task: trigger interrupt to force DMA to accelerate transmission; Low-priority task: Suspend the current thread and execute the ready task.

[0026] When the arithmetic unit completes task A, it promptly checks the data readiness status of task B and takes appropriate action based on the data readiness. By immediately jumping the program counter to execute task B or selecting a processing method based on task priority, the system's response speed and task execution flexibility are improved, ensuring that high-priority tasks are executed first and lower-priority tasks are processed at the appropriate time.

[0027] As a further limitation of the technical solution of the present invention, the method also includes an exception handling step: during the data transfer process, the scheduling unit continuously monitors the DMA status register and the operation unit status register, and when an abnormal situation is detected, it is processed according to a preset exception handling strategy.

[0028] The dispatch unit continuously monitors the status register during data transfer and promptly handles any abnormalities it detects according to the pre-set exception handling strategy. This exception handling mechanism improves the system's fault tolerance and stability, ensuring normal operation in the event of an abnormality and avoiding task interruption and data loss.

[0029] As a further limitation of the technical solution of the present invention, the exception handling strategy includes: When task data is lost or damaged, re-initiate data request; When a computing unit fails, the task is switched to other available computing nodes; When congestion occurs in the on-chip interconnect network, the data transmission path is adjusted or data transmission is suspended until the network status returns to normal.

[0030] When task data is lost or corrupted, re-issuing the data request ensures data integrity. When a computing unit fails, the task is switched to another available computing node, ensuring continued execution. When the on-chip interconnect network becomes congested, the data transmission path is adjusted or data transmission is suspended until the network returns to normal, minimizing the impact of network congestion on system performance. These exception handling strategies further improve system stability and reliability, ensuring the efficient operation of the many-core processor system under various circumstances.

[0031] The beneficial effect of the present invention is that it realizes the rapid initialization of the many-core processor system, reduces the memory access requirements, and improves the computing resource utilization. The many-core processor system effectively solves multiple bottleneck problems of traditional many-core processors through the data flow architecture. In terms of initialization efficiency, the initialization unit of the computing node monitors the data buffer through the status register and moves the data to complete the initialization, avoiding the inefficient operation of the core-by-core configuration register, greatly shortening the startup time, and improving real-time performance. In terms of memory access latency, data flows directly between different computing nodes, reducing the need for frequent access to external storage units and reducing memory access latency. At the same time, the bus matrix supports many-to-many parallel data transmission, alleviating the memory access conflict problem. In terms of computing resource utilization, the scheduling unit moves data in advance through the DMA unit, realizing the parallelization of calculation and data movement, reducing the idle waiting time of the computing unit, and improving computing resource utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0033] Figure 1 The figure is a schematic block diagram of the system architecture of an embodiment of the present invention.

[0034] Figure 2 This is a block diagram of the computing core in an embodiment of the present invention.

[0035] Figure 3 This is a block diagram of a data flow implementation method in an embodiment of the present invention. DETAILED DESCRIPTION

[0036] In order to make the purpose, features, and advantages of the present invention more obvious and easy to understand, the technical solutions of the present invention will be clearly and completely described below in conjunction with the drawings in the specific embodiments. Obviously, the embodiments described below are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0037] like Figure 1 As shown, an embodiment of the present invention provides a many-core processor system based on a data flow architecture, comprising: System control node, used to communicate with the host and receive instructions and data sent by the host; Multiple computing nodes, each of which integrates a dedicated computing core, such as Figure 2 As shown, the computing core includes an initialization unit, a scheduling unit, a DMA unit, an operation unit, a bus matrix and a cache unit; the bus matrix supports many-to-many parallel data transmission between multiple AXI Masters and AXI Slaves within the computing core; Multiple storage nodes, each storage node and at least one computing node form a computing cluster for storing and distributing data; An on-chip interconnection network connecting the system control nodes, computing nodes, and storage nodes for data transmission and routing; The system control node sends instructions and data to the storage node through the on-chip interconnect network, and the storage node distributes the data to the computing nodes in the computing cluster; The initialization unit of the computing node monitors the data buffer of the on-chip interconnect network through the status register, moves the data to the cache unit, and completes the initialization of the computing core; The scheduling unit is responsible for scheduling the task queue and moves the data required for the next task to the cache unit in advance through the DMA unit, thus achieving parallel calculation and data movement. The computing unit performs computing tasks, and data flows directly between different computing nodes, avoiding frequent access to external storage units.

[0038] In the embodiment of the present invention, the system control node receives instructions and data sent by the host, and sends the instructions and data to the storage node through the on-chip interconnection network; After receiving a data packet, if the data packet is an instruction, the storage node parses the instruction and generates a computing task queue. If the data packet is computing data, the data is split into sub-data sets according to the computing task requirements, and the sub-data sets or task instructions are repackaged into data packets. The destination address field is updated to the address of the corresponding computing node in the computing cluster, and the data is distributed to each computing node through the on-chip interconnect network. The initialization unit of the computing node monitors the data buffer of the on-chip interconnect network through the status register. When a data packet with a matching destination address is detected, the DMA unit moves the data to the local cache unit to complete the initialization of the computing core. The scheduling unit receives the computing task queue from the system control node and assigns a priority tag to each computing task; monitors the status register of the computing unit in real time to obtain the progress information of the currently executed task; and dynamically adjusts the task queue order based on task dependencies and computing resource utilization. When the computing unit executes task A, the scheduling unit analyzes the data requirements of the next task to be executed, B, in the task queue. By querying the storage node address mapping table, it locates the physical address of the data required by task B and initiates a prefetch request to the DMA unit. The request contains the source address, destination address, data amount information, and priority identifier. After receiving the prefetch request, the DMA unit initiates an AXI bus transaction through the bus matrix. During the data transfer process, the scheduling unit continuously monitors the DMA status register and the arithmetic unit status register. When task A is completed early but the data is not ready, or when the data is ready early but task A is not completed, an exception is triggered. When the computing unit completes task A, the scheduling unit checks the ready status of task B data in the cache unit; if the data is ready, the program counter immediately jumps to the entry address of task B; if the data is not ready, an interrupt is triggered according to the priority to force DMA to accelerate the transmission or suspend the current thread and execute the ready task.

[0039] In some embodiments, the system control node encapsulates the instructions and data sent by the host into a data packet that complies with the on-chip interconnection network transmission standard, and the data packet format includes: The packet type field is used to identify the instruction or data type; Destination address field, used for routing in the on-chip interconnect network; Source address field, used for response data transmission; Load data field, which stores instructions or calculation data; The on-chip interconnect network selects the optimal routing path based on the destination address field in the data packet and caches or forwards the data packet through dynamic link status monitoring until the packet reaches the target storage node. By encapsulating data packets that meet the on-chip interconnect network transmission standards, the efficiency and accuracy of data transmission are ensured. The packet format design enables the on-chip interconnect network to select the optimal routing path based on the destination address field and cache or forward the data packet through dynamic link status monitoring, further improving data transmission efficiency and solving the data transmission delay problem in traditional architectures.

[0040] In some embodiments, after receiving the data packet, the storage node performs the following operations: If the data packet is an instruction, the instruction is parsed and a computing task queue is generated; If the data packet is computing data, the data is split into sub-data sets according to the computing task requirements; The sub-datasets or task instructions are repackaged into data packets, the destination address field is updated to the address of the corresponding computing node in the computing cluster, and distributed to each computing node through the on-chip interconnection network.

[0041] Storage nodes can classify and process data packets based on their type, parsing instructions into task queues, splitting computational data into sub-datasets, and repackaging and distributing them to compute nodes. This flexible data management approach improves the flexibility and efficiency of task scheduling, while reducing data transmission redundancy and further optimizing computing resource utilization.

[0042] In some embodiments, the initialization unit of the computing node has an AXI Master function, which monitors the data status of the on-chip interconnect network data buffer in real time through a status register, and triggers the DMA unit to move the data to the local cache unit when data is detected to complete data preparation.

[0043] The initialization unit monitors the data status of the on-chip interconnect network data buffer in real time through a status register. When data is detected, it triggers the DMA unit to move the data to the local cache unit. This design reduces data waiting time during the initialization process, improves initialization efficiency, and ensures that the computing core can quickly enter the working state.

[0044] In some embodiments, the scheduling unit receives a computing task queue from a system control node and assigns a priority tag to each computing task; monitors the status register of the computing unit in real time to obtain progress information of the currently executing task; and dynamically adjusts the task queue order based on task dependencies and computing resource occupancy.

[0045] The scheduling unit assigns a priority tag to each computing task and dynamically adjusts the task queue order based on task dependencies and computing resource utilization. This dynamic scheduling mechanism optimizes the execution order of tasks based on real-time system status, further improving computing resource utilization and reducing idle waiting time of computing units.

[0046] In some embodiments, when the computing unit executes task A, the scheduling unit performs the following parallel operations: Analyze the data requirements of the next task B to be executed in the task queue; Locate the physical address of the data required by Task B by querying the storage node address mapping table; Initiate a prefetch request to the DMA unit, which includes: source address, destination address, data volume information, and priority identifier; After receiving the prefetch request, the DMA unit initiates an AXI bus transaction through the bus matrix; During data transfer, the dispatch unit continuously monitors the DMA status register and the arithmetic unit status register; exception handling is triggered when any of the following conditions occurs: Task A completes ahead of schedule but data is not ready: insert an idle cycle or switch to a lower-priority task; Data is ready in advance but task A is not completed: update the cache unit tag to standby state.

[0047] While the arithmetic unit is executing the current task, the scheduling unit pre-fetches the data required for the next task and efficiently moves data through the DMA unit and bus matrix. This parallel processing mechanism reduces data waiting time during task switching and further improves computing efficiency.

[0048] In some embodiments, when the computing unit completes task A: The scheduling unit checks the ready status of task B data in the cache unit; If the data is ready, immediately jump the program counter to the entry address of task B; If the data is not ready, the following options are selected based on priority: High priority task: trigger interrupt to force DMA to accelerate transmission; Low-priority task: Suspend the current thread and execute the ready task.

[0049] When the arithmetic unit completes its current task, the scheduling unit flexibly selects a task switching strategy based on the readiness of the data required by the next task. For high-priority tasks, an interrupt is triggered to force DMA to accelerate the transfer, ensuring rapid task startup. For low-priority tasks, the current thread is suspended and other ready tasks are executed, further optimizing the flexibility and efficiency of task scheduling.

[0050] In some embodiments, when data fails to flow between computing nodes, the scheduling unit will trigger a data retransmission mechanism and select an alternative routing path through the on-chip interconnect network.

[0051] When data fails to flow between computing nodes, the scheduling unit triggers a data retransmission mechanism and selects an alternative routing path through the on-chip interconnect network. This mechanism improves data transmission reliability, avoids task delays or failures caused by network failures or data loss, and further enhances system stability and reliability.

[0052] In the embodiment of the present invention, the system control node is responsible for communicating with the host, sending the instructions and data issued by the host to the storage node through the on-chip interconnection network. One storage node and three computing nodes form a computing cluster, such as Figure 3 As shown in the figure, the storage node is responsible for distributing data to the computing nodes in the computing cluster, shortening the system initialization time and data transmission delay; the data to be sent is packaged into a standard data packet format, where the destination address is the computing node in the computing cluster, so that data distribution can be achieved.

[0053] In an embodiment of the present invention, in order to reduce the frequency of data memory access and alleviate the problem of reduced computing efficiency caused by memory walls, the computing model is divided into different task flows, and different computing nodes complete different computing tasks. When the data calculation of different tasks is completed, it flows directly to the next task computing node instead of storing the data in storage units such as DD, thereby avoiding frequent access to external storage units, improving computing efficiency, and realizing a data flow computing mode; the compiler is responsible for compiling computing tasks into instruction code streams that can be recognized by the execution unit CPU. The computing model refers to a computing task, such as the common computing models ResNet18, MobileNet, etc. The main advantage of the data flow architecture is that it can realize the direct flow transmission of computing data between various computing nodes, avoiding multiple reading and writing of data in memory. Frequent access to memory units will seriously increase computing delays and reduce computing efficiency.

[0054] In AI training, data often needs to be frequently transferred between multiple compute nodes. This application utilizes a dataflow architecture, allowing data to flow directly between compute nodes, avoiding frequent access to external storage units (such as DDR) and reducing memory access latency. This significantly reduces the impact of memory wall issues on AI training and improves data transfer efficiency, enabling higher throughput, particularly when processing large datasets. The compiler divides computational models (such as ResNet18 and MobileNet) into multiple task flows, each executed on a different compute node. This task flow partitioning allows data to be transferred directly between compute nodes, reducing reliance on shared memory. This improves computing resource utilization, reduces multiple data reads and writes to memory, further reduces memory access latency, and enhances overall computing efficiency. Model initialization is a critical step in AI training scenarios. This application reduces initialization time by enabling collaborative work between storage and compute nodes. The storage nodes send initialization data to the cache units of the compute nodes via the on-chip interconnect network. The initialization units monitor the data buffers in real time through status registers, enabling rapid initialization. Task continuity and data timeliness are crucial in AI training. The scheduling unit of this application uses the DMA unit to move the data required for the task to the cache unit in advance, achieving parallel processing of calculation and data movement. When the current task is completed, the data required for the next task is ready and can be calculated immediately. This reduces data waiting time during task switching and improves computing efficiency, making it particularly suitable for the complex task scheduling requirements of AI training.

[0055] Each computing node is equipped with a local cache unit to store the data required for the task. The data is moved to the cache unit in advance through the DMA unit, reducing the frequency of access to the shared memory. The data access speed is improved and the memory access latency is reduced, which is particularly suitable for the frequent small data block access requirements in AI training. In summary, in the AI ​​training scenario, this application significantly improves the performance and efficiency of the system through data flow architecture, fast initialization, parallel data prefetching, dynamic task scheduling, local cache units, efficient on-chip interconnection networks and compiler optimization.

[0056] An embodiment of the present invention also provides a task scheduling method for the many-core processor system described in the above embodiment, wherein the many-core processor system includes a system control node, a computing node, and a storage node, and each node is connected through an on-chip interconnection network; the on-chip interconnection network provides a data transmission channel between the many cores, and after each node packages the data, the on-chip interconnection network completes the route selection and the control of the data transmission status, and finally transmits the data from the source node to the destination node; the system control node is responsible for communicating with the host, and sends the instructions and data issued by the host to the storage node through the on-chip interconnection network, and a storage node and three computing nodes form a computing cluster, and the storage node is responsible for data distribution among the computing nodes in the computing cluster, thereby shortening the system initialization time and data transmission delay; each computing node integrates a dedicated computing core, and the computing core includes an initial ization unit, scheduling unit, DMA (direct memory access) unit, operation unit, bus matrix and cache unit; during the system initialization process, the storage node sends the corresponding data to the corresponding data buffer of the on-chip interconnection network through the on-chip interconnection network. The initialization unit inside the computing core is a unit with master device function designed by the user and has the relevant functions of AXIMaster. The initialization unit monitors the status of the on-chip interconnection network in real time through the status register. When it detects that there is data in the on-chip interconnection network data buffer, the data is moved to the cache unit inside the computing core. The data moved during the initialization process is generally the user application program. After the data is moved, the sub-processor CPU of the corresponding unit is reset to realize the normal initialization startup of each unit; the bus matrix realizes the various AXI inside the computing core To improve communication efficiency between the Master and AXI Slave, the bus matrix supports many-to-many parallel data transmission. After the multi-core processor system is booted, it enters normal working mode. The operation unit is responsible for completing the corresponding vector operations, matrix operations, and other computing tasks. At the same time, the scheduling unit is responsible for scheduling the task queue and requests the corresponding data from the internal cache unit of the computing core through the on-chip interconnect network in advance based on the computing data required by the task. When the operation unit completes the calculation of the previous task, the data required for the next computing task is already prepared in advance, so the calculation can begin immediately without waiting for data, thereby improving computing efficiency. To further improve data transmission efficiency, the scheduling unit can achieve efficient data transfer through the DMA unit. To reduce the frequency of data memory access and alleviate the problem of reduced computing efficiency caused by memory walls, the compiler divides the computing model into different task flows, and different computing nodes complete different computing tasks. After the data calculation of different tasks is completed, it flows directly to the next task computing node instead of storing the data in storage units such as DDR. This avoids frequent access to external storage units, improves computing efficiency, and realizes a data flow computing model. The method includes the following steps: S1, the system control node receives the computing task issued by the host, encapsulates the task into a data packet and sends it to the storage node through the on-chip interconnection network; S2. The storage node parses the data packet. If the data packet is an instruction, a computing task queue is generated. If the data packet is computing data, the data is split into sub-data sets according to the computing task requirements, and the sub-data sets or task instructions are repackaged into data packets. S3. The storage node distributes the data packet to the corresponding computing node through the on-chip interconnect network according to the address of the computing node in the computing cluster; S4. The scheduling unit of the computing node receives the task queue and assigns a priority tag to each task. The scheduling unit dynamically adjusts the order of the task queue based on task dependencies and computing resource utilization. At the same time, the scheduling unit uses the DMA unit to move the data required for the next task to the cache unit in advance. S5. The arithmetic unit executes the current task, and the scheduling unit monitors the status register of the arithmetic unit in real time. When the current task is completed, the scheduling unit checks the ready status of the data required for the next task. If the data is ready, it immediately switches to the next task. If the data is not ready, it performs corresponding processing according to the task priority.

[0057] In this embodiment of the present invention, when the computing unit executes task A, the scheduling unit performs the following parallel operations: Analyze the data requirements of the next task B to be executed in the task queue; Locate the physical address of the data required by Task B by querying the storage node address mapping table; Initiate a prefetch request to the DMA unit, which includes: source address, destination address, data volume information, and priority identifier; After receiving the prefetch request, the DMA unit initiates an AXI bus transaction through the bus matrix; During data transfer, the dispatch unit continuously monitors the DMA status register and the arithmetic unit status register; exception handling is triggered when any of the following conditions occurs: Task A completes ahead of schedule but data is not ready: insert an idle cycle or switch to a lower-priority task; Data is ready in advance but task A is not completed: update the cache unit tag to standby state.

[0058] When the computing unit completes task A, the scheduling unit performs the following operations: The scheduling unit checks the ready status of task B data in the cache unit; If the data is ready, immediately jump the program counter to the entry address of task B; If the data is not ready, the following options are selected based on priority: High priority task: trigger interrupt to force DMA to accelerate transmission; Low-priority task: Suspend the current thread and execute the ready task.

[0059] The method also includes an exception handling step: during the data transfer process, the scheduling unit continuously monitors the DMA status register and the operation unit status register, and when an abnormal situation is detected, it is processed according to a preset exception handling strategy.

[0060] The exception handling strategy includes: When task data is lost or damaged, re-initiate data request; When a computing unit fails, the task is switched to other available computing nodes; When congestion occurs in the on-chip interconnect network, the data transmission path is adjusted or data transmission is suspended until the network status returns to normal.

[0061] Although the present invention has been described in detail with reference to the accompanying drawings and in conjunction with preferred embodiments, the present invention is not limited thereto. Without departing from the spirit and essence of the present invention, persons of ordinary skill in the art may make various equivalent modifications or substitutions to the embodiments of the present invention, and such modifications or substitutions shall be within the scope of the present invention. Any changes or substitutions that can be easily conceived by persons skilled in the art within the technical scope disclosed in the present invention shall be within the scope of protection of the present invention.

Claims

1. A many-core processor system based on a data flow architecture, characterized in that: include: System control node, used to communicate with the host and receive instructions and data sent by the host; Multiple computing nodes, each computing node integrates a dedicated computing core, the computing core including an initialization unit, a scheduling unit, a DMA unit, an operation unit, a bus matrix and a cache unit; The bus matrix supports many-to-many parallel data transmission between multiple AXIMasters and AXI Slaves within the computing core; Multiple storage nodes, each storage node and at least one computing node form a computing cluster for storing and distributing data; An on-chip interconnection network connecting the system control nodes, computing nodes, and storage nodes for data transmission and routing; The system control node sends instructions and data to the storage node through the on-chip interconnect network, and the storage node distributes the data to the computing nodes in the computing cluster; The initialization unit of the computing node monitors the data buffer of the on-chip interconnect network through the status register, moves the data to the cache unit, and completes the initialization of the computing core; The scheduling unit is responsible for scheduling the task queue and moves the data required for the next task to the cache unit in advance through the DMA unit, thus achieving parallel calculation and data movement. The computing unit performs computing tasks, and data flows directly between different computing nodes, avoiding frequent access to external storage units.

2. The many-core processor system based on data flow architecture according to claim 1, characterized in that: The system control node encapsulates the instructions and data sent by the host into data packets that comply with the on-chip interconnection network transmission standard. The data packet format includes: The packet type field is used to identify the instruction or data type; Destination address field, used for routing in the on-chip interconnect network; Source address field, used for response data transmission; The payload data field stores instructions or calculation data; The on-chip interconnection network selects the optimal routing path according to the destination address field in the data packet, and implements caching or forwarding of the data packet through dynamic link status monitoring until the data packet reaches the target storage node.

3. The many-core processor system based on data flow architecture according to claim 2, characterized in that: After receiving the data packet, the storage node performs the following operations: If the data packet is an instruction, the instruction is parsed and a computing task queue is generated; If the data packet is computing data, the data is split into sub-data sets according to the computing task requirements; The sub-datasets or task instructions are repackaged into data packets, the destination address field is updated to the address of the corresponding computing node in the computing cluster, and distributed to each computing node through the on-chip interconnection network.

4. The many-core processor system based on data flow architecture according to claim 3, characterized in that: The initialization unit of the computing node has the AXI Master function, which monitors the data status of the on-chip interconnect network data buffer in real time through the status register, and triggers the DMA unit to move the data to the local cache unit when data is detected to complete data preparation.

5. The many-core processor system based on data flow architecture according to claim 4, characterized in that: The scheduling unit receives the computing task queue from the system control node and assigns a priority tag to each computing task; it monitors the status register of the computing unit in real time to obtain the progress information of the currently executed task; and it dynamically adjusts the task queue order according to the task dependency and computing resource occupancy rate.

6. The many-core processor system based on data flow architecture according to claim 5, characterized in that: When the computing unit executes task A, the scheduling unit performs the following parallel operations: Analyze the data requirements of the next task B to be executed in the task queue; Locate the physical address of the data required by Task B by querying the storage node address mapping table; Initiate a prefetch request to the DMA unit, which includes: source address, destination address, data volume information, and priority identifier; After receiving the prefetch request, the DMA unit initiates an AXI bus transaction through the bus matrix; During data transfer, the dispatch unit continuously monitors the DMA status register and the arithmetic unit status register; exception handling is triggered when any of the following conditions occurs: Task A completes ahead of schedule but data is not ready: insert an idle cycle or switch to a low-priority task; Data is ready in advance but task A is not completed: update the cache unit tag to standby status.

7. The many-core processor system based on data flow architecture according to claim 6, characterized in that: When the computing unit completes task A: The scheduling unit checks the ready status of task B data in the cache unit; If the data is ready, immediately jump the program counter to the entry address of task B; If the data is not ready, the following options are selected based on priority: High priority task: trigger interrupt to force DMA to accelerate transmission; Low-priority task: Suspend the current thread and execute the ready task.

8. A task scheduling method based on the many-core processor system according to any one of claims 1 to 7, characterized in that: The following steps are involved: The system control node receives computing tasks from the host, encapsulates the tasks into data packets, and sends them to the storage node via the on-chip interconnection network; The storage node parses the data packet. If the data packet is an instruction, a computing task queue is generated. If the data packet is computing data, the data is split into sub-data sets according to the computing task requirements, and the sub-data sets or task instructions are repackaged into data packets. The storage node distributes the data packets to the corresponding computing nodes through the on-chip interconnection network according to the addresses of the computing nodes in the computing cluster; The scheduling unit of the computing node receives the task queue and assigns a priority tag to each task. The scheduling unit dynamically adjusts the order of the task queue based on task dependencies and computing resource utilization. At the same time, the scheduling unit uses the DMA unit to move the data required for the next task to the cache unit in advance. The arithmetic unit executes the current task, and the scheduling unit monitors the status register of the arithmetic unit in real time. When the current task is completed, the scheduling unit checks the readiness of the data required for the next task. If the data is ready, it immediately switches to the next task. If the data is not ready, it will be processed accordingly according to the task priority.

9. The task scheduling method of the many-core processor system according to claim 8, characterized in that: When the computing unit executes task A, the scheduling unit performs the following parallel operations: Analyze the data requirements of the next task B to be executed in the task queue; Locate the physical address of the data required by Task B by querying the storage node address mapping table; Initiate a prefetch request to the DMA unit, which includes: source address, destination address, data volume information, and priority identifier; After receiving the prefetch request, the DMA unit initiates an AXI bus transaction through the bus matrix; During data transfer, the dispatch unit continuously monitors the DMA status register and the arithmetic unit status register; exception handling is triggered when any of the following conditions occurs: Task A completes ahead of schedule but data is not ready: insert an idle cycle or switch to a low-priority task; Data is ready in advance but task A is not completed: update the cache unit tag to standby status.

10. The task scheduling method of the many-core processor system according to claim 9, characterized in that: When the computing unit completes task A, the scheduling unit performs the following operations: The scheduling unit checks the ready status of task B data in the cache unit; If the data is ready, immediately jump the program counter to the entry address of task B; If the data is not ready, the following options are selected based on priority: High priority task: trigger interrupt to force DMA to accelerate transmission; Low-priority task: Suspend the current thread and execute the ready task.

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