A serial port instruction and embedded controller-based SPD burning method and system

Abstract

The application discloses a serial port instruction and embedded controller-based SPD programming method and system, relates to the embedded field, and comprises the following steps: connecting a master and a slave through a serial port cable and configuring serial port parameters; monitoring a serial port data buffer through a timing polling mode by using an embedded controller; after obtaining a data reaching event, extracting an instruction data packet and comparing and verifying the instruction data packet with a pre-stored instruction feature library; after the instruction verification passes, receiving an SPD data packet input by a user through the serial port, performing data format analysis and verification processing; writing the SPD data after the verification passes into a target chip by using an I2C bus in a page-by-page mode, and performing read-back verification and verification after each page writing operation; and aiming at the low SPD programming efficiency and low data reliability in the prior art, the application improves the reliability of programming data by constructing an embedded controller SPD programming based on serial port instruction control and integrating multiple data verification mechanisms.

Description

Technical Field

[0001] This application relates to the field of embedded systems, and in particular to an SPD programming method and system based on serial port instructions and an embedded controller. Background Technology

[0002] With the rapid development of computer memory technology, the Serial Presence Detect (SPD) chip, as a key component of memory modules, stores important configuration information such as memory timing parameters, capacity information, and manufacturer data. The accuracy of SPD data directly affects system memory initialization, performance optimization, and compatibility, making SPD programming technology crucial in the memory industry chain. With the widespread adoption of next-generation memory standards such as DDR4 and DDR5, and the continuous improvement in memory frequency and capacity, higher demands are placed on the reliability, efficiency, and flexibility of SPD programming technology.

[0003] Currently, the industry mainly adopts three SPD programming technology solutions:

[0004] Existing Solution 1: Offline Independent Burning Technology

[0005] This solution uses a dedicated EEPROM programmer (such as RT809F, CH341A, etc.) to directly program the memory module via a DIP socket, requiring physical disassembly of the SPD chip on the memory module before off-site programming. However, this solution has significant drawbacks: the disassembly and assembly risks are extremely high, requiring physical removal of the memory heatsink or SPD chip, which can easily lead to irreversible damage such as PCB deformation and solder pad detachment; the programming efficiency is low, with programming a single chip taking approximately 30-45 seconds, only 1 / 40th the efficiency of an automated production line, and labor costs accounting for more than 60% of the total cost; compatibility is limited, the programmer firmware needs continuous updates to support new SPD chips, resulting in high maintenance costs.

[0006] Existing Solution 2: In-System Programming (ISP) Technology

[0007] This solution utilizes the SMBus interface (an I2C-derived protocol) of the memory slots and achieves hot-spinning via the motherboard PCH bridge, requiring precise control of the bus arbitration timing. However, this solution faces hardware compatibility limitations: it relies on the motherboard IC interface, and some OEMs lock bus access permissions, resulting in a spelling failure rate as high as 30%; for DDR5 memory, its PMIC (Power Management Chip) needs to be configured synchronously, and traditional ISP tools cannot provide full support, requiring additional hardware adaptation; motherboard manufacturers need to consider spelling compatibility during the design phase, increasing hardware design complexity.

[0008] Existing Solution 3: Automated Production Line Programming System

[0009] This solution is integrated into the memory module production line, employing a fully automated programming approach. It utilizes precision robotic arms for multi-channel parallel operation and AOI (Automated Optical Inspection) to ensure contact reliability, completing SPD programming during the memory module production stage. However, this solution lacks flexibility in the later stages: once memory manufacturers have programmed the SPD, it is extremely inconvenient for motherboard manufacturers to modify the SPD configuration according to their own designs; the initial investment cost is high, with equipment procurement costs typically exceeding several million yuan, and it requires a MES management system, making it suitable only for large-scale mass production, which is unaffordable for small and medium-sized enterprises; system maintenance costs are high, with annual replacement costs for easily damaged components such as probes and pneumatic modules being exorbitant.

[0010] In summary, existing SPD programming technologies suffer from low efficiency, insufficient reliability, high cost, complex operation, and poor flexibility, making it difficult to meet the current memory industry's demand for efficient, reliable, and flexible SPD programming. The limitations of existing technologies are particularly pronounced in application scenarios requiring batch modification of SPD configurations, small-to-medium-scale production, or field debugging, necessitating a new technical solution to address these issues. Summary of the Invention

[0011] To address the issues of low SPD programming efficiency and low data reliability in existing technologies, this application provides an SPD programming method and system based on serial port commands and an embedded controller. By constructing an embedded controller SPD programming system controlled by serial port commands and integrating multiple data verification mechanisms, the reliability of the programmed data is improved.

[0012] One aspect of this application provides an SPD programming method based on serial port commands and an embedded controller, comprising: connecting a host and a slave device with a serial cable; configuring serial port parameters, including baud rate, data bits, stop bits, and parity bits; using the embedded controller to monitor the serial port data buffer through a timed polling method; when a data arrival event is obtained, extracting the command data packet and comparing it with a pre-stored command feature library for verification; when the command verification is successful, receiving the SPD data packet input by the user through the serial port, performing data format parsing and verification processing; and writing the verified SPD data to the target chip page by page using the I2C bus, adopting a page-based writing mode and performing readback verification after each page writing operation.

[0013] The SPD (Serial Presence Detect) is a miniature EEPROM chip on the memory module, communicating via an I2C interface and storing key memory parameters. The SPD chip records core data such as memory type, capacity, timing parameters, and operating voltage. When the computer boots up, the BIOS automatically reads the SPD information to configure the memory controller, enabling plug-and-play functionality. Modern SPDs also include XMP overclocking configuration, supporting one-click memory performance upgrades. DDR4 memory typically has a 512-byte SPD capacity, uses a standard 100kHz I2C interface, and has a fixed address range of 0x50-0x57. This not only ensures stable memory operation but also provides the system with the ability to automatically identify and optimize memory configuration.

[0014] Embedded Controller (EC): In this solution, EC refers to a microcontroller chip integrated into the motherboard or a separate hardware module, possessing a serial communication interface and I2C bus control capabilities. This controller runs dedicated firmware, responsible for receiving and parsing serial port commands, executing SPD data processing, controlling I2C bus timing, and managing the state machine of the entire programming process. The EC has built-in non-volatile memory for storing instruction feature libraries and configuration parameters.

[0015] Data Arrival Event: This refers to an event flag triggered when the embedded controller detects the arrival of new data in the serial port data buffer through a timed polling mechanism. When the data counter in the serial port receive FIFO buffer changes or the receive interrupt flag is set, the EC recognizes this as a data arrival event and immediately initiates the data extraction and processing flow.

[0016] Command Data Packet: This refers to structured instruction information transmitted via serial port, containing components such as instruction header, function code, parameter fields, and checksum. In SPD programming applications, command data packets are used to control operations such as starting, stopping, and configuring parameters in the programming process. They have fixed format specifications and specific identifiers, facilitating EC parsing and verification.

[0017] CommandFeatureLibrary: A database of predefined instruction templates stored in the non-volatile memory of the embedded controller. It contains feature information for all legal instructions, such as instruction code, parameter range, format specifications, and functional descriptions. The EC verifies the legality and completeness of instructions by comparing each received instruction data packet with the templates in the CommandFeatureLibrary, ensuring that only authorized SPD programming instructions can be executed.

[0018] I2C (Inter-Integrated Circuit Bus) is a bidirectional two-wire serial bus protocol developed by Philips, using a serial data line (SDA) and a serial clock line (SCL) for communication. In this solution, the I2C bus serves as the data transmission channel between the embedded controller and the SPD chip, supporting master-slave communication. The EC acts as the master device, controlling the bus timing, while the SPD chip acts as the slave device, responding to read and write operations.

[0019] PageWriteMode: An optimized data writing strategy that divides large-capacity SPD data into multiple data pages of a fixed size (16 bytes in this scheme) and writes them page by page. This mode fully utilizes the page buffering characteristics of the EEPROM chip, improving write efficiency by writing a complete page of data at once. It also facilitates precise error location and recovery mechanisms. After each page is written, a readback check is performed immediately to ensure data integrity.

[0020] Specifically, this application achieves full compatibility with the entire range of SPD specifications from DDR3 to DDR5 by adopting the standard I2C protocol and a standardized SPD register mapping mechanism. Based on the unified I2C interface definition and register address mapping specifications in the SPD standard, the embedded controller's adaptive protocol stack can automatically identify different types of SPD chips and adopt corresponding timing parameters and register operation sequences. This design ensures forward compatibility and technical continuity, eliminating the need for major hardware or firmware modifications for different memory standards.

[0021] On the other hand, a state machine control approach is adopted to selectively activate debugging function modules based on serial port commands, including enabling and disabling functions such as matrix keyboard scanning and serial port printing. This mechanism avoids the resource waste caused by function modules being resident in memory and running continuously in traditional solutions. Through a dynamic resource allocation strategy, it effectively reduces the CPU utilization and power consumption of the embedded controller, thereby improving the overall system operating efficiency and response speed.

[0022] Furthermore, the data format parsing includes: receiving standardized input data, wherein the standardized input data adopts the format of register offset address + data value, wherein both the register offset address and the data value are hexadecimal numbers and separated by a preset delimiter; parsing the standardized input data using a preset regular expression pattern, extracting the register offset address and the corresponding data value, and converting the hexadecimal string into a hexadecimal value and storing it in a data buffer sorted by address; when a single line of data is extracted, the pointer is incremented to point to the next line of data; when a data end marker is detected or a preset number of lines is reached, it is determined that the data extraction is complete, and the subsequent verification process is started.

[0023] The "Register Offset Address + DataValueFormat" refers to the standardized data representation format used when users input SPD data. The "Register Offset Address" is the address offset of the internal memory unit of the SPD chip, represented by a 1-byte hexadecimal number (e.g., 00, 01, FF), used to specify the specific register location to be operated on. The "Data Value" refers to the specific data content to be written to that register address, also represented by a 1-byte hexadecimal number. The entire format adopts the structure of "address + separator + value," for example, "00A0" indicates writing data 0xA0 at offset address 0x00, and "1A,FF" indicates writing data 0xFF at offset address 0x1A. This format is easy for users to understand and input, and also facilitates program parsing and verification.

[0024] Address-Sorted Arrangement: This refers to a storage organization method in which the extracted address-data pairs in the data buffer are arranged in ascending order according to the numerical value of the register offset address. In practice, the embedded controller parses the multiple lines of "address + data" combinations input by the user and then sorts and stores them according to the hexadecimal value of the offset address (e.g., 0x00 < 0x01 < 0x02 ... < 0xFF), ensuring that data at address 0x00 is placed first and data at address 0xFF is placed last. The technical advantages of this sorting method are: it facilitates subsequent sequential writing to the SPD chip, improving the write efficiency of the I2C bus; it facilitates data management and error location; and it conforms to the physical arrangement order of the SPD chip registers, avoiding timing issues caused by random jump access.

[0025] Furthermore, the preset regular expression pattern includes a first capture group and a second capture group, wherein: the first capture group is used to match a combination of 1 to 2 hexadecimal characters and extract the register offset address; the second capture group is used to match a combination of 1 to 2 hexadecimal characters and extract the corresponding data value; the regular expression pattern is ^([0-9A-Fa-f]{1,2})[ / s,]+([0-9A-Fa-f]{1,2}), wherein the first capture group and the second capture group are separated by a whitespace character or a comma separator.

[0026] Here, ^ (line start anchor) indicates that the match must start from the beginning of the string, ensuring the strictness of the entire line's data format. In the SPD programming scheme, this anchor prevents invalid characters or spaces from being introduced into the user's input data line, ensuring that each line of data is parsed starting from a valid register address, thus improving the accuracy of data format verification.

[0027] ([0-9A-Fa-f]{1,2}) (First Capture Group): Parentheses (): Define the first capture group, used to extract the matched register offset address; [0-9A-Fa-f]: Character class, matching a single hexadecimal character, including the digits 0-9 and the letter AF (case-insensitive); {1,2}: Quantifier, indicating that the preceding character class must appear 1 to 2 times, allowing input of single-byte (such as A, F) or double-byte (such as 0A, FF) hexadecimal addresses; In this scheme, this capture group is specifically used to extract the register offset address of the SPD chip, supporting all valid address values ​​in the range of 0x00 to 0xFF.

[0028] [ / s,]+ (Separator Mode): [ / s,]: Character class, matches whitespace characters (including spaces, tabs) or commas; +: Quantifier, indicates that the preceding character class must appear once or more; This mode is designed to identify the separator between addresses and data, supports a variety of common separators (such as "00A0", "00,A0", "00A0"), and improves the flexibility and error tolerance of user input.

[0029] ([0-9A-Fa-f]{1,2}) (Second Capture Group): This group has the same structure as the first capture group and is used to extract the data value to be written to the SPD chip. This capture group supports 1 to 2 hexadecimal characters, allowing the user to input any data value within the range of 0x00 to 0xFF, satisfying the writing requirements of the SPD chip's 8-bit data register.

[0030] In particular, this regular expression enables automatic recognition and parsing of standardized data formats in the SPD burning solution. It extracts address and data information simultaneously through a dual capture group mechanism and ensures the validity of input data through strict character class restrictions, providing a reliable data source for subsequent hexadecimal conversion and SPD writing operations.

[0031] When the format parsing of standardized input data using a preset regular expression pattern fails, an error report is generated by the embedded controller and fed back via serial port to ensure the integrity and correctness of the input data.

[0032] Further, the verification process includes: initializing a 16-bit CRC checksum; reading the SPD data to be verified byte by byte; performing a left-shift XOR operation on each data byte, shifting the byte data left by N bits and then XORing it with the current CRC value; preferably, N is set to 8. Multiple shift operations are performed on the XOR result, shifting left by 1 bit each time and checking the status of the most significant bit. If the most significant bit is 1, it is XORed with a preset polynomial; otherwise, only a left shift operation is performed. After processing each byte, the lowest 16 bits of the result are truncated as the updated CRC value, and this process is repeated until all data verification calculations are completed. The final CRC verification result is compared with the pre-stored CRC baseline value in the SPD to verify data integrity.

[0033] Among them, the most significant bit (MSB): in the CRC check calculation process, it refers to the leftmost bit (15th bit, bit

[15] ) of the current operation result binary data. In the CRC-16 algorithm implementation of this scheme, after each left shift operation, it is necessary to check the status of the most significant bit of the operation result: if the most significant bit is 1, it means that the data overflow needs to be corrected by polynomial. At this time, an XOR operation with the preset CRC generator polynomial (such as 0x1021) is performed to eliminate the overflow effect; if the most significant bit is 0, only a simple left shift operation is performed. This mechanism is a key component of the core logic of the CRC algorithm, ensuring the mathematical correctness of the check calculation and the error detection capability.

[0034] The least significant 16 bits refer to the lowest 16 bits (bits [15:0]) extracted from the CRC checksum result during the calculation process, discarding the higher bits. In this SPD programming scheme, due to the use of the CRC-16 checksum algorithm, the final checksum length is fixed at 16 bits. After completing the CRC calculation for each byte, regardless of the number of bits in the intermediate calculation result, only the lowest 16 bits are retained as the valid CRC checksum value, thus ensuring the consistency of the checksum length and the standardization of the algorithm.

[0035] CRC Reference Value: This refers to a 16-bit cyclic redundancy check code pre-stored in a specific register of the SPD chip, serving as a standard reference value for data integrity verification. This reference value is typically calculated and generated when the SPD chip leaves the factory or during its first successful programming, and written to the SPD chip's dedicated CRC register (e.g., addresses 0x7E-0x7F). In the data verification process of this programming scheme, the real-time CRC check result calculated by the embedded controller needs to be compared bit-by-bit with this reference value: if they are completely consistent, it indicates that no errors occurred during SPD data transmission and storage, and data integrity is verified; if there are differences, it indicates that the data may have been corrupted during transmission or storage, and the programming operation needs to be re-executed.

[0036] Furthermore, the verified SPD data is written to the target chip page by page using the I2C bus, including: reading 16 bytes of data to be written from the start address of the data buffer; selecting the target I2C physical channel through the data selector and generating an I2C start signal; sending a 7-bit slave address byte, where the read / write bits of the address byte are set to 0 to indicate the write operation mode, and waiting for the slave to return an ACK signal to confirm successful address recognition; when the slave returns an ACK signal, starting the data transmission sequence, transmitting 16 bytes of data byte by byte in the order of the most significant bit first, and waiting for the slave to return an ACK signal after each byte transmission before continuing to transmit the next byte; after completing the 16-byte data page write operation, starting the data readback verification process, reading the written data from the SPD chip through the I2C read operation, and performing line-by-line bit verification with the original written data.

[0037] The I2C physical channel (I2CPhysicalChannel) refers to the specific hardware path for data transmission between the embedded controller and the SPD chip. In this programming scheme, the I2C physical channel consists of a two-wire bus composed of a serial data line (SDA) and a serial clock line (SCL). A specific target channel can be selected from multiple I2C channels using a data selector (such as a multiplexer), enabling independent access to different SPD chips. This physical channel supports master-slave communication mode, where the embedded controller acts as the master device, controlling the bus timing and data transmission rhythm, and the SPD chip acts as the slave device, responding to read and write operations. The channel's electrical characteristics conform to the I2C standard specification.

[0038] The I2C Start Signal is a specific timing signal used in the I2C communication protocol to identify the start of data transmission. In this SPD programming scheme, the start signal is generated by transitioning the serial data line (SDA) from high to low while the serial clock line (SCL) is held high. This signal announces to all devices on the bus that a new data transmission transaction is about to begin, and all slave devices enter listening mode to prepare to receive address information. The start signal is a key component of the I2C bus arbitration mechanism, ensuring communication order and data integrity in a multi-master environment.

[0039] Slave Address Byte: This refers to the 8-bit address information used to identify the target slave device in I2C communication. In this SPD programming scheme, this address byte consists of a 7-bit device address and a 1-bit read / write control bit. The 7-bit device address is determined by the configuration of the SPD chip's A0, A1, and A2 pins, and is used to uniquely identify a specific SPD chip on the I2C bus. The least significant bit (LSB) is the read / write control bit; setting it to 0 indicates write operation mode, and setting it to 1 indicates read operation mode. After the master controller sends this address byte, the SPD chip with a matching address on the bus will respond and participate in subsequent data transmission, while other devices remain silent.

[0040] The Acknowledge Signal (ACK) is a feedback signal used by the slave device in the I2C protocol to acknowledge successful data reception. In this SPD programming scheme, the timing of the ACK signal is as follows: After the master device sends 8 bits of data (address byte or data byte), it releases control of the SDA line in the 9th clock cycle. If the slave device successfully receives and recognizes the data, it pulls the SDA line low to generate an ACK signal (logic 0) in that clock cycle. If the slave device fails to receive the data correctly or the address mismatch occurs, it keeps the SDA line high to generate a NACK signal (logic 1). The embedded controller determines the success of communication by detecting the status of the ACK signal, providing a basis for subsequent data transmission decisions and error handling.

[0041] Furthermore, the data readback verification process also includes: when the readback verification fails, querying the current retry counter status; if the number of retries has not exceeded a preset threshold, re-initiating the readback operation for secondary verification; preferably, the threshold is set to 3, i.e., 3 retries. If the threshold is exceeded, it is determined to be a data error, a page erase command is sent to the SPD chip, the corresponding page data is retransmitted, and the verification state machine is reset; continuously monitoring the data pointer offset of the buffer register, comparing it with the total data length register to determine the write progress, and when the pointer offset reaches the total data length, sending an I2C stop signal and releasing bus control.

[0042] The retry counter (RetryCounter) is a counter register maintained internally by the embedded controller to record the number of failed readback verifications of the current data page. In this SPD programming scheme, when a readback verification failure occurs, the retry counter automatically increments by 1. The system compares the current value of the counter with a preset threshold (3 times) to determine whether to continue the retry operation. The counter is automatically reset to 0 when each new data page begins to be written, ensuring that each page of data has an independent retry opportunity. The retry counter mechanism effectively distinguishes between temporary errors caused by transient signal interference and persistent errors caused by hardware failures, improving the system's fault tolerance and data reliability.

[0043] Pointer Offset: This refers to the byte offset of the current processing position in the data buffer relative to the starting address. In this SPD programming scheme, the embedded controller maintains a data pointer to track the amount of data that has been written. The pointer offset represents the cumulative number of bytes from the buffer's starting address 0x00 to the current processing position. After each page of 16 bytes of data is successfully written, the pointer offset automatically increments by 16. By comparing it with the total data length register in real time, the system can accurately determine the entire programming progress. When the pointer offset equals the total data length, it indicates that all data has been written.

[0044] Furthermore, the SPD chip is connected to the embedded controller via the I2C interface. The SCL and SDA pins of the SPD chip are directly connected to the corresponding I2C interface pins of the embedded controller. The A0, A1, and A2 pins of the SPD chip are configured to high or low levels to set the I2C device address, thereby enabling addressing of different SPD chips.

[0045] The SCL and SDA pins (Serial Clock Line and Serial Data Line Pins) refer to the physical connection pins corresponding to the two core signal lines in the I2C bus protocol. The SCL (Serial Clock Line) pin is used to transmit a synchronous clock signal, controlled by the master device (embedded controller), providing a timing reference for data transmission. The SDA (Serial Data Line) pin is used for bidirectional data transmission, completing the transmission and reception of address, data, and control information under the control of the clock signal. In this programming scheme, the SCL and SDA pins of the SPD chip are directly connected to the corresponding pins of the embedded controller, forming a standard I2C bus communication link, supporting open-drain output and bus arbitration mechanisms.

[0046] I2C Interface Pins: These are the dedicated hardware interface pins on the embedded controller chip used for I2C communication, including the SCL output pin and the SDA bidirectional pin. These pins typically have built-in pull-up resistors and open-drain output characteristics, conforming to I2C electrical standards. In this SPD programming solution, the embedded controller establishes a direct hardware connection with the SPD chip through these dedicated I2C interface pins, eliminating the need for additional level conversion or signal conditioning circuitry. This simplifies hardware design and ensures reliable signal transmission and accurate timing.

[0047] Pins A0, A1, and A2 (Address Selection Pins): These are three address selection pins on the SPD chip used to configure the I2C device address. In this programming scheme, these three pins are connected to either a high level (VCC) or a low level (GND), and the unique device address of the SPD chip on the I2C bus is set through eight different high-low level combinations (000, 001, 010, 011, 100, 101, 110, 111). This address configuration, combined with the SPD chip's base address, forms a complete 7-bit I2C slave address, enabling the embedded controller to accurately address and access different SPD chips on the same I2C bus, realizing multi-chip parallel operation and selective programming functions.

[0048] Furthermore, a start signal is generated by the SDA line of the I2C bus transitioning from high to low during the SCL high level, ensuring the execution of the I2C communication protocol. The I2C communication protocol refers to the standardized serial bus protocol used in this SPD programming solution for data communication between the embedded controller and the SPD chip. Developed by Philips (now NXP), this protocol employs a two-wire design, requiring only two signal lines—the serial data line (SDA) and the serial clock line (SCL)—to achieve full-duplex communication.

[0049] Specifically, in this application, the embedded controller acts as the master device, controlling the bus timing and communication rhythm. The SPD chip acts as the slave device, responding to the master device's read and write requests, thus implementing a unidirectional control data transmission mechanism. The protocol specifies strict timing requirements, including standardized operation sequences such as a start signal (SDA transitions from high to low when SCL is high), a stop signal (SDA transitions from low to high when SCL is high), and data transmission timing (SDA changes state when SCL is low and remains stable when SCL is high). It supports 7-bit or 10-bit device addressing mechanisms. In this scheme, multi-device addressing is achieved through the configuration of the SPD chip's A0, A1, and A2 pins, allowing multiple SPD chips to be connected on the same bus and selectively accessed. After every 8 bits of data transmitted, a 1-bit acknowledgment bit (ACK / NACK) is inserted. The slave device confirms successful data reception by pulling the SDA line low to generate an ACK signal. The master device uses this signal to determine the communication status and decide on subsequent operations. This protocol provides a standardized SPD chip access method for embedded controllers, supports efficient data transmission in page write mode, ensures the reliability of data burning through error detection and retransmission mechanisms at the protocol level, and ensures the compatibility and scalability of the solution through its openness and standardization.

[0050] Another aspect of this application provides an SPD programming system based on serial port commands and an embedded controller, comprising: a serial communication module for establishing a serial port connection between a master and slave device and configuring baud rate, data bits, stop bits, and parity parameters; an embedded controller for monitoring the serial port data buffer via timed polling, extracting command data packets upon detecting a data arrival event, and comparing and verifying them with a pre-stored command feature library; a data processing module for receiving SPD data packets input by the user through the serial port, performing data format parsing and multiple verification processing, the multiple verification processing including regular expression format verification and CRC cyclic redundancy check; and an I2C bus interface module for transmitting the verified SPD data... The system writes data to the target chip page by page, using a paginated write mode, writing 16 bytes of data per page and controlling the data transmission sequence. A readback verification module performs data readback verification after each page write operation, comparing the readback data bit-by-bit with the original written data. An error handling module executes a retry mechanism and error recovery process when readback verification fails. The error recovery process includes re-initiating the readback operation, sending a page erase command, and resetting the verification state machine. An SPD chip connects to the embedded controller via an I2C interface. The SCL and SDA pins of the SPD chip are directly connected to the corresponding I2C interface pins of the embedded controller. Pins A0, A1, and A2 are configured to set the I2C device address.

[0051] Compared to existing technologies, the advantages of this application are:

[0052] (1) The SPD chip and the embedded controller are directly connected using the standard I2C bus protocol. By directly connecting the SCL and SDA pins of the SPD chip to the corresponding I2C interface pins of the embedded controller, the need for complex level conversion circuits, signal conditioning modules, and dedicated programmers in traditional solutions is eliminated. Based on the open-drain output characteristics and built-in pull-up resistor mechanism of the I2C protocol, this design ensures that the electrical characteristics of signal transmission meet the specifications, reduces hardware implementation costs by more than 60%, and improves the system integration and reliability.

[0053] (2) Real-time dynamic modification capability of SPD configuration parameters is realized through serial port command control mechanism. Based on the instruction parsing engine of embedded controller and the real-time read and write characteristics of I2C bus, users can send configuration commands through standardized serial port protocol. The embedded controller parses the commands in real time and converts them into corresponding I2C read and write timing, directly operating the register contents of SPD chip. This mechanism does not require any modification to the hardware architecture of the target system. SPD content update can be completed through software-level command interaction, improving configuration modification efficiency by more than 90%, and significantly improving the adaptability and maintenance convenience of the system.

[0054] (3) Establish a triple verification architecture, including serial port frame format verification, page write back read comparison verification and I2C physical layer ACK / NACK status monitoring. Through multi-level verification, ensure end-to-end integrity of data transmission; implement intelligent retransmission mechanism, automatically perform up to 3 retry operations when data error is detected, and dynamically adjust I2C timing parameters to adapt to different electrical environments, significantly improving the reliability of data transmission. Attached Figure Description

[0055] This application will be further described by way of exemplary embodiments, which will be described in detail with reference to the accompanying drawings. These embodiments are not limiting; in these embodiments, the same reference numerals denote the same structures, wherein:

[0056] Figure 1 This is an exemplary flowchart illustrating an SPD programming method based on serial port commands and an embedded controller, according to some embodiments of this application.

[0057] Figure 2 This is an exemplary flowchart of sub-steps for data format parsing and verification processing according to some embodiments of this application. Detailed Implementation

[0058] The methods and systems provided in the embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0059] A method for programming SPDs based on serial port commands and EC (Extended Circuit-Regulator) is presented. This debugging method is suitable for programming computer memory SPDs and has been put into mass production. The overall process of the method is as follows: Figure 1 As shown, it includes the following steps:

[0060] First, the serial port needs to be physically connected from the host to the slave device. Ensure the required serial cable is ready. Plug one end of the cable into the host's serial port and the other end into the slave's serial port, ensuring the transmit and receive ports are connected correctly. Connect the host's transmit port to the slave's receive port, and vice versa, ensuring data transmission and reception are secure. After connection, carefully inspect the serial cable for any bends, damage, or looseness to ensure stable communication.

[0061] Start the communication program for both the master and slave devices, and configure the corresponding serial port parameters, such as baud rate, data bits, stop bits, and parity bits. For example, the baud rate should be 112000, the data bits 8, and the stop bits 1. These parameters must be consistent on both the master and slave devices. Perform a preliminary communication test to confirm the serial port connection and communication are normal. You can send simple commands and observe the slave device's response to ensure that data is transmitted correctly.

[0062] When the slave device inputs the SPD programming command via serial port, the embedded controller (EC) employs a multi-level command verification mechanism to ensure command validity. Specifically, the EC monitors the serial port data buffer through periodic polling. Upon detecting a data arrival event, it immediately extracts the latest received command data packet. This command data packet is then sent to the command parsing engine for line-by-line comparison and verification against the command feature library pre-stored in the EC's non-volatile memory. If the command perfectly matches the SPD programming function command features, the EC immediately initiates the SPD programming process (see step 4 for details). If the match fails, an error log is recorded, and an invalid command response is returned via the serial port. The EC then continues to poll and monitor the serial port data buffer for command detection.

[0063] If the instruction matches the characteristics of the SPD programming function instruction perfectly, the SPD programming process begins. The user programs the SPD chip data via serial port in a specific format, and the embedded controller (EC) executes an intelligent data processing and verification process. Specifically, after receiving the SPD data packet from the user, the EC first parses the data format and extracts the valid data fields; then, it initiates a multi-factor verification mechanism, including data length verification, regular expression matching, and CRC cyclic redundancy check. Figure 2 As shown.

[0064] Specifically, this step includes the following sub-steps:

[0065] When inputting SPD byte data in a standardized format via serial port, each line of data input by the user adopts a fixed format of "register offset address + data value", where the register offset address is a 1-byte hexadecimal number and the data value is a 1-byte hexadecimal number, separated by a preset separator (such as a space or comma).

[0066] Upon receiving data, the EC first performs a format compliance check, verifying that each line of data contains complete and valid address-value pairs. Specifically, the EC uses a pre-defined regular expression pattern ^([0-9A-Fa-f]{1,2})[ / s,]+([0-9A-Fa-f]{1,2}), which matches standard format SPD data lines. The first capture group extracts the register offset address, and the second capture group extracts the corresponding data value. When receiving user-input SPD data, the EC applies the regular expression line by line for pattern matching. Upon successful matching, the hexadecimal string is automatically converted to a hexadecimal value and stored in a data buffer sorted by address. For any data lines that fail to match, the EC immediately generates an error report and sends it back via serial port.

[0067] Once a single row of data is successfully extracted, the pointer automatically increments to point to the next row of data for further processing. If a data end marker is detected or the preset number of rows is reached, the data extraction is considered complete, and the CRC check process is initiated. If the extraction is not complete, the pointer remains at its current position to continue processing subsequent rows of data.

[0068] After the data is extracted, the CRC check process begins. Specifically, the EC performs the following check process: First, it initializes the 16-bit CRC check value to 0x0000. Then, it reads the data to be checked byte by byte, shifts each byte left by 8 bits, and performs an XOR operation with the current CRC value. Next, it performs 8 bitwise operations on the XOR result, shifting left by 1 bit each time and checking the status of the highest bit. If the highest bit is 1, it performs an XOR operation with the preset polynomial 0x1021; otherwise, it only performs a shift operation. After processing each byte, it retains the lower 16 bits of the CRC value. The above process is repeated until all data is processed, and finally, a 16-bit CRC check result is obtained.

[0069] If the obtained CRC check result is consistent with the result in the corresponding CRC register in the SPD, then the CRC check passes.

[0070] After the CRC check passes, the EC writes the parsed SPD data to the target chip page by page through the IC bus interface, using a page-based writing mode, writing 16 bytes of data per page, and immediately performing a readback check after each page write operation.

[0071] Specifically, this step includes the following sub-steps:

[0072] The EC reads 16 bits of data starting from the beginning address of the buffer register. After selecting the target I2C physical channel through the data selector, the master controller generates a start signal (START). Specifically, the SDA line of the I2C bus first transitions from high to low during the SCL high level to generate the start signal. Then, a 7-bit slave address byte is sent, where the most significant bit (MSB) is fixed at 0 to indicate write operation mode. This address byte is immediately followed by an ACK bit.

[0073] When the EC detects a valid acknowledgment (ACK) signal from the slave device, it immediately initiates a data transmission sequence, transmitting 16 bits of data in the buffer register sequentially in MSBfirst order. After each data byte is transmitted, an acknowledgment detection window of one clock cycle is automatically inserted. If no valid acknowledgment signal is detected within the preset timeout period, the EC automatically triggers a retransmission mechanism, which includes: regenerating the start signal, retransmitting the slave address byte (keeping the least significant bit at 0 to indicate a write operation), and reinitializing the data transmission process.

[0074] After completing the write operation of the 16-bit data page, the EC immediately initiates the data readback verification process. It reads the 16-bit data that was just written from the SPD chip by re-initiating the I2C read operation. The EC's internal data verification engine compares the readback data with the original written data bit by bit. If all bits match successfully, it automatically increments the data pointer by 16 bits to prepare for processing the next data page.

[0075] When a failure is detected in comparing the readback data with the original write data, EC first queries the current retry counter status. If the number of retries does not exceed the preset threshold (3 times), the readback operation is immediately re-initiated for secondary verification. This mechanism can effectively eliminate misjudgments caused by instantaneous signal interference.

[0076] If three consecutive verifications fail, it is determined to be a substantial data error. The EC will automatically execute the error recovery process: first, send a page erase command to the SPD chip, then retransmit the 16 bits of data of that page, and reset the verification state machine.

[0077] The EC continuously monitors the data pointer offset of the buffer register and compares it with the preset total data length register in real time to determine the current write progress. When the data pointer offset is detected to be less than the total data length, the EC automatically keeps the I2C bus active and continues to read the next data block from the buffer register to perform the write operation. When the pointer offset reaches the total data length, the EC executes a termination sequence: first, it sends an I2C stop signal (STOPcondition), then releases bus control, and updates the completion flag bit of the status register.

[0078] The foregoing illustrative description of the present application and its embodiments is not restrictive and can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. The accompanying drawings are only one embodiment of the present application, and the actual structure is not limited thereto. Therefore, if those skilled in the art are inspired by this description and design similar structures and embodiments without departing from the spirit of the present application, such designs should fall within the scope of protection of this application. Furthermore, the word "comprising" does not exclude other elements or steps, and the word "a" preceding an element does not exclude the inclusion of "a plurality" of that element. Terms such as "first," "second," etc., are used to indicate names and do not indicate any specific order.

Claims

1. A method for programming an SPD based on serial port commands and an embedded controller, characterized in that, include: Connect the serial cable between the host and the slave device, and configure the serial port parameters, including baud rate, data bits, stop bits, and parity bits. An embedded controller is used to monitor the serial port data buffer through timed polling. When data arrives, the instruction data packet is extracted and compared with a pre-stored instruction feature library for verification. Once the command verification is successful, the SPD data packet input by the user through the serial port is received, and the data format is parsed and verified. After the SPD data passes the verification, it is written to the target chip page by page using the I2C bus. The page writing mode is adopted and a readback verification is performed after each page writing operation. Data format parsing, including: Receive standardized input data, wherein the standardized input data adopts the format of register offset address + data value, wherein both the register offset address and the data value are hexadecimal numbers and are separated by a preset delimiter; The standardized input data is parsed using a preset regular expression pattern, the register offset address and corresponding data value are extracted, and the hexadecimal string is converted into a hexadecimal value and stored in a data buffer sorted by address. Once a single row of data is extracted, the incrementing pointer moves to the next row of data. When the end of data is detected or the preset number of rows is reached, the data extraction is considered complete, and the subsequent verification process is started. Verification processing includes: Initialize a 16-bit CRC checksum and read the SPD data to be checked byte by byte; Perform a left shift XOR operation on each data byte, shifting the byte data left by N bits and then XORing it with the current CRC value; Perform multiple shift operations on the XOR result, shifting left by 1 bit each time and checking the state of the most significant bit. If the most significant bit is 1, perform XOR with the preset polynomial; otherwise, only perform the left shift operation. After processing each byte, the lowest 16 bits of the result are truncated as the updated CRC value. This process is repeated until all data verification calculations are completed. The final CRC check result is compared with the CRC baseline value pre-stored in the SPD to verify data integrity. The verified SPD data is written to the target chip page by page via the I2C bus, including: Read 16 bytes of data to be written from the start address of the data buffer, select the target I2C physical channel through the data selector and generate an I2C start signal; Send a 7-bit slave address byte, where the read / write bit of the address byte is set to 0 to indicate write operation mode, and wait for the slave to return an ACK signal to confirm that the address has been successfully recognized; When a slave device returns an acknowledgment signal, a data transmission sequence is initiated, transmitting 16 bytes of data byte by byte in the order of the most significant bit. After each byte is transmitted, the system waits for the slave device to return an acknowledgment signal before continuing to transmit the next byte. After completing the 16-byte data page write operation, the data readback verification process is started. The written data is read from the SPD chip through I2C read operation and verified bit by bit with the original written data. Initiating the data readback verification process also includes: When the readback verification fails, check the current retry counter status. If the number of retries has not exceeded the preset threshold, re-initiate the readback operation for secondary verification. If the threshold is exceeded, it is determined to be a data error, a page erase command is sent to the SPD chip, the corresponding page data is retransmitted and the verification state machine is reset; The data pointer offset of the buffer register is continuously monitored. The writing progress is determined by comparing it with the total data length register. When the pointer offset reaches the total data length, an I2C stop signal is sent and bus control is released. The default regular expression pattern includes a first capturing group and a second capturing group, where: The first capture group is used to match 1 to 2 hexadecimal character combinations and extract the register offset address; The second capture group is used to match 1 to 2 hexadecimal character combinations and extract the corresponding data values; The regular expression pattern is ^([0-9A-Fa-f]{1,2})[\s,]+([0-9A-Fa-f]{1,2}), where the first and second capturing groups are separated by a whitespace character or a comma separator.

2. The SPD programming method based on serial port commands and embedded controller according to claim 1, characterized in that: When the format parsing of standardized input data using a preset regular expression pattern fails, an error report is generated by the embedded controller and fed back via serial port to ensure the integrity and correctness of the input data.

3. The SPD programming method based on serial port commands and embedded controller according to claim 1, characterized in that: The SPD chip connects to the embedded controller via the I2C interface. The SCL and SDA pins of the SPD chip are directly connected to the corresponding I2C interface pins of the embedded controller. The A0, A1, and A2 pins of the SPD chip are configured to high or low levels to set the I2C device address, thereby enabling addressing of different SPD chips.

4. The SPD programming method based on serial port commands and embedded controller according to claim 3, characterized in that: The execution of the I2C communication protocol is ensured by generating a start signal by switching the SDA line of the I2C bus from high to low during the SCL high level.

5. An SPD programming system based on serial port commands and an embedded controller, used to execute the method described in any one of claims 1 to 4, characterized in that, include: The serial communication module establishes a serial connection between the master and slave devices and configures the baud rate, data bits, stop bits, and parity parameters. The embedded controller monitors the serial port data buffer through periodic polling. When data is detected to reach an event, it extracts the instruction data packet and compares and verifies it with a pre-stored instruction feature library. The data processing module receives SPD data packets input by the user through the serial port, performs data format parsing and multiple verification processing, including regular expression format verification and CRC cyclic redundancy check. The I2C bus interface module writes the verified SPD data to the target chip page by page, using a page-based writing mode, writing 16 bytes of data per page, and controlling the data transmission sequence. The readback verification module performs data readback verification after each page data write operation, comparing the readback data with the original written data bit by bit. The error handling module executes a retry mechanism and an error recovery process when the readback verification fails. The error recovery process includes re-initiating the readback operation, sending a page erase command, and resetting the verification state machine. The SPD chip connects to the embedded controller via the I2C interface. The SCL and SDA pins of the SPD chip are directly connected to the corresponding I2C interface pins of the embedded controller. The A0, A1, and A2 pins are configured to set the I2C device address.

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