A method of quickly testing decoders for a variety of fpga implementations

Abstract

The application discloses a method for quickly testing a plurality of FPGA implementation decoders, comprising: a host computer generates a data packet and sends, receives a decoding result of a lower computer, processes a block error rate and a bit error rate; the lower computer uses a state machine to control the whole test system; a read-write control block controls writing of to-be-decoded data into two RAMs and reading of a decoding result into a FIFO; a decoding control block controls starting, reading, ending and resetting of the decoder. The method follows the idea that when one RAM is storing data, the decoder reads data in the other RAM, and compared with a test structure following the idea of series connection of generating data, sending, decoding and receiving processing, the running time can be shortened.

Description

Technical Field

[0001] This invention belongs to the field of decoding testing technology, and specifically relates to a method for rapidly testing decoders implemented in various FPGAs. Background Technology

[0002] PCI-Express (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard. PCIe is a high-speed serial point-to-point dual-channel high-bandwidth transmission, where each connected device has its own dedicated channel bandwidth and does not share the bus bandwidth. It primarily supports active power management, error reporting, and end-to-end reliable transmission. Its main advantage is its high data transfer rate. Hardware implementation of decoders, compared to software implementation, can reduce runtime while ensuring reliable decoding results. When testing hardware-implemented decoders, the common approach is a series of steps: host computer generates data, sends it, FPGA receives it, FPGA decodes it, FPGA sends the result, and host computer receives and processes it to obtain the bit error rate and block error rate. This approach wastes a lot of time in non-decoding stages. Therefore, it is necessary to design a faster testing method to reduce decoder latency. Summary of the Invention

[0003] In view of this, the present invention proposes a method for rapidly testing decoders implemented in various FPGAs, with the aim of testing the performance of decoder architectures implemented in FPGAs more quickly.

[0004] Includes the following steps:

[0005] S1. The host computer generates and sends data packets, and receives the decoding results from the slave computer to process and calculate the block error rate and bit error rate.

[0006] S2. The lower-level machine uses a state machine to control the entire test system;

[0007] S3, the read / write control block controls the writing of the data to be decoded into two RAMs and the reading of the decoding result from the FIFO;

[0008] S4, the decoding control block, controls the start, reading, end, and reset of the decoder.

[0009] Furthermore, step S1 specifically includes:

[0010] S11. The composition of each data packet includes: the first part is information, the second part is multiple sets of data to be decoded, and the TEAMNUM value is defined to control the number of data groups in a data packet. Among them, information[2] is 1 to indicate the last data packet.

[0011] S12. The data generation process is as follows: generate the TEAMNUM group of data to be decoded, generate 2 packets of data for the first time, and save the generated data before encoding to OriginalData1 or OriginalData2. The two signals are used alternately.

[0012] S13. After receiving the decoding result from the lower-level machine, the host computer first converts the signal into binary, and then compares it with the corresponding OriginalData1 or OriginalData2 signal to calculate the number of error blocks and the number of error codes.

[0013] Furthermore, step S2 specifically includes:

[0014] S21. The state machine has 5 states: state0 is the ready state, state1 is the receive state, state2 is the decode state, state3 is the transmit state, and state4 is the blank state. It is triggered by the rising edge of CLK or the rising edge of RST, where CLK is the clock signal and RST is the reset signal. The state machine controls the rData signal, infor signal, rCount signal, and rState signal. The rData signal is the receive data signal, the infor signal is the information signal for the received data packet, the rCount signal is the receive or transmit counter signal, and the rState signal is the status signal. When RST is triggered, the rData signal, infor signal, rCount signal, and rState signal are set to 0.

[0015] S22. When the state machine is in state0, rCount is set to 0. When CHNL_RX is pulled high, it means that data has been received from the host computer, and rState is set to state1. When decode_stop and decode_done are pulled high, it means that decoding has stopped and preparation has been completed, and one packet of data has been decoded, and rState is set to state3.

[0016] S23. When the state machine is in state1, when CHNL_RX_DATA_VALID goes high, it indicates that the data is valid, rData equals CHNL_RX_DATA, indicating that data has been received, and rCount starts counting; when rCount = 0, infor equals CHNL_RX_DATA, and the information of the data packet is saved; when rCount = rLen, indicating that rCount equals the number of received data, rState is set to state2.

[0017] S24. When the state machine is in state2, rCount is set to 0. When decode_done goes high, it means that a packet of data has been decoded and rState is set to state3.

[0018] S25. When the state machine is in state3, when CHNL_TX_DATA_REN goes high, it indicates that transmission is allowed and rCount starts counting. When rCount equals the set number of transmissions, if decode_stop goes high, it enters a blank state and rState is set to state4, indicating that it stops. Otherwise, rState is set to state0, and it enters a ready state, indicating that it will continue to the next round of decoding.

[0019] When the state of the S26 state machine is state4, it does nothing and waits for a reset signal to trigger a reset to 0.

[0020] Furthermore, step S3 specifically includes:

[0021] The S31 and ramwren signals are the master switch for writing. A high signal indicates that data is being written to both RAMs. This is triggered by the rising edge of CLK or RST. When the reset signal is triggered, ramwren is set to 0. When rCount is 0, ramwren is 0. When the CHNL_RX_DATA_VALID signal is high, the data is valid, and ramwren is set to 1.

[0022] S32, the channelwraddr signal is the write address, triggered by the rising edge of CLK. When rState is in state1 (receive state), if ramwren is 1 and channelwraddr is less than the number of data packets needed to send one packet of data to be decoded minus 1, then channelwraddr is incremented by 1; if channelwraddr is equal to the number of data packets needed to send one packet of data to be decoded minus 1, then channelwraddr is reset to 0; otherwise, channelwraddr remains unchanged; in other cases, channelwraddr is 0.

[0023] S33 and wrflag signals are RAM selectors. When they are 0, they are written to RAM1; otherwise, they are written to RAM2. They are triggered by the rising edge of CLK or the rising edge of RST. The reset signal sets them to 0. Whenever channelwraddr equals the number of data packets to be decoded minus 1, it is inverted; otherwise, it remains unchanged.

[0024] S34, fiford_en is the switch to read data from the FIFO. It is pulled high when both send preparation and rState are in state3.

[0025] Furthermore, step S4 specifically includes:

[0026] S41. The decoder's start is controlled by the rdstart, decode_start, and start signals. When rdstart is 1, it indicates that there is enough data in RAM, and decoding begins. This is triggered by the rising edge of CLK or RST. The specific operation is as follows: The reset signal sets rdstart to 0; when channelwraddr equals the number of data packets needed to send a set of data to be decoded, it is in the first receiving state of receiving two data packets, and rdstart is set to 1; when decode_done is 1, one data packet has been decoded, decode_stop is 0, indicating that decoding can continue, and empty is 0. Empty is given by FIFO and represents the read empty flag. When pro_empty is 1, pro_empty is given by FIFO and represents the read empty warning signal. The warning line is set to one more data packet than empty, that is, when one data packet has been decoded and has entered state3, rdstart is set to 1; when decode_start is 1, rdstart is set to 0; otherwise, rdstart retains its original value.

[0027] `decode_start` is a bridging signal. If pulled high, it will remain high until one data packet is decoded. It is triggered by the rising edge of `sys_clk` or the rising edge of `RST`, where `sys_clk` represents the clock used by the decoder. Its operation is as follows: the reset signal sets `decode_start` to 0; when `rdstart` is 1, `decode_start` is set to 1; when `numcnt` equals `TEAMNUM`, `decode_start` is set to 0, where `numcnt` represents the number of decoded packets; otherwise, `decode_start` remains unchanged.

[0028] `start` is the decoder switch. When it is 1, it indicates that decoding has started. It is triggered by the rising edge of `sys_clk` or the falling edge of `sys_rst`. The reset signal sets `start` to 0. When `decode_start` is 1, `start` is set to 1. When the decoding result is output, `start` is set to 0. Otherwise, it remains unchanged. `sys_rst` represents the reset signal used by the decoder.

[0029] S42. Decoder reading is controlled by start and rdflag. When start is 1 and rdflag is 1, it reads from RAM1. When start is 1 and rdflag is 0, it reads from RAM2. rdflag uses combinational logic circuits, triggered by the rising edge of RST and the rising edge of decode_done. RST sets rdflag to 0, and decode_done inverts rdflag.

[0030] S43. The decoder has two end signals: decoding_done and decode_done, as well as the total end flag decode_stop.

[0031] `decodeing_done` indicates that a set of data has been decoded. The operation is as follows: `decodeing_done` and `numcnt` are triggered by the rising edge of `sys_clk` or the rising edge of `RST`. The reset signal sets `decodeing_done` and `numcnt` to 0. When `numcnt` equals `TEAMNUM`, both `decodeing_done` and `numcnt` are set to 0. When the decoder's decoding output is enabled and the number of outputs equals the value of a set of decoding results, `decodeing_done` is set to 1, and `numcnt` is incremented by 1, indicating that a set of data has been decoded. In other cases, `decodeing_done` is set to 0, and `numcnt` remains unchanged.

[0032] `decode_done` indicates that a data packet has been decoded. It is triggered by the rising edge of `sys_clk` or the rising edge of `RST`, and the reset signal sets `decode_done` to 0. When `numcnt` equals `TEAMNUM`, `decode_done` is set to 1. When `rdstart` is 1, `decode_done` is set to 0. Otherwise, it remains unchanged.

[0033] decode_stop indicates that decoding preparation has stopped. It is triggered by the rising edge of CLK or the rising edge of RST. The reset signal sets decode_stop to 0. When information[2] is equal to 1, rState is equal to state0 and decode_done is 1, decode_stop is set to 1. In other cases, it remains unchanged.

[0034] S44. The reset signal sys_rst used by the decoder is triggered by the rising edge of sys_clk or the rising edge of RST, and the operation is as follows: the reset signal sets sys_rst to 0; when decoding_done is 1, sys_rst is set to 0; otherwise, sys_rst is set to 1.

[0035] The beneficial effects of the technical solution provided by this invention are:

[0036] This method follows the idea that while one RAM is storing data, the decoder reads data from another RAM. Compared to test structures that follow the cascaded approach of generating, transmitting, decoding, and receiving data, this method can shorten runtime and test the performance of FPGA-implemented decoder structures more quickly. Attached Figure Description

[0037] Figure 1This is a flowchart of a method for rapidly testing decoders implemented in various FPGAs according to the present invention;

[0038] Figure 2 This is a flowchart illustrating the process of a host computer generating a data packet according to an embodiment of the present invention.

[0039] Figure 3 This is a schematic diagram of the data structure generated by the host computer in an embodiment of the present invention;

[0040] Figure 4 This is a flowchart of the host computer's workflow according to an embodiment of the present invention;

[0041] Figure 5 This is a state machine transition diagram according to an embodiment of the present invention;

[0042] Figure 6 This is a simulation waveform diagram of the read / write control module in an embodiment of the present invention; wherein... Figure 6 (a) is a waveform diagram of the ramwren signal operation content in an embodiment of the present invention. Figure 6 (b) is a waveform diagram of the operation content of the channelwraddr signal and wrflag signal in an embodiment of the present invention. Figure 6 (c) is a waveform diagram of the fiford_en signal operation content in an embodiment of the present invention;

[0043] Figure 7 This is a simulation waveform diagram of the decoding control block operation according to an embodiment of the present invention; wherein Figure 7 (a) is a diagram showing the relationship between the three signals rdstart, decode_start, and start in an embodiment of the present invention. Figure 7 (b) is a waveform diagram of the decoder reading controlled by start and rdflag in an embodiment of the present invention. Figure 7 (c1) is a waveform diagram showing the combined effect of the decoding_done and numcnt signals in an embodiment of the present invention. Figure 7 (c2) is a waveform diagram of the decode_done signal in an embodiment of the present invention. Figure 7 (c3) is a waveform diagram of the decode_stop signal in an embodiment of the present invention. Figure 7 (c4) is a waveform diagram of the effect of the sys_rst signal in an embodiment of the present invention;

[0044] Figure 8 This is an interface diagram of the lower-level machine testing section in an embodiment of the present invention;

[0045] Figure 9 This is a diagram showing the running results of an embodiment of the present invention. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0047] refer to Figure 1 , Figure 1 This is a schematic diagram of a method for rapidly testing decoders implemented in various FPGAs according to the present invention.

[0048] This invention provides a method for rapidly testing decoders implemented in various FPGAs, comprising the following steps:

[0049] S1. The host computer generates and sends data packets, and receives the decoding results from the slave computer to process and calculate the block error rate and bit error rate.

[0050] S11. Each data packet consists of: the first part is information, and the second part is multiple sets of data to be decoded. The TEAMNUM value is defined to control the number of data sets in a data packet. Among them, information[2] is 1 to indicate the last data packet. Reference Figure 2 , Figure 2 This is a flowchart illustrating the process of a host computer generating a data packet according to an embodiment of the present invention. The data packet contains TEAMNUM group data. The generated data to be decoded needs to be packaged, resulting in a packet like... Figure 3 Data structures in Figure 3 This is a schematic diagram of the data structure generated by the host computer in an embodiment of the present invention.

[0051] S12. The data generation process is as follows: generate the TEAMNUM group of data to be decoded, generate 2 packets of data initially, and save the generated pre-encoding data to OriginalData1 or OriginalData2. The two signals are used alternately. This operation is for subsequent comparison.

[0052] refer to Figure 4 , Figure 4 This is a flowchart of the host computer operation process according to an embodiment of the present invention.

[0053] The `select` option is used to switch between using `OriginalData_0` and `OriginalData_1`, saving the original data for subsequent comparisons. A value of 0 corresponds to `OriginalData_0`. `select = ~select` performs an inversion operation. This corresponds to the dual-RAM structure in the FPGA. When one RAM is storing data, the decoder reads data from the other RAM, achieving continuous decoding. When data is first written to RAM, the host computer sends two data packets; otherwise, it sends one packet. The total number of data packets sent is `simulation + 3`, which is equivalent to (simulation + 3) * `TEAMUNM` groups of data.

[0054] Specifically, `select` is initialized to 0, and `i` is a loop counter, also initialized to 0. First, a data packet is generated and stored in `OrignalData_0`. Then, another data packet is generated and stored in `OrignalData_1`. These two data packets are sent to the lower-level machine. Next, data sent from the lower-level machine is received, converted to binary, and compared with `OrignalData_select`. When `select` is 0, it is compared with `OrignalData_0`; when `select` is 1, it is compared with `OrignalData_1`. Error blocks and error codes are counted. Then, the loop process begins, including generating a data packet and storing it in `OrignalData_select`, sending the generated data, inverting `select`, receiving data, and performing the same processing as above. After looping through `simulation` times, the loop stops. Then, a data packet is generated and stored, sent, `select` is inverted, two data packets are received, one data packet is processed, `select` is inverted, another data packet is processed, and the block error rate and bit error rate are calculated.

[0055] S13. After receiving the decoding result from the lower-level machine, the host computer first converts the signal into binary, and then compares it with the corresponding OriginalData (OriginalData1 or OriginalData2) signal to calculate the number of error blocks and the number of error codes.

[0056] S2. The lower-level machine uses a state machine to control the entire test system. (Refer to...) Figure 5 , Figure 5 This is a state machine transition diagram according to an embodiment of the present invention.

[0057] S21. The state machine has 5 states: state0 (ready), state1 (receive), state2 (decode), state3 (transmit), and state4 (blank), triggered by the rising edge of CLK (clock signal) or the rising edge of RST (reset signal). The state machine controls the rData signal (receive data), the infor signal (received data packet information), the rCount signal (receive / transmit counter), and the rState signal (state). When the reset signal is triggered, all four signals are set to 0.

[0058] S22. When the state machine is in state0, rCount is set to 0; when CHNL_RX is high (indicating that data has been received from the host computer), rState is set to state1; when decode_stop (decoding stop preparation) and decode_done are high (decoding a packet of data is complete), it indicates the state when decoding the last packet of data, and rState is set to state3.

[0059] S23. When the state machine is in state1, when CHNL_RX_DATA_VALID goes high (indicating that the data is valid), rData equals CHNL_RX_DATA (data), and rCount starts counting; when rCount = 0, infor equals CHNL_RX_DATA, and the information of the data packet is saved; when rCount = rLen (number of received data), rState is set to state2.

[0060] S24. When the state machine is in state2, rCount is set to 0. When decode_done goes high, it means that a packet of data has been decoded and rState is set to state3.

[0061] S25. When the state machine is in state3, when CHNL_TX_DATA_REN goes high (transmission enabled), rCount starts counting. When rCount equals the set number of transmissions, if decode_stop goes high, rState is set to state4, entering a blank state, indicating a stop. Otherwise, rState is set to state0, entering a ready state, indicating the continuation of the next round of decoding.

[0062] S26. When the state machine is in state4, no operation is performed, and it waits for the reset signal to trigger and set it to 0.

[0063] S3, the read / write control block controls the writing of the data to be decoded into two RAMs and the reading of the decoding result from the FIFO. The three signals ramwren, channelwraddr, and wrflag control the writing of data into the two RAMs, where ramwren is the write enable, channelwraddr is the write address, and wrflag is the write select.

[0064] refer to Figure 6 , Figure 6 This is a simulation waveform diagram of the read / write control module in an embodiment of the present invention.

[0065] The S31 and ramwren signals are the master switch for writing; pulling them high indicates that data can be written to both RAMs. They are triggered by the rising edge of CLK or RST. For details on the ramwren signal operation, please refer to [link / reference needed]. Figure 6 (a), specifically:

[0066] 1. The reset signal triggers the setting to 0.

[0067] 2. When rCount is 0, ramwren is 0 because the first data in the received data packet needs to be saved infor and is not written to RAM.

[0068] 3. When the CHNL_RX_DATA_VALID signal goes high, ramwren is set to 1.

[0069] The S32 and channelwraddr signals are write addresses, triggered by the rising edge of CLK. The signal operation details are as follows: Figure 6 As shown in (b), the control content is as follows:

[0070] 1. When rState is in state1 (receive state), if ramwren is 1 and channelwraddr is less than BACK-1 (BACK is the number of data packets required to send one packet of data to be decoded), then channelwraddr is incremented by 1; if channelwraddr is equal to BACK-1, then channelwraddr is reset to 0; otherwise, channelwraddr remains unchanged.

[0071] 2. In other cases, channelwraddr is 0.

[0072] The S33 and wrflag signals are RAM write selectors; a value of 0 writes to RAM1, otherwise it writes to RAM2. This is triggered by the rising edge of CLK or RST. The reset signal sets them to 0. They are inverted whenever channelwraddr equals BACK-1, otherwise they remain unchanged. The operation is as follows: Figure 6 As shown in (b).

[0073] S34, fiford_en, is the switch for reading data from the FIFO. It goes high when both CHNL_TX_DATA_REN (transmit ready) and CHNL_TX_DATA_VAILD (high when rState is state3, transmit state) are active. The waveform is as follows. Figure 6 As shown in (c).

[0074] S4, the decoding control block, controls the start, reading, end, and reset of the decoder.

[0075] S41. The decoder's start is controlled by the rdstart, decode_start, and start signals, and their relationship is as follows: Figure 7 As shown in (a), the operation steps are as follows:

[0076] 1. When rdstart is 1, it indicates that there is enough data in RAM and decoding can begin. This is triggered by the rising edge of CLK or the rising edge of RST. The specific operation is as follows:

[0077] (1) The reset signal sets it to 0;

[0078] (2) When channelwraddr equals the number of data packets to be received before sending a set of data to be decoded, and at this time it is in the first receiving state of receiving two data packets, rdstart is set to 1. This operation means that when the data is written to RAM for the first time, the host computer sends two data packets, otherwise it sends one data packet.

[0079] (3) When decode_done is 1, decode_stop is 0, empty (given by fifo, read empty flag) is 0, and pro_empty (given by fifo, read empty warning signal, the warning line can be customized, here it is set to have 1 more data than empty) is 1, that is, when a packet of data is decoded, it is not the last packet of data and has entered state3 to send dynamics, rdstart is set to 1. This operation ensures the safe transmission of the decoding result and prevents the situation where the decoder completes a round of decoding work before state2 and there is no data in RAM to continue reading;

[0080] (4) When decode_start is 1, rdstart is set to 0;

[0081] (5) In other cases, rdstart remains unchanged.

[0082] 2. `decode_start` is a bridging signal. If pulled high, it will remain high until one data packet is decoded. It is triggered by the rising edge of `sys_clk` (the clock used by the decoder) or the rising edge of `RST`. Its operation is as follows:

[0083] (1) The reset signal sets it to 0;

[0084] (2) When rdstart is 1, decode_start is set to 1;

[0085] (3) When numcnt (used to count the number of decoding completion groups, a packet of data contains TEAMNUM groups) equals TEAMNUM, decode_start is set to 0;

[0086] (4) In other cases, decode_start remains unchanged.

[0087] 3. `start` is the decoder switch. A value of 1 indicates the start of the decoder operation, triggered by the rising edge of `sys_clk` (the clock used by the decoder) or the falling edge of `sys_rst`. The reset signal sets it to 0. When `decode_start` is 1, `start` is set to 1. After the decoding result is output, if it is valid and the number of outputs is a set of decoded results, `start` is set to 0. The enable signal corresponds to... Figure 8 When out_en is 1, the number of outputs corresponds to... Figure 8The value of out_addr ， Figure 8 This is the interface diagram of the lower-level machine testing section in an embodiment of the present invention; other aspects remain unchanged.

[0088] S42. Decoder reads are controlled by start and rdflag. When start is 1 and rdflag is 1, it reads from RAM1 (RAM1_rden is pulled high); when it is 0, it reads from RAM2 (RAM2_rden is pulled high). The waveform is as follows: Figure 7 As shown in (b), rdflag uses combinational logic circuitry, triggered by the rising edge of RST and the rising edge of decode_done. RST sets it to 0, and decode_done inverts it.

[0089] S43. The decoder has two end signals: decoding_done (decoding a set of data is complete) and decode_done, as well as the overall end flag decode_stop. The operation details are as follows:

[0090] 1. The decoding_done and numcnt signals are triggered by the rising edge of sys_clk or the rising edge of RST. The reset signal sets both decoding_done and numcnt signals to 0. When numcnt equals TEAMNUM, both are set to 0. When the decoder provides a decoding result output enable and the number of outputs is the quantity of a set of decoding results, the enable corresponds to... Figure 8 When out_en is 1, the number of outputs corresponds to... Figure 8 The value of `out_addr` is such that `decoding_done` is set to 1 and `numcnt` is incremented by 1, indicating that one group has been decoded; otherwise, `decoding_done` is set to 0 and `numcnt` remains unchanged, as shown in the waveform. Figure 7 As shown in (c1).

[0091] 2. `decode_done` indicates that a data packet has been decoded. It is triggered by the rising edge of `sys_clk` or the rising edge of `RST`, and the reset signal sets it to 0. When `numcnt` equals `TEAMNUM`, `decode_done` is set to 1; when `rdstart` is 1, `decode_done` is set to 0; otherwise, it remains unchanged, as shown in the waveform. Figure 7 As shown in (c2).

[0092] 3. decode_stop indicates decoding stop preparation, triggered by the rising edge of CLK or RST, and set to 0 by the reset signal; when information[2] equals 1 and rState equals state0 and decode_done is 1, decode_stop is set to 1; otherwise, it remains unchanged, and the waveform is as follows. Figure 7 As shown in (c3).

[0093] S44. The reset signal sys_rst used by the decoder is triggered by the rising edge of sys_clk or the rising edge of RST, and its operation is as follows:

[0094] The reset signal sets it to 0; when decoding_done is 1, sys_rst is set to 0; otherwise, sys_rst is set to 1, and the waveform is as follows. Figure 7 As shown in (c4).

[0095] Figure 8 The lower-level machine test interface provided for this design can be used by connecting the decoder interface to it. The input signals to the decoder of the test module in this design are: sys_clk clock signal, sys_rst reset signal, start signal, and rd_data data to be decoded read from RAM; the output signals from the decoder to the test module are: out_data decoding result, out_en decoding output enable, out_addr output result count, and rd_addr address of the signal read from RAM.

[0096] like Figure 9 As shown, a data packet contains 100 data sets. The host computer generates 3 data packets, i.e., processes 300 data sets. The time intervals are as follows: generating the first data packet 7.421703ms, generating the second data packet 7.530258ms, sending data 0.205228ms, decoding and receiving the decoding result of the first packet 3.863693ms, processing data 0.002970ms, generating the last data packet 7.451407ms, decoding and receiving the decoding result of the second packet 0.074260ms, and so on. The third packet decoding result was received in 3.902848ms, and the processing time for two packets was 0.003240ms and 0.002970ms respectively, for a total time of 30.596029ms. Under the cascaded approach, the second packet decoding result should have been received in approximately 3.8ms, while this design received the second packet decoding result in 0.074260ms. This shows that this design saves most of the decoder's waiting time. As the number of data packets increases, this design's method for quickly testing decoders implemented with various FPGAs can save even more time.

[0097] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for rapidly testing decoders implemented in various FPGAs, characterized in that, Includes the following steps: S1. The host computer generates and sends data packets, and receives the decoding results from the slave computer to process and calculate the block error rate and bit error rate. S2. The lower-level machine uses a state machine to control the entire test system; S3, the read / write control block controls the writing of the data to be decoded into two RAMs and the reading of the decoding result from the FIFO; S4, the decoding control block controls the start, reading, end, and reset of the decoder; Step S4 is as follows: S41. The decoder starts using the rdstart, decode_start, and start signals. When rdstart is 1, it indicates that there is enough data in RAM, and decoding begins. This is triggered by the rising edge of CLK or the rising edge of RST, where CLK is the clock signal and RST is the reset signal. The specific operation is as follows: the reset signal sets rdstart to 0; when channelwraddr equals the number of data packets to be received before sending a set of data to be decoded, the decoder is in the first receiving state of receiving two data packets, and rdstart is set to 1, where the channelwraddr signal is the write address. When decode_done is 1, one packet of data has been decoded. decode_stop is 0, indicating that decoding can continue. empty is 0, which is given by FIFO and represents the read empty flag. When pro_empty is 1, pro_empty is given by FIFO and represents the read empty warning signal. The warning line is set to one more set of data than empty. That is, when one packet of data has been decoded and has entered state3 for dynamic output, rdstart is set to 1. When decode_start is 1, rdstart is set to 0; otherwise, rdstart retains its original value. `decode_start` is a bridging signal. If pulled high, it will remain high until one data packet is decoded. It is triggered by the rising edge of `sys_clk` or the rising edge of `RST`, where `sys_clk` represents the clock used by the decoder. Its operation is as follows: the reset signal sets `decode_start` to 0; when `rdstart` is 1, `decode_start` is set to 1; when `numcnt` equals `TEAMNUM`, `decode_start` is set to 0, where `numcnt` represents the number of decoded packets; otherwise, `decode_start` remains unchanged. The `TEAMNUM` value controls the number of data packets in one data packet. `start` is the decoder switch. When it is 1, it indicates that decoding has started. It is triggered by the rising edge of `sys_clk` or the falling edge of `sys_rst`. The reset signal sets `start` to 0. When `decode_start` is 1, `start` is set to 1. When the decoding result is output, `start` is set to 0. Otherwise, it remains unchanged. `sys_rst` represents the reset signal used by the decoder. S42. Decoder reading is controlled by start and rdflag. When start is 1 and rdflag is 1, it reads from RAM1. When start is 1 and rdflag is 0, it reads from RAM2. rdflag uses combinational logic circuits, triggered by the rising edge of RST and the rising edge of decode_done. RST sets rdflag to 0, and decode_done inverts rdflag. S43. The decoder has two end signals: decoding_done and decode_done, as well as the total end flag decode_stop. `decodeing_done` indicates that a set of data has been decoded. The operation is as follows: `decodeing_done` and `numcnt` are triggered by the rising edge of `sys_clk` or the rising edge of `RST`. The reset signal sets `decodeing_done` and `numcnt` to 0. When `numcnt` equals `TEAMNUM`, both `decodeing_done` and `numcnt` are set to 0. When the decoder's decoding output is enabled and the number of outputs equals the value of a set of decoding results, `decodeing_done` is set to 1, and `numcnt` is incremented by 1, indicating that a set of data has been decoded. In other cases, `decodeing_done` is set to 0, and `numcnt` remains unchanged. `decode_done` indicates that a data packet has been decoded. It is triggered by the rising edge of `sys_clk` or the rising edge of `RST`, and the reset signal sets `decode_done` to 0. When `numcnt` equals `TEAMNUM`, `decode_done` is set to 1. When `rdstart` is 1, `decode_done` is set to 0. Otherwise, it remains unchanged. decode_stop indicates that decoding preparation has stopped. It is triggered by the rising edge of CLK or the rising edge of RST. The reset signal sets decode_stop to 0. When information[2] is equal to 1, rState is equal to state0 and decode_done is 1, decode_stop is set to 1. In other cases, it remains unchanged. S44. The reset signal sys_rst used by the decoder is triggered by the rising edge of sys_clk or the rising edge of RST, and the operation is as follows: the reset signal sets sys_rst to 0; when decoding_done is 1, sys_rst is set to 0; otherwise, sys_rst is set to 1.

2. The method for rapidly testing decoders implemented in various FPGAs according to claim 1, characterized in that, Step S1 is as follows: S11. The composition of each data packet includes: the first part is information, the second part is multiple sets of data to be decoded, and the TEAMNUM value is defined to control the number of data groups in a data packet. Among them, information[2] is 1 to indicate the last data packet. S12. The data generation process is as follows: generate the TEAMNUM group of data to be decoded, generate 2 packets of data for the first time, and save the generated data before encoding to OriginalData1 or OriginalData2. The two signals are used alternately. S13. After receiving the decoding result from the lower-level machine, the host computer first converts the signal into binary, and then compares it with the corresponding OriginalData1 or OriginalData2 signal to calculate the number of error blocks and the number of error codes.

3. The method for rapidly testing decoders implemented in various FPGAs according to claim 2, characterized in that, Step S2 is as follows: S21. The state machine has 5 states: state0 is the ready state, state1 is the receive state, state2 is the decode state, state3 is the transmit state, and state4 is the blank state. It is triggered by the rising edge of CLK or the rising edge of RST, where CLK is the clock signal and RST is the reset signal. The state machine controls the rData signal, infor signal, rCount signal, and rState signal. The rData signal is the receive data signal, the infor signal is the information signal for the received data packet, the rCount signal is the receive or transmit counter signal, and the rState signal is the status signal. When RST is triggered, the rData signal, infor signal, rCount signal, and rState signal are set to 0. S22. When the state machine is in state0, rCount is set to 0. When CHNL_RX is pulled high, it means that data has been received from the host computer, and rState is set to state1. When decode_stop and decode_done are pulled high, it means that decoding has stopped and preparation has been completed, and one packet of data has been decoded, and rState is set to state3. S23. When the state machine is in state1, if CHNL_RX_DATA_VALID goes high, it means the data is valid, rData equals CHNL_RX_DATA, indicating that data has been received, and rCount starts counting; when rCount=0, infor equals CHNL_RX_DATA, and the information of the data packet is saved; when rCount=rLen, indicating that rCount equals the number of received data, rState is set to state2. S24. When the state machine is in state2, rCount is set to 0. When decode_done goes high, it means that a packet of data has been decoded and rState is set to state3. S25. When the state machine is in state3, when CHNL_TX_DATA_REN goes high, it indicates that transmission is allowed and rCount starts counting. When rCount equals the set number of transmissions, if decode_stop goes high, it enters a blank state and rState is set to state4, indicating that it stops. Otherwise, rState is set to state0, and it enters a ready state, indicating that it will continue to the next round of decoding. When the state of the S26 state machine is state4, it does nothing and waits for a reset signal to trigger a reset to 0.

4. The method for rapidly testing decoders implemented in various FPGAs according to claim 3, characterized in that, Step S3 is as follows: The S31 and ramwren signals are the master switch for writing. A high signal indicates that data is being written to both RAMs. This is triggered by the rising edge of CLK or RST. When the reset signal is triggered, ramwren is set to 0. When rCount is 0, ramwren is 0. When the CHNL_RX_DATA_VALID signal is high, the data is valid, and ramwren is set to 1. S32, the channelwraddr signal is the write address, triggered by the rising edge of CLK. When rState is in state1 (receive state), if ramwren is 1 and channelwraddr is less than the number of data packets needed to send one packet of data to be decoded minus 1, then channelwraddr is incremented by 1; if channelwraddr is equal to the number of data packets needed to send one packet of data to be decoded minus 1, then channelwraddr is reset to 0; otherwise, channelwraddr remains unchanged; in other cases, channelwraddr is 0. S33 and wrflag signals are RAM selectors. When they are 0, they are written to RAM1; otherwise, they are written to RAM2. They are triggered by the rising edge of CLK or the rising edge of RST. The reset signal sets them to 0. Whenever channelwraddr equals the number of data packets to be decoded minus 1, it is inverted; otherwise, it remains unchanged. S34, fiford_en is the switch to read data from the FIFO. It is pulled high when both send preparation and rState are in state3.

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