Parallel compiling method and system based on FPGA (Field Programmable Gate Array) and medium

Abstract

The invention discloses an FPGA (Field Programmable Gate Array)-based parallel compiling method and system and a medium, mainly relates to the technical field of parallel compiling, and is used for solving the problems that the utilization rate of a DSP (Digital Signal Processor) in an existing scheme is reduced, and an existing high-level comprehensive tool lacks automatic vectorization capability and cannot bind operation to a single DSP. Comprising the steps that a preset high-level language is converted into LLVM IR through the front end of an LLVM compiler; screening out a plurality of binary operation instructions meeting a candidate instruction identification rule from the LLVM IR; combining the binary operation instructions into tuples meeting the digit width of the input port of the DSP in a dynamic grouping rule; based on an instruction optimization rule, packaging the tuple into a final operation instruction for the DSP, and combining operands of the instructions in the tuple into an operand of the final operation instruction; and inserting the final operation instruction into a preset replacement point through a tuple replacement rule, and marking an original instruction tuple of the preset replacement point as a dead code.

Description

Technical Field

[0001] The present application relates to the field of image processing technology, and in particular to a parallel compilation method, system, and medium based on FPGA. Background Art

[0002] With the rapid development of deep learning technology, the demand for high-performance computing and memory bandwidth for deep learning models is rapidly increasing. FPGA (Field Programmable Gate Array) accelerators, as a deeply customizable and energy-efficient hardware acceleration solution, are widely used in the deep learning field. FPGAs rely on their internal DSP (Digital Signal Processing) units to accelerate arithmetic operations. Therefore, improving the utilization efficiency of the FPGA's internal DSP units will significantly increase computing throughput and alleviate memory bandwidth bottlenecks.

[0003] Research has shown that quantization can be used to reduce computational and storage requirements while maintaining acceptable inference accuracy in deep learning inference. However, due to the fixed bit width of the DSP modules within the FPGA, quantized parameters only occupy a portion of the DSP bit width, resulting in reduced DSP utilization. Existing high-level synthesis tools lack automatic vectorization capabilities and cannot bind operations to a single DSP, forcing developers to perform manual optimization. Summary of the Invention

[0004] The present application provides an FPGA-based parallel compilation method, system and medium to solve the problem that the existing solution has reduced DSP utilization and the existing high-level synthesis tools lack automatic vectorization capabilities and cannot bind operations to a single DSP.

[0005] In a first aspect, the present application provides an FPGA-based parallel compilation method, the method comprising: Obtain a preset PASS processing unit for instruction parallel optimization of the FPGA's DSP; wherein the preset PASS processing unit includes at least: candidate instruction identification rules, dynamic grouping rules, instruction optimization rules, and tuple replacement rules; insert the preset PASS processing unit between the LLVM compiler front end and back end; Convert the preset high-level language into LLVM IR through the LLVM compiler front end; filter out several binary operation instructions that meet the candidate instruction identification rules from the LLVM IR; Combining binary operation instructions into tuples that satisfy the input port bit width of the DSP in the dynamic grouping rule; Based on the instruction optimization rules, the tuple is packaged into a final operation instruction for the DSP, and the operands of the instructions in the tuple are combined into the operands of the final operation instruction; Through the tuple replacement rule, the final operation instruction is inserted into the preset replacement point, and the original instruction tuple at the preset replacement point is marked as dead code.

[0006] In one implementation of the present application, several binary operation instructions that meet the candidate instruction identification rules are screened out from the LLVM IR, specifically including: Use FunctionPass or BasicBlockPass to traverse the basic blocks in LLVM IR and extract all binary instructions; Parallel arithmetic instructions are selected from all binary instructions as binary operation instructions.

[0007] In one implementation of the present application, binary operation instructions are grouped into tuples that satisfy the DSP input port bit width in the dynamic grouping rule, specifically including: Process the binary operation instructions one by one in their original order in the basic block, prioritizing placing the current binary operation instruction into the first free DSP slot that meets the bit width requirement. Based on the bit width constraint of the DSP hard core, assign the binary operation instruction to the slot closest to the operand width of the binary operation instruction to form a tuple. When the number of remaining instructions is less than a complete tuple, insert no-ops or copy existing instructions to fill the slot.

[0008] In one implementation of the present application, after marking the original instruction tuple at the preset replacement point as dead code, the method further includes: Invoke the compiler's dead code elimination routine to remove dead code.

[0009] In one implementation of the present application, the final operation instruction is inserted into a preset replacement point through a tuple replacement rule, specifically including: The placeholder instruction is called to replace the original instruction tuple at the preset replacement point with the final operation instruction, and the operands in the original instruction tuple are packaged into the operand format of the placeholder instruction and transmitted to the placeholder instruction.

[0010] In a second aspect, the present application provides an FPGA-based parallel compilation system, the system comprising: An acquisition module is configured to acquire a preset PASS processing unit for instruction parallel optimization of the FPGA's DSP; wherein the preset PASS processing unit includes at least: candidate instruction identification rules, dynamic grouping rules, instruction optimization rules, and tuple replacement rules; and the preset PASS processing unit is inserted between the front-end and back-end of the LLVM compiler; The candidate instruction identification module is used to convert the preset high-level language into LLVM IR through the LLVM compiler front end; and filter out several binary operation instructions that meet the candidate instruction identification rules from the LLVM IR; A dynamic grouping module, used for grouping binary operation instructions into tuples that satisfy the input port bit width of the DSP in the dynamic grouping rule; An instruction optimization module, for packaging the tuple into a final operation instruction for the DSP based on an instruction optimization rule, and combining operands of the instructions in the tuple into operands of the final operation instruction; The tuple replacement module is used to insert the final operation instruction into the preset replacement point through the tuple replacement rule, and mark the original instruction tuple at the preset replacement point as dead code.

[0011] In one implementation of the present application, the candidate instruction recognition module includes a candidate instruction recognition unit, Used to traverse the basic blocks in LLVM IR using FunctionPass or BasicBlockPass and extract all binary instructions; Parallel arithmetic instructions are selected from all binary instructions as binary operation instructions.

[0012] In one implementation of the present application, the dynamic grouping module includes a dynamic grouping unit, It processes binary operation instructions one by one in their original order in the basic block, and prioritizes placing the current binary operation instruction into the first free DSP slot that meets the bit width requirement. Based on the bit width constraint of the DSP hard core, it assigns the binary operation instruction to the slot closest to the operand width of the binary operation instruction to form a tuple. When the number of remaining instructions is less than a complete tuple, insert no-ops or copy existing instructions to fill the slot.

[0013] In one implementation of the present application, the tuple replacement module further includes a removal unit, Used to call the compiler's dead code elimination routine to remove dead code.

[0014] In a third aspect, the present application provides a non-volatile computer storage medium having computer instructions stored thereon, which, when executed, implement an FPGA-based parallel compilation method as described above.

[0015] It can be seen from the above technical solutions that this application has the following advantages: This application directly addresses the core issue of low bit-width utilization in DSP modules within FPGAs by presetting dynamic grouping and tuple replacement rules within the PASS processing unit. Once binary operation instructions are identified within the LLVM IR, this application dynamically combines instruction tuples based on the DSP input port bit width, packaging previously dispersed low-bit operations (such as 8-bit quantization parameters) into compound instructions that conform to the DSP's full bit width (e.g., 32 bits). This hardware-level instruction binding enables a single DSP module to simultaneously process discrete operations that would otherwise require multiple DSP units, directly improving the physical utilization of the DSP compute units. Furthermore, the tuple replacement rules intelligently mark dead code, eliminating the logic resources occupied by redundant instructions in traditional manual optimization and further freeing up the FPGA's programmable logic resources. This mechanism completes hardware adaptation during the compilation phase, eliminating the need for developers to intervene in underlying hardware description language optimization.

[0016] This application achieves fully automatic vectorization conversion from high-level languages ​​to hardware instructions through deep integration of the LLVM compiler architecture. The collaborative work of candidate instruction identification rules and instruction optimization rules enables the compiler to autonomously screen operation modes suitable for parallelization (such as matrix multiplication and addition operations) and reconstruct them into DSP-friendly instruction packages. This automated process completely avoids the defects of existing high-level synthesis tools that rely on manual intervention. Developers do not need to manually write Verilog / VHDL code to achieve instruction-level parallelism. More importantly, the tuple replacement rule, while keeping the original algorithm logic unchanged, ensures that the optimization process does not introduce numerical precision loss through semantic equivalence conversion in the compiler's intermediate representation layer, so that the quantized deep learning model can achieve higher hardware execution efficiency while maintaining reasoning accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solution of the present invention, the following is a brief introduction to the drawings required for the description. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 This is a flow chart of a parallel compilation method based on FPGA provided in an embodiment of the present application.

[0019] Figure 2 This is a schematic diagram of the internal structure of an FPGA-based parallel compilation system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0021] It should be understood by those skilled in the art that the embodiments described below are merely preferred embodiments of the present disclosure and do not imply that the present disclosure can only be implemented through these preferred embodiments. These preferred embodiments are merely intended to explain the technical principles of the present disclosure and are not intended to limit the scope of protection of the present disclosure. Based on the preferred embodiments provided by the present disclosure, all other embodiments obtained by those skilled in the art without creative effort should still fall within the scope of protection of the present disclosure.

[0022] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0023] The present invention proposes a parallel compilation method and system based on FPGA, which realizes superword-level parallel optimization through automation of the compilation process, improves the efficiency of the operation unit, and thus improves the energy efficiency ratio of the accelerator.

[0024] The technical solutions proposed in the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0025] The embodiment provides a parallel compilation method based on FPGA, such as Figure 1 As shown, the method provided in the embodiment of the present application mainly includes the following steps: Step 110: Obtain a preset PASS processing unit for instruction parallel optimization of the DSP of the FPGA; and insert the preset PASS processing unit between the front-end and back-end of the LLVM compiler.

[0026] In some embodiments, wherein the preset PASS processing unit includes at least: candidate instruction identification rules, dynamic grouping rules, instruction optimization rules, and tuple replacement rules; It will be understood by those skilled in the art that the present application adds an optimized PASS processing unit to the existing compiler LLVM, and can subsequently identify a set of instructions that can be calculated in parallel in a single DSP in an FPGA program written in a high-level language, and automatically package this set of instructions into instructions executable by a single DSP through PASS to replace the original set of computational instructions with a higher overhead. In the prior art, the above operation requires developers to manually identify optimization possibilities and perform manual optimization. The purpose of the present invention is to automate the process of discovering and optimizing this parallelism. This automated process can be broken down into multiple sub-processes such as the following candidate instruction identification process, dynamic grouping process, and instruction optimization process.

[0027] Step 120: Convert the preset high-level language into LLVM IR through the LLVM compiler front end; and select a number of binary operation instructions that meet the candidate instruction identification rules from the LLVM IR.

[0028] Among them, several binary operation instructions that meet the candidate instruction identification rules are screened out from LLVM IR, which can be specifically: Use FunctionPass or BasicBlockPass to traverse the basic blocks in LLVM IR and extract all binary instructions; Parallel arithmetic instructions are selected from all binary instructions as binary operation instructions.

[0029] Based on the above description, this step uses the LLVM compiler front-end to convert the high-level language into an intermediate representation (LLVMIR), providing a unified, hardware-independent abstraction layer for subsequent optimization. This ensures that code from different source languages ​​(such as C++ and Rust) can participate in the same optimization process. When screening binary operation instructions at the LLVM IR level, a FunctionPass / BasicBlockPass traversal mechanism is employed to systematically scan instructions within all basic blocks, avoiding potential optimizable instructions that might be missed during manual screening. By using clearly defined candidate instruction identification rules (particularly focusing on parallel arithmetic instructions), the compiler can accurately identify instruction types suitable for subsequent DSP parallelization (such as associative / commutative operations like addition and multiplication). This targeted screening significantly reduces the analysis overhead of invalid instructions. Furthermore, limiting the screening scope to binary operation instructions rather than generalized multi-operand instructions not only accommodates the typical dual-input port hardware characteristics of FPGA DSP modules but also reduces the complexity of instruction combinations. The entire process is fully automated within the compiler, eliminating the need for developers to manually identify parallelizable code segments, while retaining the convenience of high-level language programming.

[0030] Step 130: Combine the binary operation instructions into a tuple that satisfies the DSP input port bit width in the dynamic grouping rule.

[0031] In some embodiments, binary operation instructions are grouped into tuples that satisfy the input port bit width of the DSP in the dynamic grouping rule, specifically including: Process the binary operation instructions one by one in their original order in the basic block, prioritizing placing the current binary operation instruction into the first free DSP slot that meets the bit width requirement. Based on the bit width constraint of the DSP hard core, assign the binary operation instruction to the slot closest to the operand width of the binary operation instruction to form a tuple. When the number of remaining instructions is less than a complete tuple, insert no-ops or copy existing instructions to fill the slot.

[0032] More specifically, this step may be: grouping the binary operation instructions that can be used for DSP parallelism optimization found in the above parsing process according to the operand bit width to ensure that the instruction group meets the DSP input alignment (for example, if the DSP input port is 48 bits, four 12-bit additions or two 24-bit additions can be allocated to the same tuple).

[0033] This step may also include detecting shared operands, that is, identifying sharable common operands in the operation (for example, there are 4 candidate instructions a * b, a * c, a * d, a * e, the grouping PASS can identify that these 4 instructions share operand a, and group these 4 instructions into the same tuple. Through the above grouping process, the 4 multiplication instructions are combined into a tuple, which shares operand a, and one operand of each instruction can be packed into one operand in the subsequent optimization process, thereby packing the tuple into an instruction that can be calculated on a single DSP: a * b, a * c, a * d, a * e -> a * (b pack c packd pack e)).

[0034] The grouping strategy can also be implemented using a greedy algorithm, grouping instructions by instruction order and bit width to prioritize filling the DSP's parallel slots. Furthermore, if the remaining candidate instructions after grouping are insufficient to fit within the tuple capacity, the remaining candidate instructions are filled to the tuple capacity and assigned to the corresponding tuple.

[0035] Based on the above description, this step improves FPGA DSP resource utilization efficiency through an intelligent instruction grouping strategy. This dynamic grouping rule-based grouping mechanism fully accounts for the physical characteristics of the DSP core. By processing instructions one by one in their original order and prioritizing empty slots, it ensures streamlined instruction processing without introducing additional latency due to grouping. Precise alignment of the DSP input port bit width (for example, a 48-bit port can accommodate four 12-bit instructions or two 24-bit instructions) systematically addresses the low DSP bit width utilization previously caused by quantization. This hardware adaptation directly increases the effective computational throughput of the DSP module per clock cycle. The introduction of a shared operand detection mechanism further optimizes the datapath. When multiple instructions share common operands (such as ab and ac), operand packing compresses duplicate operands that would otherwise require multiple loads into a single load, reducing both data bus bandwidth usage and on-chip memory access pressure. The application of a greedy algorithm imbues the grouping process with deterministic processing characteristics. The strategy of filling instructions according to their original order and bit-width constraints not only avoids the compilation delays introduced by complex scheduling algorithms, but also ensures that DSP slots are fully populated in most scenarios. In cases where there are insufficient remaining instructions, the use of no-ops or instruction duplication to fill the slots introduces a small amount of redundant computation, but ensures that the DSP core always runs at the full bit-width. This design trade-off maintains hardware utilization while avoiding wasted DSP clock cycles due to partial loading. The entire grouping process is fully automated, allowing developers to achieve optimized parallel computing results without having to understand the details of the underlying DSP architecture, significantly lowering the threshold for high-performance computing on FPGAs.

[0036] Step 140: Based on the instruction optimization rule, the tuple is packaged into a final operation instruction for the DSP, and the operands of the instructions in the tuple are combined into the operands of the final operation instruction.

[0037] Based on the above description, this step achieves efficient utilization of the DSP hard core through instruction-level packing optimization. The tuple packing mechanism based on instruction optimization rules can convert the grouped discrete instructions into a composite instruction format executable by the DSP. This conversion process strictly follows the instruction set architecture constraints of the DSP hard core to ensure that the generated final operation instructions can be directly mapped to the hardware execution unit. The intelligent combination function of operands analyzes the data dependencies of the instructions in the tuple and packs multiple independent operands into continuously stored operand blocks. This data layout optimization not only reduces the number of memory accesses, but also improves the transmission efficiency of the data bus. The final instruction replacement strategy maintains the equivalence of the original computational semantics. Under the premise of ensuring the correctness of the algorithm, multiple arithmetic operations that originally required multiple cycles to process can be completed in a single DSP cycle. This optimization process is fully automated and does not require developers to manually write hardware-specific instruction scheduling code, significantly lowering the development threshold for FPGA high-performance computing.

[0038] Step 150: Insert the final operation instruction into the preset replacement point through the tuple replacement rule, and mark the original instruction tuple at the preset replacement point as dead code.

[0039] In some embodiments, the final operation instruction is inserted into a preset replacement point using a tuple replacement rule, specifically including: The placeholder instruction is called to replace the original instruction tuple at the preset replacement point with the final operation instruction, and the operands in the original instruction tuple are packaged into the operand format of the placeholder instruction and transmitted to the placeholder instruction.

[0040] Based on the above description, this step ensures that the resulting DSP-optimized instructions are accurately inserted into the preset replacement points through deterministic operation of tuple replacement rules. This positioning mechanism avoids the execution order disorder that may be caused by instruction stream reorganization. The design of using placeholder instructions as the replacement medium not only preserves the data dependencies of the original operands, but also achieves standardized conversion of the operand format to the requirements of the DSP hard core, solving the compatibility issues between heterogeneous instruction sets. The processing method of marking the replaced instruction tuple as dead code enables subsequent compiler optimization stages (such as dead code elimination) to automatically clean up redundant instructions and reduce unnecessary resource usage. The entire replacement process strictly maintains program semantic equivalence, achieving a seamless transition from general instructions to DSP-specific instructions while ensuring computational correctness. This automated replacement mechanism eliminates the risk of human error that may be introduced by traditional manual optimization, while ensuring that the optimized code can still participate in subsequent regular compiler optimization processes.

[0041] After marking the original instruction tuple at the preset replacement point as dead code, the method further includes: Invoke the compiler's dead code elimination routine to remove dead code.

[0042] As described above, this embodiment directly addresses the core issue of low bit-width utilization in DSP modules within FPGAs by pre-setting dynamic grouping and tuple replacement rules within the PASS processing unit. Once binary operation instructions are identified within the LLVM IR, the application dynamically combines instruction tuples based on the DSP input port bit width, packaging previously dispersed low-bit operations (such as 8-bit quantization parameters) into compound instructions that conform to the DSP's full bit-width (e.g., 32-bit). This hardware-level instruction binding enables a single DSP module to simultaneously process discrete operations that would otherwise require multiple DSP units, directly improving the physical utilization of the DSP compute units. Furthermore, the tuple replacement rules intelligently mark dead code, eliminating the logic resources occupied by redundant instructions in traditional manual optimization and further freeing up the FPGA's programmable logic resources. This mechanism completes hardware adaptation during the compilation phase, eliminating the need for developers to intervene in underlying hardware description language optimization.

[0043] This application achieves fully automatic vectorization conversion from high-level languages ​​to hardware instructions through deep integration of the LLVM compiler architecture. The collaborative work of candidate instruction identification rules and instruction optimization rules enables the compiler to autonomously screen operation modes suitable for parallelization (such as matrix multiplication and addition operations) and reconstruct them into DSP-friendly instruction packages. This automated process completely avoids the defects of existing high-level synthesis tools that rely on manual intervention. Developers do not need to manually write Verilog / VHDL code to achieve instruction-level parallelism. More importantly, the tuple replacement rule, while keeping the original algorithm logic unchanged, ensures that the optimization process does not introduce numerical precision loss through semantic equivalence conversion in the compiler's intermediate representation layer, so that the quantized deep learning model can achieve higher hardware execution efficiency while maintaining reasoning accuracy.

[0044] In addition, this application Figure 2 The embodiment of the present application provides a parallel compilation system based on FPGA. Figure 2 As shown, the system provided in the embodiment of the present application mainly includes: An acquisition module 210 is used to acquire a preset PASS processing unit for instruction parallel optimization of the FPGA's DSP; wherein the preset PASS processing unit includes at least: candidate instruction identification rules, dynamic grouping rules, instruction optimization rules, and tuple replacement rules; and the preset PASS processing unit is inserted between the front-end and back-end of the LLVM compiler.

[0045] The candidate instruction identification module 220 is used to convert a preset high-level language into LLVMIR through the LLVM compiler front end; and filter out a number of binary operation instructions that meet the candidate instruction identification rules from the LLVM IR.

[0046] The candidate instruction recognition module 220 includes a candidate instruction recognition unit, Used to traverse the basic blocks in LLVM IR using FunctionPass or BasicBlockPass and extract all binary instructions; Parallel arithmetic instructions are selected from all binary instructions as binary operation instructions.

[0047] The dynamic grouping module 230 is configured to group binary operation instructions into tuples that satisfy the DSP input port bit width in the dynamic grouping rules.

[0048] The dynamic grouping module 230 includes a dynamic grouping unit, It processes binary operation instructions one by one in their original order in the basic block, and prioritizes placing the current binary operation instruction into the first free DSP slot that meets the bit width requirement. Based on the bit width constraint of the DSP hard core, it assigns the binary operation instruction to the slot closest to the operand width of the binary operation instruction to form a tuple. When the number of remaining instructions is less than a complete tuple, insert no-ops or copy existing instructions to fill the slot.

[0049] The instruction optimization module 240 is configured to pack the tuples into final operation instructions for the DSP based on instruction optimization rules, and combine the operands of the instructions in the tuples into operands of the final operation instructions.

[0050] The tuple replacement module 250 is used to insert the final operation instruction into the preset replacement point according to the tuple replacement rule, and mark the original instruction tuple at the preset replacement point as dead code.

[0051] The tuple replacement module 250 further includes a removal unit, Used to call the compiler's dead code elimination routine to remove dead code.

[0052] As described above, this embodiment directly addresses the core issue of low bit-width utilization in DSP modules within FPGAs by pre-setting dynamic grouping and tuple replacement rules within the PASS processing unit. Once binary operation instructions are identified within the LLVM IR, the application dynamically combines instruction tuples based on the DSP input port bit width, packaging previously dispersed low-bit operations (such as 8-bit quantization parameters) into compound instructions that conform to the DSP's full bit-width (e.g., 32-bit). This hardware-level instruction binding enables a single DSP module to simultaneously process discrete operations that would otherwise require multiple DSP units, directly improving the physical utilization of the DSP compute units. Furthermore, the tuple replacement rules intelligently mark dead code, eliminating the logic resources occupied by redundant instructions in traditional manual optimization and further freeing up the FPGA's programmable logic resources. This mechanism completes hardware adaptation during the compilation phase, eliminating the need for developers to intervene in underlying hardware description language optimization.

[0053] This application achieves fully automatic vectorization conversion from high-level languages ​​to hardware instructions through deep integration of the LLVM compiler architecture. The collaborative work of candidate instruction identification rules and instruction optimization rules enables the compiler to autonomously screen operation modes suitable for parallelization (such as matrix multiplication and addition operations) and reconstruct them into DSP-friendly instruction packages. This automated process completely avoids the defects of existing high-level synthesis tools that rely on manual intervention. Developers do not need to manually write Verilog / VHDL code to achieve instruction-level parallelism. More importantly, the tuple replacement rule, while keeping the original algorithm logic unchanged, ensures that the optimization process does not introduce numerical precision loss through semantic equivalence conversion in the compiler's intermediate representation layer, so that the quantized deep learning model can achieve higher hardware execution efficiency while maintaining reasoning accuracy.

[0054] In addition, an embodiment of the present application further provides a non-volatile computer storage medium on which executable instructions are stored. When the executable instructions are executed, the above-mentioned FPGA-based parallel compilation method is implemented.

[0055] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A parallel compilation method based on FPGA, characterized in that: The method comprises: Obtain a preset PASS processing unit for instruction parallel optimization of the FPGA's DSP; wherein the preset PASS processing unit includes at least: candidate instruction identification rules, dynamic grouping rules, instruction optimization rules, and tuple replacement rules; insert the preset PASS processing unit between the LLVM compiler front end and back end; Convert the preset high-level language into LLVM IR through the LLVM compiler front end; filter out several binary operation instructions that meet the candidate instruction identification rules from the LLVM IR; Combining binary operation instructions into tuples that satisfy the input port bit width of the DSP in the dynamic grouping rule; Based on the instruction optimization rules, the tuple is packaged into a final operation instruction for the DSP, and the operands of the instructions in the tuple are combined into the operands of the final operation instruction; Through the tuple replacement rule, the final operation instruction is inserted into the preset replacement point, and the original instruction tuple at the preset replacement point is marked as dead code.

2. The FPGA-based parallel compilation method according to claim 1, wherein: Filter out several binary operation instructions that meet the candidate instruction identification rules from LLVM IR, including: Use FunctionPass or BasicBlockPass to traverse the basic blocks in LLVM IR and extract all binary instructions; Parallel arithmetic instructions are selected from all binary instructions as binary operation instructions.

3. The FPGA-based parallel compilation method according to claim 1, characterized in that: Binary operation instructions are combined into tuples that meet the DSP input port width in the dynamic grouping rules, specifically including: Process the binary operation instructions one by one in their original order in the basic block, prioritizing placing the current binary operation instruction into the first free DSP slot that meets the bit width requirement. Based on the bit width constraint of the DSP hard core, assign the binary operation instruction to the slot closest to the operand width of the binary operation instruction to form a tuple. When the number of remaining instructions is less than a complete tuple, insert no-ops or copy existing instructions to fill the slot.

4. The FPGA-based parallel compilation method according to claim 1, wherein: After marking the original instruction tuple at the preset replacement point as dead code, the method further includes: Invoke the compiler's dead code elimination routine to remove dead code.

5. The FPGA-based parallel compilation method according to claim 1, wherein: The final operation instruction is inserted into the preset replacement point through the tuple replacement rule, including: The placeholder instruction is called to replace the original instruction tuple at the preset replacement point with the final operation instruction, and the operands in the original instruction tuple are packaged into the operand format of the placeholder instruction and transmitted to the placeholder instruction.

6. A parallel compilation system based on FPGA, characterized in that: The system comprises: An acquisition module is configured to acquire a preset PASS processing unit for instruction parallel optimization of the FPGA's DSP; wherein the preset PASS processing unit includes at least: candidate instruction identification rules, dynamic grouping rules, instruction optimization rules, and tuple replacement rules; and the preset PASS processing unit is inserted between the front-end and back-end of the LLVM compiler; The candidate instruction identification module is used to convert the preset high-level language into LLVM IR through the LLVM compiler front end; and filter out several binary operation instructions that meet the candidate instruction identification rules from LLVM IR; A dynamic grouping module, used for grouping binary operation instructions into tuples that satisfy the input port bit width of the DSP in the dynamic grouping rule; An instruction optimization module, for packaging the tuple into a final operation instruction for the DSP based on an instruction optimization rule, and combining operands of the instructions in the tuple into operands of the final operation instruction; The tuple replacement module is used to insert the final operation instruction into the preset replacement point through the tuple replacement rule, and mark the original instruction tuple at the preset replacement point as dead code.

7. The FPGA-based parallel compilation system according to claim 6, characterized in that: The candidate instruction recognition module includes a candidate instruction recognition unit, Used to traverse the basic blocks in LLVM IR using FunctionPass or BasicBlockPass and extract all binary instructions; Parallel arithmetic instructions are selected from all binary instructions as binary operation instructions.

8. The FPGA-based parallel compilation system according to claim 6, characterized in that: The dynamic grouping module includes a dynamic grouping unit, It processes binary operation instructions one by one in their original order in the basic block, and prioritizes placing the current binary operation instruction into the first free DSP slot that meets the bit width requirement. Based on the bit width constraint of the DSP hard core, it assigns the binary operation instruction to the slot closest to the operand width of the binary operation instruction to form a tuple. When the number of remaining instructions is less than a complete tuple, insert no-ops or copy existing instructions to fill the slot.

9. The FPGA-based parallel compilation system according to claim 6, characterized in that: The tuple replacement module also includes the removal unit, Used to call the compiler's dead code elimination routine to remove dead code.

10. A non-volatile computer storage medium, characterized in that Computer instructions are stored thereon, and when the computer instructions are executed, the parallel compilation method based on FPGA is implemented as described in any one of claims 1 to 5.

Images