Dual-wire type intelligent air switch loading storage system

Abstract

The present application relates to the technical fields of street lamp networking system, street lamp control and intelligent air switch, in particular to a double-wire type intelligent air switch loading and storage system, the present application solves the contradiction between reliability and operation mode of traditional storage devices through SPDT switching circuit, SD to USB conversion circuit and double control switching logic, in particular: SD-NAND adopts soldering type packaging, avoiding mechanical contact failure problem; through SPDT switching circuit, flexible switching of online mode and offline mode is realized, without disassembling storage device, firmware update or data repair can be completed; the unit storage cost of SD-NAND is lower than that of NOR Flash and EMMC, and through general SD burning tool, special burning equipment is saved; the double control design of dial code manual switching and GPIO automatic switching supports forced offline operation during first time burning, and meets the automatic switching demand during running, improving system maintenance efficiency.

Description

Technical Field

[0001] This invention relates to the fields of lighting network systems, street light control, and intelligent circuit breaker technology, and more specifically, to a dual-line intelligent circuit breaker loading and storage system. Background Technology

[0002] With the widespread adoption of smart circuit breakers and lighting network systems, storage devices need to simultaneously meet the requirements of high reliability and flexible operation. In existing technologies, while Flash memory offers high reliability, it only supports online operation and requires specialized tools for programming, making offline upgrades impossible. SD cards, while supporting offline operation and being low-cost, suffer from poor mechanical contact reliability, making them unsuitable for high-vibration environments. Furthermore, existing SD-NAND devices, although improving reliability through soldering packaging, only support online operation and are incompatible with offline modes. Therefore, how to retain the low-cost advantage of SD cards while addressing their reliability issues and achieving dual-mode operation (compatible with both online and offline modes) has become a pressing technical challenge. The core of this invention lies in its innovative control circuit design, combined with SD-NAND memory, which retains the high reliability of soldered packaging while supporting dual-mode operation, thereby overcoming the shortcomings of existing technologies. Summary of the Invention

[0003] The purpose of this invention is to provide a dual-line intelligent open-circuit loading and storage system to improve the above-mentioned technical problems.

[0004] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0005] On one hand, embodiments of this application provide a dual-line intelligent open circuit breaker loading storage system, the system including: an SD-NAND memory, which is soldered and integrated on a circuit board;

[0006] A single-pole double-throw (SPDT) switching circuit is connected to the SD-NAND memory and is used to switch the communication channel between the SD-NAND memory and the CPU's SD interface or SD-to-USB conversion circuit. An SD-to-USB conversion circuit, connected to the SPDT switching circuit, is used to convert SD interface signals into USB signals to enable communication with an external PC. A DIP manual switching control circuit, connected to the SPDT switching circuit, is used to manually control channel switching. A GPIO automatic switching control circuit, connected to the SPDT switching circuit, automatically controls channel switching via the CPU's GPIO signals. The SPDT switching circuit switches the communication channel of the SD-NAND memory to online or offline mode according to the instructions of the DIP manual switching control circuit or the GPIO automatic switching control circuit. In online mode, the SD-NAND memory interacts with the CPU through the SD interface; in offline mode, the SD-NAND memory interacts with the PC through the SD-to-USB conversion circuit, achieving dual-line operation.

[0007] Optionally, the DIP switch manual switching control circuit and the GPIO automatic switching control circuit adopt a dual-control design, so that manual switching and automatic switching are effective independently and do not conflict with each other, and manual switching has a higher priority than automatic switching.

[0008] Optionally, the SD to USB conversion circuit includes an STM32XX, GD32XX, or GL823K chip to perform level adaptation and rate conversion between SD and USB signals.

[0009] Optionally, in the online mode, the CPU performs online read and write operations on the SD-NAND memory through the SD interface; in the offline mode, the PC directly performs firmware burning or data repair on the SD-NAND memory through the USB interface.

[0010] Optionally, the SPDT switching circuit is initially connected to the CPU's SD interface by default. When a manual DIP switch signal or a GPIO automatic switching signal is detected, it switches to the SD to USB conversion circuit.

[0011] Optionally, the system supports a bidirectional operation mode in the following ways:

[0012] Step 1: Generate a switching signal through the GPIO automatic switching control circuit to switch the communication channel of the SD-NAND memory to the CPU side;

[0013] Step 2: The CPU reads or writes data to the SD-NAND memory via the SD interface;

[0014] Step 3: When offline operation is required, the GPIO automatic switching control circuit generates a switching signal to switch the communication channel to the SD to USB conversion circuit side;

[0015] Step 4: The PC performs data update or repair operations on the SD-NAND memory via the USB interface;

[0016] In this process, the output of step 1 serves as the input of step 2, and the output of step 3 serves as the input of step 4, ultimately achieving bi-line data interaction.

[0017] Optionally, the SD-NAND memory has a capacity of 8GB or greater, and its unit storage cost is lower than that of NOR Flash or EMMC memory of the same capacity.

[0018] The beneficial effects of this invention are as follows:

[0019] This invention resolves the contradiction between reliability and operating modes in traditional storage devices through an SPDT switching circuit, an SD-to-USB conversion circuit, and dual-control switching logic. Specifically:

[0020] High reliability and compatibility with dual-line operation: SD-NAND uses soldered packaging, avoiding mechanical contact failure issues and is suitable for high vibration environments; through the SPDT switching circuit, it can flexibly switch between online and offline modes, and can complete firmware updates or data repairs without removing the memory.

[0021] Cost advantages: The unit storage cost of SD-NAND is lower than that of NOR Flash and EMMC, and it can be directly operated through a general SD programming tool, eliminating the need for dedicated programming equipment and significantly reducing system costs.

[0022] Operational flexibility: The dual-control design of manual switching of DIP switches and automatic switching of GPIO supports both forced offline operation during the first programming and automatic switching during runtime, improving system maintenance efficiency.

[0023] Two-way data interaction capability: Through time-division multiplexing mechanism, CPU and PC can alternately access the same memory, supporting data synchronization and repair in complex scenarios, and avoiding system paralysis caused by single point of failure in traditional storage systems.

[0024] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing embodiments of the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is an architectural block diagram of a dual-line intelligent open-loop loading and storage system as described in an embodiment of the present invention.

[0027] Figure 2 This is a schematic diagram of the SPDT switching circuit and dual-control logic described in the embodiments of the present invention.

[0028] Figure 3 This is a block diagram of a dual-line intelligent open-circuit loading storage device as described in an embodiment of the present invention. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0030] It should be noted that similar reference numerals or letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0031] Example 1:

[0032] like Figure 1-2 As shown, this embodiment provides a dual-line intelligent open-circuit load storage system, the system comprising:

[0033] SD-NAND memory uses a soldered package and is integrated onto a circuit board;

[0034] The SPDT single-pole double-throw switch circuit is connected to the SD-NAND memory and is used to switch the communication channel between the SD-NAND memory and the CPU's SD interface or the SD to USB conversion circuit. In the initial state, the SPDT single-pole double-throw switch circuit is connected to the CPU's SD interface by default. When a DIP manual switching signal or a GPIO automatic switching signal is detected, it switches to the SD to USB conversion circuit.

[0035] An SD to USB conversion circuit, connected to the SPDT switching circuit, is used to convert SD interface signals into USB signals to enable communication with an external PC. The SD to USB conversion circuit includes an STM32XX, GD32XX, or GL823K chip to perform level adaptation and rate conversion between SD and USB signals.

[0036] A DIP switch manual switching control circuit is connected to the SPDT switching circuit and is used to manually control channel switching;

[0037] The GPIO automatic switching control circuit is connected to the SPDT switching circuit and automatically controls channel switching through the GPIO signals of the CPU.

[0038] The SPDT switching circuit switches the communication channel of the SD-NAND memory to online or offline mode according to the instructions of the DIP manual switching control circuit or the GPIO automatic switching control circuit. In online mode, the SD-NAND memory interacts with the CPU through the SD interface, and in offline mode, the SD-NAND memory interacts with the PC through the SD to USB conversion circuit, realizing dual-line operation.

[0039] The manual switching control circuit and the automatic switching control circuit of GPIO adopt a dual-control design, so that manual switching and automatic switching are effective independently and do not conflict with each other, and manual switching has a higher priority than automatic switching.

[0040] In the online mode, the CPU performs online read and write operations on the SD-NAND memory through the SD interface; in the offline mode, the PC directly performs firmware burning or data repair on the SD-NAND memory through the USB interface, and the capacity of the SD-NAND memory is greater than or equal to 8GB, and the unit storage cost is lower than that of NOR Flash or EMMC memory of the same capacity.

[0041] The dual-line intelligent open-circuit loading storage system described in this embodiment resolves the contradiction between reliability and operating modes in traditional storage devices through SPDT switching circuits, SD-to-USB conversion circuits, and dual-control switching logic. Specifically: High reliability and dual-line operation compatibility: SD-NAND uses soldered packaging, avoiding mechanical contact failures and making it suitable for high-vibration environments; the SPDT switching circuit enables flexible switching between online and offline modes, allowing firmware updates or data repairs without disassembling the storage device. Cost advantage: The unit storage cost of SD-NAND is lower than that of NOR Flash and EMMC, and it can be directly operated using general-purpose SD programming tools, eliminating the need for dedicated programming equipment and significantly reducing system costs. Operational flexibility: The dual-control design, with manual switching via DIP switches and automatic switching via GPIO, supports both forced offline operation during initial programming and automatic switching during runtime, improving system maintenance efficiency. Two-way data interaction capability: Through a time-division multiplexing mechanism, the CPU and PC can alternately access the same storage device, supporting data synchronization and repair in complex scenarios and avoiding system paralysis caused by single-point failures in traditional storage systems.

[0042] Example 2:

[0043] This embodiment, based on Embodiment 1, provides a specific implementation method for a bidirectional operation mode based on a dual-line intelligent open-loop loading and storage system. The method includes:

[0044] Step 1: Generate a switching signal through the GPIO automatic switching control circuit to switch the communication channel of the SD-NAND memory to the CPU side;

[0045] Step 2: The CPU reads or writes data to the SD-NAND memory via the SD interface;

[0046] Step 3: When offline operation is required, the GPIO automatic switching control circuit generates a switching signal to switch the communication channel to the SD to USB conversion circuit side;

[0047] Step 4: The PC performs data update or repair operations on the SD-NAND memory via the USB interface;

[0048] In this process, the output of step 1 serves as the input of step 2, and the output of step 3 serves as the input of step 4, ultimately achieving bi-line data interaction.

[0049] Example 3:

[0050] like Figure 1-2 As shown, this embodiment describes the dual-line intelligent open circuit breaker loading and storage system from three aspects: its structure, connection method, and operation mode.

[0051] Hardware composition and connection relationships:

[0052] SD-NAND memory: The SD-NAND chip (8GB capacity) uses a soldered package and is directly soldered to the circuit board to avoid mechanical contact failure issues. Its interface signals include CLK, CMD, and DAT0-DAT3, which are connected to the SPDT switching circuit.

[0053] SPDT single-pole double-throw switch circuit: composed of high-speed analog switch chips (such as TS5A23157), containing two independent channels:

[0054] Channel A: Connects to the CPU's SD interface (SD_CLK, SD_CMD, SD_DAT0-DAT3).

[0055] Channel B: Connects to the SD to USB conversion circuit;

[0056] The control terminal of the SPDT switching circuit is connected to the DIP manual switching control circuit and the GPIO automatic switching control circuit, respectively.

[0057] SD to USB conversion circuit: The GL823K chip is used to convert the SD interface signal to a USB 2.0 signal and connect to the PC through the Micro-USB interface to realize signal adaptation and communication during offline operation.

[0058] Manual DIP switch control circuit: It consists of 4 DIP switches and pull-up resistors, and directly controls the channel selection of the SPDT switching circuit through high and low levels.

[0059] GPIO automatic switching control circuit: The CPU outputs high and low level signals through GPIO pins (such as GPIO12) to control the automatic switching logic of the SPDT switching circuit.

[0060] Connection relationships:

[0061] The SD-NAND interface signal lines are connected to the common terminal of the SPDT switching circuit;

[0062] Channel A of the SPDT switching circuit is connected to the CPU's SD interface, and channel B is connected to the SD to USB conversion circuit.

[0063] The output of the DIP switch is connected in parallel with the GPIO pin and then connected to the control terminal of the SPDT switching circuit to ensure that manual switching has a higher priority than automatic switching.

[0064] Work mode and operation process:

[0065] Mode 1: Online Mode (CPU Interaction)

[0066] Initial state: The SPDT switching circuit is connected to channel A (CPU side) by default, and the GPIO automatic switching control circuit outputs a low level.

[0067] Operating procedures:

[0068] 1. The CPU sends read and write commands to the SD-NAND via the SD interface (such as reading configuration files or updating firmware).

[0069] 2. The SD-NAND responds to commands and completes data exchange through the SD interface;

[0070] 3. If it is necessary to switch to offline mode, the CPU outputs a high-level signal through GPIO12 to trigger the SPDT switching circuit to disconnect channel A and connect channel B.

[0071] Mode 2: Offline Mode (PC Interaction)

[0072] Forced Switching: When burning SD-NAND for the first time or when emergency repair is required, manually toggle the DIP switch to the "OFFLINE" position to force the SPDT switching circuit to connect to channel B.

[0073] Operating procedures:

[0074] 1. The PC sends the burning command via USB interface (e.g., using the Win32DiskImager tool);

[0075] 2. The SD to USB conversion circuit converts the USB signal into an SD interface signal, which is then directly written to the SD-NAND.

[0076] 3. After the operation is completed, reset the DIP switch, and the system will automatically return to online mode.

[0077] Mode 3: Bidirectional operation (time-division multiplexing).

[0078] Automatic switching logic:

[0079] 1. The CPU outputs a low level through GPIO12, and SPDT switches to channel A to read the running data from the SD-NAND.

[0080] 2. When an offline operation request is detected from the PC, GPIO12 outputs a high level, switching to channel B;

[0081] 3. After the PC completes the data update, GPIO12 returns to low level and switches back to channel A;

[0082] 4. The CPU continues to process the updated data, forming a closed-loop interaction.

[0083] Secondly, the dual-line intelligent open circuit breaker loading and storage system described in this embodiment also includes:

[0084] Bad block repair function: The PC can use the SD Formatter tool via USB connection to directly detect and repair bad blocks on the SD-NAND without removing the chip;

[0085] Multi-device compatibility: The SD to USB conversion circuit supports the USB Type-C interface, adapting to different PC devices;

[0086] Low power consumption design: The SPDT switching circuit automatically enters sleep mode when idle, reducing system power consumption.

[0087] Example 4:

[0088] Corresponding to the above method embodiments, this disclosure also provides a dual-line intelligent open circuit breaker loading storage device. The specific implementation method of the dual-line intelligent open circuit breaker loading storage device described below and the bidirectional operation mode described above can be referred to each other.

[0089] Figure 3 This is a block diagram illustrating a two-line intelligent open-circuit load storage device according to an exemplary embodiment. For example... Figure 3 As shown, the electronic device 800 may include a processor 801 and a memory 802. The electronic device 800 may also include one or more of a multimedia component 803, an I / O interface 804, and a communication component 805.

[0090] The processor 801 controls the overall operation of the electronic device 800 to complete all or part of the steps in the aforementioned two-wire intelligent circuit breaker loading and storage method. The memory 802 stores various types of data to support the operation of the electronic device 800. This data may include, for example, instructions for any application or method operating on the electronic device 800, and application-related data such as contact data, sent and received messages, pictures, audio, video, etc. The memory 802 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. Multimedia component 803 may include a screen and an audio component. The screen may be, for example, a touchscreen, and the audio component is used to output and / or input audio signals. For example, the audio component may include a microphone for receiving external audio signals. The received audio signals may be further stored in memory 802 or transmitted via communication component 805. The audio component also includes at least one speaker for outputting audio signals. I / O interface 804 provides an interface between processor 801 and other interface modules, such as a keyboard, mouse, buttons, etc. These buttons may be virtual or physical buttons. Communication component 805 is used for wired or wireless communication between the electronic device 800 and other devices. Wireless communication may include Wi-Fi, Bluetooth, Near Field Communication (NFC), 2G, 3G, or 4G, or a combination of these. Therefore, the corresponding communication component 805 may include a Wi-Fi module, a Bluetooth module, or an NFC module.

[0091] In an exemplary embodiment, the electronic device 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to execute the above-described two-wire intelligent open-circuit load memory method.

[0092] In another exemplary embodiment, a computer-readable storage medium including program instructions is also provided, which, when executed by a processor, implement the steps of the dual-wire intelligent open-circuit load storage method described above. For example, the computer-readable storage medium may be the memory 802 including the program instructions described above, which may be executed by the processor 801 of the electronic device 800 to complete the dual-wire intelligent open-circuit load storage method described above.

[0093] Example 5:

[0094] Corresponding to the above method embodiments, this disclosure also provides a readable storage medium. The readable storage medium described below can be referred to in conjunction with the dual-line intelligent open-circuit loading storage method described above.

[0095] A readable storage medium storing a computer program, wherein when the computer program is executed by a processor, the steps of the two-line intelligent open circuit loading storage method described in the above method embodiment are implemented.

[0096] Specifically, the readable storage medium can be a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, or any other readable storage medium capable of storing program code.

[0097] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A dual-line intelligent open-circuit loading and storage system, characterized in that, The system includes: SD-NAND memory uses a soldered package and is integrated onto a circuit board; SPDT single-pole double-throw switch circuit, connected to the SD-NAND memory, is used to switch the communication channel between the SD-NAND memory and the CPU's SD interface or SD to USB conversion circuit; An SD to USB conversion circuit, connected to the SPDT switching circuit, is used to convert SD interface signals into USB signals to enable communication with an external PC. A DIP switch manual switching control circuit is connected to the SPDT switching circuit and is used for manual control of channel switching; The GPIO automatic switching control circuit is connected to the SPDT switching circuit and automatically controls channel switching through the GPIO signals of the CPU. The SPDT switching circuit switches the communication channel of the SD-NAND memory to online or offline mode according to the instructions of the DIP manual switching control circuit or the GPIO automatic switching control circuit. In online mode, the SD-NAND memory interacts with the CPU through the SD interface, and in offline mode, the SD-NAND memory interacts with the PC through the SD to USB conversion circuit, realizing dual-line operation.

2. The dual-line intelligent open-circuit loading and storage system according to claim 1, characterized in that, The manual switching control circuit and the automatic switching control circuit of GPIO adopt a dual-control design, so that manual switching and automatic switching are effective independently and do not conflict with each other, and manual switching has a higher priority than automatic switching.

3. The dual-line intelligent open-circuit loading and storage system according to claim 2, characterized in that, The SD to USB conversion circuit includes an STM32XX, GD32XX, or GL823K chip, used to perform level adaptation and rate conversion between SD and USB signals.

4. The dual-line intelligent open-circuit loading and storage system according to claim 3, characterized in that, In the online mode, the CPU performs online read and write operations on the SD-NAND memory through the SD interface; in the offline mode, the PC directly performs firmware burning or data repair on the SD-NAND memory through the USB interface.

5. The dual-line intelligent open-circuit loading and storage system according to claim 4, characterized in that, The SPDT single-pole double-throw switch circuit is initially connected to the CPU's SD interface by default. When a manual DIP switch signal or a GPIO automatic switch signal is detected, it switches to the SD to USB conversion circuit.

6. The dual-line intelligent open-circuit loading and storage system according to claim 5, characterized in that, The system supports a bidirectional operation mode in the following way: Step 1: Generate a switching signal through the GPIO automatic switching control circuit to switch the communication channel of the SD-NAND memory to the CPU side; Step 2: The CPU reads or writes data to the SD-NAND memory via the SD interface; Step 3: When offline operation is required, the GPIO automatic switching control circuit generates a switching signal to switch the communication channel to the SD to USB conversion circuit side; Step 4: The PC performs data update or repair operations on the SD-NAND memory via the USB interface; In this process, the output of step 1 serves as the input of step 2, and the output of step 3 serves as the input of step 4, ultimately achieving bi-line data interaction.

7. The dual-line intelligent open-circuit loading and storage system according to claim 5, characterized in that, The SD-NAND memory has a capacity of 8GB or more, and its unit storage cost is lower than that of NOR Flash or EMMC memory of the same capacity.

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