Driving method of display panel, display panel and display device

Abstract

The invention provides a driving method of a display panel, the display panel and a display device, relates to the technical field of display, and is used for reducing power consumption. The display panel applied by the driving method comprises a pixel circuit connected with a data line; a circuit row; the gating unit is connected with one source signal line, at least two control lines and at least two data lines; the circuit rows comprise a first circuit row and a second circuit row which are adjacent to each other, the control lines comprise first control lines, and the data lines comprise first data lines; the driving method comprises the steps that in the circuit line scanning process, at least two control lines provide effective levels in a time-sharing mode, a first control line provides a first effective level, and the first effective level is overlapped with the scanning time of a first circuit line and a second circuit line; in the process of providing the first effective level, the source signal line writes the voltage required by the circuit in the first circuit row into the first data line when the first circuit row is scanned, and writes the voltage required by the circuit in the second circuit row into the first data line when the second circuit row is scanned.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel driving method, a display panel, and a display device. Background Art

[0002] The display device includes a display panel and a driver chip. The driver chip provides data voltages to data lines in the display panel, thereby driving sub-pixels in the display panel to emit light.

[0003] Currently, display panels can also include a gating unit, which is used to write data voltages to the data lines in an orderly, time-sharing manner. This can reduce the number of pins in the driver chip, thereby reducing the chip's physical size and achieving lower costs. However, the gating unit consumes significant power during operation, increasing panel power consumption and impacting performance. Summary of the Invention

[0004] Embodiments of the present invention provide a display panel driving method, a display panel, and a display device, which can effectively reduce the power consumption generated by a gating unit during operation.

[0005] In a first aspect, an embodiment of the present invention provides a method for driving a display panel, wherein the display panel used in the method includes: a plurality of pixel circuits, wherein the pixel circuits are electrically connected to the first scan line and the data line respectively; a plurality of circuit rows arranged along a first direction, the circuit rows including a plurality of the pixel circuits arranged along a second direction, the first direction intersecting the second direction; a plurality of gating units, each of the gating units comprising at least two switches; in each of the gating units, input terminals of at least two of the switches are electrically connected to the same source signal line, control terminals of at least two of the switches are electrically connected to at least two control lines, and output terminals of at least two of the switches are electrically connected to at least two data lines; The circuit rows include adjacent first and second circuit rows, the control lines include first control lines, the data lines include first data lines, and the first control lines and the first data lines are connected to the same switch; The driving method includes: controlling the first scanning line to scan the plurality of circuit rows row by row, driving the pixel circuits in the circuit rows to perform a data writing operation; during the scanning process of the circuit rows, at least two of the control lines provide an effective voltage in a time-sharing manner, controlling at least two of the switches in the gating unit to be turned on in a time-sharing manner, so that the data voltage in the source signal line is written into the corresponding data line; wherein the valid level provided by the first control line comprises a first valid level, and a coverage time of the first valid level overlaps with a scan time of a first circuit row and a second circuit row; During the process of the first control line providing the first effective level, the source signal line writes the data voltage required for the pixel circuit in the first circuit row to the first data line during the scanning time of the first circuit row, and writes the data voltage required for the pixel circuit in the second circuit row to the first data line during the scanning time of the second circuit row.

[0006] In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a display panel, including: a plurality of pixel circuits, each of which is electrically connected to a first scan line and a data line, and configured to perform a data writing operation under the scanning action of the first scan line; a plurality of circuit rows arranged along a first direction, the circuit rows including a plurality of the pixel circuits arranged along a second direction, the first direction intersecting the second direction; a plurality of gating units, each of the gating units comprising at least two switches; in each of the gating units, input terminals of at least two of the switches are electrically connected to the same source signal line, control terminals of at least two of the switches are electrically connected to at least two control lines, and output terminals of at least two of the switches are electrically connected to at least two data lines; The circuit rows include adjacent first and second circuit rows, the control lines include first control lines, the data lines include first data lines, and the first control lines and the first data lines are connected to the same switch; The first control line is used to provide a first effective level, and the coverage time of the first effective level overlaps with the scanning time of a first circuit row and a second circuit row at the same time; in the process of the first control line providing the first effective level, the source signal line writes the data voltage required by the pixel circuit in the first circuit row to the first data line during the scanning time of the first circuit row, and writes the data voltage required by the pixel circuit in the second circuit row to the first data line during the scanning time of the second circuit row.

[0007] In a third aspect, based on the same inventive concept, an embodiment of the present invention further provides a display device comprising the above-mentioned display panel.

[0008] The technical solution provided by the embodiment of the present invention has the following beneficial effects: The embodiment of the present invention adjusts the signal timing of the control lines, and changes the order in which different control lines output valid levels during the driving process of the first circuit row and the second circuit row. When the source signal line sends the data voltage to the pixel circuit connected to the first data line in the two circuit rows, the signal of the first control line does not need to undergo a voltage jump, thereby reducing the number of voltage jumps in the signal provided by the first control line, effectively saving the power consumption generated by the selection unit during operation, reducing the panel power consumption while ensuring that the display effect is not affected, and improving the product competitiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative labor.

[0010] Figure 1 A schematic diagram of a structure of a display panel in related technology; Figure 2 It is a timing diagram in the related art; Figure 3 A schematic structural diagram of a display panel provided by an embodiment of the present invention; Figure 4 A signal timing diagram provided by an embodiment of the present invention; Figure 5 Another structural schematic diagram of a display panel provided by an embodiment of the present invention; Figure 6 Another timing diagram provided by an embodiment of the present invention; Figure 7 Another timing diagram provided by an embodiment of the present invention; Figure 8 Another timing diagram provided by an embodiment of the present invention; Figure 9 Another timing diagram provided by an embodiment of the present invention; Figure 10 Another timing diagram provided by an embodiment of the present invention; Figure 11 A schematic structural diagram of a pixel circuit provided by an embodiment of the present invention; Figure 12 Another timing diagram provided by an embodiment of the present invention; Figure 13 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0011] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0012] It should be understood that the embodiments described are only a portion of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative work are within the scope of protection of the present invention.

[0013] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The singular forms "a", "an", "the" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0014] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0015] Figure 1 A schematic diagram of a structure of a display panel in related technology is shown in FIG. Figure 1 As shown, the display panel includes a plurality of pixel circuits 1, and the pixel circuits 1 are electrically connected to the data lines Data. Figure 1 In the figure, multiple pixel circuits are represented by reference numerals 1-1 to 1-4 respectively to distinguish different pixel circuits 1, thereby facilitating the description of the working process of the display panel.

[0016] The display panel further includes a plurality of circuit rows 2 arranged along a first direction x. The circuit rows 2 include a plurality of pixel circuits 1 arranged along a second direction y. The first direction x intersects the second direction y. Figure 1 Only the i-th to i+3-th circuit rows are shown. For easy distinction, these four circuit rows are represented by reference numerals 2-1 to 2-i+3, respectively.

[0017] The display panel further includes a plurality of gating units 3, each including at least two switches 4. In the gating unit 3, input ends of at least two switches 4 are electrically connected to the same source signal line source, control ends of at least two switches 4 are electrically connected to at least two control lines mux, and output ends of at least two switches 4 are electrically connected to at least two data lines Data. Figure 1The gating unit 3 includes two switches 4 as an example. The two switches are represented by reference numerals 4-1 and 4-2 respectively. Correspondingly, the control lines connected to the switches 4-1 and 4-2 are represented by reference numerals mux-1 and mux-2 respectively.

[0018] During the driving process of the display panel, a plurality of circuit rows 2 are scanned row by row. During the scanning process, the pixel circuits 1 included in the circuit rows 2 perform data writing operations.

[0019] In the related art, during the scanning process of each circuit row 2, multiple control lines mux provide effective levels in sequence and in a time-sharing manner, thereby controlling multiple switches 4 in the selection unit 3 to be turned on in a time-sharing manner, so that the data voltage in the source signal line source can be transmitted to the corresponding data line Data through the turned-on switch 4, and then written into the pixel circuit 1 of the circuit row 2.

[0020] The following combination Figure 2 , the driving process of the i-th to i+3-th circuit rows 2-i+3 is explained. Figure 2 It is a timing diagram in the related art, wherein the reference numerals of the various signals in the timing diagram are consistent with the reference numerals of the corresponding signal lines.

[0021] In the scanning process t1 of the i-th circuit row 2-i: first, the control line mux-2 provides a valid level, and the data voltage v1 in the source signal line source is written into the pixel circuit 1-1 in the i-th circuit row 2-i via the switch 4-1 and the data line Data connected thereto; then, the control line mux-1 provides a valid level, and the data voltage v2 in the source signal line source is written into the pixel circuit 1-2 in the i-th circuit row 2-i via the switch 4-2 and the data line Data connected thereto, so as to complete the image sending operation for the pixel circuit in the i-th circuit row 2-i.

[0022] Then, the scanning process t2 of the i+1th circuit row 2-i+1 is entered. In this process: first, the control line mux-2 provides a valid level, and the data voltage v3 in the source signal line source is written into the pixel circuit 1-3 in the i+1th circuit row 2-i+1 via the switch 4-1 and the data line Data connected thereto; then, the control line mux-1 provides a valid level, and the data voltage v4 in the source signal line source is written into the pixel circuit 1-4 in the i+1th circuit row 2-i+1 via the switch 4-2 and the data line Data connected thereto, so as to complete the image sending operation for the pixel circuit in the i+1th circuit row 2-i+1.

[0023] Then, the scanning process t3 of the i+2th circuit row 2-i+2 is entered. In this process: first, the control line mux-2 provides a valid level, and the data voltage v1 in the source signal line source is written into the pixel circuit 1-1 in the i+2th circuit row 2-i+2 via the switch 4-1 and the data line Data connected thereto; then, the control line mux-1 provides a valid level, and the data voltage v2 in the source signal line source is written into the pixel circuit 1-2 in the i+2th circuit row 2-i+2 via the switch 4-2 and the data line Data connected thereto, so as to complete the image sending operation for the pixel circuit in the i+2th circuit row 2-i+2.

[0024] Then, the scanning process t4 of the i+3th circuit row 2-i+3 is entered. In this process: first, the control line mux-2 provides a valid level, and the data voltage v3 in the source signal line source is written into the pixel circuit 1-3 in the i+3th circuit row 2-i+3 via the switch 4-1 and the data line Data connected thereto; then, the control line mux-1 provides a valid level, and the data voltage v4 in the source signal line source is written into the pixel circuit 1-4 in the i+3th circuit row 2-i+3 via the switch 4-2 and the data line Data connected thereto, so as to complete the image sending operation for the pixel circuit in the i+3th circuit row 2-i+3.

[0025] In summary, during the driving process of the display panel, the order of sending images to the pixel circuits 1 in the plurality of circuit rows 2 is “1-1, 1-2, 1-3, 1-4, 1-1, 1-2, 1-3, 1-4, 1-1, 1-2, 1-3, 1-4…”. Figure 1 The bold black lines in the figure are used to indicate the order in which the images are sent.

[0026] In related art, during the driving process of each circuit row 2, multiple control line muxes provide valid voltage levels in a consistent order. Taking two control line muxes as an example, each control line mux undergoes a voltage jump every time the source signal line "source" sends a data voltage. This results in frequent voltage jumps in the control signal. The voltage difference between the high and low levels in the control signal is around 15V, which in turn results in high power consumption.

[0027] In this regard, an embodiment of the present invention provides a method for driving a display panel. The method adjusts the manner in which a control line provides a signal, thereby significantly saving power consumption generated during the operation of a gating unit.

[0028] The driving method provided by the embodiment of the present invention is applied in Figure 3 In the panel structure shown, Figure 3 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention is shown in FIG. Figure 3As shown, the display panel includes a plurality of pixel circuits 1 , which are electrically connected to the first scan line S1 and the data line Data, respectively. The pixel circuits 1 perform a data writing operation in response to a first scan signal. Figure 3 In the figure, multiple pixel circuits are represented by reference numerals 1-1 to 1-4 respectively to distinguish different pixel circuits 1, thereby facilitating the description of the working process of the display panel.

[0029] The display panel further includes a plurality of circuit rows 2 arranged along a first direction x. The circuit rows 2 include a plurality of pixel circuits 1 arranged along a second direction y. The first direction x intersects the second direction y. Figure 3 Only the i-th to i+3-th circuit rows are illustrated. For easy distinction, these four circuit rows are represented by reference numerals 2-1 to 2-i+3, respectively. Correspondingly, the first scan lines corresponding to these four circuit rows are represented by reference numerals S1-i to S1-i+3, respectively.

[0030] The display panel further includes a plurality of gating units 3, each including at least two switches 4. In the gating unit 3, input ends of at least two switches 4 are electrically connected to the same source signal line source, control ends of at least two switches 4 are electrically connected to at least two control lines mux, and output ends of at least two switches 4 are electrically connected to at least two data lines Data. Figure 3 The diagram is provided by taking the example of a gating unit 3 including two switches 4. The two switches 4 are denoted by reference numerals 4-1 and 4-2, respectively. Correspondingly, the control lines corresponding to the switches 4-1 and 4-2 are denoted by reference numerals mux-1 and mux-2, respectively.

[0031] The circuit row 2 includes an adjacent first circuit row 5 and a second circuit row 6. The control line mux includes a first control line mux (1), and the data line Data includes a first data line Data (1). The first control line mux (1) and the first data line Data (1) are connected to the same switch 4.

[0032] Figure 4 A signal timing diagram provided by an embodiment of the present invention, combined with Figure 3 and Figure 4 , the display panel driving method provided by the embodiment of the present invention includes: The first scan line S1 is controlled to scan the plurality of circuit rows 2 row by row, driving the pixel circuits 1 in the circuit rows 2 to perform a data write operation. Specifically, the process involves the plurality of first scan lines S1 sequentially outputting active levels, controlling the pixel circuits 1 in each circuit row 2 to perform a data write operation in response to the active levels.

[0033] During the scanning process of circuit row 2, at least two control lines mux provide active levels in a time-sharing manner to control at least two switches 4 in the selection unit 3 to be turned on in a time-sharing manner, so that the data voltage in the source signal line source is written into the corresponding data line Data.

[0034] The effective level provided by the first control line mux (1) includes a first effective level 7, and the coverage time of the first effective level 7 overlaps with the scanning time of a first circuit row 5 and a second circuit row 6. In the process of the first control line mux (1) providing the first effective level 7, the source signal line source writes the data voltage required by the pixel circuit 1 in the first circuit row 5 to the first data line Data (1) during the scanning time of the first circuit row 5, and writes the data voltage required by the pixel circuit 1 in the second circuit row 6 to the first data line Data (1) during the scanning time of the second circuit row 6.

[0035] by Figure 3 For example, the control line mux-1 is the first control line mux (1), the i-th circuit row 2-i is the first circuit row 5, and the i+1-th circuit row 2-i+1 is the second circuit row 6. Figure 3 and Figure 4 , during the driving process of the i-th and i+1-th circuit rows, one of the first effective levels 7 output by the control line mux-1 (first control line mux (1)) simultaneously overlaps with the effective level of the first scanning signal S1-i corresponding to the i-th circuit row 2-i (first circuit row 5) and the effective level of the first scanning signal S1-i+1 corresponding to the i+1-th circuit row 2-i+1 (second circuit row 6).

[0036] During the time when the first active level 7 overlaps with the active level in the first scanning signal S1-i, the source signal line source writes the data voltage v2 required for the pixel circuit 1-2 in the i-th circuit row 2-i to the first data line Data(1). During the time when the first active level 7 overlaps with the active level in the first scanning signal S1-i+1, the source signal line source writes the data voltage v4 required for the pixel circuit 1-4 in the i+1-th circuit row 2-i+1 to the first data line Data(1).

[0037] That is, in the driving process of the i-th and i+1-th circuit rows, the order of sending images to the pixel circuit 1 is changed from "1-1, 1-2, 1-3, 1-4" in the related art to "1-1, 1-2, 1-4, 1-3". Figure 3The bold black lines in the figure represent the image transmission sequence. The image transmission processes of pixel circuits 1-2 and 1-4 are adjacent. When the source signal line source transmits the data voltage to pixel circuits 1-2 and 1-4, the signal provided by the first control line mux (1) (control line mux-1) does not need to undergo voltage jumps, thereby reducing the number of voltage jumps in the signal.

[0038] In summary, the embodiment of the present invention adjusts the signal timing of the control line mux. When the source signal line source sends the data voltage to the pixel circuit 1 connected to the first data line Data (1) in the first circuit row 5 and the second circuit row 6, the signal of the first control line mux (1) does not need to undergo voltage jump, thereby reducing the number of voltage jumps in the signal provided by the first control line mux (1), effectively saving the power consumption generated by the selection unit 3 during operation, reducing the panel power consumption while ensuring that the display effect is not affected, and improving the product competitiveness.

[0039] It should be noted that, compared with the related art, the frequency of refreshing the data voltage in the source signal line source in the embodiment of the present invention is unchanged.

[0040] Combine Figure 3 and Figure 4 In a feasible implementation manner, the first circuit rows 5 and the second circuit rows 6 are arranged alternately.

[0041] The display panel includes a plurality of circuit groups 8 arranged along a first direction x, and the circuit row 2 includes a first circuit row 5 and a second circuit row 6 arranged along a second direction y. The signal provided by the first control line mux (1) includes alternating first active levels 7 and inactive levels, and the coverage time of a first active level 7 overlaps with the scanning time of the first circuit row 5 and the second circuit row 6 in the same circuit group 8.

[0042] In this driving mode, the signal provided by the first control line mux (1) is periodic. Compared with the related art, the number of voltage jumps in the signal provided by the first control line mux (1) is reduced by half, which can save more power consumption.

[0043] Combine Figure 3 and Figure 4 In a feasible implementation manner, the control line mux further includes a second control line mux (2), the data line Data includes a second data line Data (2), and the second control line mux (2) and the second data line Data (2) are connected to the same switch 4.

[0044] The effective level provided by the second control line mux (2) includes a second effective level 9, and the coverage time of the second effective level 9 overlaps with the scanning time of the second circuit row 6 in the previous circuit group 8 and the first circuit row 5 in the next circuit group 8 in the two adjacent circuit groups 8. In the process of the second control line mux (2) providing the second effective level 9, the source signal line source writes the data voltage required by the pixel circuit 1 in the first circuit row 5 to the second data line Data (2) during the scanning time of the first circuit row 5, and writes the data voltage required by the pixel circuit 1 in the second circuit row 6 to the second data line Data (2) during the scanning time of the second circuit row 6.

[0045] For example, see Figure 3 , the control line mux-2 is the second control line mux (2), the i-th to i+3-th circuit rows constitute two adjacent circuit groups 8, the former circuit group 8 includes the i-th and i+1-th circuit rows, and the latter circuit group 8 includes the i+2-th circuit row 2-i+2 and the i+3-th circuit row 2-i+3.

[0046] One of the second effective levels 9 output by the control line mux-2 (the second control line mux (2)) simultaneously overlaps with the effective level of the first scanning signal S1-i+1 corresponding to the i+1th circuit row 2-i+1 (the second circuit row 6 in the previous circuit group 8) and the effective level of the first scanning signal S1-i+2 corresponding to the i+2th circuit row 2-i+2 (the first circuit row 5 in the next circuit group 8).

[0047] During the time when the second effective level 9 overlaps with the effective level in the first scanning signal S1-i+1, the source signal line source writes the data voltage v3 required by the pixel circuit 1-3 in the i+1th circuit row 2-i+1 to the second data line Data(2). During the time when the second effective level 9 overlaps with the effective level in the first scanning signal S1-i+2, the source signal line source writes the data voltage v1 required by the pixel circuit 1-1 in the i+2th circuit row 2-i+2 to the second data line Data(2).

[0048] The following combination Figure 3 and Figure 4 , the driving process of the i-th to i+3-th circuit rows 2-i+3 is explained.

[0049] In the driving process t1 of the i-th circuit row 2-i: in the first half, the control line mux-2 provides the second effective level 9, and the data voltage v1 in the source signal line source is written into the pixel circuit 1-1 in the i-th circuit row 2-i; in the second half, the control line mux-1 provides the first effective level 7, and the data voltage v2 in the source signal line source is written into the pixel circuit 1-2 in the i-th circuit row 2-i.

[0050] In the scanning process t1 of the i+1th circuit row 2-i+1: in the first half, the control line mux-1 maintains and provides the first effective level 7, and the data voltage v2 in the source signal line source is written into the pixel circuit 1-4 in the i+1th circuit row 2-i+1; in the second half, the control line mux-2 provides the first effective level 7, and the data voltage v3 transmitted in the source signal line source is written into the pixel circuit 1-3 in the i+1th circuit row 2-i+1.

[0051] In the scanning process t3 of the i+2th circuit row 2-i+2: in the first half, the control line mux-2 maintains to provide the second effective level 9, and the data voltage v1 in the source signal line source is written into the pixel circuit 1-1 in the i-th circuit row 2-i; in the second half, the control line mux-1 provides the first effective level 7, and the data voltage v2 in the source signal line source is written into the pixel circuit 1-2 in the i-th circuit row 2-i.

[0052] In the scanning process t4 of the i+3th circuit row 2-i+3: in the first half, the control line mux-1 maintains and provides the first effective level 7, and the data voltage v2 in the source signal line source is written into the pixel circuit 1-4 in the i+1th circuit row 2-i+1; in the second half, the control line mux-2 provides the first effective level 7, and the data voltage v3 transmitted in the source signal line source is written into the pixel circuit 1-3 in the i+1th circuit row 2-i+1.

[0053] In summary, during the scanning process of the i-th to i+3-th circuit rows, the image transmission order for pixel circuit 1 is "1-1, 1-2, 1-4, 1-3, 1-1, 1-2, 1-4, 1-3". During the image transmission process of pixel circuits 1-2 and 1-4, the signal provided by the control line mux-1 (first control line mux (1)) does not need to undergo voltage jumps, so that the number of voltage jumps in the signal is reduced. At the same time, during the image transmission process of pixel circuits 1-3 and 1-1, the signal provided by the control line mux-2 (second control line mux (2)) does not need to undergo voltage jumps, so the number of voltage jumps in the signal is also reduced.

[0054] The above driving method can further reduce the voltage jump frequency in the signal provided by the second control line mux (2), thereby further saving the power consumption generated by the gating unit 3 during operation, and the power consumption of the panel can be reduced to a lower level.

[0055] In a feasible implementation manner, the duration of the first effective level 7 is equal to the duration of the second effective level 9 .

[0056] That is, the connection time between the source signal line source and the first data line Data (1) is consistent with the connection time between the source signal line source and the second data line Data (2), which helps to improve the charging consistency of the first data line Data (1) and the second data line Data (2).

[0057] In one possible embodiment, combining Figure 3 and Figure 4 , the gating unit 3 may include only two gating switches 4. Accordingly, the display panel includes two control lines mux, one of which is a first control line mux (1) and the other is a second control line mux (2). After adopting the above driving method, the voltage jump frequency of the signals provided by the two control lines mux can be reduced to half.

[0058] Or, in another possible embodiment, combined with Figure 5 and Figure 6 The selection unit 3 may also include at least three switches 4. Correspondingly, the display panel includes at least three control lines mux, one of the at least three control lines mux is a first control line mux (1), another is a second control line mux (2), and the remaining at least one is a third control line mux (3).

[0059] Specifically, Figure 5 Another structural diagram of a display panel provided by an embodiment of the present invention is shown in FIG. Figure 6 Another timing diagram provided by an embodiment of the present invention is: Figure 5 In the figure, multiple pixel circuits are represented by reference numerals 1- to 1-F, respectively, to distinguish different pixel circuits 1, thereby facilitating the description of the working process of the display panel.

[0060] like Figure 5 and Figure 6 As shown, the control line mux further includes a third control line mux (3), the data line Data includes a third data line Data (3), and the third control line mux (3) and the third data line Data (3) are connected to the same switch 4. In the second direction y, the pixel circuit 1 connected to the third data line Data (3) is located between the pixel circuits 1 connected to the first data line Data (1) and the second data line Data (2).

[0061] The effective level provided by the third control line mux (3) includes an interval of a third effective level 10 and a fourth effective level 11, and the coverage time of the third effective level 10 and the fourth effective level 11 is separated by a coverage time of a first effective level 7 or a coverage time of a second effective level 9. The coverage time of a third effective level 10 overlaps with a scanning time of a first circuit row 5. During the process of the third control line mux (3) providing the third effective level 10, the source signal line source writes the data voltage required by the pixel circuit 1 in the first circuit row 5 to the third data line Data (3). The coverage time of a fourth effective level 11 overlaps with a scanning time of a second circuit row 6. During the process of the third control line mux (3) providing the fourth effective level 11, the source signal line source writes the data voltage required by the pixel circuit 1 in the second circuit row 6 to the third data line Data (3).

[0062] The following combination Figure 5 and Figure 6 , the driving process of the i-th to i+3-th circuit rows is described. The driving process of each circuit row 2 includes three sub-periods.

[0063] In the scanning process t1 of the i-th circuit row 2-i: in the first sub-period, the control line mux-2 maintains to provide the second effective level 9, and the data voltage vA in the source signal line source is written into the pixel circuit 1-A in the i-th circuit row 2-i; in the second sub-period, the control line mux-3 provides the third effective level 10, and the data voltage vB in the source signal line source is written into the pixel circuit 1-B in the i-th circuit row 2-i; in the third sub-period, the control line mux-1 provides the first effective level 7, and the data voltage vC in the source signal line source is written into the pixel circuit 1-C in the i-th circuit row 2-i.

[0064] In the scanning process t2 of the i+1th circuit row 2-i+1: in the first sub-period, the control line mux-1 (the first control line mux (1)) maintains to provide the first effective level 7, and the data voltage vF in the source signal line source is written into the pixel circuit 1-F in the i+1th circuit row 2-i+1; in the second sub-period, the control line mux-3 (the third control line mux (3)) provides the fourth effective level 11, and the data voltage vE in the source signal line source is written into the pixel circuit 1-E in the i+1th circuit row 2-i+1; in the third sub-period, the control line mux-2 (the second control line mux (2)) provides the first effective level 7, and the data voltage vD transmitted in the source signal line source is written into the pixel circuit 1-D in the i+1th circuit row 2-i+1.

[0065] In the scanning process t3 of the i+2th circuit row 2-i+2: in the first sub-period, the control line mux-2 maintains to provide the second effective level 9, and the data voltage vA in the source signal line source is written into the pixel circuit 1-A in the i+2th circuit row 2; in the second sub-period, the control line mux-3 provides the third effective level 10, and the data voltage vB in the source signal line source is written into the pixel circuit 1-B in the i+2th circuit row 2; in the third sub-period, the control line mux-1 provides the first effective level 7, and the data voltage vC in the source signal line source is written into the pixel circuit 1-C in the i+2th circuit row 2.

[0066] In the scanning process t4 of the i+3th circuit row 2-i+3, in the first sub-period, the control line mux-1 maintains to provide the first effective level 7, and the data voltage vF in the source signal line source is written into the pixel circuit 1-F in the i+3th circuit row 2-i+3; in the second sub-period, the control line mux-3 provides the fourth effective level 11, and the data voltage vE in the source signal line source is written into the pixel circuit 1-E in the i+3th circuit row 2-i+3; in the third sub-period, the control line mux-2 provides the first effective level 7, and the data voltage vD transmitted in the source signal line source is written into the pixel circuit 1-D in the i+3th circuit row 2-i+3.

[0067] In summary, based on the above driving method, during the driving process of the display panel, the order of sending images to the pixel circuit 1 is "1-A, 1-B, 1-C, 1-F, 1-E, 1-D, 1-A, 1-B, 1-C, 1-F, 1-E, 1-D, 1-A, 1-B, 1-C, 1-F, 1-E, 1-D...", Figure 5 The bold black lines in the figure are used to reflect the image transmission sequence. In the image transmission process of pixel circuit 1-C and pixel circuit 1-F, the signal provided by control line mux-1 (first control line mux (1)) does not need to undergo voltage jumps, and the number of voltage jumps in the signal is reduced. At the same time, in the image transmission process of pixel circuit 1-D and pixel circuit 1-A, the signal provided by control line mux-2 (second control line mux (2)) does not need to undergo voltage jumps, and the number of voltage jumps in the signal is also reduced.

[0068] In a panel architecture where the gating unit 3 includes at least three switches 4, the above driving method can reduce the voltage jump frequency in the signals provided by two of the control lines mux, thereby significantly saving the power consumption generated by the gating unit 3 during operation.

[0069] Furthermore, the time during which the source signal line source transmits the data voltage required by the pixel circuit 1 connected to the first data line Data (1) is longer than the time during which the source signal line source transmits the data voltage required by the pixel circuit 1 connected to the third data line Data (3); and / or the time during which the source signal line source transmits the data voltage required by the pixel circuit 1 connected to the second data line Data (2) is longer than the time during which the source signal line source transmits the data voltage required by the pixel circuit 1 connected to the third data line Data (3).

[0070] For example, Figure 7 Another timing diagram provided by an embodiment of the present invention is as follows: Figure 7 As shown, the time when the source signal line source transmits the data voltage required by the pixel circuit 1 connected to the first data line Data (1) is k1, that is, the time when the source signal line source transmits the data voltage vC and the data voltage vF is k1.

[0071] The time during which the data voltage required by the pixel circuit 1 connected to the second data line Data (2) is transmitted in the source signal line source is also k1, that is, the time during which the data voltage vD and the data voltage vA are transmitted in the source signal line source is k1.

[0072] The time during which the source signal line source transmits the data voltage required by the pixel circuit 1 connected to the third data line Data (3) is k2, that is, the time during which the source signal line source transmits the data voltage vB and the data voltage vE is k2.

[0073] Among them, k1>k2.

[0074] The duration of a single first effective level 7 is longer than the total duration of the two third effective levels 10 and the fourth effective level 11, thereby increasing the time for the source signal line source to transmit the data voltage required by the pixel circuit 1 connected to the first data line Data (1), thereby allowing the data voltage in the source signal line source to still be written into the first data line Data (1) within the extra duration, thereby improving the charging effect of the first data line Data (1).

[0075] Similarly, the duration of a single second effective level 9 is longer than the total duration of the two third effective levels 10 and the fourth effective level 11. Therefore, the time for transmitting the data voltage required by the pixel circuit 1 connected to the second data line Data (2) in the source signal line source can also be increased, and the data voltage in the source signal line source can still be written into the second data line Data (2) during the extra duration, thereby improving the charging effect of the second data line Data (2).

[0076] See again Figure 4 In a feasible implementation, the time interval Δt between two adjacent valid levels provided by different control lines mux is greater than 0.2 μs, so that a sufficient time interval is provided between the source signal line source and the connection paths established between different data lines Data, thereby improving the accuracy of the signal written on the data line Data.

[0077] Figure 8 Another timing diagram provided by an embodiment of the present invention, in a feasible implementation manner, combined with Figure 3 and Figure 8 , the moment p1 at which the source signal line source starts transmitting the first data voltage is earlier than the moment p2 at which the first control line mux (1) starts providing the first effective level 7; the first data voltage is the data voltage required by the pixel circuit 1 connected to the first data line Data (1) in the first circuit row 5. And / or, the moment p3 at which the source signal line source stops transmitting the second data voltage is later than the moment p4 at which the first control line mux (1) stops providing the first effective level 7; the second data voltage is the data voltage required by the pixel circuit 1 connected to the first data line Data (1) in the second circuit row 6.

[0078] For example, based on Figure 3 The first data voltage includes a data voltage v2, and the second data voltage includes a data voltage v4.

[0079] Based on the above design, before the first control line mux (1) starts to provide the first effective level 7, the source signal line source is controlled to start transmitting the first data voltage, and then after the first control line mux (1) controls the corresponding switch 4 to be turned on, the first data voltage in the source signal line source can be written to the first data line Data (1) more quickly, so that the first data line Data (1) can be charged more fully during the scanning process of the first circuit row 5. And / or, after the first control line mux (1) stops providing the first effective level 7, that is, after the first control line mux (1) controls the corresponding switch 4 to be turned off, the source signal line source is controlled to stop transmitting the first data voltage, so that the first data line Data (1) can be charged more fully during the scanning process of the second circuit row 6.

[0080] Similarly, in order to improve the charging effect of the second data line Data (2), combined with Figure 3 and Figure 7, the moment p5 at which the source signal line source starts transmitting the third data voltage is earlier than the moment p6 at which the second control line mux (2) starts providing the second effective level 9; the third data voltage is the data voltage required by the pixel circuit 1 connected to the second data line Data (2) in the second circuit row 6. And / or, the moment p7 at which the source signal line source stops transmitting the fourth data voltage is later than the moment p8 at which the second control line mux (2) stops providing the first effective level 7; the fourth data voltage is the data voltage required by the pixel circuit 1 connected to the second data line Data (2) in the first circuit row 5.

[0081] For example, based on Figure 3 The third data voltage includes the data voltage v3, and the fourth data voltage includes the data voltage v1.

[0082] Combine Figure 3 and Figure 8 In a feasible embodiment, the moment h1 at which the source signal line source stops transmitting the first data voltage is later than the moment h2 at which the first circuit row 5 stops scanning; the first data voltage is the data voltage required by the pixel circuit 1 connected to the first data line Data (1) in the first circuit row 5. And / or, the moment h3 at which the source signal line source starts transmitting the second data voltage is earlier than the moment h4 at which the second circuit row 6 starts scanning; the second data voltage is the data voltage required by the pixel circuit 1 connected to the first data line Data (1) in the second circuit row 6.

[0083] For example, based on Figure 3 The first data voltage includes a data voltage v2, and the second data voltage includes a data voltage v4.

[0084] In the above design, after the first circuit row 5 stops scanning, the source signal line source is controlled to stop transmitting the first data voltage, which can improve the charging sufficiency of the pixel circuits 1 connected to the first data line Data (1) in the first circuit row 5. And / or, before the second circuit row 6 starts scanning, the source signal line source is controlled to start transmitting the second data voltage, and then after the second circuit row 6 starts scanning, the second data voltage in the source signal line source can be quickly written into the pixel circuit 1, thereby improving the charging sufficiency of the pixel circuits 1 connected to the first data line Data (1) in the second circuit row 6.

[0085] Similarly, to improve the charging effect of the pixel circuits 1 connected to the second data line Data (2), the moment h4 at which the source signal line source stops transmitting the third data voltage is later than the moment h5 at which the first circuit row 5 stops scanning; the third data voltage is the data voltage required by the pixel circuits 1 connected to the second data line Data (2) in the second circuit row 6. And / or, the moment h7 at which the source signal line source starts transmitting the fourth data voltage is earlier than the moment h8 at which the second circuit row 6 starts scanning; the fourth data voltage is the data voltage required by the pixel circuits 1 connected to the second data line Data (2) in the first circuit row 5.

[0086] For example, based on Figure 3 The first data voltage includes a data voltage v2, and the second data voltage includes a data voltage v4.

[0087] In a feasible embodiment, the display panel further includes a green light emitting element, and the pixel circuit 1 connected to the first data line Data (1) is also electrically connected to the green light emitting element.

[0088] Exemplary, participating Figure 3 The pixel circuit 1 includes a first pixel circuit 20 electrically connected to the red light emitting element, a second pixel circuit 30 electrically connected to the green light emitting element, and a third pixel circuit 40 electrically connected to the blue light emitting element.

[0089] The display panel includes first circuit columns 50 and second circuit columns 60 alternately arranged along a second direction y. The first circuit columns 50 include first pixel circuits 20 and third pixel circuits 40 alternately arranged along a first direction x. The second circuit columns 60 include a plurality of second pixel circuits 30 arranged along the first direction x. In two adjacent first circuit columns 50, the first pixel circuits 20 in one first circuit column 50 are aligned with the third pixel circuits 40 in the other first circuit column 50 in the second direction y.

[0090] The first data line Data (1) is electrically connected to the second circuit column 60, and the second data line Data (2) is electrically connected to the first circuit column 50.

[0091] in, Figure 9 Another timing diagram provided by an embodiment of the present invention is as follows: Figure 9 As shown, the time k3 for transmitting the data voltage required for the pixel circuit 1 connected to the first data line Data (1) in the source signal line source is greater than the time k4 for transmitting the data voltage required for the pixel circuit 1 connected to other data lines Data in the source signal line source.

[0092] The brightness of the green sub-pixel contributes more to the brightness of the screen. Therefore, when the first data line Data (1) is connected to the green sub-pixel, the time for transmitting the data voltage required for the green sub-pixel in the source signal line source can be set to be longer to improve the charging sufficiency of the green sub-pixel.

[0093] Figure 10 Another timing diagram provided by an embodiment of the present invention, in a feasible implementation manner, combined with Figure 3 and Figure 10 The control line mux further includes a second control line mux (2), the data line Data includes a second data line Data (2), and the second control line mux (2) and the second data line Data (2) are connected to the same switch 4.

[0094] The effective levels provided by the second control line mux (2) include an interval of a fifth effective level 12 and a sixth effective level 13. The coverage time of the fifth effective level 12 overlaps with the scanning time of a first circuit row 5. During the process of the second control line mux (2) providing the fifth effective level 12, the source signal line source writes the data voltage required by the pixel circuit 1 in the first circuit row 5 to the second data line Data (2). The coverage time of the sixth effective level 13 overlaps with the scanning time of a second circuit row 6. During the process of the second control line mux (2) providing the sixth effective level 13, the source signal line source writes the data voltage required by the pixel circuit 1 in the second circuit row 6 to the second data line Data (2).

[0095] This design makes a differentiated design for the timing of the first control line mux (1) and the second control line mux (2). In the process of sending the image to the pixel circuit 1-3 in the second circuit row 6 and the pixel circuit 1-1 in the first circuit row 5, the second control line mux (2) is not made to provide a continuous valid level, but is made to provide two intervals of the fifth valid level 12 and the sixth valid level 13. In this way, the connection path between the source signal line source and the second data line Data (2) can be cut off after the source signal line source stops transmitting the data voltage v3 and before it starts transmitting the data voltage v1, thereby avoiding the charging interference of the second data line Data (2) when the second circuit row 6 and the first circuit row 5 are scanned. For example, see Figure 3 The second data line Data (2) is connected to the first pixel circuit 20 and the third pixel circuit 40. The first pixel circuit 20 and the third pixel circuit 40 correspond to sub-pixels of different colors respectively. The luminescence difference between sub-pixels of different colors may be large. Therefore, the second control line mux (2) adopts this timing design to avoid luminescence crosstalk between sub-pixels of different colors caused by charging interference of the second data line Data.

[0096] Based on the same inventive concept, an embodiment of the present invention provides a display panel. Figure 3 and Figure 4 The display panel includes a plurality of pixel circuits 1, which are electrically connected to the first scan line S1 and the data line Data, respectively. The pixel circuits 1 are configured to perform a data writing operation under the scanning action of the first scan line S1.

[0097] The display panel further includes a plurality of circuit rows 2 arranged along a first direction x. The circuit rows 2 include a plurality of pixel circuits 1 arranged along a second direction y. The first direction x intersects the second direction y.

[0098] The display panel further includes a plurality of gating units 3, each including at least two switches 4. In the gating unit 3, input ends of at least two switches 4 are electrically connected to the same source signal line source, control ends of at least two switches 4 are electrically connected to at least two control lines mux, and output ends of at least two switches 4 are electrically connected to at least two data lines Data.

[0099] The circuit row 2 includes an adjacent first circuit row 5 and a second circuit row 6, the control line mux includes a first control line mux (1), the data line Data includes a first data line Data (1), and the first control line mux (1) and the first data line Data (1) are connected to the same switch 4.

[0100] The first control line mux (1) is used to provide a first effective level 7, and the coverage time of the first effective level 7 overlaps with the scanning time of a first circuit row 5 and a second circuit row 6. In the process of the first control line mux (1) providing the first effective level 7, the source signal line source writes the data voltage required by the pixel circuit 1 in the first circuit row 5 to the first data line Data (1) during the scanning time of the first circuit row 5, and writes the data voltage required by the pixel circuit 1 in the second circuit row 6 to the first data line Data (1) during the scanning time of the second circuit row 6.

[0101] Combined with the above analysis, it can be seen that when the display panel provided by the embodiment of the present invention is used, the number of voltage jumps in the signal provided by the first control line mux (1) corresponding to the gating unit 3 is reduced during its operation, thereby effectively saving the power consumption generated by the gating unit 3 during its operation, thereby reducing the power consumption of the panel.

[0102] See again Figure 3 and Figure 4 In a feasible implementation manner, the first circuit rows 5 and the second circuit rows 6 are arranged alternately.

[0103] The display panel includes a plurality of circuit groups 8 arranged along a first direction x, and the circuit rows 2 include a first circuit row 5 and a second circuit row 6 arranged along a second direction y. The coverage time of a first active level 7 overlaps with the scanning time of the first circuit row 5 and the second circuit row 6 in the same circuit group 8.

[0104] The control line mux further includes a second control line mux (2), and the data line Data includes a second data line Data (2). The second control line mux (2) and the second data line Data (2) are connected to the same switch 4. The effective level provided by the second control line mux (2) includes a second effective level 9, and the coverage time of the second effective level 9 overlaps with the scanning time of the second circuit row 6 in the previous circuit group 8 and the first circuit row 5 in the next circuit group 8 in the two adjacent circuit groups 8; in the process of the second control line mux (2) providing the second effective level 9, the source signal line source writes the data voltage required by the pixel circuit 1 in the first circuit row 5 to the second data line Data (2) during the scanning time of the first circuit row 5, and writes the data voltage required by the pixel circuit 1 in the second circuit row 6 to the second data line Data (2) during the scanning time of the second circuit row 6.

[0105] The working process of the above structure has been described in the previous embodiment and will not be repeated here. In this structure, the signals provided by the first control line mux (1) and the second control line mux (2) are periodic. Compared with the related art, the number of voltage jumps in the signals provided by the first control line mux (1) and the second control line mux (2) is reduced by half, thereby saving more power consumption.

[0106] See again Figure 3 Furthermore, the pixel circuit 1 includes a first pixel circuit 20 , a second pixel circuit 30 and a third pixel circuit 40 .

[0107] The display panel further includes first circuit columns 50 and second circuit columns 60 alternately arranged along the second direction y. The first circuit columns 50 include first pixel circuits 20 and third pixel circuits 40 alternately arranged along the first direction x. The second circuit columns 60 include multiple second pixel circuits 30 arranged along the first direction x.

[0108] The first data line Data (1) is electrically connected to the second circuit column 60, and the second data line Data (2) is electrically connected to the first circuit column 50.

[0109] This structure adopts a design in which the gating unit 3 includes only two switches 4. Accordingly, the display panel includes two control line muxes, one of which is a first control line mux (1) and the other is a second control line mux (2). The voltage jump frequency of the signals provided by the two control line muxes can be reduced to half, thereby significantly saving the power consumption generated by the gating unit 3 during operation.

[0110] See again Figure 5 and Figure 6 In a feasible embodiment, the control line mux further includes a third control line mux (3), the data line Data includes a third data line Data (3), the third control line mux (3) and the third data line Data (3) are connected to the same switch 4, and along the second direction y, the pixel circuit 1 connected to the third data line Data (3) is located between the pixel circuit 1 connected to the first data line Data (1) and the second data line Data (2).

[0111] The effective level provided by the third control line mux (3) includes an interval of a third effective level 10 and a fourth effective level 11, and the covering time of the third effective level 10 and the fourth effective level 11 is separated by a covering time of a first effective level 7 or a covering time of a second effective level 9. The covering time of a third effective level 10 overlaps with a scanning time of a first circuit row 5, and in the process of the third control line mux (3) providing the third effective level 10, the source signal line source writes the data voltage required by the pixel circuit 1 in the first circuit row 5 to the third data line Data (3); the covering time of a fourth effective level 11 overlaps with a scanning time of a second circuit row 6, and in the process of the third control line mux (3) providing the fourth effective level 11, the source signal line source writes the data voltage required by the pixel circuit 1 in the second circuit row 6 to the third data line Data (3).

[0112] This structure adopts a design in which the gating unit 3 includes at least three switches 4. Accordingly, the display panel includes at least three control lines mux, one of which is a first control line mux (1), another is a second control line mux (2), and the remaining at least one is a third control line mux (3). The voltage jump frequency of the signals provided by the first control line mux (1) and the second control line mux (2) can be reduced to half, thereby significantly saving the power consumption generated by the gating unit 3 during operation.

[0113] See again Figure 5 Furthermore, the pixel circuit 1 includes a first pixel circuit 20 , a second pixel circuit 30 and a third pixel circuit 40 .

[0114] The display panel also includes a first circuit column 50, a second circuit column 60 and a third circuit column 70 arranged alternately along the second direction y, the first circuit column 50 includes a plurality of first pixel circuits 20 arranged along the first direction x, the second circuit column 60 includes a plurality of second pixel circuits 30 arranged along the first direction x, and the third circuit column 70 includes a plurality of third pixel circuits 40 arranged along the first direction x.

[0115] The first data line Data (1) is electrically connected to the third circuit column 70, the second data line Data (2) is electrically connected to the first circuit column 50, and the third data line Data (3) is electrically connected to the second circuit column 60.

[0116] This structure adopts a design in which the selection unit 3 includes three switches 4. Accordingly, the display panel includes at least three control line muxes, wherein the voltage jump frequency of the signals provided by two control line muxes can be reduced to half, and only the voltage jump frequency of the signal provided by one control line mux remains the original design, which has a more significant effect on reducing power consumption.

[0117] It should be noted that, in an embodiment of the present invention, the gating unit 3 may further include four or more switches 4. For example, each gating unit 3 includes four switches 4, and the four switches 4 are electrically connected to the data lines corresponding to four consecutive first circuit columns 50 and second circuit columns 60, respectively. The working mode of the gating unit under this architecture is similar to the working mode of the gating unit in the aforementioned embodiment, and will not be repeated here.

[0118] The following combination Figure 11 and Figure 12 , the structure and working process of the pixel circuit 1 are described, and then the function of the first scanning line S1 is explained.

[0119] Figure 11 A schematic structural diagram of a pixel circuit 1 provided in an embodiment of the present invention is shown in FIG. Figure 12 Another timing diagram provided by an embodiment of the present invention is as follows: Figure 11 and Figure 12 As shown, the pixel circuit 1 may specifically include: Drive transistor M0.

[0120] The first reset transistor M1 has a gate electrically connected to the second scan line S2 , a first electrode electrically connected to the first reset line Ref1 , and a second electrode electrically connected to the gate of the driving transistor M0 .

[0121] The data writing transistor M2 has a gate electrically connected to the first scan line S1 , a first electrode electrically connected to the data line Data, and a second electrode electrically connected to the first electrode of the driving transistor M0 .

[0122] The threshold compensation transistor M3 has a gate electrically connected to the first scan line S1 , a first electrode electrically connected to the second electrode of the driving transistor M0 , and a second electrode electrically connected to the gate of the driving transistor M0 .

[0123] The second reset transistor M4 has a gate electrically connected to the first scan line S1 , a first electrode electrically connected to the first reset line Ref2 , and a second electrode electrically connected to the light emitting element 80 .

[0124] The first light emitting control transistor M5 has a gate electrically connected to the light emitting control scanning line Emit, a first electrode electrically connected to the power line PVDD, and a second electrode electrically connected to the first electrode of the driving transistor M0.

[0125] The first light emitting control transistor M6 has a gate electrically connected to the light emitting control scanning line Emit, a first electrode electrically connected to the second electrode of the driving transistor M0 , and a second electrode electrically connected to the light emitting element 80 .

[0126] The storage capacitor Cst is connected between the power line PVDD and the gate of the driving transistor M0 .

[0127] The working process of the pixel circuit 1 includes: During the initialization period t11 , the second scan line S2 provides an active level, the first reset transistor M1 is turned on, and the first reset voltage is written into the gate of the driving transistor M0 , and the pixel circuit 1 performs an initialization operation.

[0128] During the charging period t22, the first scan line S1 provides a valid level, the data writing transistor M2 and the threshold compensation transistor M3 are turned on, the data voltage is written to the gate of the driving transistor M0, and the pixel circuit 1 performs data writing and threshold compensation operations; at the same time, the second reset transistor M4 is turned on, and the second reset voltage is written to the light-emitting element 80 to reset the anode of the light-emitting element 80.

[0129] During the light emitting period t33, the light emitting control scanning line Emit provides an effective level, the first light emitting control transistor M5 and the second light emitting control transistor M6 are turned on, and the driving current converted by the driving transistor M0 is written into the light emitting element 80, driving the light emitting element 80 to emit light.

[0130] Based on the same inventive concept, an embodiment of the present invention further provides a display device, such as Figure 13 As shown, Figure 13 1 is a schematic structural diagram of a display device provided by an embodiment of the present invention, the display device includes the above-mentioned display panel 100. Of course, Figure 13 The display device shown is for illustrative purposes only. The display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e-reader, or a television.

[0131] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0132] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for driving a display panel, characterized in that: The display panel includes: a plurality of pixel circuits, wherein the pixel circuits are electrically connected to the first scan line and the data line respectively; a plurality of circuit rows arranged along a first direction, the circuit rows comprising a plurality of the pixel circuits arranged along a second direction, the first direction intersecting the second direction; a plurality of gating units, each of the gating units comprising at least two switches; in each of the gating units, input terminals of at least two of the switches are electrically connected to the same source signal line, control terminals of at least two of the switches are electrically connected to at least two control lines, and output terminals of at least two of the switches are electrically connected to at least two data lines; The circuit rows include adjacent first and second circuit rows, the control lines include first control lines, the data lines include first data lines, and the first control lines and the first data lines are connected to the same switch; The driving method includes: controlling the first scanning line to scan the plurality of circuit rows row by row, driving the pixel circuits in the circuit rows to perform a data writing operation; during the scanning process of the circuit rows, at least two of the control lines provide an effective voltage in a time-sharing manner, controlling at least two of the switches in the gating unit to be turned on in a time-sharing manner, so that the data voltage in the source signal line is written into the corresponding data line; wherein the valid level provided by the first control line comprises a first valid level, and a coverage time of the first valid level overlaps with a scan time of a first circuit row and a second circuit row; During the process of the first control line providing the first effective level, the source signal line writes the data voltage required for the pixel circuit in the first circuit row to the first data line during the scanning time of the first circuit row, and writes the data voltage required for the pixel circuit in the second circuit row to the first data line during the scanning time of the second circuit row.

2. The method for driving a display panel according to claim 1, wherein: The first circuit rows and the second circuit rows are arranged alternately; The display panel includes a plurality of circuit groups arranged along the first direction, and the circuit rows include a first circuit row and a second circuit row arranged along the second direction; The signal provided by the first control line includes the first active level and the inactive level alternately, and the coverage time of one first active level overlaps with the scanning time of the first circuit row and the second circuit row in the same circuit group.

3. The method for driving a display panel according to claim 2, wherein: The control line further includes a second control line, the data line includes a second data line, and the second control line and the second data line are connected to the same switch; The active level provided by the second control line includes a second active level, and the coverage time of the second active level overlaps with the scanning time of the second circuit row in the first circuit group and the first circuit row in the second circuit group in two adjacent circuit groups; During the process of the second control line providing the second effective level, the source signal line writes the data voltage required for the pixel circuit in the first circuit row to the second data line during the scanning time of the first circuit row, and writes the data voltage required for the pixel circuit in the second circuit row to the second data line during the scanning time of the second circuit row.

4. The method for driving a display panel according to claim 3, wherein: The duration of the first effective level is equal to the duration of the second effective level.

5. The method for driving a display panel according to claim 3, wherein: The control line further includes a third control line, and the data line includes a third data line. The third control line and the third data line are connected to the same switch. Along the second direction, the pixel circuit connected to the third data line is located between the pixel circuits connected to the first data line and the second data line. The valid levels provided by the third control line include a third valid level and a fourth valid level that are spaced apart, and the coverage time of the third valid level and the fourth valid level is separated by a coverage time of the first valid level or a coverage time of the second valid level; The covering time of the third effective level overlaps with the scanning time of the first circuit row, and during the process of the third control line providing the third effective level, the source signal line writes the data voltage required by the pixel circuit in the first circuit row into the third data line; The covering time of the fourth effective level overlaps with the scanning time of the second circuit row. During the process of the third control line providing the fourth effective level, the source signal line writes the data voltage required by the pixel circuit in the second circuit row to the third data line.

6. The method for driving a display panel according to claim 5, wherein: The time during which the data voltage required by the pixel circuit connected to the first data line is transmitted in the source signal line is longer than the time during which the data voltage required by the pixel circuit connected to the third data line is transmitted in the source signal line; And / or, the time during which the data voltage required for the pixel circuit connected to the second data line is transmitted in the source signal line is greater than the time during which the data voltage required for the pixel circuit connected to the third data line is transmitted in the source signal line.

7. The method for driving a display panel according to claim 1, wherein: The time interval between two adjacent valid levels provided by different control lines is greater than 0.2 μs.

8. The method for driving a display panel according to claim 1, wherein: The source signal line starts transmitting a first data voltage earlier than the first control line starts providing the first active level, the first data voltage being a data voltage required by the pixel circuits connected to the first data line in the first circuit row; And / or, the source signal line stops transmitting the second data voltage later than the first control line stops providing the first valid level, and the second data voltage is the data voltage required by the pixel circuit connected to the first data line in the second circuit row.

9. The method for driving a display panel according to claim 1, wherein: The source signal line stops transmitting the first data voltage later than the first circuit row stops scanning, and the first data voltage is the data voltage required by the pixel circuit connected to the first data line in the first circuit row; And / or, the source signal line starts transmitting the second data voltage earlier than the second circuit row starts scanning, and the second data voltage is the data voltage required by the pixel circuit connected to the first data line in the second circuit row.

10. The method for driving a display panel according to claim 1, wherein: The display panel further includes a green light emitting element, and the pixel circuit connected to the first data line is also electrically connected to the green light emitting element; The time required for the source signal line to transmit the data voltage required for the pixel circuit connected to the first data line is longer than the time required for the source signal line to transmit the data voltage required for the pixel circuits connected to other data lines.

11. The method for driving a display panel according to claim 2, wherein: The control line further includes a second control line, the data line includes a second data line, and the second control line and the second data line are connected to the same switch; The active levels provided by the second control line include a fifth active level and a sixth active level that are spaced apart; The covering time of the fifth effective level overlaps with the scanning time of the first circuit row, and during the process of the second control line providing the fifth effective level, the source signal line writes the data voltage required by the pixel circuit in the first circuit row into the second data line; The covering time of the sixth effective level overlaps with the scanning time of the second circuit row. During the process of the second control line providing the sixth effective level, the source signal line writes the data voltage required by the pixel circuit in the second circuit row to the second data line.

12. A display panel, characterized in that: include: a plurality of pixel circuits, each of which is electrically connected to a first scan line and a data line, and configured to perform a data writing operation under the scanning action of the first scan line; a plurality of circuit rows arranged along a first direction, the circuit rows comprising a plurality of the pixel circuits arranged along a second direction, the first direction intersecting the second direction; a plurality of gating units, each of the gating units comprising at least two switches; in each of the gating units, input terminals of at least two of the switches are electrically connected to the same source signal line, control terminals of at least two of the switches are electrically connected to at least two control lines, and output terminals of at least two of the switches are electrically connected to at least two data lines; The circuit rows include adjacent first and second circuit rows, the control lines include first control lines, the data lines include first data lines, and the first control lines and the first data lines are connected to the same switch; The first control line is used to provide a first effective level, and the coverage time of the first effective level overlaps with the scanning time of a first circuit row and a second circuit row at the same time; in the process of the first control line providing the first effective level, the source signal line writes the data voltage required by the pixel circuit in the first circuit row to the first data line during the scanning time of the first circuit row, and writes the data voltage required by the pixel circuit in the second circuit row to the first data line during the scanning time of the second circuit row.

13. The display panel according to claim 12, wherein: The first circuit rows and the second circuit rows are arranged alternately; The display panel includes a plurality of circuit groups arranged along the first direction, and the circuit rows include a first circuit row and a second circuit row arranged along the second direction; wherein a coverage time of the first effective level overlaps with a scanning time of the first circuit row and the second circuit row in the same circuit group; The control line further includes a second control line, the data line includes a second data line, and the second control line and the second data line are connected to the same switch; The effective level provided by the second control line includes a second effective level, and the coverage time of the second effective level overlaps with the scanning time of the second circuit row in the first circuit group and the first circuit row in the second circuit group in the second adjacent circuit groups; in the process of the second control line providing the second effective level, the source signal line writes the data voltage required for the pixel circuit in the first circuit row to the second data line during the scanning time of the first circuit row, and writes the data voltage required for the pixel circuit in the second circuit row to the second data line during the scanning time of the second circuit row.

14. The display panel according to claim 13, wherein: The pixel circuit includes a first pixel circuit, a second pixel circuit and a third pixel circuit; The display panel further includes a first circuit column and a second circuit column alternately arranged along the second direction, the first circuit column including the first pixel circuits and the third pixel circuits alternately arranged along the first direction, and the second circuit column including a plurality of the second pixel circuits arranged along the first direction; The first data line is electrically connected to the second circuit column, and the second data line is electrically connected to the first circuit column.

15. The display panel according to claim 13, wherein: The control line further includes a third control line, and the data line includes a third data line. The third control line and the third data line are connected to the same switch. Along the second direction, the pixel circuit connected to the third data line is located between the pixel circuits connected to the first data line and the second data line. The active levels provided by the third control line include a third active level and a fourth active level that are spaced apart, and the covering time of the third active level and the fourth active level is separated by a covering time of the first active level or a covering time of the second active level; a covering time of the third active level overlaps with a scanning time of the first circuit row, and during the process of the third control line providing the third active level, the source signal line writes the data voltage required by the pixel circuit in the first circuit row into the third data line; The covering time of the fourth effective level overlaps with the scanning time of the second circuit row. During the process of the third control line providing the fourth effective level, the source signal line writes the data voltage required by the pixel circuit in the second circuit row to the third data line.

16. The display panel according to claim 15, wherein: The pixel circuit includes a first pixel circuit, a second pixel circuit and a third pixel circuit; The display panel further includes a first circuit column, a second circuit column, and a third circuit column alternately arranged along the second direction, the first circuit column including a plurality of the first pixel circuits arranged along the first direction, the second circuit column including a plurality of the second pixel circuits arranged along the first direction, and the third circuit column including a plurality of the third pixel circuits arranged along the first direction; The first data line is electrically connected to the third circuit column, the second data line is electrically connected to the first circuit column, and the third data line is electrically connected to the second circuit column.

17. A display device, characterized in that: Comprising the display panel according to any one of claims 12 to 16.

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