A data packet receiving method, a data processing unit, a host and a network card

Abstract

This application relates to a data packet receiving method, a data processing unit, a host, and a network interface card (NIC), comprising: when data packets need to be received, the host prepares an idle buffer unit and generates a first buffer descriptor; when the data processing unit receives a data packet (network small packet), it writes it into the local buffer unit according to the buffer line alignment principle to form an aggregated data packet, and writes the aggregated data packet into the host-side buffer unit according to the first buffer descriptor, and sends a completion descriptor to the host; the host can parse the aggregated data packet according to the content of the completion descriptor to obtain the individual network small packets. This application, by aggregating multiple network small packets into a larger aggregated data packet, reduces the number of PCIe writes, improves bandwidth utilization, and reduces buffer unit occupation, thereby improving resource utilization, while maintaining compatibility with the existing Virtio protocol.

Description

Technical Field

[0001] This application relates to the field of network data transmission technology, specifically to a data packet receiving method, a data processing unit, a host, a network interface card (NIC), and a computer program product. Background Technology

[0002] Network packets are small data packets in network transmission. When receiving network packets based on the traditional virtio virtualization protocol, each time a virtio network device receives a network packet, it needs to write the received network packet to the host-side buffer via PCIe (Peripheral Component Interconnect Express) and notify the host software. However, because the data volume of network packets is small, only a small amount of data is written each time, resulting in very low bandwidth utilization of PCIe. At the same time, each network packet occupies one host-side buffer, resulting in very low resource utilization of the host-side buffer. Summary of the Invention

[0003] The purpose of this application is to provide a data packet receiving method, a data processing unit, a host, a network card, and a computer program product to improve the bandwidth utilization of PCIe for receiving network packets based on the virtio virtualization protocol and the resource utilization of the host-side cache unit.

[0004] To achieve the above objectives, according to a first aspect of this application, a data packet receiving method is provided, the method comprising:

[0005] Receive the reception notification sent by the host and obtain the index of the first cache descriptor;

[0006] The first cache descriptor is read from the first descriptor table on the host side according to the first cache descriptor index; the first cache descriptor includes at least the address of the cache unit on the host side and the length of the cache unit;

[0007] Upon receiving data packets, data packets (network small packets) from the same queue are written into the local cache unit according to the cache line alignment principle to form aggregated data packets;

[0008] The aggregated data packet is written to the cache unit on the host side according to the address of the cache unit;

[0009] A completion descriptor is generated based on the aggregated data packet, and the completion descriptor is sent to the host; the completion descriptor includes at least an aggregation identifier and the actual length of each data packet in the aggregated data packet, the aggregation identifier is used to indicate that the data packet written to the host side is an aggregated data packet, and the aggregated data packet includes at least two data packets;

[0010] The host is notified that the aggregated data packet has been written to the host-side cache unit.

[0011] The method provided in the first aspect of this application involves a data processing unit writing multiple network packets into a local cache unit according to the cache line alignment principle to form an aggregated data packet. Then, the aggregated data packet is written to the host-side cache unit through a single PCIe write operation. While maintaining compatibility with the existing Virtio protocol, the increased data volume per write reduces the number of PCIe write operations, avoiding bandwidth waste caused by frequent small data writes, and significantly improving PCIe bandwidth utilization. Moreover, in the traditional method, each network packet requires a host-side cache unit, resulting in low cache unit resource utilization. However, the method provided in the first aspect of this application aggregates multiple network packets and writes them into the same cache unit, greatly reducing the number of cache units occupied and improving the resource utilization of the cache units.

[0012] Optionally, generating a completion descriptor based on the aggregated data packet includes:

[0013] A first completion descriptor and a second completion descriptor are generated based on the aggregated data packet; the first completion descriptor includes the aggregate identifier, and the second completion descriptor includes the actual length of each data packet in the aggregated data packet;

[0014] Write the first completion descriptor into the first descriptor cache unit on the host side;

[0015] The second completion descriptor is written into the second descriptor cache unit on the host side.

[0016] Optionally, the first completion descriptor may also include the actual length of the aggregated data packet.

[0017] Optionally, writing the first completion descriptor into the first descriptor cache unit on the host side specifically includes:

[0018] Write the first completed descriptor into the descriptor entry corresponding to the first cached descriptor index in the first descriptor table to replace the first cached descriptor;

[0019] The step of writing the second completion descriptor into the second descriptor cache unit on the host side includes:

[0020] The second completion descriptor is written into the descriptor entry in the second descriptor table on the host side that corresponds to the first cached descriptor index; wherein, both the first descriptor table and the second descriptor table include multiple descriptor entries, and the multiple descriptor entries in the first descriptor table correspond one-to-one with the cached descriptor indices of the multiple descriptor entries in the second descriptor table.

[0021] Optionally, the second completion descriptor includes a pattern field and multiple length fields of the same bit width, wherein the pattern field contains the maximum length of the data packet, and the multiple length fields of the same bit width each contain the actual length of each data packet in the aggregated data packet.

[0022] Optionally, writing the aggregated data packet into the cache unit on the host side specifically includes:

[0023] If the length of the aggregated data packet reaches the PCIe bandwidth within a set waiting time, the aggregated data packet will be written into the cache unit on the host side; or, the aggregated data packet will be written into the cache unit on the host side when the set waiting time is reached.

[0024] According to a second aspect of this application, a data packet receiving method is provided, the method comprising:

[0025] When a data packet needs to be received, an idle host-side buffer unit is obtained, a first buffer descriptor is generated based on the address and length of the host-side buffer unit, and the first buffer descriptor is written into the host-side first descriptor table; wherein, the first buffer descriptor includes the address and length of the host-side buffer unit;

[0026] Send a reception notification to the data processing unit to request the data processing unit to write the received data packets of the target queue into the cache unit on the host side;

[0027] Receive a completion notification from the data processing unit, and obtain the first descriptor index based on the completion notification;

[0028] Obtain the completion descriptor sent by the data processing unit, parse the completion descriptor to obtain the aggregation identifier and the actual length of each data packet (network packet) in the aggregation data packet; wherein, the aggregation identifier is used to indicate that the data packet written to the cache unit on the host side is an aggregation data packet, and the aggregation data packet includes at least two data packets;

[0029] The aggregated data packet is read from the corresponding cache unit on the host side according to the first descriptor index;

[0030] Based on the actual length of each data packet in the aggregated data packet, at least two data packets are extracted from the aggregated data packet according to the cache line alignment principle.

[0031] Specifically, when a data packet needs to be received, the host notifies the data processing unit to receive the data packet. After receiving the notification, when the data processing unit receives a small network packet, it writes multiple small network packets into the local cache unit according to the cache line alignment principle to form an aggregated data packet. Then, it writes the aggregated data packet into the cache unit on the host side through a single PCIe write operation. This aggregated write operation, while being compatible with the existing Virtio protocol, reduces the number of PCIe write operations, significantly improves the bandwidth utilization of PCIe, avoids bandwidth waste caused by frequent small data writes, and at the same time, by aggregating multiple small network packets and writing them into the same cache unit, it greatly reduces the number of cache units occupied and improves the resource utilization of the cache units. After receiving the completion notification from the data processing unit, the host can obtain the aggregated data packet and the actual length of each data packet in the aggregated data packet according to the first descriptor index, and extract each data packet in the aggregated data packet according to the cache line alignment principle, making the data extraction process more efficient and accurate.

[0032] Optionally, the completion descriptor includes a first completion descriptor and a second completion descriptor, wherein the first completion descriptor includes the aggregation identifier and the second completion descriptor includes the actual length of each data packet in the aggregated data packet.

[0033] Optionally, obtaining the completion descriptor sent by the data processing unit and parsing the completion descriptor to obtain the aggregation identifier and the actual length of each data packet in the aggregated data packet includes:

[0034] Obtain the first descriptor index, read the first completion descriptor from the descriptor entry corresponding to the first cached descriptor index in the first descriptor table, and parse the first completion descriptor to obtain the aggregation identifier;

[0035] The second completion descriptor is read from the descriptor entry corresponding to the first cache descriptor index in the second descriptor table on the host side according to the aggregation identifier;

[0036] Both the first descriptor table and the second descriptor table include multiple descriptor entries, and the cached descriptor indices of the multiple descriptor entries in the first descriptor table correspond one-to-one with the cached descriptor indices of the multiple descriptor entries in the second descriptor table.

[0037] Optionally, the second completion descriptor includes a pattern field and multiple length fields of the same bit width, wherein the pattern field contains the maximum length of the data packet, and the multiple length fields of the same bit width each contain the actual length of each data packet in the aggregated data packet.

[0038] Optionally, the first completion descriptor may further include the actual length of the aggregated data packet;

[0039] The method further includes:

[0040] Integrity checks are performed on at least two data packets extracted from the aggregated data packet based on the actual length of the aggregated data packet.

[0041] According to a third aspect of this application, a data processing unit is provided, comprising the following modules for performing the method described in the first aspect:

[0042] The notification receiving module is used to receive notifications sent by the host and obtain the index of the first cache descriptor.

[0043] The descriptor reading module is used to read the first cache descriptor from the first descriptor table on the host side according to the first cache descriptor index; the first cache descriptor includes at least the address of the cache unit on the host side and the length of the cache unit;

[0044] The data packet receiving module is used to receive data packets and write data packets in the same queue into the local cache unit according to the cache line alignment principle to form aggregated data packets;

[0045] A data packet uploading module is used to write the aggregated data packet into the cache unit on the host side according to the address of the cache unit;

[0046] The completion descriptor module is used to generate a completion descriptor based on the aggregated data packet and send the completion descriptor to the host; the completion descriptor includes at least an aggregation identifier and the actual length of each data packet in the aggregated data packet, the aggregation identifier is used to indicate that the data packet written to the host side is an aggregated data packet, and the aggregated data packet includes at least two data packets;

[0047] The notification sending module is used to notify the host that the aggregated data packet has been written to the host-side cache unit.

[0048] According to a fourth aspect of this application, a host is provided, comprising the following modules for performing the method described in the second aspect:

[0049] The descriptor generation module is used to allocate an idle buffer unit when it is necessary to receive a data packet, generate a first buffer descriptor according to the address and length of the idle buffer unit, and write the first buffer descriptor into the first descriptor table on the host side; wherein, the first buffer descriptor includes the address and length of the buffer unit on the host side;

[0050] The notification sending module is used to send a reception notification to the data processing unit to request the data processing unit to write the received data packets of the target queue into the cache unit on the host side.

[0051] The notification receiving module is used to receive the completion descriptor, the completion descriptor index and the completion notification sent by the data processing unit, and to obtain the first descriptor index in response to the completion notification;

[0052] The descriptor reading module is used to obtain the completion descriptor according to the completion descriptor index, and parse the completion descriptor to obtain the aggregation identifier and the actual length of each data packet in the aggregation data packet; wherein, the aggregation identifier is used to indicate that the data packet written to the cache unit on the host side is an aggregation data packet, and the aggregation data packet includes at least two data packets;

[0053] The data packet reading module is used to read aggregated data packets from the corresponding cache unit on the host side according to the completion descriptor index;

[0054] The data packet parsing module is used to extract at least two data packets from the aggregated data packet according to the actual length of each data packet in the aggregated data packet and the cache line alignment principle.

[0055] According to a fifth aspect of this application, a network interface card (NIC) is provided, comprising the data processing unit described in the third aspect and / or the host described in the fourth aspect.

[0056] According to a sixth aspect of this application, a computer program product is provided, including computer program instructions that instruct a computer device to perform an operation corresponding to the method described in the first or second aspect. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings required in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0058] Figure 1 This is a flowchart of a data packet receiving method according to an embodiment of this application.

[0059] Figure 2 This is a schematic diagram of a virtio device based on a DPU to implement a backend device in an embodiment of this application.

[0060] Figure 3 This is a schematic diagram of a typical split mode virtqueue structure in the embodiments of this application.

[0061] Figure 4 This is a schematic diagram of the data processing flow of the Virtio 1.0 virtualization protocol receiving direction in the split mode in the embodiments of this application.

[0062] Figure 5 This is a simplified schematic diagram of the virtio-net receiving network in the embodiments of this application.

[0063] Figure 6 This is a schematic diagram of the data transmission delay model of the Virtio protocol in the receiving direction under the Split mode in this application embodiment.

[0064] Figure 7 This is a schematic diagram of the virtio virtualization protocol receiving direction processing structure of the method in the embodiments of this application.

[0065] Figure 8 This illustrates the correspondence between the pkt len ​​descriptor ring and the descriptor ring in the embodiments of this application.

[0066] Figure 9 This is a schematic diagram of the structure of the newly added length descriptor entry in the embodiments of this application.

[0067] Figure 10 This is a flowchart of another data packet receiving method in the embodiments of this application. Detailed Implementation

[0068] The detailed description of the accompanying drawings is intended to illustrate the present embodiments of this application and is not intended to represent only the forms in which this application can be implemented. It should be understood that the same or equivalent functions can be accomplished by different embodiments intended to be included within the spirit and scope of this application.

[0069] See Figure 1 Embodiment 1 of this application provides a data packet receiving method, applied to the data processing unit (DPU) side. Specifically, as follows: Figure 2 The diagram shows the communication structure between the Data Processing Unit (DPU) and the host in the Vitio protocol split mode implementation. The host's Guest OS (software) allocates an idle buffer, places the address and length of the allocated buffer into the descriptor entry of the first descriptor table, and notifies (kicks) the DPU. The DPU retrieves the idle buffer information from the avring entry and waits to use it. When a data packet is received from a remote device, it needs to be sent by the DPU to the host's idle buffer.

[0070] like Figure 3The diagram shows a typical virtqueue structure in split mode, mainly consisting of three ring structures: a descriptor ring (also known as a descriptor table), an available ring, and a used ring. These rings facilitate data exchange between the DPU and the Host. The functions of each ring are as follows:

[0071] The descriptor ring has a maximum of queue_size (number of queues) entries. Each entry is called a descriptor entry. The host software prepares an idle buffer and fills the descriptor entry with information such as address, length, flag, and next of the idle buffer. This buffer can be used cyclically. Each descriptor entry has its own index (di) to uniquely identify a descriptor entry.

[0072] The available ring has a maximum of `queue_size` entries, each called an avring entry. The descriptor entry ID is filled into the avring's entry field. The DPU hardware can then read this data to retrieve the descriptor entry and, based on the buffer information carried in the descriptor entry, send data packets to that buffer, allowing for cyclical use. Besides the descriptor entry ID, the avring also contains an `idx` field for updating the producer index. This pointer is the host's producer pointer, primarily indicating the number of available ring entries generated. After the host generates the index, it calls the `kick` function to send a Notify to the DPU.

[0073] The used ring has a maximum of `queue_size` entries, each called a usedring entry. After the DPU finishes uploading data, it fills the used descriptor entry ID and the actual data length sent to the Host back into the usedring entry. Then, it updates the consumer index in the usedring idx field and sends an interrupt to the Host. Upon receiving the interrupt, the Host retrieves the position of the usedring entry based on the usedring index. The Host then looks up the descriptor entry ID, locates a specific buffer address, performs the corresponding data processing, and releases the buffer and descriptor entry into the idle queue for future allocation after the Host front-end driver finishes processing the data.

[0074] Virtio currently has four protocol versions: Virtio 0.95, Virtio 1.0, Virtio 1.1, and Virtio 1.2. Virtio 1.0 and later versions introduced the concept of packed queues, which simplifies the ring structure compared to the split mode. The three rings mentioned above are reduced to a single descriptor ring, and the wrap cnt replaces the indication function of the avring and used ring. This can effectively reduce the number of PCIe operations and improve hardware and software performance.

[0075] Figure 4 This is a simplified diagram illustrating the data processing flow of the Virtio 1.0 virtualization protocol in split mode, specifically for the sending direction. Figure 4 The process is described in detail below:

[0076] Step 1: When the host sends out a descriptor entry, the descriptor entry carries information such as the address of the reserved free buffer for the receiving direction, the buffer length, and the buffer ID. When injecting the free buffer, since the actual size of the received packet is unknown, the host typically allocates a fixed-size free buffer to all entries to ensure complete packet reception. The specific free buffer size and descriptor entry chain structure are as follows... Figure 4As shown in the diagram, this illustration illustrates all the allocation modes of the Virtio RX direction idle buffers currently supported by the host. These are mainly categorized into three types: BIG, SMALL, and MERGEABLE. Each category is further divided into different operating systems such as Linux kernel, DPDK, and WINDOWS, resulting in a wide variety of modes. For simplicity, this design will use a single 4KB descriptor entr idle buffer as an example for explanation. Since a typical host does not know the number of subsequent received packets, to ensure sufficient idle buffers for receiving RX direction data, the host generally allocates the largest Queue_size of idle buffers, with a fixed size of 4KB.

[0077] Step 2: Fill the address, length, flag, next and other information of the free buffer into the descriptorentry;

[0078] Step 3: The Host sends a Notification to the DPU, commonly known as the doorbell. At this time, the DPU will read the avring index from the Host side to get the position of the avring entry, and then read the avring entry to parse the index of the descriptorentry.

[0079] Step 4: The DPU reads the descriptor entry from the host to obtain information such as the address and length of the idle buffer, and stores it locally for later use;

[0080] Step 5: When the DPU receives a packet (frame_packet) from the network interface, it will write frame_packet0, ..., frame_packetn into the free buffer allocated in step 4 in sequence;

[0081] Step 6: The DPU writes information such as the buffer ID (identifying a unique buffer) and buffer length into the usedring entry, so that the Host can query the specific buffer information written, and then update the usedring index.

[0082] Step 7: The DPU sends an msix interrupt notification to the Host, indicating that the data upload has been completed and data processing can begin.

[0083] Specifically, the host typically allocates `Queue_size` free buffers of the same size. This presents a problem: in scenarios where received network packets are small, the utilization rate of the injection buffer is low, leading to poor hardware and software performance. For example, the host allocates 4KB of free buffers for the transmit queue (RX), but the received packet data is mostly small packets (less than 64 bytes) or short packets (64 bytes to 1518 bytes). In this case, the buffer space utilization is very low, only 1.5% (64 ÷ 4096). When receiving small packets, the process requires steps ① to ⑦, involving multiple PCIe read / write operations. Since the physical bandwidth of PCIe is a decisive factor affecting performance, the performance of RX for small packets has its limits.

[0084] Considering the Virtio-net hardware offload scenario, the Virtio-net receiving network data model is simplified as follows: Figure 5 As shown, the Host is responsible for preparing the idle buffer and filling the data of each ring, and sending it to the DPU for backup. After receiving the network packets sent by the remote device, the DPU forwards the data to the Host.

[0085] Summarize the transmission delay model for DPU processing RX data as follows: Figure 6 As shown, the delay analysis for each stage is as follows:

[0086] T1: The latency of the host sending a notification, which is the latency of one PCIe write, typically 1000ns;

[0087] T2: DPU reads available ring index latency per operation. Assuming a symmetric PCIe link latency model, the latency from request initiation to response reception is 2 * 1000 ns (unique to split mode).

[0088] T3: DPU reads available ring entry latency per cycle, with a latency value of 1000ns; (unique to split mode)

[0089] T4: The latency of a single DPU read of a descriptor entry, with a latency value of 1000ns;

[0090] T5: The DPU receives messages sent from remote devices via the Ethernet interface, with indefinite latency.

[0091] T6: DPU writes to Host memory, sending the received data to the Host via PCIe. Its latency is the latency of a single PCIe write operation, 1000ns.

[0092] T7: DPU writes usedring entry operations. If it is in packed mode, it writes descriptor entry. For a single PCIe write operation, the delay is 1000ns.

[0093] T8: DPU write usedring index operation, with a latency of 1000ns for a single PCIe write operation; (unique to split mode)

[0094] T9: DPU write msix interrupt, with a delay of 1000ns for a single PCIe write operation.

[0095] The above analysis shows that the total processing time for n received data points, Tsum, is Tsum = n * (T1 + T2 + T3 + T4 + T5 + ...

[0096] The design concept (T6+T7+T8+T9) aims to reduce Tsum, thereby improving data transmission performance. Specifically:

[0097] The time T1 can be reduced by aggregating notifications through software, thereby reducing the number of doorbell sends and achieving a reduction of n*T1.

[0098] T2 is the unique time for reading the avring index in split mode. Software can achieve this by aggregating the indexes, ensuring that each index update is greater than 1, which can effectively reduce the number of PCIe reads and thus reduce n*T2.

[0099] T3 is the time for reading avring entries unique to split mode. By reading multiple avring entries at once, the number of PCIe reads is reduced, thereby reducing the time to n*T3.

[0100] T4 represents the latency of reading a descriptor entry. By reading multiple descriptor entries at once, the number of PCIe reads is reduced, thereby reducing the time of n*T4.

[0101] T5 represents the latency of the DPU's internal data reception processing. High-performance DPUs can already achieve very low latency, so improvements are limited.

[0102] T6 represents the write latency to host memory, the longest latency in the entire path, and the write latency of n PCIe operations. It is a key factor affecting performance. When processing large packets, the PCIe write bandwidth is already saturated and cannot be improved. However, when processing small packets, the PCIe write bandwidth can be increased, and multiple PCIe writes can be merged into a single write. By reducing the number of PCIe writes, the time n*T6 can be reduced.

[0103] T7 represents the latency for writing usedring entries. By aggregating entries, the number of PCIe writes can be reduced, thus lowering the time by n*T7.

[0104] T8 represents the latency of writing to the usedring index. By aggregating the indexes, a single index update can be greater than 1, reducing the number of PCIe writes and lowering the time by n*T8.

[0105] T9 represents the latency of writing to the msix interrupt. Interrupt merging can reduce the number of PCIe writes, thereby reducing the latency by n*T9.

[0106] Analysis reveals that T6 accounts for a significant portion of the time spent on I / O processing of received packets, especially when writing multiple small packets to host memory. Effectively reducing T6 time during this process can greatly improve the performance of small packet reception. Therefore, the method in this embodiment primarily improves network small packet reception performance by shortening T6 latency.

[0107] Specifically, the method of this embodiment includes the following steps:

[0108] Step S11: Receive the reception notification sent by the host and obtain the index of the first cache descriptor;

[0109] Specifically, the method in this embodiment is compatible with the split mode and packed mode of the existing Virtio protocol. After receiving the reception notification from the host, the DPU determines that it needs to receive data packets. Based on the split mode or packed mode mentioned above, it obtains the first cache descriptor index from the corresponding ring. The first cache descriptor index is the id of a certain entry in the first descriptor table.

[0110] Step S12: Read the first cache descriptor from the first descriptor table on the host side according to the first cache descriptor index; the first cache descriptor includes at least the address of the cache unit on the host side and the length of the cache unit;

[0111] Specifically, the traditional Virtio protocol's buffer descriptor contains four fields: buffer address, buffer length, flag, and next. In this embodiment, the first buffer descriptor only uses the buffer address, buffer length, and next fields. The address of the cache unit on the host side points to the cache unit in the host's memory used to store aggregated data packets. The data processing unit will write the received data packets to this address. The length of the cache unit represents the capacity of the host-side cache unit, that is, the maximum amount of data that the data processing unit can write. The data processing unit needs to ensure that the amount of data written does not exceed this length.

[0112] Step S13: Receive data packets and write data packets (network small packets) in the same queue into the local cache unit according to the cache line alignment principle to form aggregated data packets;

[0113] Specifically, the DPU continuously receives data packets. When it receives a small network packet, it identifies it as such and automatically writes the packets (small network packets) from the same queue into its local cache unit according to the cache line alignment principle to form an aggregated data packet. The aggregated data packet includes at least two small network packets. The cache line alignment principle refers to storing data on specific boundaries (usually multiples of the cache line size) to optimize data access efficiency. For example, if the host-side allocated free buffer is 4KB, and the data processing unit receives only small network packets, it will sequentially write the rx_packets from the target queue. Network packets such as _0, rx_packet_1, rx_packet_2, ..., rx_packet_n-1 are written into the local cache unit (i.e., the buffer of the data processing unit) according to the cache line alignment principle. Taking a cache line of 64 bytes as an example, the length of the network packet is not an integer multiple of 64 bytes. The part of the last bit that is less than 64 bytes will be written with 0 to padded the entire network packet to an integer multiple of 64 bytes. Therefore, each network packet will occupy an integer multiple of the cache line, and each buffer contains the storage space of multiple cache lines.

[0114] Step S14: Write the aggregated data packet into the cache unit on the host side according to the address of the cache unit;

[0115] Specifically, such as Figure 7As shown, the network packets rx_packet_0, rx_packet_1, rx_packet_2, ..., rx_packet_n-1 in the target queue are aggregated in the data processing unit to obtain an aggregated data packet. This aggregated data packet is written to the host-side buffer unit through a single write operation. For example, if the length of the first network packet pkt_len0 is 0x46 bytes, it is written to buffer0, with the starting address being the starting address of buffer0 plus the offset address. The offset of the first network packet is 0x0000h, and its length is an integer multiple of 0x40 bytes, so it will be padded to 0x40 bytes. For byte-level alignment, rx_packet0 will be padded to address 0x0080h, and then the next small network packet will be written. The length of this small network packet is pkt_len1 = 0x32B. It starts writing from the offset address 0x0080h of buffer0 and writes to 0x00B2h. The cache_line is padded to position 0x00C0h. The subsequent rx_packet2, ..., rx_packetn-1 are written in sequence. Therefore, a 4Kbyte free buffer can store a maximum of 64 network packets smaller than 64 bytes (4096B / 64B), and a maximum of 32 network packets between 64 bytes and 128 bytes (4096B / 128B), and so on. It can be seen that the smaller the network packet, the more buffer space is saved.

[0116] Step S15: Generate a completion descriptor based on the aggregated data packet and send the completion descriptor to the host; the completion descriptor includes at least an aggregation identifier and the actual length of each data packet in the aggregated data packet, the aggregation identifier is used to indicate that the data packet written to the host side is an aggregated data packet, and the aggregated data packet includes at least two data packets;

[0117] Specifically, the completion descriptor provides the Host with the necessary parsing information for parsing the aggregated data packets. Thus, after the Host obtains the aggregated data packets, it can correctly segment and parse the original individual data packets according to the content in the completion descriptor. This step ensures the integrity and accuracy of data transmission and is an important part of the data packet receiving process in the Virtio protocol of this embodiment.

[0118] Step S16: Notify the host that the aggregated data packet has been written to the host-side cache unit.

[0119] Specifically, after receiving the completion notification, the Host reads the aggregated data packet from the corresponding buffer and segments the aggregated data packet into individual network packets according to the information in the completion descriptor. The notification mechanism can be an interrupt notification, which can be referred to in the split mode and packed mode, and will not be elaborated here.

[0120] In summary, in this embodiment, the data processing unit writes multiple network packets into the local cache unit of the DPU according to the cache line alignment principle to form an aggregated data packet. Then, it writes the aggregated data packet into the cache unit on the host side through a single PCIe write operation. While maintaining compatibility with the existing Virtio protocol, this reduces the number of PCIe write operations. Because the amount of data written each time is increased, the bandwidth utilization of PCIe is significantly improved, avoiding bandwidth waste caused by frequent small data writes. Moreover, in the traditional method, each network packet needs to occupy a cache unit on the host side, resulting in low cache unit resource utilization. However, the method provided in the first aspect of this application aggregates multiple network packets and writes them into the same cache unit, greatly reducing the number of cache units occupied and improving the resource utilization of the cache units.

[0121] Optionally, step S15, which generates a completion descriptor based on the aggregated data packet, includes:

[0122] Step S151: Generate a first completion descriptor and a second completion descriptor based on the aggregated data packet; the first completion descriptor includes the aggregation identifier, and the second completion descriptor includes the actual length of each data packet in the aggregated data packet;

[0123] Step S152: Write the first completion descriptor into the first descriptor cache unit on the host side;

[0124] Step S153: Write the second completion descriptor into the second descriptor cache unit on the host side.

[0125] Specifically, the Host first reads the first completion descriptor from the first descriptor cache unit. If the first completion descriptor contains an aggregation identifier (indicating that the data being read is an aggregated data packet formed by aggregating multiple network packets), then it further reads the second completion descriptor from the second descriptor cache unit and parses the aggregated data packet to obtain each network packet. The design of the first and second completion descriptors in this embodiment is to be compatible with the existing Virtio protocol. The field structure of the first completion descriptor is the same as the field structure of the traditional cache descriptor. However, in this embodiment, only the flag field is used to fill the aggregation identifier, while the second completion descriptor is a newly added descriptor structure.

[0126] Optionally, the first completion descriptor may also include the actual length of the aggregated data packet.

[0127] Specifically, the first completion descriptor also includes a length field, which is filled with the actual length of the aggregated data packet. This is used by the Host to perform data integrity verification after parsing the aggregated data packet, that is, to determine whether the actual length of the aggregated data packet is consistent with the sum of the lengths of the parsed individual network packets.

[0128] Optionally, step S152 specifically includes:

[0129] Write the first completion descriptor into the first descriptor table to update the first cache descriptor;

[0130] Specifically, after receiving the interrupt notification from the DPU, the Host will obtain the first cached descriptor index (i.e., the completion descriptor index) and read the first completion descriptor from the first descriptor table (DescriptorRing) according to the first cached descriptor index.

[0131] Step S153 specifically includes:

[0132] The second completion descriptor is written into the second descriptor table (Packet length descriptorring) on ​​the host side, and the index of the second descriptor in the second descriptor table is the same as the index of the first cache descriptor in the first descriptor table.

[0133] By setting a first completion descriptor and a second completion descriptor, and updating the first cache descriptor using the first completion descriptor, the host reads the second completion descriptor only if the aggregation flag in the first completion descriptor is valid. If the aggregation flag in the first completion descriptor is invalid (i.e., under the existing Virtio protocol), the host does not need to read the second completion descriptor. This method improves PCIe bandwidth utilization while maintaining compatibility with the existing Virtio protocol.

[0134] Among them, such as Figure 8As shown, both the first descriptor ring and the second descriptor ring (Packet length descriptor ring) include multiple descriptor entries, and the cached descriptor indices (index / id) of the multiple descriptor entries in the first descriptor ring and the multiple descriptor entries in the second descriptor ring (Packet length descriptor ring) correspond one-to-one. The structure of the first descriptor ring is consistent with that of the descriptor ring of the existing virtio protocol. Each entry's descriptor contains fields such as address, length, flag, and next, which is used to ensure compatibility with the existing virtio protocol. Based on this, the host can subsequently read the second completion descriptor from the second descriptor ring (Packet length descriptor ring) according to the first cached descriptor index.

[0135] Optionally, the second completion descriptor includes a mode field and multiple length fields with the same bit width. The mode field is used to describe the bit width corresponding to the actual length of each data packet in the aggregated data packet, and the multiple length fields with the same bit width respectively contain the actual length of each data packet in the aggregated data packet.

[0136] Specifically, the DPU needs to ensure that the length of each field in each length information entry filled into the length information table is consistent, so that the Host can identify the length (pkt_len) of each network packet. Taking a 16-byte (128-bit) length information entry as an example, to improve space utilization, bits [1:0] are used to represent the maximum value of a single rxpacket_len (network packet in the receiving direction), i.e., the size of the bit width occupied. This is named the mode field, and the meanings of each mode are as follows:

[0137] mode=0: means that the maximum length of a Packet_len is 64 bytes, occupying 6 bits. lnn=0 means 1 byte, lnn=1 means 2 bytes, and so on. lnn=63 means 64 bytes. Therefore, the remaining 126 bits (128 bits - 2 bits) can complete the transmission of a maximum of 21 (126 ÷ 6) small packets smaller than 64 bytes.

[0138] mode=1: means that the maximum length of a Packet_len is 128 bytes, occupying 7 bits. lnn=0 means 1 byte, lnn=1 means 2 bytes, and so on, lnn=127 means 128 bytes. Therefore, the remaining 126 bits (128 bits - 2 bits) can complete the transmission of a maximum of 18 (126 ÷ 7) small packets smaller than 128 bytes.

[0139] mode=2: This means that the maximum length of a Packet_len is 256 bytes, occupying 8 bits. lnn=0 represents a length of 1 byte, lnn=1 represents a length of 2 bytes, and so on. lnn=255 represents a length of 256 bytes. Therefore, the remaining 126 bits (128 bits - 2 bits) can be used to send up to a maximum of 15 (126 ÷ 8) small packets of data smaller than 256 bytes.

[0140] mode=3: This means that the maximum length of a Packet_len is 512 bytes, which occupies 9 bits. lnn=0 means 1 byte, lnn=1 means 2 bytes, and so on. lnn=511 means 512 bytes. Therefore, the remaining 126 bits (128 bits - 2 bits) can complete the transmission of up to 14 (126 ÷ 9) small packets of data smaller than 512 bytes.

[0141] Using mode=0 as an example, the field layout is shown as follows: Figure 3 The meanings of each field are explained in the following table:

[0142]

[0143]

[0144] Other modes are similar to mode=0, and will not be shown here.

[0145] Optionally, step S14, based on the address of the cache unit, specifically includes:

[0146] If the length of the aggregated data packet reaches the PCIe bandwidth within a set waiting time, the aggregated data packet will be written into the cache unit on the host side; or, the aggregated data packet will be written into the cache unit on the host side when the set waiting time is reached.

[0147] Specifically, suppose an aggregated data packet is formed by aggregating two network packets, with lengths of 6 bytes and 8 bytes respectively, and a buffer line length of 12 bytes. The first network packet occupies 6 bytes and needs to be padded with (12 - (6% 12))% 12 = 6 bytes, for a total of 12 bytes. The second network packet occupies 8 bytes and needs to be padded with (12 - (8% 12))% 12 = 4 bytes, for a total of 12 bytes. Therefore, the length of the aggregated data packet is 6 + 8 + 6 + 4 = 24 bytes, because it occupies two complete buffer lines in memory. The PCIe bandwidth is the maximum data length that the DPU can send to the host buffer in a single write operation, which can be understood as the maximum length of the aggregated data packet. If the PCIe bandwidth is set to 1024 bytes, the data processing unit will continue to aggregate data packets in the local buffer unit until the length reaches or exceeds 1024 bytes, at which point the aggregated data packet will be sent.

[0148] The set wait time refers to the time window during which the DPU waits for subsequent network packets from the target queue to arrive after receiving the first network packet to be aggregated. The length of this time window can be adjusted according to network traffic and system load. For example, if the wait time is set to 10 milliseconds, the DPU will wait 10 milliseconds after receiving the first network packet to see if more network packets arrive and aggregate them. During the set wait time, the DPU will continue to receive and aggregate data packets. If the length of the aggregated data packet reaches the aggregation length limit within the wait time, the DPU will immediately write the aggregated data packet into the host-side buffer and stop waiting. If the wait time ends but the length of the aggregated data packet has not yet reached the aggregation length limit, the DPU will stop waiting and also write the current aggregated data packet into the host-side buffer to ensure that data does not remain in the local buffer for too long and is promptly delivered to the host for processing, avoiding potential delays.

[0149] Embodiment 2 of this application provides a data packet receiving method applied to the host side, the method comprising:

[0150] Step S21: When it is necessary to receive a data packet, allocate an idle buffer unit, generate a first buffer descriptor according to the address and length of the idle buffer unit, and write the first buffer descriptor into the first descriptor table on the host side; wherein, the first buffer descriptor includes the address and length of the buffer unit on the host side.

[0151] Step S22: Send a reception notification to the data processing unit to request the data processing unit to write the received data packets of the target queue into the cache unit on the host side;

[0152] Step S23: Receive the completion descriptor, completion descriptor index and completion notification sent by the data processing unit, and obtain the completion descriptor index in response to the completion notification;

[0153] Step S24: Obtain the completion descriptor according to the completion descriptor index, and parse the completion descriptor to obtain the aggregation identifier and the actual length of each data packet (network packet) in the aggregation data packet; wherein, the aggregation identifier is used to indicate that the data packet written to the cache unit on the host side is an aggregation data packet, and the aggregation data packet includes at least two data packets;

[0154] Specifically, after the DPU completes the uploading of the aggregated data packet, it sends a completion descriptor and a completion notification to the Host, as detailed in the description of the method in Implementation Example 1.

[0155] Step S25: Read the aggregated data packet from the corresponding host-side cache unit according to the completion descriptor index;

[0156] Specifically, the host can determine the corresponding buffer based on the first descriptor index, because the buffer is allocated by the host, and there is a one-to-one correspondence between the first descriptor index and the buffer. The host has already determined and recorded this when it completes the generation of the first buffer descriptor.

[0157] Step S26: Based on the actual length of each data packet in the aggregated data packet, extract at least two data packets from the aggregated data packet according to the cache line alignment principle.

[0158] Specifically, when a data packet needs to be received, the host notifies the data processing unit to receive the data packet. After receiving the notification, when the data processing unit receives a small network packet, it writes multiple small network packets into the local cache unit according to the cache line alignment principle to form an aggregated data packet. Then, it writes the aggregated data packet into the cache unit on the host side through a single PCIe write operation. This aggregated write operation, while being compatible with the existing Virtio protocol, reduces the number of PCIe write operations, significantly improves the bandwidth utilization of PCIe, avoids bandwidth waste caused by frequent small data writes, and at the same time, by aggregating multiple small network packets and writing them into the same cache unit, it greatly reduces the number of cache units occupied and improves the resource utilization of the cache units. After receiving the completion notification from the data processing unit, the host can obtain the aggregated data packet and the actual length of each data packet in the aggregated data packet according to the first descriptor index, and extract each data packet in the aggregated data packet according to the cache line alignment principle, making the data extraction process more efficient and accurate.

[0159] Optionally, the completion descriptor includes a first completion descriptor and a second completion descriptor, wherein the first completion descriptor includes the aggregation identifier and the second completion descriptor includes the actual length of each data packet in the aggregated data packet.

[0160] Optionally, step S24, obtaining the completion descriptor based on the completion descriptor index and parsing the completion descriptor to obtain the aggregation identifier and the actual length of each data packet in the aggregated data packet, includes:

[0161] Step S241: Read the first completion descriptor and parse the first completion descriptor to obtain the aggregation identifier;

[0162] Specifically, the host obtains the completion descriptor index (i.e., the index corresponding to the first cached descriptor), reads the first completion descriptor from the descriptor entry corresponding to the first cached descriptor index in the first descriptor table, and parses the first completion descriptor to obtain the aggregation identifier;

[0163] Step S242: Read the second completion descriptor from the descriptor entry corresponding to the first cache descriptor index in the second descriptor table on the host side according to the aggregation identifier;

[0164] Specifically, both the first descriptor table and the second descriptor table include multiple descriptor entries, and the cached descriptor indices of the multiple descriptor entries in the first descriptor table correspond one-to-one with the cached descriptor indices of the multiple descriptor entries in the second descriptor table.

[0165] Optionally, the second completion descriptor includes a pattern field and multiple length fields with the same bit width. The pattern field is used to describe the bit width corresponding to the actual length of each data packet in the aggregated data packet, and the multiple length fields with the same bit width respectively contain the actual length of each data packet in the aggregated data packet.

[0166] Optionally, the first completion descriptor may further include the actual length of the aggregated data packet;

[0167] Step S26 further includes:

[0168] Integrity checks are performed on at least two data packets extracted from the aggregated data packet based on the actual length of the aggregated data packet.

[0169] Specifically, assuming an aggregated data packet is formed by aggregating two network packets with lengths of 6 bytes and 8 bytes respectively, then the actual length of the aggregated data packet is 6 + 8 = 14 bytes.

[0170] It should be noted that Embodiment 2 is a data processing method flow executed on the Host side, which corresponds to the data processing method flow executed on the DPU side in Embodiment 1. Therefore, any content not detailed in the data processing method of Embodiment 2 can be obtained by referring to the content of the data processing method of Embodiment 1. Therefore, Embodiment 2 will not be described in detail.

[0171] Embodiment 3 of this application provides a data processing unit, including the following modules for performing the method described in Embodiment 1:

[0172] The notification receiving module is used to receive notifications sent by the host and obtain the index of the first cache descriptor.

[0173] The descriptor reading module is used to read the first cache descriptor from the first descriptor table on the host side according to the first cache descriptor index; the first cache descriptor includes at least the address of the cache unit on the host side and the length of the cache unit;

[0174] The data packet receiving module is used to receive data packets and write data packets in the same queue into the local cache unit according to the cache line alignment principle to form aggregated data packets;

[0175] A data packet uploading module is used to write the aggregated data packet into the cache unit on the host side according to the address of the cache unit;

[0176] The completion descriptor module is used to generate a completion descriptor based on the aggregated data packet and send the completion descriptor to the host; the completion descriptor includes at least an aggregation identifier and the actual length of each data packet in the aggregated data packet, the aggregation identifier is used to indicate that the data packet written to the host side is an aggregated data packet, and the aggregated data packet includes at least two data packets;

[0177] The notification sending module is used to notify the host that the aggregated data packet has been written to the host-side cache unit.

[0178] Optionally, the completion descriptor module includes:

[0179] The descriptor generation module is used to generate a first completion descriptor and a second completion descriptor based on the aggregated data packet; the first completion descriptor includes the aggregation identifier, and the second completion descriptor includes the actual length of each data packet in the aggregated data packet;

[0180] The first write descriptor module is used to write the first completed descriptor into the first descriptor cache unit on the host side;

[0181] The second write descriptor module is used to write the second completion descriptor into the second descriptor cache unit on the host side.

[0182] Optionally, the first write descriptor module is used to write the first completed descriptor into the first descriptor table to update the first cached descriptor;

[0183] The second write descriptor module is used to write the second completion descriptor into the second descriptor table on the host side, and the index of the second descriptor in the second descriptor table is the same as the index of the first cache descriptor in the first descriptor table;

[0184] Both the first descriptor table and the second descriptor table include multiple descriptor entries, and the cached descriptor indices of the multiple descriptor entries in the first descriptor table correspond one-to-one with the cached descriptor indices of the multiple descriptor entries in the second descriptor table.

[0185] Optionally, the second completion descriptor includes a pattern field and multiple length fields with the same bit width. The pattern field is used to describe the bit width corresponding to the actual length of each data packet in the aggregated data packet, and the multiple length fields with the same bit width respectively contain the actual length of each data packet in the aggregated data packet.

[0186] Optionally, the data packet uploading module is configured to write the aggregated data packet into the cache unit on the host side if the length of the aggregated data packet reaches the length of the PCIe bandwidth within a set waiting time; or, when the set waiting time is reached, write the aggregated data packet into the cache unit on the host side.

[0187] It should be noted that the data processing unit in this embodiment corresponds to the method described in Embodiment 1. The contents of the data processing unit in this embodiment that are not described in detail can be obtained by referring to the contents of the method described in Embodiment 1, and will not be repeated in this embodiment.

[0188] Embodiment 4 of this application provides a host computer including the following modules for performing the method described in Embodiment 2:

[0189] The descriptor generation module is used to allocate an idle host-side buffer unit when it is necessary to receive data packets, generate a first buffer descriptor according to the address and length of the idle host-side buffer unit, and write the first buffer descriptor into the first descriptor table on the host side; wherein, the first buffer descriptor includes the address and length of the host-side buffer unit;

[0190] The notification sending module is used to send a reception notification to the data processing unit to request the data processing unit to write the received data packets of the target queue into the cache unit on the host side.

[0191] The notification receiving module is used to receive the completion descriptor, the completion descriptor index and the completion notification sent by the data processing unit, and to obtain the completion descriptor index in response to the completion notification.

[0192] The descriptor reading module is used to obtain the completion descriptor according to the completion descriptor index, and parse the completion descriptor to obtain the aggregation identifier and the actual length of each data packet in the aggregation data packet; wherein, the aggregation identifier is used to indicate that the data packet written to the cache unit on the host side is an aggregation data packet, and the aggregation data packet includes at least two data packets;

[0193] The data packet reading module is used to read aggregated data packets from the corresponding cache unit on the host side according to the completion descriptor index;

[0194] The data packet parsing module is used to extract at least two data packets from the aggregated data packet according to the actual length of each data packet in the aggregated data packet and the cache line alignment principle.

[0195] Optionally, the completion descriptor includes a first completion descriptor and a second completion descriptor, wherein the first completion descriptor includes the aggregation identifier and the second completion descriptor includes the actual length of each data packet in the aggregated data packet.

[0196] Optionally, the descriptor reading module includes:

[0197] The first completion descriptor reading module is used to obtain the completion descriptor index, read the first completion descriptor from the descriptor entry corresponding to the completion cache descriptor index in the first descriptor table, and parse the first completion descriptor to obtain the aggregation identifier;

[0198] The second completion descriptor reading module is used to read the second completion descriptor from the descriptor entry corresponding to the first cached descriptor index in the second descriptor table on the host side according to the aggregation identifier;

[0199] Both the first descriptor table and the second descriptor table include multiple descriptor entries, and the cached descriptor indices of the multiple descriptor entries in the first descriptor table correspond one-to-one with the cached descriptor indices of the multiple descriptor entries in the second descriptor table.

[0200] Optionally, the second completion descriptor includes a pattern field and multiple length fields with the same bit width. The pattern field is used to describe the bit width corresponding to the actual length of each data packet in the aggregated data packet, and the multiple length fields with the same bit width respectively contain the actual length of each data packet in the aggregated data packet.

[0201] It should be noted that the host in this embodiment corresponds to the method described in Embodiment 2. The contents of the host in this embodiment that are not described in detail can be obtained by referring to the contents of the method described in Embodiment 2, and will not be repeated in this embodiment.

[0202] Embodiment 5 of this application provides a network interface card (NIC) including the data processing unit described in Embodiment 3 and / or the host described in Embodiment 4.

[0203] Embodiment Six of this application provides a computer program product, including computer program instructions that instruct a computer device to perform an operation corresponding to the method described in Embodiment One.

[0204] Specifically, the computer program product includes a series of computer program instructions, which are codes written in a computer program. These instructions define how to perform specific operations. The computer program instructions are designed to be loaded onto a computer device and instruct the device to perform specific operations, which refer to the various steps in the method described in Embodiment 1 above. In this way, the computer program product of this embodiment provides a complete software solution that can run on various computer devices to implement the method of Embodiment 1 above.

[0205] Embodiment 7 of this application provides a computer program product, including computer program instructions that instruct a computer device to perform an operation corresponding to the method described in Embodiment 2.

[0206] Specifically, the computer program product includes a series of computer program instructions, which are codes written in a computer program. These instructions define how to perform specific operations. The computer program instructions are designed to be loaded onto a computer device and instruct the device to perform specific operations, which refer to the various steps in the method described in Embodiment 2 above. In this way, the computer program product of this embodiment provides a complete software solution that can run on various computer devices to implement the method of Embodiment 2 above.

[0207] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or technological improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A data packet receiving method, applied to a data processing unit, characterized in that, The method includes: Receive the reception notification sent by the host and obtain the index of the first cache descriptor; The first cache descriptor is read from the first descriptor table on the host side according to the first cache descriptor index; the first cache descriptor includes at least the address of the cache unit on the host side and the length of the cache unit; Receive data packets and write data packets from the same queue into the cache unit of the data processing unit according to the cache line alignment principle to form aggregated data packets; The aggregated data packet is written to the cache unit on the host side according to the address of the cache unit; A completion descriptor is generated based on the aggregated data packet, and the completion descriptor is sent to the host; the completion descriptor includes at least an aggregation identifier and the actual length of each data packet in the aggregated data packet, the aggregation identifier is used to indicate that the data packet written to the host side is an aggregated data packet, and the aggregated data packet includes at least two data packets; The host is notified that the aggregated data packet has been written to the host-side cache unit.

2. The method of claim 1, wherein, The step of generating a completion descriptor based on the aggregated data packet includes: A first completion descriptor and a second completion descriptor are generated based on the aggregated data packet; the first completion descriptor includes the aggregate identifier, and the second completion descriptor includes the actual length of each data packet in the aggregated data packet; Write the first completion descriptor into the first descriptor cache unit on the host side; The second completion descriptor is written into the second descriptor cache unit on the host side.

3. The method of claim 2, wherein, The first completion descriptor also includes the actual length of the aggregated data packet.

4. The method of claim 2, wherein, The step of writing the first completion descriptor into the first descriptor cache unit on the host side specifically includes: Write the first completion descriptor into the first descriptor table to update the first cache descriptor; The step of writing the second completion descriptor into the second descriptor cache unit on the host side includes: The second completion descriptor is written into the second descriptor table on the host side, and the index of the second descriptor in the second descriptor table is the same as the index of the first cache descriptor in the first descriptor table.

5. The method of claim 2, wherein, The second completion descriptor includes a mode field and multiple length fields with the same bit width. The mode field is used to determine the bit width used to describe the actual length of each data packet in the aggregated data packet under the mode. The multiple length fields with the same bit width each contain the actual length of each data packet in the aggregated data packet.

6. The method according to any one of claims 1 to 5, characterized in that, The step of writing the aggregated data packet into the cache unit on the host side according to the address of the cache unit specifically includes: If the length of the aggregated data packet reaches the PCIe bandwidth within a set waiting time, the aggregated data packet is written into the cache unit on the host side; or, when the set waiting time is reached, the aggregated data packet is written into the cache unit on the host side.

7. A data packet receiving method applied to a host, comprising: The method includes: When a data packet needs to be received, an idle buffer unit is allocated, a first buffer descriptor is generated based on the address and length of the idle buffer unit, and the first buffer descriptor is written into the first descriptor table on the host side; wherein, the first buffer descriptor includes the address and length of the buffer unit on the host side; Send a reception notification to the data processing unit to request the data processing unit to write the received data packets of the target queue into the cache unit on the host side; Receive the completion descriptor, completion descriptor index and completion notification sent by the data processing unit, and retrieve the completion descriptor index in response to the completion notification; The completion descriptor is obtained according to the completion descriptor index, and the completion descriptor is parsed to obtain the aggregation identifier and the actual length of each data packet in the aggregation data packet; wherein, the aggregation identifier is used to indicate that the data packet written to the cache unit on the host side is an aggregation data packet, and the aggregation data packet includes at least two data packets; The aggregated data packet is read from the corresponding host-side cache unit according to the completion descriptor; Based on the actual length of each data packet in the aggregated data packet, at least two data packets are extracted from the aggregated data packet according to the cache line alignment principle.

8. The method of claim 7, wherein, The completion descriptor includes a first completion descriptor and a second completion descriptor. The first completion descriptor includes the aggregation identifier, and the second completion descriptor includes the actual length of each data packet in the aggregated data packet.

9. The method of claim 8, wherein, The step of obtaining the completion descriptor and parsing the completion descriptor to obtain the aggregation identifier and the actual length of each data packet in the aggregated data packet includes: The first completion descriptor is read according to the completion descriptor index, and the aggregation identifier is obtained by parsing the first completion descriptor; The second completion descriptor is read from the descriptor entry corresponding to the completion descriptor index in the second descriptor table on the host side according to the aggregation identifier.

10. The method of claim 9, wherein, The second completion descriptor includes a mode field and multiple length fields with the same bit width. The mode field is used to determine the bit width used to describe the actual length of each data packet in the aggregated data packet under the mode. The multiple length fields with the same bit width each contain the actual length of each data packet in the aggregated data packet.

11. The method according to claim 8, characterized in that, The first completion descriptor also includes the actual length of the aggregated data packet; The method further includes: Integrity checks are performed on at least two data packets extracted from the aggregated data packet based on the actual length of the aggregated data packet.

12. A data processing unit, characterized in that, include: The notification receiving module is used to receive notifications sent by the host and obtain the index of the first cache descriptor. The descriptor reading module is used to read the first cache descriptor from the first descriptor table on the host side according to the first cache descriptor index; the first cache descriptor includes at least the address of the cache unit on the host side and the length of the cache unit; The data packet receiving module is used to receive data packets and write data packets in the same queue into the local cache unit according to the cache line alignment principle to form aggregated data packets; A data packet uploading module is used to write the aggregated data packet into the cache unit on the host side according to the address of the cache unit; The completion descriptor module is used to generate a completion descriptor based on the aggregated data packet and send the completion descriptor to the host; the completion descriptor includes at least an aggregation identifier and the actual length of each data packet in the aggregated data packet, the aggregation identifier is used to indicate that the data packet written to the host side is an aggregated data packet, and the aggregated data packet includes at least two data packets; The notification sending module is used to notify the host that the aggregated data packet has been written to the host-side cache unit.

13. A host, characterized by include: The descriptor generation module is used to allocate an idle buffer unit when it is necessary to receive a data packet, generate a first buffer descriptor according to the address and length of the idle buffer unit, and write the first buffer descriptor into the first descriptor table on the host side; wherein, the first buffer descriptor includes the address and length of the buffer unit on the host side; The notification sending module is used to send a reception notification to the data processing unit to request the data processing unit to write the received data packets of the target queue into the cache unit on the host side. The notification receiving module is used to receive the completion descriptor, the completion descriptor index and the completion notification sent by the data processing unit, and to obtain the completion descriptor index in response to the completion notification. The descriptor reading module is used to obtain the completion descriptor according to the completion descriptor index, and parse the completion descriptor to obtain the aggregation identifier and the actual length of each data packet in the aggregation data packet; wherein, the aggregation identifier is used to indicate that the data packet written to the cache unit on the host side is an aggregation data packet, and the aggregation data packet includes at least two data packets; The data packet reading module is used to read aggregated data packets from the corresponding cache unit on the host side according to the completion descriptor index; The data packet parsing module is used to extract at least two data packets from the aggregated data packet according to the actual length of each data packet in the aggregated data packet and the cache line alignment principle.

14. A network card, comprising: Includes the data processing unit as described in claim 12.

15. A computer program product, characterised in that, It includes computer program instructions that instruct a computer device to perform an operation corresponding to the method described in any one of claims 1 to 11.

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