Display substrate and display device

Abstract

The invention provides a display substrate and a display device. The display substrate comprises a display area (AA) and a peripheral area (NA) located on the periphery of the display area (AA), and the peripheral area (NA) comprises a first binding area (BA1); the display substrate further comprises: a substrate (100); the first bonding pad (P1) is arranged on the substrate (100) and located in the first binding area (BA1), the first bonding pad (P1) comprises a plurality of first sub-bonding pads (P11) and a plurality of second sub-bonding pads (P12) which are arranged at intervals, and the second sub-bonding pads (P12) are located on the sides, close to the display area (AA), of the first sub-bonding pads (P11); the driving chip (IC) is arranged on the first bonding pad (P1), and the side edge, away from the display area (AA), of the driving chip (IC) protrudes out of the edge of the first sub bonding pad (P11); the connecting wire (L) is arranged on the substrate (100), one end of the connecting wire (L) is electrically connected with the first sub-bonding pad (P11), and the other end of the connecting wire (L) extends in the direction away from the display area (AA); the insulation protection part (Q) is positioned on one side, far away from the substrate (100), of the connection wire (L), and the insulation protection part (Q) at least covers one part of the connection wire (L); the orthographic projection, on the substrate (100), of the side edge, away from the display area (AA), of the driving chip (IC) is located in the orthographic projection, on the substrate (100), of the insulation protection part (Q).

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the development of display technology, "full screen" has become a trend. Driven by the pursuit of increasingly narrow bezels around display devices, chip-on-panel (COP) packaging technology has emerged. This technology directly attaches the driver chip to the display panel, allowing the lower end of the display panel to be bent to the back, where it is then bonded to a flexible printed circuit (FPC), resulting in a very narrow lower bezel. However, ensuring the yield rate of driver chip bonding in COP packaging technology is a key concern for display product developers.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure and therefore the above information may contain information that does not constitute prior art.

[0004] Summary of the Invention

[0005] In one aspect, a display substrate is provided, comprising a display area and a peripheral area located around the display area, wherein the peripheral area comprises a first binding area; the display substrate comprises:

[0006] substrate;

[0007] a first pad disposed on the base substrate and located in the first binding area, the first pad including a plurality of first sub-pads and a plurality of second sub-pads spaced apart from each other, the plurality of second sub-pads being located on a side of the plurality of first sub-pads close to the display area;

[0008] A driver chip is disposed on the first pad, wherein a side of the driver chip away from the display area protrudes beyond an edge of the first sub-pad;

[0009] a connecting wire, disposed on the base substrate, wherein one end of the connecting wire is electrically connected to the first sub-pad and the other end of the connecting wire is extended in a direction away from the display area; and

[0010] an insulating protection portion, located on a side of the connecting wire away from the substrate, the insulating protection portion covering at least a portion of the connecting wire;

[0011] The orthographic projection of the side of the driving chip away from the display area on the base substrate is located within the orthographic projection of the insulating protection portion on the base substrate.

[0012] According to some exemplary embodiments, the orthographic projection of the insulating protection portion on the base substrate has a first edge close to the display area and a second edge away from the display area, and the orthographic projection of the driving chip on the base substrate has a third edge away from the display area, and the third edge is located between the first edge and the second edge.

[0013] According to some exemplary embodiments, the display substrate further includes an organic insulating portion, the organic insulating portion being located on a side of the connecting trace away from the base substrate and covering a portion of the connecting trace, the organic insulating portion being spaced apart from the first sub-pad, an orthographic projection of the organic insulating portion on the base substrate having a fourth edge close to the display area, and the second edge being farther away from the display area than the fourth edge; and / or,

[0014] An orthographic projection of the connecting trace on the base substrate has a fifth edge close to the display area, and the first edge is flush with the fifth edge.

[0015] According to some exemplary embodiments, the display substrate includes:

[0016] a driving function layer, located on the base substrate, the driving function layer comprising multiple driving metal layers; and

[0017] The touch function layer is located on a side of the driving function layer away from the base substrate.

[0018] According to some exemplary embodiments, the connection trace is located in the driving function layer, and the insulating protection portion is located in the touch function layer.

[0019] According to some exemplary embodiments, the touch function layer includes a touch base barrier layer located on a side of the driving function layer away from the base substrate, a first touch metal layer located on a side of the touch base barrier layer away from the driving function layer, a touch insulating layer located on a side of the first touch metal layer away from the touch base barrier layer, and a second touch metal layer located on a side of the touch insulating layer away from the first touch metal layer;

[0020] Wherein, the insulating protection portion is located on at least one of the touch substrate barrier layer and the touch insulating layer.

[0021] According to some exemplary embodiments, the first sub-pad includes a first solder sub-portion and a second solder sub-portion located on a side of the first solder sub-portion away from the base substrate;

[0022] The first soldering sub-part is located on at least a portion of the driving metal layer, and the second soldering sub-part is located on the touch function layer.

[0023] According to some exemplary embodiments, the multi-layer driving metal layer includes a first gate metal layer located on the base substrate, a first source-drain metal layer located on a side of the first gate metal layer away from the base substrate, and a second source-drain metal layer located on a side of the first source-drain metal layer away from the first gate metal layer;

[0024] Wherein, the first bonding pad is located in at least one of the first gate metal layer, the first source / drain metal layer, and the second source / drain metal layer; or

[0025] The multi-layer drive metal layer includes a first gate metal layer located on the base substrate, a first source-drain metal layer located on a side of the first gate metal layer away from the base substrate, a second source-drain metal layer located on a side of the first source-drain metal layer away from the first gate metal layer, and a third source-drain metal layer located on a side of the second source-drain metal layer away from the first source-drain metal layer;

[0026] The first bonding pad is located at at least one of the first gate metal layer, the first source / drain metal layer, the second source / drain metal layer, and the third source / drain metal layer.

[0027] According to some exemplary embodiments, the touch function layer includes a first touch metal layer and a second touch metal layer located on a side of the first touch metal layer away from the base substrate;

[0028] The second solder plate portion is located on at least one of the first touch metal layer and the second touch metal layer.

[0029] According to some exemplary embodiments, the first sub-pad is located on at least a portion of the driving metal layer.

[0030] According to some exemplary embodiments, the multi-layer driving metal layer includes a first gate metal layer located on the base substrate, a first source-drain metal layer located on a side of the first gate metal layer away from the base substrate, and a second source-drain metal layer located on a side of the first source-drain metal layer away from the first gate metal layer;

[0031] Wherein, the first sub-pad is located in at least one of the first gate metal layer, the first source-drain metal layer, and the second source-drain metal layer; or

[0032] The multi-layer drive metal layer includes a first gate metal layer located on the base substrate, a first source-drain metal layer located on a side of the first gate metal layer away from the base substrate, a second source-drain metal layer located on a side of the first source-drain metal layer away from the first gate metal layer, and a third source-drain metal layer located on a side of the second source-drain metal layer away from the first source-drain metal layer;

[0033] The first sub-pad is located in at least one of the first gate metal layer, the first source-drain metal layer, the second source-drain metal layer and the third source-drain metal layer.

[0034] According to some exemplary embodiments, the connection trace is located in the driving function layer, and the insulating protection portion is located in the driving function layer.

[0035] According to some exemplary embodiments, the connecting trace includes:

[0036] a first sub-layer, directly connected to the first sub-pad;

[0037] a second sublayer, located on a side of the first sublayer away from the base substrate, the second sublayer being spaced apart from the first sub-pad and exposing a first portion of the first sublayer;

[0038] The insulating protection portion is located on a side of the first sub-layer away from the base substrate and covers at least a first portion of the first sub-layer.

[0039] According to some exemplary embodiments, the insulating protection portion extends from the surface of the first part to between the first sub-layer and the second sub-layer, the insulating protection portion has a via, the via is located on the side of the first part away from the first sub-pad, and the area between the first sub-layer and the second sub-layer has a via, and the first sub-layer and the second sub-layer are overlapped through the via.

[0040] According to some exemplary embodiments, the driving function layer includes a first source-drain metal layer, a first passivation layer located on a side of the first source-drain metal layer away from the substrate, and a second source-drain metal layer located on a side of the first passivation layer away from the first source-drain metal layer;

[0041] Wherein, the first sub-layer is located in the first source-drain metal layer, the second sub-layer is located in the second source-drain metal layer, and the insulating protection portion is located in the first passivation layer; or

[0042] The driving function layer includes a first source-drain metal layer, a first passivation layer located on a side of the first source-drain metal layer away from the substrate, a second source-drain metal layer located on a side of the first passivation layer away from the first source-drain metal layer, a second passivation layer located on a side of the second source-drain metal layer away from the first passivation layer, and a third source-drain metal layer located on a side of the second passivation layer away from the second source-drain metal layer;

[0043] In which, the first sublayer is located in the first source-drain metal layer, the second sublayer is located in the second source-drain metal layer, and the insulating protection part is located in the first passivation layer; or, the first sublayer is located in the second source-drain metal layer, the second sublayer is located in the third source-drain metal layer, and the insulating protection part is located in the second passivation layer.

[0044] According to some exemplary embodiments, the display substrate further includes a sidewall protection portion, the sidewall protection portion at least partially covers a sidewall of the first sub-pad, and the sidewall protection portion is made of an insulating material.

[0045] According to some exemplary embodiments, the display substrate further includes a sidewall protection portion, the sidewall protection portion at least partially covers a sidewall of the first sub-pad, and the sidewall protection portion and the insulating protection portion are located in the same layer.

[0046] According to some exemplary embodiments, the peripheral area further includes a second binding area, and the second binding area is located on a side of the first binding area away from the display area;

[0047] The display substrate also includes a second pad arranged on the base substrate and located in the second binding area, one end of the connecting trace is electrically connected to the first sub-pad and the other end is electrically connected to the second pad, and the insulating protection portion extends from one end of the connecting trace close to the first sub-pad to the other end of the connecting trace close to the second pad.

[0048] In another aspect, a display substrate is provided, comprising a display area and a peripheral area located around the display area, wherein the peripheral area comprises a first binding area; the display substrate comprises:

[0049] a first pad disposed on the base substrate and located in the first binding area, the first pad including a plurality of first sub-pads and a plurality of second sub-pads spaced apart from each other, the plurality of second sub-pads being located on a side of the plurality of first sub-pads close to the display area;

[0050] A driver chip is disposed on the first pad, wherein a side of the driver chip away from the display area protrudes beyond an edge of the first sub-pad;

[0051] a connecting wire, disposed on the base substrate, wherein one end of the connecting wire is electrically connected to the first sub-pad and the other end of the connecting wire is extended in a direction away from the display area;

[0052] an insulating protection portion, located on a side of the connecting wire away from the substrate, the insulating protection portion covering at least a portion of the connecting wire; and

[0053] a sidewall protection portion, at least partially covering the sidewall of the first pad, wherein the sidewall protection portion is made of an insulating material,

[0054] The insulating protection portion and the sidewall protection portion are located in the same layer, and an orthographic projection of the sidewall protection portion on the base substrate at least partially overlaps with an orthographic projection of the driver chip on the base substrate.

[0055] In another aspect, a display device is provided, comprising the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings.

[0057] FIG1 is a schematic cross-sectional view of a display substrate in the related art.

[0058] FIG2 schematically shows a plan view of a display substrate according to an embodiment of the present disclosure.

[0059] FIG3 shows a partial schematic diagram of area B in FIG2 .

[0060] FIG. 4 is a schematic cross-sectional view of a display substrate at a position CC′ in FIG. 3 according to some exemplary embodiments of the present disclosure.

[0061] FIG. 5 is a schematic cross-sectional view of a display substrate at the line FF′ in FIG. 2 according to some exemplary embodiments of the present disclosure.

[0062] FIG. 6 is a schematic cross-sectional view of a display substrate at a position DD′ in FIG. 3 according to some exemplary embodiments of the present disclosure.

[0063] FIG. 7 is a schematic cross-sectional view of a display substrate at the CC′ position in FIG. 3 according to some exemplary embodiments of the present disclosure.

[0064] FIG. 8 is a schematic cross-sectional view of a display substrate at the CC′ position in FIG. 3 according to some exemplary embodiments of the present disclosure.

[0065] FIG. 9 is a schematic cross-sectional view of a display substrate at a position CC′ in FIG. 3 according to some exemplary embodiments of the present disclosure.

[0066] FIG. 10 is a schematic cross-sectional view of a display substrate at the CC′ position in FIG. 3 according to some exemplary embodiments of the present disclosure.

[0067] FIG. 11 is a schematic cross-sectional view of a display substrate at a position CC′ in FIG. 3 according to some exemplary embodiments of the present disclosure. DETAILED DESCRIPTION

[0068] In the following description, for the purpose of explanation, many specific details are set forth to provide a comprehensive understanding of the various exemplary embodiments. However, it is apparent that the various exemplary embodiments can be implemented without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. In addition, the various exemplary embodiments can be different, but not necessarily exclusive. For example, the specific shape, configuration, and characteristics of the exemplary embodiment can be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0069] In the accompanying drawings, the sizes and relative sizes of the elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0070] When an element is described as being "on" another element, "connected to" another element, or "coupled to" another element, the element may be directly on, directly connected to, or directly coupled to another element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to," or "directly coupled to," another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, the Y-axis, and the Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, the Y-axis, and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XY, YZ, and XZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0071] It should be understood that although the terms first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, a first element may be named a second element, and similarly, a second element may be named a first element without departing from the scope of the exemplary embodiments.

[0072] FIG1 is a schematic cross-sectional view of a display substrate in the related art.

[0073] Referring to Figure 1, the pad P used to bind the driver chip IC and the outer pad used to bind the flexible circuit board are connected through the metal trace L. Usually, the metal trace L is partially covered by the planarization layer PLN. However, since the thickness of the planarization layer PLN is relatively thick, in order to avoid interference caused by the planarization layer PLN when binding the driver chip IC, the planarization layer PLN will be spaced apart from the pad P, and the spacing distance is set to be relatively large, which will cause a portion of the metal trace L close to the pad P to be exposed.

[0074] Furthermore, when the driver chip IC is bonded, the outer shell of the driver chip IC extends a certain distance beyond the pad P. The driver chip IC and the pad P are electrically connected via anisotropic conductive film (ACF). ACF is primarily composed of a resin adhesive and conductive particles. The conductive particles are anisotropic and only conduct electricity when under pressure. During the bonding process, pressure is applied to the driver chip IC, squeezing the conductive particles in the ACF and achieving electrical connection between the driver chip IC and the pad P.

[0075] However, the inventors discovered through research that during the pressure-bonding process, the conductive particles within the ACF may be squeezed toward the edge of the driver IC. If the conductive particles happen to get stuck between the driver IC housing and the exposed metal trace L, a short circuit may occur between the driver IC housing and the metal trace L. Furthermore, because the driver IC housing is typically negatively charged, such as -7V, if the shorted metal trace L is a high-level signal trace, such as the analog power supply voltage (Analog VDD, AVDD) trace, the voltage signal on the shorted high-level signal trace will be pulled down, thereby causing display problems.

[0076] Figure 2 schematically shows a plan view of a display substrate according to an embodiment of the present disclosure, Figure 3 shows a partial schematic view of area B in Figure 2, and Figure 4 shows a cross-sectional schematic view of the display substrate at the CC' position in Figure 3 according to some exemplary embodiments of the present disclosure.

[0077] 2 , the display substrate includes a display area AA and a peripheral area NA located around the display area AA. The peripheral area includes first binding areas BA1 and second binding areas BA2 that are spaced apart. The second binding area BA2 is located on a side of the first binding area BA1 away from the display area AA.

[0078] For example, the first binding area BA1 is located outside one side of the display area AA. For example, taking the display substrate applied to a mobile phone as an example, the first binding area is located at the lower side of the display area AA.

[0079] 3 and 4 , the substrate is shown to include a base substrate 100 , a first pad P1 , a second pad P2 , a driver chip IC, connection traces L, and an insulating protection portion Q.

[0080] The first pad P1 is arranged on the base substrate 100 and is located in the first binding area BA1. The first pad P1 includes a plurality of first sub-pads P11 and a plurality of second sub-pads P12 arranged at intervals. The plurality of second sub-pads P12 are located on the side of the plurality of first sub-pads P11 close to the display area AA. For example, the first sub-pad P11 serves as a signal input pad, and the second sub-pad P12 serves as a signal output pad.

[0081] The driver IC is mounted on first pad P1 and has pins. Electrically connecting the pins to pad P1 allows the IC to be attached to the display. For example, the pins include a signal input pin and a signal output pin. The signal input pin is electrically connected to first sub-pad P11, while the signal output pin is electrically connected to second sub-pad P12. The side of the driver IC facing away from the display area protrudes beyond the edge of first sub-pad P11.

[0082] The second pads P2 are disposed on the base substrate 100 and are located in the second bonding area BA2. For example, the display substrate has a plurality of spaced-apart second pads P2 and a plurality of spaced-apart first sub-pads P11. The number of second pads P2 is the same as the number of first sub-pads P11, and the second pads P2 are disposed in a one-to-one correspondence with the first sub-pads P11. The second pads P2 can be used for bonding to the flexible printed circuit board.

[0083] The connecting trace L is arranged on the base substrate 100. One end of the connecting trace L close to the display area AA is electrically connected to the first sub-pad P11, and the other end extends in a direction away from the display area AA and is electrically connected to the second pad P2. The connecting trace L serves as a signal transmission trace between the first sub-pad P11 and the second pad P2.

[0084] The insulating protection portion Q is located on a side of the connecting trace L that is away from the base substrate 100, and the insulating protection portion Q covers at least a portion of the connecting trace L. The orthographic projection of the side of the driver chip IC that is away from the display area AA (see the side indicated by reference numeral B3 in FIG. 3 ) on the base substrate 100 is located within the orthographic projection of the insulating protection portion Q on the base substrate 100, thereby preventing the driver chip IC housing from shorting to the connecting trace L.

[0085] FIG. 5 is a schematic cross-sectional view of a display substrate at the line FF′ in FIG. 2 according to some exemplary embodiments of the present disclosure.

[0086] According to some exemplary embodiments, referring to FIG5 , a display substrate includes a base substrate 100, a driving function layer 200, a light-emitting device layer 300, an encapsulation function layer 400, and a touch function layer 500. The driving function layer 200 is located on the base substrate 100, the light-emitting device layer 300 is located on a side of the driving function layer 200 away from the base substrate 100, the encapsulation function layer 400 is located on a side of the light-emitting device layer 300 away from the driving function layer 200, and the touch function layer 500 is located on a side of the encapsulation function layer 400 away from the light-emitting device layer 300. The first pad P1, the second pad P2, the connection trace L, and the insulating protection portion Q are respectively located in at least one or a portion of the driving function layer 200, the light-emitting device layer 300, the encapsulation function layer 400, and the touch function layer 500.

[0087] For example, the driving function layer 200 includes the following layers stacked on the substrate in a direction away from the substrate: a light shielding layer, an isolation layer, a first buffer layer, a first active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, a first interlayer insulating layer, a second buffer layer, a second active layer, a third gate insulating layer, a third gate metal layer, a second interlayer insulating layer, a first source / drain metal layer, a first passivation layer, a first planarization layer, a second source / drain metal layer, a second planarization layer, a pixel defining layer, and a spacer layer. Exemplarily, the material of the first active layer is low-temperature polysilicon, and the material of the second active layer is selected from metal oxide semiconductor materials, for example, the material of the second active layer is indium gallium zinc oxide.

[0088] For example, the base substrate 100 may be a flexible base substrate, such as a plastic substrate having excellent heat resistance and durability, such as polyvinyl ether phthalate, polyarylate, polyimide (PI), polyethylene terephthalate (PET), polycarbonate (PC), cycloolefin polymer (COP), cellulose acetate propionate (CAP), polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyphenylene sulfide (PPS), polyallyl ester, or cellulose triacetate (TAC). The base substrate 100 may also be a rigid base substrate, such as a glass substrate, which is not limited here.

[0089] For example, the driving function layer 200 includes the following layers stacked on the substrate in a direction away from the substrate: a light shielding layer, an isolation layer, a first buffer layer, a first active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, a first interlayer insulating layer, a second buffer layer, a second active layer, a third gate insulating layer, a third gate metal layer, a second interlayer insulating layer, a first source / drain metal layer, a first passivation layer, a first planarization layer, a second source / drain metal layer, a second passivation layer, a third source / drain metal layer, a second planarization layer, a pixel defining layer, and a spacer layer. Exemplarily, the material of the first active layer is low-temperature polysilicon, and the material of the second active layer is selected from metal oxide semiconductor materials, for example, the material of the second active layer is indium gallium zinc oxide.

[0090] For example, the materials of the isolation layer, the first buffer layer, the second buffer layer, the first gate insulation layer, the second gate insulation layer, the third gate insulation layer, the first interlayer insulation layer, the second interlayer insulation layer, the first passivation layer and the second passivation layer may include inorganic materials such as silicon oxide, silicon nitride, and silicon oxynitride, and their film layer structure may be a single-layer structure or a stacked-layer structure, which is not limited here.

[0091] For example, the materials of the first planarization layer, the second planarization layer, the third planarization layer, the pixel definition layer and the spacer layer can be organic insulating materials such as polyacrylic resin, polyepoxy acrylic resin, photosensitive polyimide resin, polyester acrylate, polyurethane acrylate resin, phenolic epoxy acrylic resin, etc., which are not limited here.

[0092] For example, the first gate metal layer, the second gate metal layer, the third gate metal layer, the first source-drain metal layer, the second source-drain metal layer and the third source-drain metal layer can be made of materials suitable for dry etching, such as molybdenum, aluminum, and titanium. Optionally, these metal film layers can be single-layer metals or stacked metals. Exemplarily, each gate metal layer is a single-layer molybdenum metal, and each source-drain metal layer is a triple-layer composed of a titanium metal layer / an aluminum metal layer / a titanium metal layer.

[0093] For example, the light emitting device layer 300 includes: an anode layer, a light emitting functional layer, and a cathode layer stacked on the driving functional layer in a direction away from the driving functional layer.

[0094] For example, the material of the anode layer can include at least one transparent conductive oxide material, including indium tin oxide, indium zinc oxide, zinc oxide, etc. Furthermore, the anode layer can include a metal with high reflectivity as a reflective layer, such as silver. Exemplarily, the anode layer is a triple stack of an indium zinc oxide layer, a silver layer, and an indium zinc oxide layer.

[0095] For example, the material of the light-emitting functional layer may include a small molecule organic material or a polymer molecule organic material, may be a fluorescent light-emitting material or a phosphorescent light-emitting material, and may emit red light, green light, blue light, or white light.

[0096] For example, the cathode layer may include various conductive materials, such as lithium, aluminum, magnesium, silver, or alloys thereof.

[0097] For example, functional layers such as a hole injection layer and a hole transport layer may be further included between the anode layer and the light-emitting functional layer; functional layers such as an electron injection layer and an electron transport layer may be further included between the cathode layer and the light-emitting layer.

[0098] For example, the encapsulation function layer 400 covers and seals the light emitting device layer 300, thereby reducing or preventing degradation of the light emitting device caused by moisture or oxygen in the environment. The encapsulation layer 400 may be a single layer structure or a composite layer structure including a stacked structure of an inorganic layer and an organic layer.

[0099] For example, the encapsulation layer 400 includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer that are sequentially stacked.

[0100] For example, the materials of the first and second inorganic encapsulation layers may include insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride. Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high density and can prevent the intrusion of water, oxygen, and the like. The material of the organic encapsulation layer may be a polymer material containing a desiccant or a polymer material that can block water vapor, such as a polymer resin, to planarize the surface of the display substrate and relieve stress in the first and second inorganic encapsulation layers. It may also include a desiccant or other water-absorbing material to absorb intrusive water, oxygen, and the like.

[0101] For example, the touch function layer 500 includes: a first touch metal layer, a touch insulating layer, and a second touch metal layer stacked on the encapsulation layer in a direction away from the encapsulation layer.

[0102] For example, the touch function layer 500 includes a touch substrate barrier layer located between the first touch metal layer and the encapsulation layer.

[0103] For example, the materials of the touch insulating layer and the touch base barrier layer may include inorganic materials such as silicon oxide, silicon nitride, and silicon oxynitride, and the film structure thereof may be a single-layer structure or a stacked-layer structure, which is not limited here.

[0104] According to some exemplary embodiments, with reference to FIG3 and FIG4 , the orthographic projection of the insulating protection portion Q on the base substrate 100 has a first edge B1 close to the display area AA and a second edge B2 away from the display area AA, and the orthographic projection of the driver chip IC on the base substrate 100 has a third edge B3 away from the display area AA, and the third edge B3 is located between the first edge B1 and the second edge B2.

[0105] According to some exemplary embodiments, with reference to FIG3 and FIG4 , the display substrate further includes an organic insulating portion N. The organic insulating portion N is located on a side of the connecting trace L away from the base substrate 100 and covers a portion of the connecting trace L. The organic insulating portion N is spaced apart from the first sub-pad P11. The orthographic projection of the organic insulating portion N on the base substrate 100 has a fourth edge B4 proximate to the display area AA, and the second edge B2 is further away from the display area AA than the fourth edge. In other words, the insulating protection portion Q partially overlaps the organic insulating portion N, with the end of the insulating protection portion Q away from the display area AA overlapping the end of the organic insulating portion N proximate to the display area AA.

[0106] For example, the organic insulating portion N is located in the second planarization layer in the driving function layer, and the thickness of the insulating protection portion Q is much smaller than the thickness of the organic insulating portion N.

[0107] According to some exemplary embodiments, referring to FIG. 3 and FIG. 4 , an orthographic projection of the connection trace L on the base substrate 100 has a fifth edge B5 close to the display area AA, and the first edge B1 is flush with the fifth edge B5 .

[0108] According to some exemplary embodiments, a portion of the connection trace L located on a side of the organic insulating portion N close to the display area AA is completely covered by the insulating protection portion Q.

[0109] 4 , the insulating protection portion Q extends from one end of the connection trace L close to the first sub-pad P11 to the other end of the connection trace L close to the second pad P2 . All exposed surfaces of the connection trace L are covered by the insulating protection portion Q.

[0110] According to some exemplary embodiments, referring to FIG. 4 and FIG. 5 , the connection trace L is located in the driving function layer 200 , and the insulating protection portion Q is located in the touch function layer 500 .

[0111] According to some exemplary embodiments, the insulating protection portion Q is located on the touch substrate barrier layer, or the insulating protection portion Q is located on the touch insulation layer, or the insulating protection portion Q is located between the touch insulation layer and the touch substrate barrier layer.

[0112] According to some exemplary embodiments, the first sub-pad P11 includes a first sub-pad portion P111 and a second sub-pad portion P112 located on a side of the first sub-pad portion P111 away from the base substrate 100; the first sub-pad portion P111 is located in at least a portion of the driving metal layer, and the second sub-pad portion P112 is located in at least a portion of the touch function layer 500.

[0113] According to some exemplary embodiments, the first pad sub-portion P111 is located in at least one of the first gate metal layer, the first source / drain metal layer, and the second source / drain metal layer.

[0114] For example, referring to Figure 4, the first pad portion P111 is located in the first gate metal layer, the first source-drain metal layer and the second source-drain metal layer, that is, the first pad portion P111 has three stacked pad portions, including a first pad portion P11a located on the base substrate 100, a second pad portion P11b located on the side of the first pad portion P11a away from the base substrate 100, and a third pad portion P11c located on the side of the second pad portion P11b away from the base substrate 100, wherein the first pad portion P11a is located in the first gate metal layer GATE1, the second pad portion P11b is located in the first source-drain metal layer SD1, and the third pad portion P11c is located in the second source-drain metal layer SD2.

[0115] According to some exemplary embodiments, the first pad sub-portion P111 is located in at least one of the first gate metal layer, the first source / drain metal layer, the second source / drain metal layer, and the third source / drain metal layer.

[0116] For example, the first pad portion P111 is located in the first gate metal layer, the first source / drain metal layer, the second source / drain metal layer, and the third source / drain metal layer, that is, the first pad portion P111 has four pad portions stacked together, including a first pad portion located on the base substrate 100, a second pad portion located on a side of the first pad portion away from the base substrate, a third pad portion located on a side of the second pad portion away from the base substrate, and a fourth pad portion located on a side of the third pad portion away from the base substrate. The first pad portion is located in the first gate metal layer, the second pad portion is located in the first source / drain metal layer, the third pad portion is located in the second source / drain metal layer, and the fourth pad portion is located in the third source / drain metal layer.

[0117] According to some exemplary embodiments, the second pad sub-part P112 is located in at least one of the first touch metal layer and the second touch metal layer. For example, referring to FIG. 4 , the second pad sub-part P112 is located in the second touch metal layer TMB.

[0118] According to some exemplary embodiments, referring to FIG. 4 , the first solder sub-part P111 is located within the first gate metal layer GATE1, the first source / drain metal layer SD1, and the second source / drain metal layer SD2; the second solder sub-part P112 is located within the second touch metal layer TMB. Specifically, when etching to form the second touch metal layer TMB, the portion of the second touch metal layer TMB corresponding to the first sub-pad P11 is retained, forming the second solder sub-part P112. This prevents the surface of the first solder sub-part P111, which is away from the substrate 100, from being exposed and damaged during etching when etching to form the second touch metal layer TMB, thereby increasing bonding resistance.

[0119] FIG. 6 shows a schematic cross-sectional view at the position DD′ in FIG. 3 .

[0120] According to some exemplary embodiments, in combination with reference to FIG6 and FIG4 , the display substrate further includes a sidewall protection portion S, which at least partially covers the side wall of the first sub-pad P11, and the sidewall protection portion S is formed of an insulating material. The orthographic projection of the sidewall protection portion S on the base substrate at least partially overlaps with the orthographic projection of the driver chip IC on the base substrate.

[0121] It should be noted that the first source / drain metal layer, the second source / drain metal layer, and the third source / drain metal layer are usually set as a stacked film layer of titanium / aluminum / titanium. When the first sub-pad P11 is located in at least one of the layers, the etching rate of aluminum is significantly greater than the etching rate of titanium, so that the first sub-pad P11 formed by etching will have an undercut structure at the side wall, that is, the upper and lower titanium layers protrude from the middle aluminum layer. In this undercut structure, there is a risk that the upper titanium layer will collapse and fall off, causing a short circuit. Therefore, a sidewall protection portion S composed of an insulating material is provided on the side wall of the first sub-pad P11 to cover the side wall of the first sub-pad P11, thereby avoiding the problem of the upper titanium layer falling off in the undercut structure.

[0122] According to some exemplary embodiments, the sidewall protection portion S is located on the touch substrate barrier layer, or the sidewall protection portion S is located on the touch insulating layer, or the sidewall protection portion S is located on the touch substrate barrier layer and the touch insulating layer.

[0123] According to some exemplary embodiments, the sidewall protection portion S and the insulating protection portion Q are located in the same layer. That is, the sidewall protection portion S and the insulating protection portion Q are formed by the same film formation and patterning process. For example, the sidewall protection portion S and the insulating protection portion Q are both located in the touch substrate barrier layer, or both in the touch insulation layer, or both in the touch substrate barrier layer and the touch insulation layer.

[0124] According to some exemplary embodiments, referring to FIG. 6 in conjunction with FIG. 4 , first solder sub-part P111 is located on the first gate metal layer GATE1, the first source / drain metal layer SD1, and the second source / drain metal layer SD2; second solder sub-part P112 is located on the second touch metal layer TMB; and sidewall protection portion S and insulation protection portion Q are both located on the touch substrate barrier layer and the touch insulation layer. Therefore, sidewall protection portion S is located between first solder sub-part P111 and second solder sub-part P112, and covers the sidewalls of first solder sub-part P111.

[0125] Furthermore, due to factors such as exposure process accuracy and etching process accuracy during the patterning process, to ensure that the sidewall protection portion S can completely cover the sidewall of the first solder sub-portion P111, the end of the sidewall protection portion S away from the base substrate 100 is extended and disposed on the surface of the first solder sub-portion P111 away from the base substrate 100. In other words, the end of the sidewall protection portion S away from the base substrate 100 is located between the first solder sub-portion P111 and the second solder sub-portion P112.

[0126] According to some exemplary embodiments, the first solder sub-part is located in the first gate metal layer, the first source / drain metal layer, and the second source / drain metal layer; the second solder sub-part is located in the first touch metal layer; and the sidewall protection portion and the insulation protection portion are both located in the touch insulation layer. The sidewall protection portion is located on the side of the second solder sub-part away from the base substrate, and the sidewall protection portion covers the sidewalls of the first and second solder sub-parts. Here, the end of the sidewall protection portion away from the base substrate is located on the surface of the first sub-pad away from the base substrate, that is, the end of the sidewall protection portion away from the base substrate is not located within the first sub-pad, thereby avoiding the problem of cracks in the first sub-pad during pressure bonding.

[0127] According to some exemplary embodiments, a side wall protection portion may also be provided at the side wall of the second sub-pad, that is, the side wall protection portion at least partially covers the side wall of the second sub-pad. The setting method of the side wall protection portion at the side wall of the second sub-pad refers to the side wall protection portion at the side wall of the first sub-pad in the above-mentioned disclosed embodiment, and will not be repeated here.

[0128] According to some exemplary embodiments, referring to FIG. 4 , the connection trace L is a double-layer trace, and the connection trace L includes a first sub-layer L1 and a second sub-layer L2 located on a side of the first sub-layer L1 away from the base substrate 100 .

[0129] According to some exemplary embodiments, the first sublayer L1 is located in the first source-drain metal layer, and the second sublayer L2 is located in the second source-drain metal layer, or the first sublayer L1 is located in the first source-drain metal layer, and the second sublayer L2 is located in the third source-drain metal layer, or the first sublayer L1 is located in the second source-drain metal layer, and the second sublayer L2 is located in the third source-drain metal layer.

[0130] According to some exemplary embodiments, referring to FIG. 4 , the first sublayer L1 is located in the first source / drain metal layer SD1 , the second sublayer L2 is located in the second source / drain metal layer SD2 , and a first passivation layer PV1 is disposed between the first sublayer L1 and the second sublayer L2 .

[0131] According to some exemplary embodiments, the first passivation layer has a via hole, and the first sub-layer L1 and the second sub-layer L2 are overlapped and connected in parallel through the via hole, so as to reduce the impedance of the connection line L.

[0132] According to some exemplary embodiments, the second pad P2 is located on at least a portion of the driving function layer 200 , or the second pad P2 is located on at least a portion of the driving function layer 200 and the touch function layer 500 .

[0133] According to some exemplary embodiments, referring to FIG. 4 , the second pad P2 is located on the first source / drain metal layer SD1 , the second source / drain metal layer SD2 , and the second touch metal layer TMB.

[0134] According to some exemplary embodiments, a sidewall protection portion may also be provided at the sidewall of the second pad P2.

[0135] FIG. 7 is a schematic cross-sectional view of a display substrate at the CC′ position in FIG. 3 according to some exemplary embodiments of the present disclosure.

[0136] According to some exemplary embodiments, referring to FIG. 7 , the first sub-pad P11 is located only on the driving function layer 200 , that is, the first sub-pad P11 is located on at least a portion of the driving metal layer.

[0137] According to some exemplary embodiments, the first sub-pad P11 is located in at least one of the first gate metal layer, the first source / drain metal layer, and the second source / drain metal layer.

[0138] For example, referring to Figure 7, the first sub-pad P11 is located in the first gate metal layer GATE1, the first source and drain metal layer SD1 and the second source and drain metal layer SD2, that is, the first sub-pad P11 has three stacked pad portions, including a first pad portion P11a located on the base substrate 100, a second pad portion P11b located on the side of the first pad portion P11a away from the base substrate 100, and a third pad portion P11c located on the side of the second pad portion P11b away from the base substrate 100, wherein the first pad portion P11a is located in the first gate metal layer GATE1, the second pad portion P11b is located in the first source and drain metal layer SD1, and the third pad portion P11c is located in the second source and drain metal layer SD2.

[0139] In this structure, to avoid etching damage to the surface of the first sub-pad P11 when forming the second touch metal layer, the display substrate preparation process was adjusted. At least one of the touch base barrier layer and the touch insulation layer was adjusted to be formed using a double patterning process.

[0140] For example, a touch substrate barrier layer is formed through two patterning processes. In the first patterning process, the portion of the touch substrate barrier layer located on the upper surface of the first sub-pad P11 is retained as an etching barrier structure. After the second touch metal layer is etched to form the second touch metal layer, the portion of the touch substrate barrier layer located on the upper surface of the first sub-pad P11 is etched away in the second patterning process.

[0141] According to some exemplary embodiments, the first sub-pad P11 is located in at least one of the first gate metal layer, the first source / drain metal layer, the second source / drain metal layer, and the third source / drain metal layer.

[0142] FIG8 shows a schematic cross-sectional view of a display substrate at the position C-C' in FIG3 according to some exemplary embodiments of the present disclosure; FIG9 shows a schematic cross-sectional view of a display substrate at the position C-C' in FIG3 according to some exemplary embodiments of the present disclosure; and FIG10 shows a schematic cross-sectional view of a display substrate at the position C-C' in FIG3 according to some exemplary embodiments of the present disclosure.

[0143] For example, referring to FIG8, FIG9, or FIG10, the first sub-pad P11 is located in the first gate metal layer GATE1, the first source / drain metal layer SD1, the second source / drain metal layer SD2, and the third source / drain metal layer SD3. That is, the first sub-pad P11 has four stacked pad portions, including a first pad portion P11a located on the base substrate 100, a second pad portion P11b located on a side of the first pad portion P11a away from the base substrate 100, a third pad portion P11c located on a side of the second pad portion P11b away from the base substrate 100, and a fourth pad portion P11d located on a side of the third pad portion P11c away from the base substrate 100. The first pad portion P11a is located in the first gate metal layer GATE1, the second pad portion P11b is located in the first source / drain metal layer SD1, the third pad portion P11c is located in the second source / drain metal layer SD2, and the fourth pad portion P11d is located in the third source / drain metal layer SD3.

[0144] According to some exemplary embodiments, referring to FIG. 7 to FIG. 10 , the display substrate further includes a sidewall protection portion S, and the sidewall protection portion S at least partially covers the sidewall of the first sub-pad P11 .

[0145] According to some exemplary embodiments, the sidewall protection portion S is located on the touch substrate barrier layer, or on the touch insulation layer, or between the touch substrate barrier layer and the touch insulation layer. The sidewall protection portion S is located on the side of the first sub-pad P11 away from the base substrate 100, completely covering the sidewall of the first sub-pad P11. The end of the sidewall protection portion S away from the base substrate 100 is located on the side of the first sub-pad P11 away from the base substrate 100. In other words, the end of the sidewall protection portion S away from the base substrate 100 is not located within the first sub-pad P11, thereby preventing cracks in the first sub-pad P11 during pressurized bonding.

[0146] According to some exemplary embodiments, referring to FIG. 7 to FIG. 10 , the connection trace L is a double-layer trace, and the connection trace L includes a first sub-layer L1 and a second sub-layer L2 located on a side of the first sub-layer L1 away from the base substrate 100 .

[0147] According to some exemplary embodiments, referring to FIG. 7 , FIG. 9 , or FIG. 10 , the first sub-layer L1 is located in the first source / drain metal layer SD1 , and the second sub-layer L2 is located in the second source / drain metal layer SD2 .

[0148] According to some exemplary embodiments, referring to FIG. 8 , the first sublayer L1 is located on the second source / drain metal layer SD2 , the second sublayer L2 is located on the third source / drain metal layer SD3 , and a second passivation layer PV2 is provided between the first sublayer L1 and the second sublayer L2 .

[0149] According to some exemplary embodiments, the second passivation layer has a via hole, and the first sub-layer L1 and the second sub-layer L2 are overlapped and connected in parallel through the via hole, so as to reduce the impedance of the connection line L.

[0150] According to some exemplary embodiments, the second pad P2 is located on the driving function layer 200 , that is, the second pad P2 is located on at least a portion of the driving metal layer.

[0151] According to some exemplary embodiments, the second pad P2 is located in at least one of the first gate metal layer, the first source / drain metal layer, and the second source / drain metal layer.

[0152] According to some exemplary embodiments, the second pad P2 is located in at least one of the first gate metal layer, the first source / drain metal layer, the second source / drain metal layer, and the third source / drain metal layer.

[0153] For example, referring to Figure 7, the second pad P2 is located in the first source-drain metal layer SD1 and the second source-drain metal layer SD2, that is, the second pad P2 has two stacked pad portions, the pad portion close to the base substrate 100 is located in the first source-drain metal layer SD1, and the pad portion away from the base substrate 100 is located in the second source-drain metal layer SD2.

[0154] For example, referring to Figure 8, the second pad P2 is located in the second source and drain metal layer SD2 and the third source and drain metal layer SD3, that is, the second pad P2 has two stacked pad portions, the pad portion close to the base substrate 100 is located in the second source and drain metal layer SD2, and the pad portion away from the base substrate 100 is located in the third source and drain metal layer SD3.

[0155] For example, referring to Figure 9, the second pad P2 is located at the first gate metal layer GATE1, the first source-drain metal layer SD1, the second source-drain metal layer SD2 and the third source-drain metal layer SD3, that is, the second pad P2 has four stacked pad portions, the pad portion closest to the base substrate 100 is located at the first gate metal layer GATE1, the two middle pad portions are located at the first source-drain metal layer SD1 and the second source-drain metal layer SD2 respectively, and the pad portion farthest from the base substrate 100 is located at the third source-drain metal layer SD3.

[0156] For example, referring to Figure 10, the second pad P2 is located in the first gate metal layer GATE1, the first source and drain metal layer SD1, and the second source and drain metal layer SD2, that is, the second pad P2 has three stacked pad portions, the pad portion closest to the base substrate 100 is located in the first gate metal layer GATE1, the middle pad portion is located in the first source and drain metal layer SD1, and the pad portion farthest from the base substrate 100 is located in the second source and drain metal layer SD2.

[0157] According to some exemplary embodiments, a sidewall protection portion is also provided on the sidewall of the second pad P2 .

[0158] According to some exemplary embodiments, the connection traces L and the insulating protection portion Q are both located in the driving function layer 200 .

[0159] FIG. 11 is a schematic cross-sectional view of a display substrate at a position CC′ in FIG. 3 according to some exemplary embodiments of the present disclosure.

[0160] According to some exemplary embodiments, referring to FIG. 11 , the connecting trace L includes a first sublayer L1 and a second sublayer L2. The first sublayer L1 is directly connected to the first subpad P11. The second sublayer L2 is located on a side of the first sublayer L1 away from the base substrate 100. The second sublayer L2 is spaced apart from the first subpad P11 and exposes a first portion L11 of the first sublayer L1. The insulating protection portion Q is located on a side of the first sublayer L1 away from the base substrate 100 and covers at least the first portion L11 of the first sublayer L1.

[0161] According to some exemplary embodiments, the insulating protection portion Q is located between the first sub-layer L1 and the second sub-layer L2. The insulating protection portion Q has a via H. The via H is located on a side of the first portion L11 away from the first sub-pad P11. The first sub-layer L1 and the second sub-layer L2 are overlapped through the via H. The first sub-layer L1 and the second sub-layer L2 are overlapped at the via H to achieve parallel connection, thereby reducing the impedance of the connecting trace L.

[0162] According to some exemplary embodiments, referring to FIG. 11 , the first sublayer L1 is located in the first source / drain metal layer SD1 , the second sublayer L2 is located in the second source / drain metal layer SD2 , and the insulating protection portion Q is located in the first passivation layer PV1 .

[0163] According to some exemplary embodiments, the first sublayer L1 is located in the first source / drain metal layer, the second sublayer L2 is located in the third source / drain metal layer, and the insulating protection portion Q is located in the first passivation layer or the second passivation layer.

[0164] According to some exemplary embodiments, the first sublayer L1 is located in the second source / drain metal layer, the second sublayer L2 is located in the third source / drain metal layer, and the insulating protection portion Q is located in the second passivation layer.

[0165] According to some exemplary embodiments, the first sub-pad P11 is located in at least one of the first gate metal layer, the first source / drain metal layer, and the second source / drain metal layer.

[0166] For example, referring to Figure 11, the first sub-pad P11 is located in the first gate metal layer, the first source-drain metal layer and the second source-drain metal layer, that is, the first sub-pad P11 has three stacked pad portions, including a first pad portion P11a located on the base substrate 100, a second pad portion P11b located on the side of the first pad portion P11a away from the base substrate 100, and a third pad portion P11c located on the side of the second pad portion P11b away from the base substrate 100, wherein the first pad portion P11a is located in the first gate metal layer GATE1, the second pad portion P11b is located in the first source-drain metal layer SD1, and the third pad portion P11c is located in the second source-drain metal layer SD2.

[0167] According to some exemplary embodiments, the first sub-pad P11 is located in at least one of the first gate metal layer, the first source / drain metal layer, the second source / drain metal layer, and the third source / drain metal layer.

[0168] For example, the first sub-pad P11 is located in the first gate metal layer, the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer. That is, the first sub-pad P11 has four stacked pad portions, including a first pad portion located on the base substrate 100, a second pad portion located on a side of the first pad portion away from the base substrate, a third pad portion located on a side of the second pad portion away from the base substrate, and a fourth pad portion located on a side of the third pad portion away from the base substrate. The first pad portion is located in the first gate metal layer, the second pad portion is located in the first source-drain metal layer, the third pad portion is located in the second source-drain metal layer, and the fourth pad portion is located in the third source-drain metal layer.

[0169] According to some exemplary embodiments, referring to FIG. 11 , the second pad P2 is located between the first source / drain metal layer SD1 and the second source / drain metal layer SD2 .

[0170] In another aspect, a display device is provided, comprising the display substrate described above. The display device may be a display device such as a liquid crystal display, electronic paper, or an OLED (Organic Light-Emitting Diode) display, as well as any product or component with touch and display functions, such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, or navigation system, that includes such a display device.

[0171] It should be understood that the display devices according to some exemplary embodiments of the present disclosure have all the features and advantages of the above-mentioned display substrate. These features and advantages can be referred to in the above description of the display substrate and will not be repeated here.

[0172] It should be understood that the display devices according to some exemplary embodiments of the present disclosure have all the features and advantages of the above-mentioned display substrate. These features and advantages can be referred to in the above description of the display substrate and will not be repeated here.

[0173] As used herein, the terms "substantially," "about," "approximately," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately," as used herein, are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0174] Although some embodiments according to the general inventive concept of the present disclosure have been illustrated and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, characterized in that, The display substrate includes a display area and a peripheral area located around the display area, and the peripheral area includes a first bonding area; the display substrate includes: A substrate; A first pad, disposed on the substrate and located in the first bonding area, the first pad includes a plurality of first sub-pads and a plurality of second sub-pads arranged at intervals, and the plurality of second sub-pads are located on a side of the plurality of first sub-pads closer to the display area; A driving chip, disposed on the first pad, and a side of the driving chip away from the display area protrudes beyond the edge of the first sub-pad; A connecting trace, disposed on the substrate, one end of the connecting trace is electrically connected to the first sub-pad and the other end extends in a direction away from the display area; and An insulating protection part, located on a side of the connecting trace away from the substrate, and the insulating protection part covers at least a part of the connecting trace; Wherein, a positive projection of the side of the driving chip away from the display area on the substrate is located within a positive projection of the insulating protection part on the substrate.

2. The display substrate according to claim 1, wherein The positive projection of the insulating protection part on the substrate has a first edge close to the display area and a second edge away from the display area, and the positive projection of the driving chip on the substrate has a third edge away from the display area, and the third edge is located between the first edge and the second edge.

3. The display substrate according to claim 1, wherein The display substrate further includes an organic insulating part, the organic insulating part is located on a side of the connecting trace away from the substrate and covers a part of the connecting trace, the organic insulating part is arranged at intervals with the first sub-pad, and the positive projection of the organic insulating part on the substrate has a fourth edge close to the display area, and the second edge is farther from the display area than the fourth edge; And / or The positive projection of the connecting trace on the substrate has a fifth edge close to the display area, and the first edge is flush with the fifth edge.

4. The display substrate according to claims 1 to 3, characterized in that The display substrate includes: A driving functional layer, located on the substrate, and the driving functional layer includes multiple driving metal layers; and A touch functional layer, located on a side of the driving functional layer away from the substrate.

5. The display substrate according to claim 4, wherein The connecting trace is located in the driving functional layer, and the insulating protection part is located in the touch functional layer.

6. The display substrate according to claim 5, wherein The touch functional layer includes a touch substrate barrier layer located on a side of the driving functional layer away from the substrate, a first touch metal layer located on a side of the touch substrate barrier layer away from the driving functional layer, a touch insulating layer located on a side of the first touch metal layer away from the touch substrate barrier layer, and a second touch metal layer located on a side of the touch insulating layer away from the first touch metal layer; Wherein, the insulating protection part is located in at least one of the touch substrate barrier layer and the touch insulating layer.

7. The display substrate according to claim 5 or 6, characterized in that, The first sub-pad includes a first pad sub-part and a second pad sub-part located on a side of the first pad sub-part away from the substrate; The first pad sub-part is located in at least part of the driving metal layer, and the second pad sub-part is located in the touch functional layer.

8. The display substrate according to claim 7, wherein, The multiple driving metal layers include a first gate metal layer located on the substrate, a first source-drain metal layer located on a side of the first gate metal layer away from the substrate, and a second source-drain metal layer located on a side of the first source-drain metal layer away from the first gate metal layer; wherein, the first pad sub-part is located on at least one of the first gate metal layer, the first source-drain metal layer, and the second source-drain metal layer; or The multiple driving metal layers include a first gate metal layer located on the substrate, a first source-drain metal layer located on a side of the first gate metal layer away from the substrate, a second source-drain metal layer located on a side of the first source-drain metal layer away from the first gate metal layer, and a third source-drain metal layer located on a side of the second source-drain metal layer away from the first source-drain metal layer; wherein, the first pad sub-part is located on at least one of the first gate metal layer, the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer.

9. The display substrate according to claim 7, wherein The touch function layer includes a first touch metal layer and a second touch metal layer located on a side of the first touch metal layer away from the substrate; wherein, the second pad sub-part is located on at least one of the first touch metal layer and the second touch metal layer.

10. The display substrate according to claim 5 or 6, characterized in that, The first sub-pad is located on at least a part of the driving metal layer.

11. The display substrate according to claim 10, wherein The multiple driving metal layers include a first gate metal layer located on the substrate, a first source-drain metal layer located on a side of the first gate metal layer away from the substrate, and a second source-drain metal layer located on a side of the first source-drain metal layer away from the first gate metal layer; wherein, the first sub-pad is located on at least one of the first gate metal layer, the first source-drain metal layer, and the second source-drain metal layer; or The multiple driving metal layers include a first gate metal layer located on the substrate, a first source-drain metal layer located on a side of the first gate metal layer away from the substrate, a second source-drain metal layer located on a side of the first source-drain metal layer away from the first gate metal layer, and a third source-drain metal layer located on a side of the second source-drain metal layer away from the first source-drain metal layer; wherein, the first sub-pad is located on at least one of the first gate metal layer, the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer.

12. The display substrate according to claim 4, wherein, The connection trace is located in the driving function layer, and the insulation protection part is located in the driving function layer.

13. The display substrate according to claim 12, wherein The connection trace includes: a first sub-layer, directly connected adjacent to the first sub-pad; a second sub-layer, located on a side of the first sub-layer away from the substrate, the second sub-layer being spaced apart from the first sub-pad and exposing a first part of the first sub-layer; wherein, the insulation protection part is located on a side of the first sub-layer away from the substrate and at least covers the first part of the first sub-layer.

14. The display substrate according to claim 13, wherein The insulation protection part is located between the first sub-layer and the second sub-layer, the insulation protection part has a via hole, the via hole is located on a side of the first part away from the first sub-pad, and the first sub-layer and the second sub-layer are overlapped through the via hole.

15. The display substrate according to claim 13 or 14, wherein The driving functional layer includes a first source-drain metal layer, a first passivation layer located on a side of the first source-drain metal layer away from the substrate, and a second source-drain metal layer located on a side of the first passivation layer away from the first source-drain metal layer; Wherein, the first sub-layer is located in the first source-drain metal layer, the second sub-layer is located in the second source-drain metal layer, and the insulation protection part is located in the first passivation layer; or The driving functional layer includes a first source-drain metal layer, a first passivation layer located on a side of the first source-drain metal layer away from the substrate, a second source-drain metal layer located on a side of the first passivation layer away from the first source-drain metal layer, a second passivation layer located on a side of the second source-drain metal layer away from the first passivation layer, and a third source-drain metal layer located on a side of the second passivation layer away from the second source-drain metal layer; Wherein, the first sub-layer is located in the first source-drain metal layer, the second sub-layer is located in the second source-drain metal layer, and the insulation protection part is located in the first passivation layer; or, the first sub-layer is located in the second source-drain metal layer, the second sub-layer is located in the third source-drain metal layer, and the insulation protection part is located in the second passivation layer.

16. The display substrate according to any one of claims 1-3, characterized in that, The display substrate further includes a sidewall protection part, at least part of which covers the sidewall of the first sub-pad, and the sidewall protection part is made of an insulating material.

17. The display substrate according to any one of claims 5-11, characterized in that, The display substrate further includes a sidewall protection part, at least part of which covers the sidewall of the first sub-pad, and the sidewall protection part and the insulation protection part are located on the same layer.

18. The display substrate according to any one of claims 4-17, characterized in that, The peripheral area further includes a second bonding area, which is located on a side of the first bonding area away from the display area; The display substrate further includes a second pad disposed on the substrate and located in the second bonding area. One end of the connection trace is electrically connected to the first sub-pad and the other end is electrically connected to the second pad. The insulation protection part extends from one end of the connection trace near the first sub-pad to the other end of the connection trace near the second pad.

19. A display substrate, characterized in that, The display substrate includes a display area and a peripheral area located around the display area. The peripheral area includes a first bonding area; the display substrate includes: A first pad disposed on the substrate and located in the first bonding area. The first pad includes a plurality of first sub-pads and a plurality of second sub-pads arranged at intervals. The plurality of second sub-pads are located on a side of the plurality of first sub-pads close to the display area; A driving chip disposed on the first pad, and a side of the driving chip away from the display area protrudes beyond the edge of the first sub-pad; A connection trace disposed on the substrate, one end of the connection trace is electrically connected to the first sub-pad and the other end extends in a direction away from the display area; An insulation protection part located on a side of the connection trace away from the substrate, and the insulation protection part covers at least a part of the connection trace; and A sidewall protection part at least partially covers the sidewall of the first pad, and the sidewall protection part is made of an insulating material, Among them, the insulation protection part and the sidewall protection part are located on the same layer, and the orthographic projection of the sidewall protection part on the substrate at least partially overlaps with the orthographic projection of the driving chip on the substrate.

20. A display device, characterized in that, The display device includes the display substrate according to any one of claims 1-19.

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