Display substrate, display device and manufacturing method

Abstract

The embodiment of the invention provides a display substrate, a display device and a manufacturing method. The display substrate comprises a driving circuit layer which comprises a plurality of pixel driving circuits; at least one pixel driving circuit in the plurality of pixel driving circuits comprises at least one storage capacitor; the storage capacitor comprises two polar plates which are oppositely arranged; the light-emitting structure layer comprises an anode layer and a pixel definition layer; wherein the anode layer comprises a plurality of anodes; the pixel definition layer comprises a plurality of sub-pixel openings; at least one anode of the plurality of anodes includes: a first anode portion located in at least one sub-pixel opening of the plurality of sub-pixel openings; wherein the orthographic projection, on the substrate, of at least one polar plate in at least one storage capacitor and the orthographic projection, on the substrate, of at least one first anode part have a first overlapping area, and the first overlapping area is an axial symmetry pattern.

Description

Display substrate, display device, and manufacturing method Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate, a display device and a manufacturing method. Background Art

[0002] With technological advancements and shifting consumer trends in the consumer electronics industry, mobile phone display modules have gradually transitioned from liquid crystal display (LCD) displays to organic light-emitting diode (OLED) displays. OLED product form factors have also evolved from rigid products of previous years to flexible products today. Furthermore, OLED products are achieving ever-increasing resolutions and refresh rates (frame rates), while pixel driver structures are becoming increasingly complex. This in turn leads to increasingly stringent requirements for product performance.

[0003] Existing OLED products have an asymmetric design of the wiring under the anode of each sub-pixel, which makes it uneven and tilted. In the black screen state, white light shining on the surface of the display panel will cause color separation problems, affecting the display effect.

[0004] Summary of the Invention

[0005] The present disclosure provides a display substrate, a display device, and a manufacturing method. The display substrate includes:

[0006] substrate;

[0007] A driving circuit layer, located on one side of the substrate, includes: a plurality of pixel driving circuits; at least one pixel driving circuit among the plurality of pixel driving circuits includes: at least one storage capacitor; the storage capacitor includes two plates arranged opposite to each other;

[0008] The light emitting structure layer is located on a side of the driving circuit layer facing away from the substrate, and includes an anode layer and a pixel definition layer; wherein the anode layer includes a plurality of anodes; the pixel definition layer includes a plurality of sub-pixel openings; at least one of the plurality of anodes includes a first anode portion located in at least one of the plurality of sub-pixel openings;

[0009] The orthographic projection of at least one electrode plate in at least one storage capacitor on the substrate has a first overlapping region with the orthographic projection of at least one first anode portion on the substrate, and the first overlapping region is an axisymmetric pattern.

[0010] In a possible implementation, the orthographic projection of the plate close to the anode in the storage capacitor on the substrate and the orthographic projection of the first anode portion on the substrate have the first overlapping region, and the first overlapping region is an axisymmetric pattern.

[0011] In a possible implementation, the orthographic projection of the electrode plate on the substrate is an axisymmetric pattern, the orthographic projection of the first anode portion on the substrate is an axisymmetric pattern, and the symmetry axis of the electrode plate coincides with the symmetry axis of the first anode portion.

[0012] In a possible implementation manner, an orthographic projection of at least one of the first anode portions on the substrate has the first overlapping region with the plate of at least one of the storage capacitors in the same pixel driving circuit.

[0013] In a possible implementation, the pixel driving circuit includes: a first storage capacitor and a second storage capacitor; the orthographic projection area of ​​the first storage capacitor on the substrate is larger than the orthographic projection area of ​​the second storage capacitor on the substrate;

[0014] The orthographic projection of the first anode portion on the substrate has the first overlapping region with the orthographic projection of only one of the first storage capacitor and the second storage capacitor on the substrate.

[0015] In one possible embodiment, the plurality of anodes include: a first anode, a second anode, and a third anode; the wavelength range of the outgoing light in the region where the first anode is located is greater than the wavelength range of the outgoing light in the region where the second anode is located; the wavelength range of the outgoing light in the region where the second anode is located is greater than the wavelength range of the outgoing light in the region where the third anode is located;

[0016] The orthographic projection of the first anode portion of the second anode on the substrate has an overlapping area only with the orthographic projection of the second storage capacitor on the substrate; the orthographic projection of the first anode portion of the first anode on the substrate has an overlapping area only with the orthographic projection of the first storage capacitor on the substrate; the orthographic projection of the first anode portion of the third anode on the substrate has an overlapping area only with the orthographic projection of the first storage capacitor on the substrate.

[0017] In a possible implementation, the pixel driving circuit includes: a first storage capacitor and a second storage capacitor; the orthographic projection area of ​​the first storage capacitor on the substrate is larger than the orthographic projection area of ​​the second storage capacitor on the substrate;

[0018] The orthographic projection of the first anode portion on the substrate has an overlapping area with the orthographic projections of the first storage capacitor and the second storage capacitor on the substrate.

[0019] In one possible embodiment, the orthographic projection of the first anode portion on the substrate and the orthographic projection of the plate on the substrate in the first storage capacitor have a first capacitor overlapping region; the orthographic projection of the first anode portion on the substrate and the orthographic projection of the plate on the substrate in the second storage capacitor have a second capacitor overlapping region; the first overlapping region includes the first capacitor overlapping region and the second capacitor overlapping region;

[0020] The area of ​​the first capacitor overlapping region is greater than the area of ​​the second capacitor overlapping region.

[0021] In a possible implementation manner, the area of ​​the first capacitor overlapping region is 1.1 to 1.5 times the area of ​​the second capacitor overlapping region.

[0022] In a possible implementation manner, an orthographic projection of at least one of the first anode portions on the substrate and the plates of at least two storage capacitors in two adjacent pixel driving circuits both have the first overlapping region.

[0023] In one possible embodiment, the plurality of anodes include: a first anode, a second anode, and a third anode; the wavelength range of the outgoing light in the region where the first anode is located is greater than the wavelength range of the outgoing light in the region where the second anode is located; the wavelength range of the outgoing light in the region where the second anode is located is greater than the wavelength range of the outgoing light in the region where the third anode is located;

[0024] The first anode portion of the first anode includes: two first sub-anode portions arranged adjacent to each other along the first direction, and the two first sub-anode portions are symmetrically distributed; the first anode portion of the second anode includes: two second sub-anode portions arranged adjacent to each other along the first direction, and the two second sub-anode portions are symmetrically distributed; the first anode portion of the third anode includes: two third sub-anode portions arranged adjacent to each other along the first direction, and the two third sub-anode portions are symmetrically distributed.

[0025] In a possible implementation, the first anode and the second anode are arranged along the second direction; the first anode and the third anode are arranged along the first direction;

[0026] The third sub-anode portion has two outer edges extending along the first direction, wherein the extension line of one of the outer edges has an overlapping area with the orthographic projection of the first sub-anode portion on the substrate, and wherein the other outer edge has an overlapping area with the orthographic projection of the second sub-anode portion on the substrate.

[0027] In a possible implementation, the display substrate further includes: a first power line extending along the second direction; an orthographic projection of the first power line on the substrate covers an orthographic projection of the first anode portion on the substrate.

[0028] In a possible implementation, the display substrate further includes: a plurality of metal pattern blocks; the orthographic projections of the metal pattern blocks on the substrate cover the orthographic projections of the first anode portion on the substrate.

[0029] In a possible implementation, the display substrate further includes: a plurality of connecting portions; and different metal pattern blocks are connected via the connecting portions.

[0030] In a possible embodiment, the display substrate further includes: a color filter layer located on the side of the light-emitting structure layer away from the driving circuit layer; the color filter layer includes a plurality of color resist portions; the orthographic projection of the color resist portion on the substrate has an overlapping area with the orthographic projection of the first anode portion on the substrate.

[0031] In a possible embodiment, the display substrate further includes: a first black matrix layer located on a side of the color filter layer facing the light emitting structure layer, and a second black matrix layer located on a side of the color filter layer facing away from the light emitting structure layer;

[0032] The orthographic projection of the second black matrix layer on the substrate covers at least a portion of the boundary of the color resist portion.

[0033] In a possible implementation, the display substrate includes: a first display area, a second display area, and a third display area; the second display area is provided with a fingerprint recognition device, and the third display area is provided with a camera component;

[0034] The area of ​​the first overlapping region of the first display area is larger than that of the first overlapping region of the third display area; the area of ​​the first overlapping region of the second display area is larger than that of the first overlapping region of the third display area.

[0035] An embodiment of the present disclosure further provides a display panel, which includes the display substrate provided by the embodiment of the present disclosure.

[0036] An embodiment of the present disclosure further provides a display device, which includes the display substrate provided by the embodiment of the present disclosure.

[0037] The present disclosure also provides a method for manufacturing the display substrate provided in the embodiment of the present disclosure, which includes:

[0038] A driving circuit layer is formed on one side of the substrate, wherein the driving circuit layer includes at least one storage capacitor; the storage capacitor includes two plates arranged opposite to each other;

[0039] A light-emitting structure layer is formed on the side of the driving circuit layer facing away from the substrate, and the light-emitting structure layer includes: a plurality of first anode portions; wherein, the orthographic projection of at least one plate in at least one of the storage capacitors on the substrate has a first overlapping area with the orthographic projection of at least one of the first anode portions on the substrate, and the first overlapping area is an axially symmetrical pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] FIG1 is a schematic structural diagram of a display device;

[0041] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0042] FIG3 is a schematic diagram of a cross-sectional structure of a display substrate;

[0043] FIG4 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0044] FIG5 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0045] FIG6 is an enlarged view of the first storage capacitor and the second storage capacitor region in FIG5 ;

[0046] FIG7 is a schematic diagram of a display substrate after a semiconductor layer pattern is formed according to the present disclosure;

[0047] FIG8A is a schematic diagram of a display substrate after forming a first conductive layer pattern according to the present disclosure;

[0048] FIG8B is a schematic diagram of the first conductive layer pattern in FIG8A ;

[0049] FIG9A is a schematic diagram of a display substrate after forming a second conductive layer pattern according to the present disclosure;

[0050] FIG9B is a schematic diagram of the second conductive layer pattern in FIG9A ;

[0051] FIG10 is a schematic diagram of a display substrate after a fourth insulating layer pattern is formed according to the present disclosure;

[0052] FIG11A is a schematic diagram of a display substrate after a third conductive layer pattern is formed thereon according to the present disclosure;

[0053] FIG11B is a schematic diagram of a third conductive layer pattern in FIG11A ;

[0054] FIG12 is a schematic diagram of a display substrate after a fifth insulating layer pattern is formed according to the present disclosure;

[0055] FIG13 is a schematic diagram of a display substrate after a fourth conductive layer pattern is formed according to the present disclosure;

[0056] FIG14 is a schematic diagram of a fourth conductive layer pattern in FIG13 ;

[0057] FIG15 shows light reflection from an anode in a related array substrate;

[0058] FIG16 shows color separation occurring in a related array substrate;

[0059] FIG17 is a schematic diagram of a display substrate according to an embodiment of the present disclosure;

[0060] FIG18A is a second schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0061] FIG18B is a third schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0062] FIG19 is a fourth schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0063] FIG20 is a fifth schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0064] FIG21 is a sixth schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0065] FIG22 is a schematic diagram of a stack of a first power line and a first anode portion provided by an embodiment of the present disclosure;

[0066] FIG23A is a seventh schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0067] FIG23B is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure;

[0068] FIG24A is an eighth schematic diagram of a display substrate provided by an embodiment of the present disclosure;

[0069] FIG24B is a schematic diagram of a single film of the anode layer in FIG24A;

[0070] FIG24C is a schematic diagram of a single film layer of the metal pattern block in FIG24A;

[0071] FIG25 is a second schematic cross-sectional view of a display substrate provided in an embodiment of the present disclosure;

[0072] FIG26 is a schematic top view of a display substrate provided in an embodiment of the present disclosure;

[0073] FIG27 is a schematic diagram of a manufacturing process of a display substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0074] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure. The implementation methods can be implemented in multiple different forms. Ordinary technicians in the relevant technical field can easily understand the fact that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following implementation methods. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other in any way.

[0075] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0076] As used herein, "approximately" or "substantially the same" or "substantially axisymmetric" include the stated values ​​and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "substantially the same" or "substantially axisymmetric" may mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, or 5%. In this specification, "substantially the same" or "substantially axisymmetric" may refer to situations where the values ​​differ by less than 10%. Therefore, in this specification, to avoid redundancy, "the same" includes the situation of "substantially the same" and "axisymmetric" includes the situation of "substantially axisymmetric."

[0077] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0078] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0079] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0080] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with one or more functions.

[0081] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode (gate), a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0082] The gate of a transistor can also be referred to as the control electrode. The functions of the "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source electrode" and "drain electrode" may be interchanged.

[0083] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus includes a state where the angle is greater than 85° and less than 95°.

[0084] In this specification, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0085] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0086] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0087] FIG1 is a schematic diagram of the structure of a display device. As shown in FIG1 , the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is respectively connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a per-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured as a shift register and may generate emission signals by sequentially transmitting emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. o may be a natural number. In an exemplary embodiment, the pixel array may be provided on a display substrate.

[0088] Figure 2 is a schematic diagram of a planar structure of a display substrate. In an exemplary embodiment, the display substrate may include a display area and a frame area located around the display area. As shown in Figure 2, the display area of ​​the display substrate may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, and a third sub-pixel P3 that emits a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting unit may include at least a light-emitting device. The light-emitting device is respectively connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0089] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, and the third subpixel P3 may be a green subpixel (G) that emits green light. In an exemplary embodiment, the subpixels may be rectangular, diamond-shaped, pentagonal, or hexagonal, and the three subpixels may be arranged horizontally, vertically, or in a triangular pattern, although this disclosure is not limited thereto.

[0090] In an exemplary embodiment, a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in the present disclosure.

[0091] FIG3 is a schematic cross-sectional view of a display substrate, illustrating the structure of three sub-pixels in the display substrate. As shown in FIG3 , in a plane perpendicular to the display substrate, the display area of ​​the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 away from the substrate 101, a black matrix BM (for example, the black matrix BM may include at least one of black matrix BM1 and black matrix BM2) and a color filter CF disposed on a side of the encapsulation structure layer 104 away from the substrate 101, and an encapsulation layer OC located on the side of the black matrix BM and color filter CF away from the encapsulation layer EN. The driving circuit layer 102 may include multiple thin-film transistors TFT; the light-emitting structure layer 103 may include multiple light-emitting elements LE, each of the multiple light-emitting elements LE including a corresponding anode from a plurality of anodes AD, a light-emitting layer EL located on the side of the corresponding anode away from the substrate 101, and a cathode CD located on the side of the light-emitting layer EL away from the corresponding anode. The corresponding anode is connected to a corresponding thin film transistor in the plurality of thin film transistors TFT. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in the present disclosure.

[0092] In an exemplary embodiment, substrate 101 may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0093] In an exemplary embodiment, the driving circuit layer 102 may include multiple circuit units, each of which may include at least a pixel driving circuit, which may include multiple transistors and storage capacitors. The light-emitting structure layer 103 may include multiple light-emitting units, each of which may include at least a light-emitting device, which may include an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color when driven by the anode and cathode.

[0094] In an exemplary embodiment, the encapsulation structure layer 104 may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0095] In exemplary embodiments, the organic light-emitting layer may include an emission layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0096] The display substrate of the present disclosure is described below by way of some exemplary embodiments.

[0097] FIG4 is an equivalent circuit diagram of a pixel driving circuit of an exemplary embodiment of the present disclosure. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 8T1C, 8T2C, or 9T2C structure. As shown in FIG4 , the pixel driving circuit of the exemplary embodiment of the present disclosure may be a 9T2C structure, for example, it may include 9 transistors (a first transistor T1 to a ninth transistor T9) and 2 storage capacitors (a first storage capacitor C1 and a second storage capacitor C2), and the pixel driving circuit may be connected to a plurality of signal lines, for example, respectively connected to 12 signal lines (a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a fourth scan signal line S4, a first light-emitting signal line EM1, a second light-emitting signal line EM2, a first initial signal line INIT1, a second initial signal line INIT2, a first reference signal line REF1, a second reference signal line REF2, a data signal line DATA, and a first power line VDD). It is understandable that some of the 12 signal lines may use the same signal, for example, the first initial signal line INIT1 and the second initial signal line INIT2.

[0098] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5. The first node N1 is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the first storage capacitor C1, respectively. The second node N2 is connected to the first electrode of the third transistor T3, the second electrode of the eighth transistor T8, and the second electrode of the fifth transistor T5, respectively. The third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively. The fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively. The fifth node N5 is connected to the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the second end of the first storage capacitor C1, and the second end of the second storage capacitor C2, respectively.

[0099] In an exemplary embodiment, a first end (lower plate) of the first storage capacitor C1 is connected to the first node N1, and a second end (upper plate) of the first storage capacitor C1 is connected to the fifth node N5. A first end (upper plate) of the second storage capacitor C2 is connected to the first power line VDD, and a second end (lower plate) of the second storage capacitor C2 is connected to the fifth node N5.

[0100] In an exemplary embodiment, a gate electrode of the first transistor T1 is connected to the fourth scan signal line S4, a first electrode of the first transistor T1 is connected to the first initialization signal line INIT1, and a second electrode of the first transistor is connected to the first node N1. When a turn-on signal is applied to the fourth scan signal line S4, the first transistor T1 transmits a first initialization voltage to the gate electrode of the third transistor T3 and the first end of the first storage capacitor C1, thereby releasing the charge accumulated in the first storage capacitor C1 and achieving initialization.

[0101] In an exemplary embodiment, a gate electrode of the second transistor T2 is connected to the second scan signal line S2, a first electrode of the second transistor T2 is connected to the first node N1, and a second electrode of the second transistor T2 is connected to the third node N3. When a turn-on signal is applied to the second scan signal line S2, the second transistor T2 connects the gate electrode of the third transistor T3 to the second electrode.

[0102] In an exemplary embodiment, the gate electrode of the third transistor T3 is connected to the first node N1, that is, the gate electrode of the third transistor T3 is connected to the first end of the first storage capacitor C1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor, and the third transistor T3 determines the magnitude of the driving current based on the potential difference between its gate electrode and the first electrode.

[0103] In an exemplary embodiment, a gate electrode of the fourth transistor T4 is connected to the third scan signal line S3, a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the fifth node N5. When a turn-on signal is applied to the third scan signal line S3, the fourth transistor T4 inputs a data voltage of the data signal line DATA to the second end of the first storage capacitor C1 and the second end of the second storage capacitor C2.

[0104] In the exemplary embodiment, a gate electrode of the fifth transistor T5 is connected to the first light emission signal line EM1, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2. A gate electrode of the sixth transistor T6 is connected to the second light emission signal line EM2, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fourth node N4. When a turn-on signal is applied to the first light emission signal line EM1 and the second light emission signal line EM2, the fifth transistor T5 and the sixth transistor T6 form a drive current path between the first power line VDD and the second power line VSS, causing the light emitting device EL to emit light.

[0105] In an exemplary embodiment, a gate electrode of the seventh transistor T7 is connected to the first scan signal line S1, a first electrode of the seventh transistor T7 is connected to the second initialization signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4. When a turn-on signal is applied to the first scan signal line S1, the seventh transistor T7 transmits the second initialization voltage to the first electrode of the light-emitting device EL, thereby releasing the charge accumulated in the first electrode of the light-emitting device EL and achieving initialization.

[0106] In an exemplary embodiment, a gate electrode of the eighth transistor T8 is connected to the first scan signal line S1, a first electrode of the eighth transistor T8 is connected to the second reference signal line REF2, and a second electrode of the eighth transistor T8 is connected to the second node N2. When a turn-on signal is applied to the first scan signal line S1, the eighth transistor T8 transmits the second reference signal to the second node N2.

[0107] In an exemplary embodiment, a gate electrode of the eighth transistor T8 is connected to the first scan signal line S1, a first electrode of the eighth transistor T8 is connected to the second reference signal line REF2, and a second electrode of the eighth transistor T8 is connected to the second node N3. When a turn-on signal is applied to the first scan signal line S1, the eighth transistor T8 transmits the second reference signal to the third node N3.

[0108] Of course, in some embodiments, the eighth transistor T8 may be provided at both the second node N2 and the third node N3.

[0109] In an exemplary embodiment, a gate electrode of the ninth transistor T9 is connected to the second scan signal line S2, a first electrode of the ninth transistor T9 is connected to the first reference signal line REF1, and a second electrode of the ninth transistor T9 is connected to the fifth node N5. When a turn-on signal is applied to the second scan signal line S2, the ninth transistor T9 transmits the first reference signal to the fifth node N5.

[0110] Of course, in some embodiments, the eighth transistor T8 and / or the ninth transistor T9 may not be provided.

[0111] In an exemplary embodiment of the present disclosure, the first transistor T1 may be referred to as a first initialization transistor, the second transistor T2 may be referred to as a compensation transistor, the third transistor T3 may be referred to as a driving transistor, the fourth transistor T4 may be referred to as a data writing transistor, the fifth transistor T5 may be referred to as a first light-emitting transistor, the sixth transistor T6 may be referred to as a second light-emitting transistor, the seventh transistor T7 may be referred to as a second initialization transistor, the eighth transistor T8 may be referred to as a second reference transistor, and the ninth transistor T9 may be referred to as a first reference transistor.

[0112] In an exemplary embodiment, the light-emitting device EL may be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode). The first electrode of the light-emitting device EL is connected to the fourth node N4, and the second electrode of the light-emitting device EL is connected to the second power line VSS. The signal of the second power line VSS is a continuously provided low-level signal, and the signal of the first power line VDD is a continuously provided high-level signal.

[0113] In an exemplary embodiment, the first transistor T1 to the ninth transistor T9 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the ninth transistor T9 may include P-type transistors and N-type transistors.

[0114] In an exemplary embodiment, the first transistor T1 to the ninth transistor T9 may be low-temperature polysilicon thin-film transistors, or may be oxide thin-film transistors, or may be low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0115] In an exemplary embodiment, the operation process of the pixel driving circuit shown in FIG. 4 may include a first stage to a fifth stage.

[0116] Phase 1. The first phase may include multiple sub-phases that are repeatedly executed, and each sub-phase may include a first sub-phase and a second sub-phase that are executed sequentially.

[0117] In the first sub-phase, the signals on the fourth scan signal line S4 and the first emission signal line EM1 are on signals, while the signals on the other signal lines are off signals. The on signal on the fourth scan signal line S4 turns on the first transistor T1, and the first initialization signal on the first initialization signal line INIT1 is provided to the first node N1 to initialize the first node N1. If the third transistor T3 is a P-type transistor, the third transistor T3 turns on. The on signal on the first emission signal line EM1 turns on the fifth transistor T5, and the first power signal on the first power line VDD is provided to the second node N2.

[0118] In the second sub-phase, the signals on the second scan signal line S2 and the first emission signal line EM1 are on signals, while the signals on the other signal lines are off signals. The on signal on the second scan signal line S2 turns on the second transistor T2, connecting the first node N1 and the third node N3. The threshold voltage of the third transistor T3 is written to the first node N1. The on signal on the second scan signal line S2 turns on the ninth transistor T9. The first reference signal on the first reference signal line REF1 is provided to the fifth node N5 to initialize it. The on signal on the first emission signal line EM1 turns on the fifth transistor T5, and the first power signal on the first power line VDD is provided to the second node N2.

[0119] Phase 2: The signal on the third scan signal line S3 is an on signal, and the signals on the other signal lines are off signals. The signal on the third scan signal line S3 is an on signal, which turns on the fourth transistor T4 and writes the data voltage provided by the data signal line DATA into the fifth node N5.

[0120] Phase 3. The signal on the first scan signal line S1 is an on signal, and the signals on the other signal lines are off signals. The signal on the first scan signal line S1 turns on the seventh transistor T7, and the second initial signal on the second initial signal line INIT2 can be written to the fourth node N4 to initialize the fourth node N4 and prevent residual signals from the previous frame from affecting the display of the current frame. The signal on the first scan signal line S1 turns on the eighth transistor T8, and the second reference signal on the second reference signal line REF2 can be written to the second node N2.

[0121] Phase 4: The signal on the second light-emitting signal line EM2 is an on signal, and the signals on the other signal lines are off signals. The signal on the second light-emitting signal line EM2 turns on the sixth transistor T6, connecting the third node N3 and the fourth node N4, so that the potentials of the third node N3 and the fourth node N4 are the same.

[0122] Phase 5. The signals on the first and second emission signal lines EM1 and EM2 are on, while the signals on the other signal lines are off. The signals on the first and second emission signal lines EM1 and EM2 are on, turning on the fifth and sixth transistors T5 and T6. The first power signal on the first power line VDD can provide a drive signal to the light-emitting device EL via the turned-on fifth, third, and sixth transistors T5, T3, and T6, driving the light-emitting device EL to emit light.

[0123] In an exemplary embodiment, when the driving transistor (i.e., the third transistor T3) remains in one state for a long time, electrons may be trapped in a trap, causing hysteresis. Therefore, in the first stage, by performing the initialization and threshold voltage writing process on the first node N1 multiple times (e.g., three times), not only can the hysteresis of the driving transistor be reduced, but the potential stability of the first node N1 can also be ensured. In the third stage, a second reference signal is written to the second node N2. By changing the potential of the second node N2, it can help reduce the hysteresis of the driving transistor. In the fourth stage, by connecting the third node N3 and the fourth node N4, the potential of the fourth node N4 can be increased, which helps to reduce the time required to reach the turn-on voltage of the light-emitting device.

[0124] The pixel driving circuit provided by the present disclosure can effectively improve the hysteresis of the driving transistor, which is beneficial to improving the display effect.

[0125] Figure 5 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of the pixel driving circuit in three circuit units (a first circuit unit, a second circuit unit, and a third circuit unit) in the display substrate. In an exemplary embodiment, the display substrate may include a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate. The driving circuit layer may include at least a plurality of circuit units, the light-emitting structure layer may include at least a plurality of light-emitting units, at least one circuit unit includes a pixel driving circuit, and at least one light-emitting unit includes a light-emitting device. The light-emitting device may include at least an anode, an organic light-emitting layer, and a cathode, and the anode in the light-emitting unit is connected to the pixel driving circuit in the corresponding circuit unit. In an exemplary embodiment, the circuit unit referred to in the present disclosure refers to an area divided according to the pixel driving circuit, and the light-emitting unit referred to in the present disclosure refers to an area divided according to the light-emitting device. In an exemplary embodiment, the position of the orthogonal projection of the light-emitting unit on the substrate may correspond to the position of the orthogonal projection of the circuit unit on the substrate, or the position of the orthogonal projection of the light-emitting unit on the substrate may not correspond to the position of the orthogonal projection of the circuit unit on the substrate.

[0126] In an exemplary embodiment, a plurality of circuit units sequentially arranged along a first direction X may be referred to as a unit row, and a plurality of circuit units sequentially arranged along a second direction Y may be referred to as a unit column. The plurality of unit rows and the plurality of unit columns constitute a circuit unit array arranged in an array, and the first direction X intersects the second direction Y.

[0127] As shown in FIG5 , in an exemplary embodiment, the driving circuit layer may further include at least one first power line 51 extending along the second direction Y, at least one second power line 52 extending along the second direction Y, at least one first power connection line 68 extending along the first direction X, and at least one second power connection line 69 extending along the first direction X. In an exemplary embodiment, the first power line 51 is connected to the pixel driving circuits in the plurality of circuit units and is configured to continuously provide a high-level signal to the pixel driving circuits. The second power line 52 is connected to the cathodes of the plurality of light-emitting units and is configured to continuously provide a low-level signal to the cathodes. In an exemplary embodiment, the first power line 51 extending along the second direction Y and the first power connection line 68 extending along the first direction X are interconnected to form a mesh structure for transmitting the first power signal. The second power line 52 extending along the second direction Y and the second power connection line 69 extending along the first direction X are interconnected to form a mesh structure for transmitting the second power signal.

[0128] In some embodiments, the second power line 52 and the second power connection line 69 may not be included.

[0129] In some embodiments, the gate of the second transistor T2 and the gate of the ninth transistor T9 may be connected to different signals, and the gate of the seventh transistor T7 and the gate of the eighth transistor T8 may be connected to different signals.

[0130] In the present disclosure, A extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions.

[0131] In an exemplary embodiment, the driving circuit layer may further include a reference signal connection line 54 and a first reference signal line 91. The shape of the first reference signal line 91 may be a line shape extending along the first direction X, and the shape of the reference signal connection line 54 may be a line shape extending along the second direction Y. The reference signal connection line 54 and the first reference signal line 91 are interconnected to form a mesh structure for transmitting the first reference signal.

[0132] In an exemplary embodiment, the driving circuit layer may include a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the substrate in a plane perpendicular to the display substrate. The first power line 51 and the first power connection line 68 may be disposed in different conductive layers, and the first power line 51 and the first power connection line 68 may be connected via a via. The second power line 52 and the second power connection line 69 may be disposed in different conductive layers, and the second power line 52 and the second power connection line 69 may be connected via a via.

[0133] In an exemplary embodiment, the first power line 51 and the second power line 52 may be provided in the same layer and formed simultaneously through the same patterning process, and the first power connection line 68 and the second power connection line 69 may be provided in the same layer and formed simultaneously through the same patterning process.

[0134] In an exemplary embodiment, the first power connection line 68 and the second power connection line 69 may be disposed in the third conductive layer, and the first power line 51 and the second power line 52 may be disposed in the fourth conductive layer.

[0135] In an exemplary embodiment, the reference signal connection line 54 and the first reference signal line 91 may be disposed in different conductive layers, and the reference signal connection line 54 and the first reference signal line 91 may be connected through a via.

[0136] In an exemplary embodiment, the first reference signal line 91 may be disposed in the third conductive layer, and the reference signal connection line 54 may be disposed in the fourth conductive layer.

[0137] In example embodiments, at least one circuit unit may include a plurality of transistors, and the semiconductor layer may include at least active layers of the plurality of transistors.

[0138] In an exemplary embodiment, at least one pixel driving circuit may include a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light emitting transistor, a sixth transistor T6 as a second light emitting transistor, a seventh transistor T7 as a second initialization transistor, an eighth transistor T8 as a second reference transistor, a ninth transistor T9 as a first reference transistor, a first storage capacitor, and a second storage capacitor.

[0139] Figure 6 is an enlarged view of the first and second storage capacitor regions in Figure 5 . As shown in Figure 6 , in an exemplary embodiment, the first storage capacitor may include at least a first electrode plate 71 and a third electrode plate 73, with the orthographic projection of the third electrode plate 73 on the substrate at least partially overlapping the orthographic projection of the first electrode plate 71 on the substrate. The second storage capacitor may include at least a second electrode plate 72 and a fourth electrode plate 74, with the orthographic projection of the fourth electrode plate 74 on the substrate at least partially overlapping the orthographic projection of the second electrode plate 72 on the substrate.

[0140] In an exemplary embodiment, the first electrode plate 71 and the second electrode plate 72 can be disposed in the first conductive layer, the third electrode plate 73 and the fourth electrode plate 74 can be disposed in the second conductive layer, the first electrode plate 71 can serve as the gate electrode of the third transistor T3, the second electrode plate 72 is connected to the third electrode plate 73, and the fourth electrode plate 74 is connected to the first power line 51.

[0141] In the exemplary embodiment, the gate electrode of the first transistor T1 is connected to the fourth scan signal line 64, the first electrode of the first transistor T1 is connected to the first initial signal line 81, and the second electrode of the first transistor T1 is respectively connected to the first electrode of the second transistor T2 and the first plate 71 of the first storage capacitor. The gate electrode of the second transistor T2 is connected to the second scan signal line 62, and the second electrode of the second transistor T2 is respectively connected to the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6. The gate electrode of the third transistor T3 serves as the first plate 71 of the first storage capacitor, and the first electrode of the third transistor T3 is respectively connected to the second electrode of the fifth transistor T5 and the second electrode of the eighth transistor T8. The gate electrode of the fourth transistor T4 is connected to the third scan signal line 63, the first electrode of the fourth transistor T4 is connected to the data signal line 53, and the second electrode of the fourth transistor T4 is respectively connected to the second electrode of the ninth transistor T9, the third plate 73 of the first storage capacitor, and the second plate 72 of the second storage capacitor. The gate electrode of the fifth transistor T5 is connected to the first light emission signal line 31, and the first electrode of the fifth transistor T5 is connected to the first power line 51. The gate electrode of the sixth transistor T6 is connected to the second light-emitting signal line 32, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7. The gate electrode of the seventh transistor T7 is connected to the first scanning signal line 61, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 82. The gate electrode of the eighth transistor T8 is connected to the first scanning signal line 61, and the first electrode of the eighth transistor T8 is connected to the second reference signal line 92. The gate electrode of the ninth transistor T9 is connected to the second scanning signal line 62, and the first electrode of the ninth transistor T9 is connected to the first reference signal line 91.

[0142] In an exemplary embodiment, the second scan signal line 62 and the fifth scan signal line 65 transmit the same scan signal.

[0143] In an exemplary embodiment, the shapes of the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the fifth scan signal line 65, the first light-emitting signal line 31, the second light-emitting signal line 32, the first initial signal line 81, the second initial signal line 82, the first reference signal line 91 and the second reference signal line 92 can be line shapes whose main parts extend along the first direction X, and the shapes of the first power line 51 and the data signal line 53 can be line shapes whose main parts extend along the second direction Y.

[0144] In an exemplary embodiment, at least one circuit unit may further include an anode connection electrode 55 connected to the second electrodes of the sixth and seventh transistors T6 and T7 , respectively, and to the anode of the light emitting unit.

[0145] In an exemplary embodiment, the driving circuit layer may further include a repair line 33 , the shape of the repair line 33 may be a strip shape with a main portion extending along the first direction X, and the orthographic projection of the repair line 33 on the substrate at least partially overlaps with the orthographic projection of the anode connection electrode 55 on the substrate.

[0146] As shown in Figures 5 and 6, in an exemplary embodiment, at least one circuit unit may further include a first connection electrode 41, which is respectively connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2 and the first plate 71 of the first storage capacitor. The first connection electrode 41 can serve as the first node of the pixel driving circuit.

[0147] In an exemplary embodiment, at least one circuit unit may further include a power shielding block 51-1, which is connected to the first power line 51, and the orthographic projection of the power shielding block 51-1 on the substrate at least partially overlaps with the orthographic projection of the first connection electrode 41 on the substrate to shield the influence of other signals in the pixel driving circuit on the first node.

[0148] In an exemplary embodiment, at least one circuit unit may further include a second connection electrode 42, which is respectively connected to the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the third plate 73 of the first storage capacitor, and the second plate 72 of the second storage capacitor. The second connection electrode 42 can serve as the fifth node N5 in the pixel driving circuit.

[0149] In an exemplary embodiment, an orthographic projection of the first power line 51 on the substrate at least partially overlaps an orthographic projection of the second connection electrode 42 on the substrate to shield the fifth node from influence of other signals in the pixel driving circuit.

[0150] In an exemplary embodiment, at least one circuit unit may further include a first shielding electrode 36. The first shielding electrode 36 is connected to the fourth electrode plate 74. The orthographic projection of the first shielding electrode 36 on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first transistor T1 on the substrate. The orthographic projection of the first shielding electrode 36 on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the second transistor T2 on the substrate. In an exemplary embodiment, the first shielding electrode 36 is configured to shield the first transistor T1 and the second transistor T2 from the effects of data voltage jumps, thereby preventing the data voltage jumps from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0151] In an exemplary embodiment, at least one circuit unit may further include a second shielding electrode 37, which is connected to the fourth electrode plate 74 and disposed between the first electrode and the second electrode of the fourth transistor T4. In an exemplary embodiment, the second shielding electrode 37 is configured to shield the fifth node from the effects of data voltage jumps, thereby preventing the data voltage jumps from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0152] In an exemplary embodiment, the fourth plate 74 , the first shield electrode 36 , and the second shield electrode 37 may be an integral structure connected to each other.

[0153] In an exemplary embodiment, at least one circuit unit may further include a third shielding electrode 38. The third shielding electrode 38 is connected to the second reference signal line 92. The orthographic projection of the third shielding electrode 38 on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the fourth transistor T4 on the substrate. In an exemplary embodiment, the third shielding electrode 38 is configured to shield the fourth transistor T4 from the effects of data voltage jumps, thereby preventing the data voltage jumps from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0154] In an exemplary embodiment, at least one circuit unit may further include a fourth shielding electrode 39, the fourth shielding electrode 39 being connected to the second reference signal line 92, with an orthographic projection of the fourth shielding electrode 39 on the substrate at least partially overlapping with an orthographic projection of a node between the two gate electrodes of the ninth transistor T9 on the substrate. In an exemplary embodiment, the fourth shielding electrode 39 is configured to shield the ninth transistor T9 from the effects of data voltage jumps, thereby preventing the data voltage jumps from affecting the normal operation of the pixel driving circuit and improving display quality.

[0155] The following is an illustrative explanation using the preparation process of a display substrate. The "patterning process" mentioned in this disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials; and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be performed by any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed by any one or more of spraying, spin coating, and inkjet printing; and etching can be performed by any one or more of dry etching and wet etching, which are not limited in this disclosure. "Thin film" refers to a thin film made by depositing, coating, or other processes on a substrate using a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer." If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0156] In an exemplary embodiment, taking three circuit units in an n-th unit row as an example, the preparation process of the display substrate of this embodiment may include the following operations.

[0157] (11) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process to form a first insulating layer covering the substrate, and a semiconductor layer disposed on the first insulating layer, as shown in FIG. 7 .

[0158] In an exemplary embodiment, the semiconductor layer pattern of each circuit unit in the display substrate may include at least a first active layer 11 of a first transistor T1, a second active layer 12 of a second transistor T2, a third active layer 13 of a third transistor T3, a fourth active layer 14 of a fourth transistor T4, a fifth active layer 15 of a fifth transistor T5, a sixth active layer 16 of a sixth transistor T6, a seventh active layer 17 of a seventh transistor T7, an eighth active layer 18 of an eighth transistor T8, and a ninth active layer 19 of a ninth transistor T9. The first to third active layers 11 to 13 and the fifth to eighth active layers 15 to 18 may be interconnected as an integral structure, and the fourth active layer 14 and the ninth active layer 19 may be interconnected as an integral structure. Of course, the active layers of all transistors may also be connected together.

[0159] In an exemplary embodiment, the fourth active layer 14 and the ninth active layer 19 of the nth unit row may be located on a side of the third active layer 13 close to the (n-1)th unit row, that is, the fourth active layer 14 and the ninth active layer 19 may be located on a side of the third active layer 13 of the circuit unit opposite to the second direction Y. The first active layer 11, the second active layer 12, and the fifth active layer 15 to the eighth active layer 18 of the nth unit row may be located on a side of the third active layer 13 close to the (n+1)th unit row, that is, the first active layer 11, the second active layer 12, and the fifth active layer 15 to the eighth active layer 18 may be located on a side of the third active layer 13 of the circuit unit in the second direction Y.

[0160] In an exemplary embodiment, the first active layer 11 may be located on one side of the third active layer 13 of the present circuit unit in the second direction Y, the fifth active layer 15 may be located on one side of the first active layer 11 of the present circuit unit in the second direction Y, and the eighth active layer 18 may be located on one side of the fifth active layer 15 of the present circuit unit in the second direction Y. The second active layer 12 may be located on one side of the third active layer 13 of the present circuit unit in the second direction Y, the sixth active layer 16 may be located on one side of the second active layer 12 of the present circuit unit in the second direction Y, and the seventh active layer 17 may be located on one side of the sixth active layer 16 of the present circuit unit in the second direction Y.

[0161] In an exemplary embodiment, the first active layer 11, the fourth active layer 14, the fifth active layer 15 and the eighth active layer 18 can be located on one side of the first direction X of the circuit unit (such as the side opposite to the first direction X), and the second active layer 12, the sixth active layer 16, the seventh active layer 17 and the ninth active layer 19 can be located on the other side of the first direction X of the circuit unit (such as one side of the first direction X).

[0162] In an exemplary embodiment, the first active layer 11 and the second active layer 12 may have an L shape, the third active layer 13 may have a C shape, the fourth active layer 14 and the ninth active layer 19 may have an N shape, and the fifth active layer 15, the sixth active layer 16, the seventh active layer 17, and the eighth active layer 18 may have an I shape.

[0163] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the second region 11-2 of the first active layer and the first region 12-1 of the second active layer may be interconnected, and the second region 11-2 of the first active layer may serve as the first region 12-1 of the second active layer. The first region 13-1 of the third active layer, the second region 15-2 of the fifth active layer, and the second region 18-2 of the eighth active layer may be interconnected, and the first region 13-1 of the third active layer may serve as both the second region 15-2 of the fifth active layer and the second region 18-2 of the eighth active layer, forming a second node N2 of the pixel driving circuit. The second region 12-2 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer may be interconnected, and the second region 13-2 of the third active layer may serve as both the second region 12-2 of the second active layer and the first region 16-1 of the sixth active layer, forming a third node N3 of the pixel driving circuit. The second region 14-2 of the fourth active layer and the second region 19-2 of the ninth active layer may be connected to each other, and the second region 14-2 of the fourth active layer may serve as the second region 19-2 of the ninth active layer. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer may be connected to each other, and the second region 16-2 of the sixth active layer may serve as the second region 17-2 of the seventh active layer, forming a fourth node N4 of the pixel driving circuit. The first region 11-1 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, the first region 17-1 of the seventh active layer, the first region 18-1 of the eighth active layer, and the first region 19-1 of the ninth active layer may be separately provided. The first region 14-1 of the fourth active layer may be located on a side of the channel region of the fourth active layer closer to the third active layer 13, and the first region 19-1 of the ninth active layer may be located on a side of the channel region of the ninth active layer closer to the third active layer 13.

[0164] In an exemplary embodiment, in at least one unit row, the semiconductor layers in the circuit units adjacent in the first direction X are connected to each other, that is, the semiconductor layer of the first circuit unit in the n-th unit row is connected to the semiconductor layer of the second circuit unit in the n-th unit row, and the semiconductor layer of the second circuit unit in the n-th unit row is connected to the semiconductor layer of the third circuit unit in the n-th unit row.

[0165] In an exemplary embodiment, the display substrate may further include a first active connection line 10 and a second active connection line 20. The first active connection line 10 may be located on one side of the ninth active layer 19 in the second direction Y and connected to the first region 19-1 of the ninth active layer of each circuit unit. The second active connection line 20 may be located on one side of the seventh active layer 17 in the second direction Y and connected to the first region 17-1 of the seventh active layer of each circuit unit.

[0166] In an exemplary embodiment, the first active connection line 10 may be shaped like a zigzag line, with the main portion extending along the first direction X. The first active connection line 10 and the ninth active layers of the plurality of circuit units may be interconnected as an integral structure. Because the first region of the ninth active layer is connected to a subsequently formed first reference signal line, the first active connection line 10 can be reused as a first reference signal line extending along the first direction X. This not only ensures that the first regions of the plurality of ninth active layers in a cell row have the same potential, but also reduces the voltage drop of the first reference signal, thereby improving the uniformity of the panel, preventing display defects on the display substrate, and ensuring the display quality of the display substrate.

[0167] In an exemplary embodiment, the second active connection line 20 may be in the shape of a straight line with a main portion extending along the first direction X. The second active connection line 20 and the seventh active layers of the plurality of circuit units may be interconnected as an integral structure. Since the first region of the seventh active layer is connected to a subsequently formed second initial signal line, the second active connection line 20 can be reused as a second initial signal line extending along the first direction X. This not only ensures that the first regions of the plurality of seventh active layers in a cell row have the same potential, but also reduces the voltage drop of the second initial signal, thereby improving the uniformity of the panel, preventing display defects on the display substrate, and ensuring the display quality of the display substrate.

[0168] In an exemplary embodiment, in at least one unit column, the semiconductor layers in the circuit units adjacent in the second direction Y are spaced apart from each other, that is, the semiconductor layer of the first circuit unit in the n-1th unit row is not connected to the semiconductor layer of the first circuit unit in the nth unit row, and the semiconductor layer of the first circuit unit in the nth unit row is not connected to the semiconductor layer of the first circuit unit in the n+1th unit row.

[0169] (12) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG8A and FIG8B , where FIG8B is a schematic diagram of the first conductive layer in FIG8A . In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0170] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display substrate includes at least: a first gate electrode 21, a second gate electrode 22, a fourth gate electrode 24, a fifth gate electrode 25, a sixth gate electrode 26, a ninth gate electrode 29, a first scan signal line 61, a first plate 71 of a first storage capacitor, and a second plate 72 of a second storage capacitor.

[0171] In an exemplary embodiment, the first gate electrode 21 may be in an L-shape and may be located on one side of the first electrode 71 in the second direction Y. The region where the first gate electrode 21 overlaps with the first active layer may serve as the gate electrode of the first transistor T1 of the dual-gate structure.

[0172] In an exemplary embodiment, the second gate electrode 22 can be in a "T" shape and can be located on one side of the first electrode 71 in the second direction Y. The area where the second gate electrode 22 overlaps with the second active layer can serve as the gate electrode of the second transistor T2 of the dual-gate structure.

[0173] In an exemplary embodiment, the fourth gate electrode 24 may be in an "L" shape and may be located on the side of the second electrode 72 in the opposite direction of the second direction Y. The area where the fourth gate electrode 24 overlaps with the fourth active layer may serve as the gate electrode of the fourth transistor T4 of the dual-gate structure.

[0174] In an exemplary embodiment, the fifth gate electrode 25 may be in the shape of a strip extending along the second direction Y and may be located on one side of the first gate electrode 21 in the second direction Y. The area where the fifth gate electrode 25 overlaps with the fifth active layer may serve as the gate electrode of the fifth transistor T5.

[0175] In an exemplary embodiment, the sixth gate electrode 26 may be in a strip shape extending along the first direction X and may be located on one side of the second gate electrode 22 in the second direction Y. The area where the sixth gate electrode 26 overlaps with the sixth active layer may serve as the gate electrode of the sixth transistor T6.

[0176] In an exemplary embodiment, the shape of the ninth gate electrode 29 can be a strip shape extending along the first direction X, and can be located on the side of the second electrode 72 in the opposite direction of the second direction Y. The area where the ninth gate electrode 29 overlaps with the ninth active layer can serve as the gate electrode of the ninth transistor T9 of the dual-gate structure.

[0177] In an exemplary embodiment, the first scan signal line 61 may be shaped as a line having a main portion extending along the first direction X, and may be located on one side of the fifth gate electrode 25 and the sixth gate electrode 26 in the second direction Y. The region where the first scan signal line 61 overlaps with the seventh active layer may serve as the gate electrode of the seventh transistor T7, and the region where the first scan signal line 61 overlaps with the eighth active layer may serve as the gate electrode of the eighth transistor T8.

[0178] In an exemplary embodiment, the shape of the first electrode 71 of the first storage capacitor can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the first electrode 71 on the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate. The first electrode 71 can serve as the lower plate of the first storage capacitor and the gate electrode of the third transistor T3 at the same time.

[0179] In an exemplary embodiment, the second plate 72 of the second storage capacitor may be rectangular, with chamfered corners. The second plate 72 may be located on a side of the first plate 71 opposite to the second direction Y, and on a side of the fourth gate electrode 24 and the ninth gate electrode 29 in the second direction Y. That is, in the second direction Y, the second plate 72 is located between the first plate 71 and the fourth gate electrode 24 (ninth gate electrode 29), and the orthographic projection of the second plate 72 on the substrate does not overlap with the orthographic projection of the semiconductor layer on the substrate. In an exemplary embodiment, the second plate 72 may serve as the lower plate of the second storage capacitor.

[0180] In an exemplary embodiment, the orthographic projection areas of the first electrode plate 71 and the second electrode plate 72 on the substrate may be the same or different.

[0181] In an exemplary embodiment, the area where the first active connection line 10 connects to the first region of the ninth active layer is bent toward the ninth active layer, forming a recessed portion on the side of the first active connection line 10 away from the ninth active layer. A protrusion 72-1 is provided on the side of the second electrode plate 72 proximal to the first active connection line 10. The protrusion 72-1 may be rectangular in shape. A first end of the protrusion 72-1 is connected to the second electrode plate 72, and a second end of the protrusion 72-1 extends into the recessed portion of the first active connection line 10.

[0182] In an exemplary embodiment, the second electrode plate 72 and the protrusion 72-1 can be an integral structure connected to each other. The present disclosure can effectively increase the area of ​​the second electrode plate 72 and the capacitance of the second storage capacitor by providing the concave portion of the first active connection line 10 and the protrusion 72-1 of the second electrode plate 72.

[0183] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the semiconductor layer. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the ninth transistor T9, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first region and the second region of the first active layer to the ninth active layer are all conductorized.

[0184] (13) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate having the aforementioned pattern formed thereon, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIG9A and FIG9B , where FIG9B is a schematic diagram of the second conductive layer in FIG9A . In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0185] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display substrate includes at least: a first light-emitting signal line 31, a second light-emitting signal line 32, a repair line 33, a first shielding electrode 36, a second shielding electrode 37, a third shielding electrode 38, a fourth shielding electrode 39, a third plate 73 of a first storage capacitor, a fourth plate 74 of a second storage capacitor, a first initial signal line 81 and a second reference signal line 92.

[0186] In an exemplary embodiment, the shapes of the first light-emitting signal line 31, the second light-emitting signal line 32, the repair line 33, the first initial signal line 81 and the second reference signal line 92 can be a line shape in which the main part extends along the first direction X, the first light-emitting signal line 31, the second light-emitting signal line 32, the repair line 33 and the first initial signal line 81 can be located between the first gate electrode 21 and the first scanning signal line 61, and the second reference signal line 92 can be located on the side of the fourth gate electrode 24 in the opposite direction of the second direction Y.

[0187] In an exemplary embodiment, the first light-emitting signal line 31 can be located on one side of the second direction Y of the first gate electrode 21 of the present circuit unit, the first initial signal line 81 can be located on one side of the second direction Y of the first light-emitting signal line 31 of the present circuit unit, the second light-emitting signal line 32 can be located on one side of the second direction Y of the first initial signal line 81 of the present circuit unit, the repair line 33 can be located on one side of the second direction Y of the second light-emitting signal line 32 of the present circuit unit, that is, the second light-emitting signal line 32 can be located between the first light-emitting signal line 31 and the repair line 33, the first initial signal line 81 can be located between the first light-emitting signal line 31 and the second light-emitting signal line 32, and the second reference signal line 92 can be located on the side opposite to the second direction Y of the first light-emitting signal line 31.

[0188] In an exemplary embodiment, a first light-emitting connection block 31-1 is provided on a side of the first light-emitting signal line 31 near the second light-emitting signal line 32. The first light-emitting connection block 31-1 can be provided in each circuit unit. A first end of the first light-emitting connection block 31-1 is connected to the first light-emitting signal line 31, and a second end of the first light-emitting connection block 31-1 extends toward the second light-emitting signal line 32. The first light-emitting connection block 31-1 is configured to be connected to the fifth gate electrode 25 via a subsequently formed seventh connection electrode. In an exemplary embodiment, the first light-emitting signal line 31 and the plurality of first light-emitting connection blocks 31-1 can be an interconnected, integrated structure.

[0189] In an exemplary embodiment, a second light-emitting connection block 32-1 is provided on a side of the second light-emitting signal line 32 adjacent to the first light-emitting signal line 31. The second light-emitting connection block 32-1 can be provided in each circuit unit. A first end of the second light-emitting connection block 32-1 is connected to the second light-emitting signal line 32, and a second end of the second light-emitting connection block 32-1 extends toward the first light-emitting signal line 31. The second light-emitting connection block 32-1 is configured to be connected to the sixth gate electrode 26 via a subsequently formed eighth connection electrode. In an exemplary embodiment, the second light-emitting signal line 32 and the plurality of second light-emitting connection blocks 32-1 can be an interconnected, integrated structure.

[0190] In an exemplary embodiment, a first initial connection block 81-1 is provided on a side of the first initial signal line 81 near the first light-emitting signal line 31. The first initial connection block 81-1 can be provided in each circuit unit. A first end of the first initial connection block 81-1 is connected to the first initial signal line 81, and a second end of the first initial connection block 81-1 extends toward the first light-emitting signal line 31. The first initial connection block 81-1 is configured to connect to the first region of the first active layer via a subsequently formed ninth connection electrode. This enables the first initial signal line 81 to connect to the first electrode of the first transistor T1. The first initial signal line 81 can write the first initial signal to the first electrode of the first transistor T1. In an exemplary embodiment, the first initial signal line 81 and the plurality of first initial connection blocks 81-1 can be an interconnected, integrated structure.

[0191] In an exemplary embodiment, a second reference connection block 92-1 is provided on a side of the second reference signal line 92 of the (n+1)th cell row away from the fourth electrode plate 74 of the (n+1)th cell row. This second reference connection block 92-1 can be provided in each circuit cell. A first end of the second reference connection block 92-1 is connected to the second reference signal line 92, and a second end of the second reference connection block 92-1 extends away from the fourth electrode plate 74, i.e., toward the nth cell row. In an exemplary embodiment, the second reference connection block 92-1 of the second reference signal line 92 in the (n+1)th cell row is configured to connect to the first region of the eighth active layer in the nth cell row via a subsequently formed sixth connection electrode, thereby providing a second reference signal to the first electrode of the eighth transistor T8 in the nth cell row. In an exemplary embodiment, the second reference signal line 92 and the plurality of second reference connection blocks 92-1 can be an interconnected, integral structure.

[0192] In an exemplary embodiment, the contour shape of the third plate 73 of the first storage capacitor can be rectangular, the corners of the rectangle can be chamfered, and it can be located between the first light-emitting signal line 31 and the second reference signal line 92 of the circuit unit. The positive projection of the third plate 73 on the substrate at least partially overlaps with the positive projection of the first plate 71 on the substrate. The third plate 73 can serve as the upper plate of the first storage capacitor, and the first plate 71 and the third plate 73 constitute the first storage capacitor C1 of the pixel driving circuit.

[0193] In an exemplary embodiment, the outline shape of the fourth plate 74 of the second storage capacitor can be rectangular, the corners of the rectangle can be chamfered, and it can be located between the second reference signal line 92 and the third plate 73 of the circuit unit. The orthographic projection of the fourth plate 74 on the substrate at least partially overlaps with the orthographic projection of the second plate 72 on the substrate. The fourth plate 74 can serve as the upper plate of the second storage capacitor, and the second plate 72 and the fourth plate 74 constitute the second storage capacitor C2 of the pixel driving circuit.

[0194] In an exemplary embodiment, the orthographic projection areas of the third plate 73 and the fourth plate 74 on the substrate may be the same or different. For example, the orthographic projection area of ​​the fourth plate 74 on the substrate may be larger than the orthographic projection area of ​​the third plate 73 on the substrate.

[0195] In an exemplary embodiment, a first opening 75 is provided on the third electrode plate 73 of each circuit unit. The first opening 75 may be located in the middle of the third electrode plate 73 and may be rectangular, forming a ring-shaped structure. The first opening 75 exposes the third insulating layer covering the first electrode plate 71, and the orthographic projection of the first electrode plate 71 on the substrate includes the orthographic projection of the first opening 75 on the substrate. In an exemplary embodiment, the first opening 75 is configured to accommodate a tenth via hole formed subsequently. The tenth via hole is located within the first opening 75 and exposes the first electrode plate 71, allowing a first connecting electrode formed subsequently to be connected to the first electrode plate 71.

[0196] In an exemplary embodiment, a second opening 76 is provided on the fourth plate 74 of each circuit unit. The second opening 76 may be located in the middle of the fourth plate 74 and may be rectangular, forming a ring-shaped structure. The second opening 76 exposes the third insulating layer covering the second plate 72, and the orthographic projection of the second plate 72 on the substrate includes the orthographic projection of the second opening 76 on the substrate. In an exemplary embodiment, the second opening 76 is configured to accommodate a subsequently formed eleventh via. The eleventh via is located within the second opening 76 and exposes the second plate 72, allowing a subsequently formed second connecting electrode to be connected to the second plate 72.

[0197] In an exemplary embodiment, the first shielding electrode 36 may be T-shaped and may be located on a side of the fourth plate 74 near the first light-emitting signal line 31. The first shielding electrode 36 may be provided in each circuit unit. The T-shaped first shielding electrode 36 may include a first extension segment 36-1 and a first shielding segment 36-2. The first end of the first extension segment 36-1 is connected to the fourth plate 74, and the second end of the first extension segment 36-1 extends toward the first light-emitting signal line 31 and then connects to the first shielding segment 36-2. The first shielding segment 36-2 may be in the shape of a strip extending along a first direction X. For each of the first shielding end of the first shielding segment 36-2, located on one side of the first extension segment 36-1 in the first direction X and the second shielding end located on the opposite side of the first extension segment 36-1 in the first direction X, the orthographic projection of the first shielding end on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the first transistor T1 in the current circuit unit. The orthographic projection of the second shielding end on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the second transistor T2 in the adjacent circuit unit. In an exemplary embodiment, the first shielding electrode 36 is configured to shield the first transistor T1 and the second transistor T2 from the influence of the data voltage jump, thereby preventing the data voltage jump from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0198] In an exemplary embodiment, the second shielding electrode 37 may be shaped like an "I" and may be located on a side of the fourth plate 74 near the second reference signal line 92. The second shielding electrode 37 may be provided in each circuit unit. A first end of the second shielding electrode 37 is connected to the fourth plate 74, and a second end of the second shielding electrode 37 extends toward the second reference signal line 92. The second end of the second shielding electrode 37 may be located between the first electrode and the second electrode of the fourth transistor T4. In an exemplary embodiment, the second shielding electrode 37 is configured to shield the fifth node N5 from the effects of data voltage jumps, thereby preventing the data voltage jumps from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0199] In an exemplary embodiment, the fourth plate 74 , the first shield electrode 36 , and the second shield electrode 37 may be an integral structure connected to each other.

[0200] In an exemplary embodiment, the third and fourth shielding electrodes 38 and 39 may be rectangular in shape and may be located on a side of the second reference signal line 92 near the fourth plate 74. The third and fourth shielding electrodes 38 and 39 may be provided in each circuit unit. A first end of the third shielding electrode 38 is connected to the second reference signal line 92, and a second end of the third shielding electrode 38 extends toward the fourth plate 74. A first end of the fourth shielding electrode 39 is connected to the second reference signal line 92, and a second end of the fourth shielding electrode 39 extends toward the fourth plate 74. The orthographic projection of the third shielding electrode 38 on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the fourth transistor T4 in this circuit unit. The orthographic projection of the fourth shielding electrode 39 on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the ninth transistor T9 in this circuit unit. In an exemplary embodiment, the third shielding electrode 38 is configured to shield the influence of the data voltage jump on the fourth transistor T4, and the fourth shielding electrode 39 is configured to shield the influence of the data voltage jump on the ninth transistor T9, thereby preventing the data voltage jump from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0201] In an exemplary embodiment, the repair line 33 is a pre-set repair line configured to repair a failed anode by welding. When a bright spot defect occurs on the display substrate, the repair line 33 is configured to input a signal to the anode of the sub-pixel with the bright spot through the repair line 33, thereby repairing the anode to a dark spot.

[0202] (14) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein a plurality of vias are provided in each circuit unit, as shown in FIG. 10 .

[0203] In an exemplary embodiment, the multiple vias of each circuit unit in the display substrate include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, a nineteenth via V19, a twentieth via V20, a twenty-first via V21, a twenty-second via V22, and a twenty-third via V23.

[0204] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed ninth connecting electrode to the first region of the first active layer through the via hole.

[0205] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second region of the first active layer (also the first region of the second active layer) on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the second via hole V2 are etched away to expose the surface of the second region of the first active layer (also the first region of the second active layer), and the second via hole V2 is configured to connect the subsequently formed first connecting electrode to the second region of the first active layer (also the first region of the second active layer) through the via hole.

[0206] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first region of the fourth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the third via hole V3 are etched away to expose the surface of the first region of the fourth active layer, and the third via hole V3 is configured to connect a subsequently formed third connecting electrode to the first region of the fourth active layer through the via hole.

[0207] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second region of the fourth active layer (also the second region of the ninth active layer) on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the fourth via hole V4 are etched away to expose the surface of the second region of the fourth active layer (also the second region of the ninth active layer), and the fourth via hole V4 is configured to connect a subsequently formed second connecting electrode to the second region of the fourth active layer (also the second region of the ninth active layer) through the via hole.

[0208] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first region of the fifth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the fifth via hole V5 are etched away to expose the surface of the first region of the fifth active layer, and the fifth via hole V5 is configured to connect a subsequently formed fourth connecting electrode to the first region of the fifth active layer through the via hole.

[0209] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the second region of the sixth active layer (also the second region of the seventh active layer) on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the sixth via V6 are etched away to expose the surface of the second region of the sixth active layer (also the second region of the seventh active layer), and the sixth via V6 is configured to connect the subsequently formed fifth connecting electrode to the second region of the sixth active layer (also the second region of the seventh active layer) through the via.

[0210] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via V7 are etched away to expose the surface of the first region of the seventh active layer, and the seventh via V7 is configured to connect a subsequently formed second initial signal line to the first region of the seventh active layer through the via.

[0211] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the first region of the eighth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the eighth via V8 are etched away to expose the surface of the first region of the eighth active layer, and the eighth via V8 is configured to connect a subsequently formed sixth connecting electrode to the first region of the eighth active layer through the via.

[0212] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the first region of the ninth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the ninth via V9 are etched away to expose the surface of the first region of the ninth active layer, and the ninth via V9 is configured to connect a subsequently formed first reference signal line to the first region of the ninth active layer through the via.

[0213] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the first opening 75 of the third electrode plate 73 on the substrate, the fourth insulating layer and the third insulating layer in the tenth via hole V10 are etched away to expose the surface of the first electrode plate 71, and the tenth via hole V10 is configured to connect the subsequently formed first connecting electrode to the first electrode plate 71 through the via hole.

[0214] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the second opening 76 of the fourth electrode plate 74 on the substrate, the fourth insulating layer and the third insulating layer in the eleventh via hole V11 are etched away to expose the surface of the second electrode plate 72, and the eleventh via hole V11 is configured to connect a subsequently formed second connecting electrode to the second electrode plate 72 through the via hole.

[0215] In an exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the third electrode plate 73 on the substrate, the fourth insulating layer in the twelfth via hole V12 is etched away to expose the surface of the third electrode plate 73, and the twelfth via hole V12 is configured to connect the subsequently formed second connecting electrode to the third electrode plate 73 through the via hole.

[0216] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 on the substrate is located within the range of the orthographic projection of the fourth electrode plate 74 on the substrate, the fourth insulating layer in the thirteenth via V13 is etched away to expose the surface of the fourth electrode plate 74, and the thirteenth via V13 is configured to connect a subsequently formed first power connection line to the fourth electrode plate 74 through the via.

[0217] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the first gate electrode 21 on the substrate, the fourth insulating layer and the third insulating layer in the fourteenth via V14 are etched away to expose the surface of the first gate electrode 21, and the fourteenth via V14 is configured to connect the subsequently formed fourth scanning signal line to the first gate electrode 21 through the via.

[0218] In an exemplary embodiment, the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the second gate electrode 22 on the substrate, the fourth insulating layer and the third insulating layer in the fifteenth via hole V15 are etched away to expose the surface of the second gate electrode 22, and the fifteenth via hole V15 is configured to connect the subsequently formed fifth scanning signal line to the second gate electrode 22 through the via hole.

[0219] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate is located within the range of the orthographic projection of the fourth gate electrode 24 on the substrate, the fourth insulating layer and the third insulating layer in the sixteenth via V16 are etched away to expose the surface of the fourth gate electrode 24, and the sixteenth via V16 is configured to connect the subsequently formed third scan signal line to the fourth gate electrode 24 through the via.

[0220] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 on the substrate is located within the range of the orthographic projection of the fifth gate electrode 25 on the substrate, the fourth insulating layer and the third insulating layer in the seventeenth via V17 are etched away to expose the surface of the fifth gate electrode 25, and the seventeenth via V17 is configured to connect the subsequently formed seventh connecting electrode to the fifth gate electrode 25 through the via.

[0221] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 on the substrate is located within the range of the orthographic projection of the sixth gate electrode 26 on the substrate, the fourth insulating layer and the third insulating layer in the eighteenth via V18 are etched away to expose the surface of the sixth gate electrode 26, and the eighteenth via V18 is configured to connect the subsequently formed eighth connecting electrode to the sixth gate electrode 26 through the via.

[0222] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 on the substrate is located within the range of the orthographic projection of the ninth gate electrode 29 on the substrate, the fourth insulating layer and the third insulating layer in the nineteenth via V19 are etched away to expose the surface of the ninth gate electrode 29, and the nineteenth via V19 is configured to connect a subsequently formed second scanning signal line to the ninth gate electrode 29 through the via.

[0223] In an exemplary embodiment, the orthographic projection of the twentieth via hole V20 on the substrate is located within the range of the orthographic projection of the first light-emitting connection block 31-1 of the first light-emitting signal line 31 on the substrate, the fourth insulating layer in the twentieth via hole V20 is etched away to expose the surface of the first light-emitting connection block 31-1, and the twentieth via hole V20 is configured to connect the subsequently formed seventh connection electrode to the first light-emitting connection block 31-1 through the via hole.

[0224] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the second light-emitting connection block 32-1 of the second light-emitting signal line 32 on the substrate, the fourth insulating layer in the twenty-first via hole V21 is etched away, exposing the surface of the second light-emitting connection block 32-1, and the twenty-first via hole V21 is configured to connect the subsequently formed eighth connection electrode to the second light-emitting connection block 32-1 through the via hole.

[0225] In an exemplary embodiment, the orthographic projection of the twenty-second via V22 on the substrate is located within the range of the orthographic projection of the second reference connection block 92-1 of the second reference signal line 92 on the substrate, the fourth insulating layer in the twenty-second via V22 is etched away to expose the surface of the second reference connection block 92-1, and the twenty-second via V22 is configured to connect the subsequently formed sixth connection electrode to the second reference connection block 92-1 through the via.

[0226] In an exemplary embodiment, the orthographic projection of the twenty-third via V23 on the substrate is located within the range of the orthographic projection of the first initial connection block 81-1 of the first initial signal line 81 on the substrate, the fourth insulating layer in the twenty-third via V23 is etched away, exposing the surface of the first initial connection block 81-1, and the twenty-third via V23 is configured to connect the subsequently formed ninth connection electrode to the first initial connection block 81-1 through the via.

[0227] (15) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on the fourth insulating layer, as shown in FIG11A and FIG11B , where FIG11B is a schematic diagram of the third conductive layer in FIG11A . In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0228] In an exemplary embodiment, the third conductive layer pattern of each circuit unit in the display substrate may include: a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45, a sixth connection electrode 46, a seventh connection electrode 47, an eighth connection electrode 48, a ninth connection electrode 49, a second scan signal line 62, a third scan signal line 63, a fourth scan signal line 64, a fifth scan signal line 65, a first power connection line 68, a second power connection line 69, a second initial signal line 82 and a first reference signal line 91.

[0229] In an exemplary embodiment, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the fifth scan signal line 65, the first power connection line 68, the second power connection line 69, the second initial signal line 82, and the first reference signal line 91 may be in the shape of lines whose main portions extend along the first direction X. The second scan signal line 62, the third scan signal line 63, and the first reference signal line 91 may be located on a side of the fourth electrode plate 74 opposite to the second direction Y. The fourth scan signal line 64, the fifth scan signal line 65, and the second initial signal line 82 may be located on a side of the third electrode plate 73 in the second direction Y. The first power connection line 68 may be located in the area where the third electrode plate 73 is located. The second power connection line 69 may be located between the fifth scan signal line 65 and the second initial signal line 82. The second power connection line 69 may be located on a side of the first power connection line 68 in the second direction Y.

[0230] In an exemplary embodiment, the orthographic projection of the second power connection line 69 on the substrate at least partially overlaps the orthographic projection of the first initial signal line 81 on the substrate. The second power connection line 69 is configured to connect to a subsequently formed second power line, forming a mesh-like interconnected low-voltage power grid structure on the display substrate. In an exemplary embodiment, the first reference signal line 91 may be located on the side of the fourth electrode plate 74 opposite to the second direction Y, the second scan signal line 62 may be located on the side of the first reference signal line 91 opposite to the second direction Y, and the third scan signal line 63 may be located on the side of the second scan signal line 62 opposite to the second direction Y.

[0231] In an exemplary embodiment, the fourth scan signal line 64 can be located on one side of the third electrode 73 in the second direction Y, the fifth scan signal line 65 can be located on one side of the fourth scan signal line 64 in the second direction Y, the second power connection line 69 can be located on one side of the fifth scan signal line 65 in the second direction Y, and the second initial signal line 82 can be located on one side of the second power connection line 69 in the second direction Y.

[0232] In an exemplary embodiment, the second scan signal line 62 is connected to the ninth gate electrode 29 in each circuit unit through the nineteenth via V19, thereby realizing that the second scan signal line 62 is connected to the ninth gate electrode 29 of the ninth transistor T9, and the second scan signal line 62 can control the conduction and disconnection of the ninth transistor T9.

[0233] In an exemplary embodiment, the second scan signal line 62 may be provided with a second scan connection block 62-1, which may be rectangular. The middle portion of the second scan connection block 62-1 is connected to the second scan signal line 62, a first end of the second scan connection block 62-1 extends toward the first reference signal line 91, and a second end of the second scan connection block 62-1 extends toward the third scan signal line 63. In an exemplary embodiment, the second scan connection block 62-1 is configured to be connected to the ninth gate electrode 29 in each circuit unit through the nineteenth via V19, thereby enabling the second scan signal line 62 to be connected to the ninth gate electrode 29 of the ninth transistor T9. The second scan signal line 62 can control the conduction and disconnection of the ninth transistor T9.

[0234] In an exemplary embodiment, the fifth scan signal line 65 is connected to the second gate electrode 22 in each circuit unit through the fifteenth via V15, thereby achieving the connection between the fifth scan signal line 65 and the second gate electrode 22 of the second transistor T2, and the fifth scan signal line 65 can control the conduction and disconnection of the second transistor T2.

[0235] In an exemplary embodiment, the fifth scan signal line 65 may be provided with a fifth scan connection block 65-1, which may be rectangular. The middle portion of the fifth scan connection block 65-1 is connected to the fifth scan signal line 65, a first end of the fifth scan connection block 65-1 extends toward the second initial signal line 82, and a second end of the fifth scan connection block 65-1 extends toward the first reference signal line 91. In an exemplary embodiment, the fifth scan connection block 65-1 is configured to be connected to the second gate electrode 22 in each circuit unit through a fifteenth via V15, thereby enabling the fifth scan signal line 65 to be connected to the second gate electrode 22 of the second transistor T2. The fifth scan signal line 65 can control the conduction and disconnection of the second transistor T2.

[0236] In an exemplary embodiment, the second scan signal line 62 and the fifth scan signal line 65 can be extended to the frame area and connected to the same gate driving circuit to output the same scan signal, that is, the second scan signal line 62 and the fifth scan signal line 65 output the same second scan signal.

[0237] In an exemplary embodiment, the third scan signal line 63 is connected to the fourth gate electrode 24 in each circuit unit through the sixteenth via V16, thereby realizing that the third scan signal line 63 is connected to the fourth gate electrode 24 of the fourth transistor T4, and the third scan signal line 63 can control the conduction and disconnection of the fourth transistor T4.

[0238] In the exemplary embodiment, a third scan connection block 63-1 is provided on a side of the third scan signal line 63 close to the first reference signal line 91. A first end of the third scan connection block 63-1 is connected to the third scan signal line 63, and a second end of the third scan connection block 63-1 extends toward the first reference signal line 91. In the exemplary embodiment, the third scan connection block 63-1 is configured to be connected to the fourth gate electrode 24 in each circuit unit through the sixteenth via V16. This enables the third scan signal line 63 to be connected to the fourth gate electrode 24 of the fourth transistor T4. The third scan signal line 63 can control the conduction and disconnection of the fourth transistor T4.

[0239] In an exemplary embodiment, the fourth scan signal line 64 is connected to the first gate electrode 21 in each circuit unit through the fourteenth via V14, thereby connecting the fourth scan signal line 64 to the first gate electrode 21 of the first transistor T1. The fourth scan signal line 64 can control the on and off of the first transistor T1.

[0240] In an exemplary embodiment, the fourth scan signal line 64 may be provided with a fourth scan connection block 64-1, which may be rectangular. The middle portion of the fourth scan connection block 64-1 is connected to the fourth scan signal line 64, a first end of the fourth scan connection block 64-1 extends toward the second initial signal line 82, and a second end of the fourth scan connection block 64-1 extends toward the first reference signal line 91. In an exemplary embodiment, the fourth scan connection block 64-1 is configured to be connected to the first gate electrode 21 in each circuit unit through a fourteenth via V14, thereby enabling the fourth scan signal line 64 to be connected to the first gate electrode 21 of the first transistor T1. The fourth scan signal line 64 can control the conduction and disconnection of the first transistor T1.

[0241] In an exemplary embodiment, the second initial signal line 82 is connected to the first region of the seventh active layer in each circuit unit through the seventh via V7, thereby realizing that the second initial signal line 82 is connected to the first electrode of the seventh transistor T7, and the second initial signal line 82 can write the second initial signal into the first electrode of the seventh transistor T7.

[0242] In an exemplary embodiment, a second initial connection block 82-1 is provided on a side of the second initial signal line 82 close to the fifth scan signal line 65. A first end of the second initial connection block 82-1 is connected to the second initial signal line 82, and a second end of the second initial connection block 82-1 extends toward the fifth scan signal line 65. In an exemplary embodiment, the second initial connection block 82-1 is configured to be connected to the first region of the seventh active layer in each circuit unit through the seventh via V7, thereby enabling the second initial signal line 82 to be connected to the first electrode of the seventh transistor T7. The second initial signal line 82 can write the second initial signal into the first electrode of the seventh transistor T7. In an exemplary embodiment, since the second active connection line 20 of the semiconductor layer is directly connected to the first area of ​​the seventh active layer of multiple circuit units in a unit row, and the second initial signal line 82 of the third conductive layer is connected to the first area of ​​the seventh active layer in multiple circuit units in a unit row through a via, the second active connection line 20 and the second initial signal line 82 constitute a signal line with a double-layer structure, which not only ensures that the first areas of multiple seventh active layers in a unit row have the same potential, but also reduces the resistance of the signal line and the voltage drop of the second initial signal, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0243] In an exemplary embodiment, the first reference signal line 91 is connected to the first region of the ninth active layer in each circuit unit through the ninth via V9, thereby realizing that the first reference signal line 91 is connected to the first electrode of the ninth transistor T9, and the first reference signal line 91 can write the first reference signal into the first electrode of the ninth transistor T9.

[0244] In an exemplary embodiment, a first reference connection block 91-1 is provided on one side of the first reference signal line 91 close to the first power connection line 68, a first end of the first reference connection block 91-1 is connected to the first reference signal line 91, and a second end of the first reference connection block 91-1 extends toward the direction of the first power connection line 68, and the first reference connection block 91-1 is configured to be connected to the first region of the ninth active layer through the ninth via V9 on the one hand, and to be connected to the reference signal connection line formed subsequently on the other hand.

[0245] In an exemplary embodiment, the first active connection line 10 may be shaped like a zigzag line, with the main portion extending along the first direction X. The first active connection line 10 and the ninth active layers of the plurality of circuit units may be interconnected as an integral structure. Because the first region of the ninth active layer is connected to a subsequently formed first reference signal line, the first active connection line 10 can be reused as a first reference signal line extending along the first direction X. This not only ensures that the first regions of the plurality of ninth active layers in a cell row have the same potential, but also reduces the voltage drop of the first reference signal, thereby improving the uniformity of the panel, preventing display defects on the display substrate, and ensuring the display quality of the display substrate.

[0246] In the exemplary embodiment, the first power connection line 68 is connected to the fourth electrode plate 74 in each circuit unit through the thirteenth via V13, thereby achieving the connection between the first power connection line 68 and the fourth electrode plate 74. Since the first power connection line 68 is connected to the first power line formed later, the first power connection line 68 can write the first power signal to the upper electrode plate of the second storage capacitor.

[0247] In the exemplary embodiment, a first power connection block 68-1 is provided on a side of the first power connection line 68 away from the second power connection line 69. A first end of the first power connection block 68-1 is connected to the first power connection line 68, and a second end of the first power connection block 68-1 extends in a direction away from the second power connection line 69. In the exemplary embodiment, the first power connection block 68-1 is configured to be connected to the fourth electrode plate 74 through the thirteenth via V13, and is also configured to be connected to a first power line to be formed later.

[0248] In an exemplary embodiment, the orthographic projection of the first power connection line 68 on the substrate at least partially overlaps with the orthographic projection of the third electrode plate 73 on the substrate, and the first power connection line 68 is configured to be connected to the subsequently formed first power line to form a high-voltage power grid structure with a mesh-like interconnected structure on the display substrate.

[0249] In an exemplary embodiment, in at least one circuit unit, a second power connection block 69-1 is provided on a side of the second power connection line 69 away from the first power connection line 68. A first end of the second power connection block 69-1 is connected to the second power connection line 69, and a second end of the second power connection block 69-1 extends in a direction away from the first power connection line 68. The second power connection block 69-1 is configured to be connected to a second power line formed later. In an exemplary embodiment, the second power connection block 69-1 can be provided between the first circuit unit and the second circuit unit.

[0250] In an exemplary embodiment, the orthographic projection of the second power connection line 69 on the substrate at least partially overlaps with the orthographic projection of the first initial signal line 81 on the substrate, and the second power connection line 69 is configured to be connected to a subsequently formed second power line to form a low-voltage power grid structure with a mesh-like interconnected structure on the display substrate.

[0251] In an exemplary embodiment, the first connection electrode 41 may be in the shape of a strip with a main portion extending along the second direction Y. The first connection electrode 41 may be located between the fourth scan signal line 64 and the first power connection line 68. A first end of the first connection electrode 41 is connected to the second region of the first active layer (also the first region of the second active layer) via a second via hole V2, and a second end of the first connection electrode 41 is connected to the first electrode plate 71 via a tenth via hole V10. In an exemplary embodiment, the first connection electrode 41 enables the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 71 of the first storage capacitor (i.e., the first end of the first storage capacitor) to have the same potential. The first connection electrode 41 may serve as the first node N1 of the pixel driving circuit.

[0252] In an exemplary embodiment, the second connection electrode 42 may be shaped like a zigzag line with a main portion extending along the second direction Y. The second connection electrode 42 may be located between the first reference signal line 91 and the first power connection line 68. A first end of the second connection electrode 42 is connected to the second region of the fourth active layer (also the second region of the ninth active layer) via a fourth via V4. A second end of the second connection electrode 42 is connected to the third electrode plate 73 via a twelfth via V12. A third end between the first and second ends is connected to the second electrode plate 72 via an eleventh via V11. In an exemplary embodiment, the second connection electrode 42 causes the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the third electrode plate 73 of the first storage capacitor (i.e., the second end of the first storage capacitor), and the second electrode plate 72 of the second storage capacitor (i.e., the second end of the second storage capacitor) to have the same potential. The second connection electrode 42 may serve as the fifth node N5 of the pixel driving circuit.

[0253] In an exemplary embodiment, the third connection electrode 43 may be rectangular in shape and may be located between the first reference signal line 91 and the first power connection line 68. The third connection electrode 43 is connected to the first region of the fourth active layer through a third via V3. In an exemplary embodiment, the third connection electrode 43 may serve as a first electrode of the fourth transistor T4 and may be configured to be connected to a subsequently formed data signal line.

[0254] In an exemplary embodiment, the fourth connection electrode 44 may be rectangular in shape and may be located between the fifth scan signal line 65 and the second initial signal line 82. The fourth connection electrode 44 is connected to the first region of the fifth active layer through a fifth via hole V5. In an exemplary embodiment, the fourth connection electrode 44 may serve as a first electrode of the fifth transistor T5 and may be configured to be connected to a first power line formed subsequently.

[0255] In an exemplary embodiment, the fifth connection electrode 45 may be in an "L" shape and may be located between the fifth scan signal line 65 and the second initial signal line 82. The fifth connection electrode 45 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through a sixth via hole V6. In an exemplary embodiment, the fifth connection electrode 45 may serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 and is configured to be connected to an anode connection electrode formed subsequently.

[0256] In an exemplary embodiment, the sixth connection electrode 46 may be in the shape of a strip with a main portion extending along the first direction X. The sixth connection electrode 46 may be located between the fifth scan signal line 65 and the second initial signal line 82. A first end of the sixth connection electrode 46 is connected to the first region of the eighth active layer via an eighth via hole V8, and a second end of the sixth connection electrode 46 is connected to the second reference connection block 92-1 via a twenty-second via hole V22. In an exemplary embodiment, the sixth connection electrode 46 may serve as the first electrode of the eighth transistor T8. Since the second reference connection block 92-1 is connected to the second reference signal line 92, the second reference signal line 92 is connected to the first electrode of the eighth transistor T8. The second reference signal line 92 in the nth cell row may write the second reference signal into the first electrode of the eighth transistor T8 in the (n-1)th cell row.

[0257] In an exemplary embodiment, the seventh connection electrode 47 may be in the shape of a bar with a main portion extending along the first direction X. The seventh connection electrode 47 may be located between the fifth scan signal line 65 and the second initial signal line 82. A first end of the seventh connection electrode 47 is connected to the fifth gate electrode 25 via a seventeenth via hole V17, and a second end of the seventh connection electrode 47 is connected to the first light-emitting connection block 31-1 via a twentieth via hole V20. Since the first light-emitting connection block 31-1 is connected to the first light-emitting signal line 31, the first light-emitting signal line 31 is connected to the fifth gate electrode 25 of the fifth transistor T5. The first light-emitting signal line 31 can control the conduction and disconnection of the fifth transistor T5.

[0258] In an exemplary embodiment, the eighth connection electrode 48 may be in the shape of a bar with a main portion extending along the first direction X. The eighth connection electrode 48 may be located between the fifth scan signal line 65 and the second initial signal line 82. A first end of the eighth connection electrode 48 is connected to the sixth gate electrode 26 via an eighteenth via hole V18, and a second end of the eighth connection electrode 48 is connected to the second light-emitting connection block 32-1 via a twenty-first via hole V21. Since the second light-emitting connection block 32-1 is connected to the second light-emitting signal line 32, the second light-emitting signal line 32 is connected to the sixth gate electrode 26 of the sixth transistor T6. The second light-emitting signal line 32 can control the conduction and disconnection of the sixth transistor T6.

[0259] In an exemplary embodiment, the ninth connection electrode 49 may be in the shape of a strip with a main portion extending along the first direction X. The ninth connection electrode 49 may be located between the fifth scan signal line 65 and the second initial signal line 82. A first end of the ninth connection electrode 49 is connected to the first region of the first active layer via a first via hole V1, and a second end of the ninth connection electrode 49 is connected to the first initial connection block 81-1 via a twenty-third via hole V23. Since the first initial connection block 81-1 is connected to the first initial signal line 81, the first initial signal line 81 is connected to the first electrode of the first transistor T1. The first initial signal line 81 can write the first initial signal to the first electrode of the first transistor T1.

[0260] (16) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming the fifth insulating layer pattern may include: depositing a fifth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fifth insulating film using a patterning process to form a fifth insulating layer covering the third conductive layer, wherein a plurality of vias are provided in each circuit unit, as shown in FIG. 12 .

[0261] In an exemplary embodiment, the plurality of via holes of each circuit unit in the display substrate includes at least a thirty-first via hole V31 , a thirty-second via hole V32 , a thirty-third via hole V33 , a thirty-fourth via hole V34 , and a thirty-fifth via hole V35 .

[0262] In an exemplary embodiment, the orthographic projection of the thirty-first via V31 on the substrate is located within the range of the orthographic projection of the third connecting electrode 43 on the substrate, the fifth insulating layer in the thirty-first via V31 is removed, exposing the surface of the third connecting electrode 43, and the thirty-first via V31 is configured to connect a subsequently formed data signal line to the third connecting electrode 43 through the via.

[0263] In an exemplary embodiment, the orthographic projection of the thirty-second via V32 on the substrate is located within the range of the orthographic projection of the fourth connecting electrode 44 on the substrate, the fifth insulating layer in the thirty-second via V32 is removed, exposing the surface of the fourth connecting electrode 44, and the thirty-second via V32 is configured to connect the subsequently formed first power line to the fourth connecting electrode 44 through the via.

[0264] In an exemplary embodiment, the orthographic projection of the thirty-third via V33 on the substrate is located within the range of the orthographic projection of the fifth connecting electrode 45 on the substrate, the fifth insulating layer in the thirty-third via V33 is removed, exposing the surface of the fifth connecting electrode 45, and the thirty-third via V33 is configured to connect the subsequently formed anode connecting electrode to the fifth connecting electrode 45 through the via.

[0265] In an exemplary embodiment, the orthographic projection of the thirty-fourth via V34 on the substrate is located within the range of the orthographic projection of the first reference connection block 91-1 of the first reference signal line 91 on the substrate, the fifth insulating layer in the thirty-fourth via V34 is removed, exposing the surface of the first reference connection block 91-1, and the thirty-fourth via V34 is configured to connect the subsequently formed reference signal connection line to the first reference connection block 91-1 through the via.

[0266] In an exemplary embodiment, the orthographic projection of the thirty-fifth via V35 on the substrate is located within the range of the orthographic projection of the first power connection block 68-1 of the first power connection line 68 on the substrate, the fifth insulating layer in the thirty-fifth via V35 is removed, exposing the surface of the first power connection block 68-1, and the thirty-fifth via V35 is configured to connect the subsequently formed first power line to the first power connection block 68-1 through the via.

[0267] In an exemplary embodiment, at least one circuit unit may further include a thirty-sixth via V36. The orthographic projection of the thirty-sixth via V36 on the substrate is located within the orthographic projection of the second power connection block 69-1 of the second power connection line 69 on the substrate. The fifth insulating layer within the thirty-sixth via V36 is removed, exposing the surface of the second power connection block 69-1. The thirty-sixth via V36 is configured to connect a subsequently formed second power line to the second power connection block 69-1 through the via. In an exemplary embodiment, the thirty-sixth via V36 may be located between the first circuit unit and the second circuit unit.

[0268] (17) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the fifth insulating layer, as shown in Figures 13 and 13B. Figure 14 is a schematic diagram of the fourth conductive layer in Figure 13. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0269] In an exemplary embodiment, the fourth conductive layer pattern of each circuit unit in the display substrate may include a first power supply line 51 , a data signal line 53 , a reference signal connection line 54 , and an anode connection electrode 55 .

[0270] In an exemplary embodiment, the shape of the first power line 51, the data signal line 53 and the reference signal connection line 54 can be a strip shape with the main portion extending along the second direction Y, the first power line 51 can be located on one side of the data signal line 53 in the first direction X, and the reference signal connection line 54 can be located on one side of the first power line 51 in the first direction X, that is, the first power line 51 can be located between the data signal line 53 and the reference signal connection line 54.

[0271] In an exemplary embodiment, the first power line 51 may be shaped like a zigzag line with a main portion extending along the second direction Y. The first power line 51 is connected to the fourth connection electrode 44 via the thirty-second via V32 and to the first power connection block 68-1 via the thirty-fifth via V35. Since the fourth connection electrode 44 is connected to the first region of the fifth active layer via the via, the first power line 51 writes the first power signal to the first electrode of the fifth transistor T5. Since the first power connection block 68-1 is connected to the first power connection line 68, the first power connection line 68, whose main portion extends along the first direction X, is interconnected with the first power line 51, whose main portion extends along the second direction Y. This allows the first power lines 51 and 68 to form a mesh structure on the display substrate that transmits the first power signal. This effectively reduces the resistance of the first power line 51 and the voltage drop of the first power signal, and also effectively improves the uniformity of the first power signal across the display substrate, thereby enhancing display uniformity and improving display quality.

[0272] In an exemplary embodiment, a power shielding block 51-1 is disposed on a side of the first power line 51 near the reference signal connection line 54. A first end of the power shielding block 51-1 is connected to the first power line 51, and a second end of the power shielding block 51-1 extends toward the reference signal connection line 54. The power shielding block 51-1 may be rectangular in shape, and the orthographic projection of the power shielding block 51-1 on the substrate at least partially overlaps with the orthographic projection of the first connection electrode 41 on the substrate. Because the first connection electrode 41 serves as the first node N1 in the pixel driving circuit, the constant voltage power shielding block 51-1 can effectively shield the first node N1 from the effects of other signals in the pixel driving circuit, preventing other signals (such as data voltage jumps) from affecting the potential of the first node N1 of the pixel driving circuit, thereby improving the display effect.

[0273] In an exemplary embodiment, the first power line 51 and the power shielding block 51 - 1 may be an integral structure connected to each other.

[0274] In an exemplary embodiment, the orthographic projection of the power shielding block 51 - 1 on the substrate may include the orthographic projection of the first connection electrode 41 on the substrate.

[0275] In an exemplary embodiment, a third power connection block 51-2 is provided on a side of the first power line 51 near the reference signal connection line 54. The third power connection block 51-2 may be in the shape of a bar extending along the first direction X. A first end of the third power connection block 51-2 is connected to the first power line 51, and a second end of the third power connection block 51-2 extends toward the reference signal connection line 54 and is connected to the first power connection block 68-1 through a thirty-fifth via V35.

[0276] In an exemplary embodiment, the first power line 51 and the third power connection block 51 - 2 may be an integral structure connected to each other.

[0277] In the exemplary embodiment, the orthographic projection of the first power line 51 on the substrate at least partially overlaps with the orthographic projection of the second connection electrode 42 on the substrate. Because the second connection electrode 42 serves as the fifth node N5 in the pixel driving circuit, the constant voltage first power line 51 can effectively shield the fifth node N5 from the influence of other signals in the pixel driving circuit, preventing other signals from affecting the potential of the fifth node N5 of the pixel driving circuit, thereby improving the display effect.

[0278] In an exemplary embodiment, the first power lines 51 may be designed with unequal widths. The unequal width design of the first power lines 51 not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the first power lines and the data signal lines.

[0279] In an exemplary embodiment, the data signal line 53 may be in the shape of a straight line with a main portion extending along the second direction Y. The data signal line 53 is connected to the third connection electrode 43 through the thirty-first via hole V31. Since the third connection electrode 43 is connected to the first region of the fourth active layer through the via hole, the data signal line 53 writes the data signal to the first electrode of the fourth transistor T4.

[0280] In an exemplary embodiment, a data signal connection block 53-1 is provided on a side of the data signal line 53 close to the first power line 51. A first end of the data signal connection block 53-1 is connected to the data signal line 53, and a second end of the data signal connection block 53-1 extends toward the first power line 51. The data signal connection block 53-1 may be rectangular in shape. The data signal connection block 53-1 is configured to be connected to the third connection electrode 43 through the thirty-first via hole V31.

[0281] In an exemplary embodiment, the reference signal connection line 54 may be shaped as a straight line, with the main portion extending along the second direction Y. The reference signal connection line 54 is connected to the first reference connection block 91-1 via a thirty-fourth via hole V34. Since the first reference connection block 91-1 is connected to the first reference signal line 91, the first reference signal line 91, whose main portion extends along the first direction X, is interconnected with the reference signal connection line 54, whose main portion extends along the second direction Y. This allows the first reference signal line 91 and the reference signal connection line 54 to form a mesh structure on the display substrate for transmitting the first reference signal. This effectively reduces the resistance of the first reference signal line and the voltage drop of the first reference signal, and also effectively improves the uniformity of the first reference signal across the display substrate, thereby enhancing display uniformity and improving display quality.

[0282] In an exemplary embodiment, a reference signal connection block 54-1 is provided on a side of the reference signal connection line 54 close to the data signal line 53. A first end of the reference signal connection block 54-1 is connected to the reference signal connection line 54, and a second end of the reference signal connection block 54-1 extends toward the data signal line 53. The reference signal connection block 54-1 may be rectangular in shape. The reference signal connection block 54-1 is configured to be connected to the first reference connection block 91-1 through the thirty-fourth via V34.

[0283] In an exemplary embodiment, the anode connection electrode 55 may be rectangular in shape and is connected to the fifth connection electrode 45 via a thirty-third via hole V33. Since the fifth connection electrode 45 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) via the via hole, the anode connection electrode 55 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. In an exemplary embodiment, the anode connection electrode 55 is configured to be connected to a subsequently formed anode, thereby enabling the pixel driving circuit to drive the light-emitting device.

[0284] In an exemplary embodiment, an orthographic projection of the anode connection electrode 55 on the substrate at least partially overlaps with an orthographic projection of the repair line 33 on the substrate.

[0285] In an exemplary embodiment, at least one circuit unit may further include a second power line 52. The second power line 52 may be in the form of a straight line with a main portion extending along the second direction Y. The second power line 52 is connected to the second power connection block 69-1 via a thirty-sixth via hole V36. Since the second power connection block 69-1 is connected to the second power connection line 69, the second power connection line 69 extending along the first direction X and the second power line 52 extending along the second direction Y are interconnected. This allows the second power lines 52 and 69 to form a mesh structure on the display substrate that transmits the second power signal. This not only effectively reduces the resistance of the second power line 52 and the voltage drop of the second power signal, but also effectively improves the uniformity of the second power signal across the display substrate, effectively enhancing display uniformity and improving display quality.

[0286] In an exemplary embodiment, the second power line 52 may be located between the reference signal connection line 54 of the first circuit unit and the data signal line 53 of the second circuit unit.

[0287] In an exemplary embodiment, the second power line 52 is provided with a fourth power connection block 52-1. The middle portion of the fourth power connection block 52-1 is connected to the second power line 52. The first end of the fourth power connection block 52-1 extends toward the reference signal connection line 54 of the first circuit unit, and the second end of the fourth power connection block 52-1 extends toward the data signal line 53 of the second circuit unit. The fourth power connection block 52-1 can be rectangular in shape. In an exemplary embodiment, the fourth power connection block 52-1 is configured to connect to the second power connection block 69-1 through the thirty-sixth via V36.

[0288] In an exemplary embodiment, the first power connection line 68 of the third conductive layer can be set in each unit row, and the first power line 51 of the fourth conductive layer can be set in each unit column. Multiple first power lines 51 are respectively connected to multiple first power connection lines 68 to form a mesh structure for transmitting the first power signal.

[0289] In an exemplary embodiment, the first reference signal line 91 of the third conductive layer can be set in each unit row, and the reference signal connection line 54 of the fourth conductive layer can be set in each unit column. Multiple first reference signal lines 91 are respectively connected to multiple reference signal connection lines 54 to form a mesh structure for transmitting the first reference signal.

[0290] In an exemplary embodiment, the second power connection line 69 of the third conductive layer can be arranged in each unit row, and the second power line 52 of the fourth conductive layer can be arranged every two unit columns. Multiple second power lines 52 are respectively connected to multiple second power connection lines 69 to form a mesh structure for transmitting the second power signal.

[0291] The subsequent preparation process may include forming a first flat layer pattern, a plurality of anode vias are provided on the first flat layer, the orthographic projection of the anode vias on the substrate is located within the range of the orthographic projection of the anode connection electrode on the substrate, the first flat layer in the anode via is removed to expose the surface of the anode connection electrode, and the anode via is configured to connect the subsequently formed anode to the anode connection electrode through the via.

[0292] At this point, the driving circuit layer of this embodiment is prepared on the substrate. In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer and an encapsulation structure layer can be sequentially prepared on the driving circuit layer, which will not be described in detail here.

[0293] The inventors of the present disclosure have discovered that the flatness of the anode in a display panel may adversely affect image display. For example, the tilt of the anode may cause color separation. In the present disclosure, it was discovered that the signal line under the anode can significantly affect the degree of anode tilt. In one example, under the anode, a signal line is arranged on one side, while no signal line exists on the other side. This results in an uneven surface of the planarization layer above the signal line. The uneven surface of the planarization layer in turn causes the anode above the planarization layer to tilt. For example, the presence of a signal line under the left portion of the planarization layer results in an uneven surface of the planarization layer, which in turn causes the anode above the planarization layer to tilt toward the right. The tilted anode reflects more light toward the right side of the display panel. In a display panel, the anodes associated with sub-pixels of different colors have different tilt angles, so the light reflected by the anodes in the sub-pixels of different colors reflects light of different colors at different angles. The cumulative effect of this problem leads to color separation at large viewing angles.

[0294] The inventors of the present disclosure have also discovered that with the development of color on encapsulation (COE) technology, the color separation problem caused by the unevenness of the surface on which the anode is disposed has become more prominent.

[0295] Figure 15 shows light reflection from anodes in a related array substrate. Figure 15 shows a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. As shown in Figure 15 , ambient light enters a sub-pixel and is reflected by the corresponding anode in the sub-pixel.

[0296] FIG16 illustrates color separation occurring in a related array substrate. Referring to FIG16 , when the array substrate is in a black screen state, light from an external light source ELS impinges on the array substrate and is reflected by the anodes (which function as mirrors). FIG3 illustrates a green subpixel matrix GSM and a red subpixel matrix RSM. External light enters the green subpixel matrix GSM and is reflected by the anodes in the green subpixel matrix GSM. The external light reflected by the anodes in the green subpixel matrix GSM is filtered at least once by a green color filter and converted into green light. External light enters the red subpixel matrix RSM and is reflected by the anodes in the red subpixel matrix RSM. The external light reflected by the anodes in the red subpixel matrix RSM is filtered at least once by a red color filter and converted into red light. When an observer's eye E views the displayed image, it perceives an image formed by the reflected green and red light. However, because the anodes in the green subpixel matrix GSM are tilted differently than those in the red subpixel matrix RSM, the observer's eye E sees two separate images: a green image and a red image. This difference in anode tilt results in color separation in the displayed image, where the green and red components appear slightly separated or misaligned.

[0297] To address at least one of the above problems, an embodiment of the present application provides a display substrate, as shown in FIG3 , FIG6 , and FIG17 , wherein FIG17 is a schematic diagram showing a first anode portion (shown in a thick solid frame in FIG17 ) based on FIG6 , including:

[0298] substrate 101;

[0299] The driving circuit layer 102 is located on one side of the substrate 101. The driving circuit layer 102 may include at least a plurality of circuit units, at least one of which includes a pixel driving circuit. At least one of the plurality of pixel driving circuits includes at least one storage capacitor. The storage capacitor includes two oppositely disposed plates. For example, as shown in FIG6 , the pixel driving circuit may include a first storage capacitor and a second storage capacitor. The first storage capacitor may include a first plate 71 and a third plate 73 oppositely disposed plates. The second storage capacitor may include a second plate 72 and a fourth plate 74 oppositely disposed plates.

[0300] The light-emitting structure layer 103 is located on a side of the driving circuit layer 102 facing away from the substrate 101 and includes at least a plurality of light-emitting units, at least one of which includes a light-emitting device. The light-emitting device may include at least an anode, an organic light-emitting layer, and a cathode. The anode in the light-emitting unit is connected to the pixel driving circuit in the corresponding circuit unit. The light-emitting structure layer 103 may also include a pixel definition layer located on a side of the anode layer facing away from the driving structure layer. The pixel definition layer includes: a plurality of sub-pixel openings; at least one of the plurality of anodes includes: a first anode portion ADA located in at least one of the plurality of sub-pixel openings;

[0301] The orthographic projection of at least one plate of at least one storage capacitor on the substrate has a first overlapping region with the orthographic projection of at least one first anode portion ADA on the substrate, and the first overlapping region is an axisymmetric pattern. For example, as shown in FIG17 , the orthographic projection of the first anode portion ADA on the substrate covers the orthographic projection of the first plate 71 of the first storage capacitor on the substrate. The first overlapping region formed by the orthographic projection of the first plate 71 on the substrate and the orthographic projection of the first anode portion ADA on the substrate is the region where the first plate 71 is located, and the first overlapping region is an axisymmetric pattern.

[0302] In the embodiment of the present disclosure, by making the orthographic projection of at least one electrode plate on the substrate and the orthographic projection of at least one first anode portion ADA on the substrate an axially symmetrical pattern, since the electrode plate of the storage capacitor is usually a whole flat film layer with a large area, by making a relatively large part of the first anode portion ADA be arranged in the area where the electrode plate of the storage capacitor is located (for example: the overlapping area of ​​the first anode portion ADA and the electrode plate of at least one storage capacitor is larger than the overlapping area of ​​the first anode portion ADA with the storage capacitor electrode plate), the flatness consistency of the first anode portion ADA can be improved, the color separation problem caused by the unevenness of the first anode portion ADA can be avoided, the product display effect can be improved, and it has broad application prospects.

[0303] In a possible implementation, the size and / or position of the first anode portion ADA and the size and / or position of the storage capacitor may be adjusted so that the overlapping region thereof forms an axisymmetric pattern.

[0304] In one possible embodiment, the first overlapping region is an axisymmetric pattern, which can be understood as the first overlapping region having at least one axis of symmetry, and the first overlapping region is symmetrical about the axis of symmetry. In one possible embodiment, the axis of symmetry of the first overlapping region can be parallel to the first direction X; in another possible embodiment, the axis of symmetry of the first overlapping region can be parallel to the second direction Y.

[0305] In one possible embodiment, the orthographic projection of the plate near the anode in the storage capacitor on the substrate has a first overlapping area with the orthographic projection of the first anode portion on the substrate, and the first overlapping area is an axisymmetric pattern. Optionally, for example, in the first storage capacitor, the third plate 73 is located on the side of the first plate 71 closer to the anode, then the overlapping area between the third plate 73 and the first anode portion ADA can be an axisymmetric pattern. For another example, in the second storage capacitor, the fourth plate 74 is located on the side of the second plate 72 closer to the anode, then the overlapping area between the fourth plate 74 and the first anode portion ADA can be an axisymmetric pattern.

[0306] In the embodiment of the present disclosure, by making the overlapping area of ​​the orthographic projection of the plate close to the anode in the storage capacitor on the substrate and the orthographic projection of the first anode part on the substrate an axially symmetrical pattern, it is more conducive to achieving the consistency of the flatness of the first anode part ADA and improving the color separation problem caused by the unevenness of the first anode part ADA.

[0307] In one possible embodiment, the orthographic projection of the electrode plate on the substrate is an axisymmetric pattern, the orthographic projection of the first anode portion ADA on the substrate is an axisymmetric pattern, and the symmetry axis of the electrode plate coincides with the symmetry axis of the first anode portion. For example, as shown in FIG17 , the orthographic projection of the third substrate 73 of the first storage capacitor on the substrate has a first symmetry axis k1 parallel to the second direction Y, and the orthographic projection of the first anode portion ADA on the substrate has a second symmetry axis k2 parallel to the second direction Y, and the first symmetry axis k1 coincides with the second symmetry axis k2.

[0308] In the embodiment of the present disclosure, the orthographic projection of the electrode plate on the substrate is an axially symmetrical pattern, the orthographic projection of the first anode portion ADA on the substrate is an axially symmetrical pattern, and the symmetry axis of the electrode plate coincides with the symmetry axis of the first anode portion, which is more conducive to making the overlapping area of ​​the electrode plate of the storage capacitor and the first anode portion ADA an axially symmetrical pattern, and further conducive to achieving the consistency of the flatness of the first anode portion ADA, and improving the color separation problem caused by the unevenness of the first anode portion ADA.

[0309] In one possible embodiment, an orthographic projection of at least one first anode portion ADA on the substrate has a first overlapping region with a plate of at least one storage capacitor in the same pixel driving circuit. For example, an orthographic projection of the first anode portion ADA on the substrate has an overlapping region with a plate of one storage capacitor in the same pixel driving circuit; for another example, an orthographic projection of the first anode portion ADA on the substrate has an overlapping region with the plates of both storage capacitors in the same pixel driving circuit.

[0310] In one possible embodiment, referring to FIG17 , the pixel driving circuit includes: a first storage capacitor C1, and a second storage capacitor C2; the orthographic projection area of ​​the first storage capacitor C1 on the substrate is larger than the orthographic projection area of ​​the second storage capacitor C2 on the substrate; the orthographic projection of the first anode portion ADA on the substrate has a first overlapping area only with the orthographic projection of one of the first storage capacitor C1 and the second storage capacitor C2 on the substrate.

[0311] In one possible embodiment, the orthographic projection of the first storage capacitor on the substrate can be understood as the orthographic projection of the overlapping area of ​​the first electrode plate 71 and the third electrode plate 73 in the first storage capacitor on the substrate. For example, the orthographic projection area of ​​the third electrode plate 73 on the substrate is larger than the orthographic projection area of ​​the first electrode plate 71 on the substrate, and the orthographic projection of the third electrode plate 73 on the substrate covers the orthographic projection of the first electrode plate 71 on the substrate. Then, the orthographic projection of the first storage capacitor on the substrate can be the area where the first electrode plate 71 is located; similarly, the orthographic projection of the second storage capacitor on the substrate can be understood as the orthographic projection of the overlapping area of ​​the second electrode plate 72 and the fourth electrode plate 74 in the second storage capacitor on the substrate.

[0312] In a possible embodiment, referring to FIG. 18A and FIG. 18B , the plurality of anodes include: a first anode AD1, a second anode AD2, and a third anode AD3; wherein the first anode AD1 may be the anode of a red sub-pixel, the second anode AD2 may be the anode of a green sub-pixel, and the third anode may be the anode of a blue sub-pixel; the anode of the red sub-pixel (i.e., the first anode AD1), the anode of the green sub-pixel (i.e., the second anode AD2), and the anode of the blue sub-pixel (i.e., the third anode AD3) may all include a first anode portion ADA (i.e., the portion of the anode exposed by the sub-pixel opening of the pixel definition layer); the wavelength band range of the outgoing light in the region where the first anode AD1 is located is greater than the wavelength band range of the outgoing light in the region where the second anode AD2 is located; the wavelength band range of the outgoing light in the region where the second anode AD2 is located is greater than the wavelength band range of the third anode AD3. The wavelength band range of the output light in the area where D3 is located; optionally, for example, the light output from the area where the first anode AD1 is located is red light, the light output from the area where the second anode AD2 is located is green light, and the light output from the area where the third anode AD3 is located is blue light; optionally, the first anode AD1 can be the anode of the red sub-pixel, the second anode AD2 can be the anode of the green sub-pixel, and the third anode AD3 can be the anode of the blue sub-pixel; the orthographic projection of the first anode portion ADA of the second anode AD2 on the substrate only has an overlapping area with the orthographic projection of the second storage capacitor C2 on the substrate; the orthographic projection of the first anode portion ADA of the first anode AD1 on the substrate only has an overlapping area with the orthographic projection of the first storage capacitor on the substrate; the orthographic projection of the first anode portion AD3 of the third anode AD3 on the substrate only has an overlapping area with the orthographic projection of the first storage capacitor on the substrate.

[0313] In the embodiment of the present disclosure, since the orthographic projection area of ​​the first storage capacitor C1 on the substrate is larger and the orthographic projection area of ​​the second storage capacitor C2 on the substrate is smaller, by making the second storage capacitor C2 with a smaller orthographic projection area overlap only with the first anode portion ADA of the second anode AD2 which also has a smaller orthographic projection area, and making the first storage capacitor C1 with a larger orthographic projection area overlap only with the first anode portion ADA of the first anode AD1 which also has a larger orthographic projection area, and making the first storage capacitor C1 with a larger orthographic projection area overlap only with the first anode portion ADA of the third anode AD3 which also has a larger orthographic projection area, the first anode portions ADA of different area sizes can all be relatively flat, thereby improving the color separation problem.

[0314] It can be understood that the orthographic projection of the first anode portion ADA of the second anode AD2 on the substrate has an overlapping area only with the orthographic projection of the second storage capacitor C2 on the substrate, and combined with Figure 18A or 18B, it refers to the first anode portion ADA and the second storage capacitor C2 in the same sub-pixel; the orthographic projection of the first anode portion ADA of the first anode AD1 on the substrate has an overlapping area only with the orthographic projection of the first storage capacitor C1 on the substrate, and combined with Figure 18A or 18B, it refers to the first anode portion ADA and the first storage capacitor C1 in the same sub-pixel; the orthographic projection of the first anode portion AD3 of the third anode AD3 on the substrate has an overlapping area only with the orthographic projection of the first storage capacitor C1 on the substrate, and combined with Figure 18A or 18B, it refers to the first anode portion ADA and the first storage capacitor C1 in the same sub-pixel.

[0315] In one possible embodiment, as shown in FIG18A , the orthographic projection of the first anode portion ADA on the substrate may be a rectangle. In another possible embodiment, as shown in FIG18B , the orthographic projection of the first anode portion ADA on the substrate may be an ellipse. Of course, the orthographic projection of the first anode portion ADA on the substrate may also be other shapes, such as a circle, a trapezoid, a pentagon, a hexagon, an octagon, or a rhombus.

[0316] In one possible embodiment, the pixel driving circuit includes: a first storage capacitor C1, and a second storage capacitor C2; the orthographic projection area of ​​the first storage capacitor C1 on the substrate is larger than the orthographic projection area of ​​the second storage capacitor C2 on the substrate; as shown in Figure 19, the orthographic projection of the first anode portion ADA on the substrate has an overlapping area with the orthographic projections of the first storage capacitor C1 and the second storage capacitor C2 on the substrate.

[0317] In a possible embodiment, referring to FIG19 , the orthographic projection of the first anode portion ADA on the substrate has a first capacitor overlapping area C10 with the orthographic projection of the plate substrate of the first storage capacitor C1; the orthographic projection of the first anode portion ADA on the substrate has a second capacitor overlapping area C20 with the orthographic projection of the plate substrate of the second storage capacitor C2; the first overlapping area includes the first capacitor overlapping area C10 and the second capacitor overlapping area C20; the area of ​​the first capacitor overlapping area C10 is greater than the area of ​​the second capacitor overlapping area C20.

[0318] In the disclosed embodiment, the first anode portion ADA has a larger overlapping area with the first storage capacitor C1 , which helps to make most of the area of ​​the first anode portion ADA in a relatively flat region, thereby improving the color separation problem.

[0319] In one possible implementation, the area of ​​the first capacitor overlap region C10 is 1.1 to 2.5 times the area of ​​the second capacitor overlap region C20. For example, the area of ​​the first capacitor overlap region C10 is 1.2, 1.5, or 2 times the area of ​​the second capacitor overlap region C20.

[0320] In one possible embodiment, as shown in FIG20 , the orthographic projection of at least one first anode portion ADA on the substrate has a first overlapping region with the plates of at least two storage capacitors in two adjacent pixel driving circuits. Optionally, as shown in FIG20 , the orthographic projection of the first anode portion ADA on the substrate has an overlapping region with the storage capacitor in the first circuit unit and also has an overlapping region with the storage capacitor in the second circuit unit.

[0321] In one possible embodiment, as shown in FIG20 , the orthographic projection of the first anode portion ADA on the substrate has a first sub-overlapping region CC1 with the plate of a storage capacitor in one pixel driver circuit; the orthographic projection of the first anode portion ADA on the substrate has a second sub-overlapping region CC2 with the plate of a storage capacitor in another pixel driver circuit; the first overlapping region includes the first sub-overlapping region CC1 and the second sub-overlapping region CC2; and at least a portion of the first sub-overlapping region CC1 is symmetrically distributed with at least a portion of the second sub-overlapping region CC2. For example, as shown in FIG20 , when an anode portion ADA overlaps with storage capacitors in different pixel driver circuits, this helps reduce color separation issues caused by unevenness of the first anode portion ADA.

[0322] In a possible embodiment, referring to FIG21 , the plurality of anodes AD include: a first anode AD1, a second anode AD2, and a third anode AD3; the wavelength band range of the outgoing light in the region where the first anode AD is located is greater than the wavelength band range of the outgoing light in the region where the second anode AD2 is located; the wavelength band range of the outgoing light in the region where the second anode AD2 is located is greater than the wavelength band range of the outgoing light in the region where the third anode AD3 is located; the first anode portion ADA of the first anode AD1 includes: two first sub-anode portions AD11 arranged adjacent to each other along the first direction X, and the two first sub-anode portions AD11 are symmetrically distributed. For example, as shown in FIG21 , the two first sub-anodes AD11 may be symmetrical about an axis k3 parallel to the second direction Y; the first anode portion ADA of the second anode AD2 includes: two second sub-anode portions AD22 arranged adjacent to each other along the first direction X, and the two second sub-anode portions AD22 are symmetrically distributed; the first anode portion ADA of the third anode AD3 includes: two third sub-anode portions AD33 arranged adjacent to each other along the first direction X, and the two third sub-anode portions AD33 are symmetrically distributed.

[0323] In an embodiment of the present invention, the first anode portion ADA includes two first sub-anode portions AD11, and the two first sub-anode portions AD11 are symmetrically distributed; the second anode AD2 includes two second sub-anode portions AD22, and the two second sub-anode portions AD22 are symmetrically distributed; the third anode AD3 includes two third sub-anode portions AD33, and the two third sub-anode portions AD33 are symmetrically distributed; that is, the light output colors of two adjacent sub-pixels are the same, and the sub-anode portions of two adjacent sub-pixels are symmetrically distributed, which can reduce color separation and crosstalk.

[0324] In a possible embodiment, referring to FIG21 , in the first anode AD1, the two first sub-anode portions AD11 are respectively driven by corresponding different pixel circuits; in the second anode AD2, the two second sub-anode portions AD22 are respectively driven by corresponding different pixel circuits; and in the third anode AD3, the two third sub-anode portions AD33 are respectively driven by corresponding different pixel circuits.

[0325] In a possible embodiment, referring to FIG21 , the pixel circuits corresponding to the two first sub-anode portions AD11 in the first anode AD1 are symmetrically distributed, the pixel circuits corresponding to the two first sub-anode portions AD22 in the second anode AD2 are symmetrically distributed, and the pixel circuits corresponding to the two third sub-anode portions AD33 in the third anode AD3 are symmetrically distributed, which can make the separation angles complementary, thereby reducing color separation and crosstalk.

[0326] In a possible embodiment, referring to FIG21 , the first anode AD1, the second anode AD2, and the third anode AD3 are staggered; optionally, the first anode AD1 and the second anode AD2 are arranged along the second direction Y; the first anode AD1 and the third anode AD3 are arranged along the first direction X; the second anode AD2 and the third anode AD3 are arranged along the first direction X; the third sub-anode portion AD3 has two outer edges w extending along the first direction X, wherein the extension line of one outer edge w has an overlapping area with the orthographic projection of the first sub-anode portion AD11 on the substrate, and the other outer edge w has an overlapping area with the orthographic projection of the second sub-anode portion AD22 on the substrate.

[0327] In a possible embodiment, referring to FIG21 , the orthographic projection of the first sub-anode portion AD11 on the substrate has an overlapping area with the first storage capacitor C1 and the second storage capacitor C2 in the sub-pixel; the orthographic projection of the second sub-anode portion AD22 on the substrate has an overlapping area with the first storage capacitor C1 and the second storage capacitor C2 in the sub-pixel; the orthographic projection of the third sub-anode portion AD33 on the substrate has an overlapping area with the first storage capacitor C1 in the sub-pixel, and also has an overlapping area with the second storage capacitor C2 in the sub-pixel in the next unit row.

[0328] In one possible implementation, the shape of the plates in the first storage capacitor C1 and / or the second storage capacitor C2 can be modified to provide symmetry, thereby improving the flatness of the anodes disposed in the corresponding regions and thereby improving the color separation problem. For example, as shown in FIG19 , the second plate 72 in the second storage capacitor C2 is currently not symmetrical. This can be adjusted to a symmetrical pattern that is parallel to the second direction Y and symmetrical about the first direction X. This can improve the flatness of the anodes disposed in the corresponding regions and thereby improve the color separation problem.

[0329] In one possible embodiment, as shown in conjunction with Figures 13, 14, and 22, the display substrate further includes: a first power line 51 extending along the second direction Y; the orthographic projection of the first power line 51 on the substrate overlaps with the orthographic projection of the first anode portion ADA on the substrate. In the disclosed embodiment, since the first power line 51 is relatively wide in the first direction X and is located closer to the anode than the storage capacitor, the overlap between the first anode portion ADA and the first power line 51 can improve the flatness of the first anode portion ADA, thereby improving the color separation problem.

[0330] In one possible implementation, the orthographic projection of the first power line 51 on the substrate overlaps the orthographic projection of the first anode portion ADA on the substrate. In the disclosed embodiment, the orthographic projection of the first power line 51 on the substrate overlaps the orthographic projection of the first anode portion ADA on the substrate, thereby substantially flattening the area where the first anode portion ADA is located. This ensures that the area closer to the first anode portion ADA becomes increasingly flat, maximizing the flatness of the first anode portion ADA and improving color separation issues.

[0331] In one possible embodiment, the orthographic projection of the first power line 51 on the substrate may cover the orthographic projection of the first electrode plate 71 and / or the third electrode plate 73 in the first storage capacitor C1 on the substrate, and / or cover the orthographic projection of the second electrode plate 72 and / or the fourth electrode plate 74 in the second storage capacitor C2 on the substrate.

[0332] In one possible implementation, as shown in FIG22 , in the region where the first anode portion ADA is located, a width d1 of the first power line 51 in the first direction X is greater than a width d2 of the storage capacitor (the first storage capacitor C1 and / or the second storage capacitor C2) in the first direction X. For example, if d1 is greater than d2, the orthographic projection of the second electrode plate 72 and / or the fourth electrode plate 74 of the second storage capacitor C2 on the substrate may also be an axisymmetric shape, such as a square or a rectangle.

[0333] It should be noted that Figure 22 clearly illustrates the first power line 51 and compares it with the width of the storage capacitor (the first storage capacitor C1 and / or the second storage capacitor C2), while omitting the illustration of other film layers. In specific implementation, the display substrate of the embodiment of the present disclosure may also include other film layers, but the embodiment of the present disclosure is not limited to this.

[0334] In one possible embodiment, as shown in conjunction with Figures 13, 14, and 22, the orthographic projection of the first anode portion ADA on the substrate may overlap with the orthographic projection of the power shielding block 51-1 on the substrate. Because the orthographic projection of the power shielding block 51-1 on the substrate is relatively large, positioning the first anode portion ADA in the area where the power shielding block 51-1 is located can improve the flatness of the first anode portion ADA, thereby improving color separation.

[0335] In a possible embodiment, in combination with Figures 13, 14 and 22, the orthographic projection of the first anode portion ADA on the substrate can have an overlapping area with the orthographic projection of the first power line 51 on the substrate, which can cover the first transistor, the second transistor, and the third transistor.

[0336] In one possible embodiment, as shown in FIG. 23A , the display substrate further includes: a plurality of metal pattern blocks PEB, wherein the orthographic projections of the metal pattern blocks PEB on the substrate overlap the orthographic projections of the first anode portion ADA on the substrate. In the disclosed embodiment, the display substrate further includes a plurality of metal pattern blocks PEB, wherein the orthographic projections of the metal pattern blocks PEB on the substrate overlap the orthographic projections of the first anode portion ADA on the substrate. This can further improve the flatness of the first anode portion ADA, thereby improving color separation issues.

[0337] In one possible embodiment, referring to Figures 24A, 24B, and 24C, Figure 24A is a schematic top view of another display substrate provided in an embodiment of the present disclosure, Figure 24B is a schematic diagram of a single film layer of the layer where the anode in Figure 24A resides, and Figure 24C is a schematic diagram of a single film layer of the layer where the metal pattern block PEB in Figure 24A resides. The display substrate further includes: a plurality of metal pattern blocks PEB, wherein the orthographic projections of the metal pattern blocks PEB on the substrate overlap the orthographic projections of the first anode portion ADA on the substrate. In this embodiment of the present disclosure, the display substrate further includes a plurality of metal pattern blocks PEB, wherein the orthographic projections of the metal pattern blocks PEB on the substrate overlap the orthographic projections of the first anode portion ADA on the substrate. This can further improve the flatness of the first anode portion ADA, thereby improving color separation issues.

[0338] It should be noted that, in FIG24A , except for the anode layer and the layer where the metal pattern block PEB is located, the film layers can be conventional technologies or the film layer structures in any embodiment of the present disclosure, and the embodiments of the present disclosure will not be described in detail here.

[0339] In one possible embodiment, as shown in Figures 24A, 24B, and 24C, the display substrate further includes: a plurality of connecting portions PEC; different metal pattern blocks PEB are connected by the connecting portions PEC, thereby forming a mesh structure of the metal pattern blocks PEB and the connecting portions PEC. Optionally, the connecting portions PEC and the metal pattern blocks PEB can be located on the same layer.

[0340] In some possible implementations, as shown in FIG. 24C , at least a portion of the metal pattern block PEB has a recessed portion PED. Combined with FIG. 24A , the orthographic projection of the recessed portion PED on the substrate overlaps the orthographic projection of the first anode portion ADA on the substrate. For example, the recessed portion PED can expose the fifth and sixth transistors.

[0341] In some possible implementations, as shown in FIG. 23A , different metal pattern blocks PEB may not be connected to each other and may be multiple independent blocks separated from each other.

[0342] In some possible embodiments, for example, as shown in conjunction with Figures 23A and 23B, on a plane perpendicular to the display substrate, as shown in conjunction with Figure 23B (for example, along the Y-axis direction of Figure 23A), the driving circuit layer 102 may include the following layers arranged in sequence on the substrate 101: a light shielding layer LS, which is located on the substrate 101; a buffer layer BUF, which is located on a side of the light shielding layer LS away from the substrate 101; a first semiconductor material layer SML1, which is located on a side of the buffer layer BUF away from the substrate 101; a gate insulating layer GI, which is located on a side of the first semiconductor material layer SML1 away from the substrate 101; and a first gate metal layer Gate1. (which can be used as a first conductive layer), which is located on the side of the gate insulating layer GI away from the first semiconductor material layer SML1; the insulating layer IN, which is located on the side of the first gate metal layer Gate1 away from the gate insulating layer GI; the second gate metal layer Gate2 (which can be used as a second conductive layer), which is located on the side of the insulating layer IN away from the first gate metal layer Gate1; the first interlayer dielectric layer ILD1, which is located on the side of the second gate metal layer Gate2 away from the insulating layer IN; the second semiconductor material layer SML2, which is located on the side of the first interlayer dielectric layer ILD1 away from the second gate metal layer Gate2; the second interlayer dielectric layer I LD2, which is located on the side of the second semiconductor material layer SML2 away from the first interlayer dielectric layer ILD1; the third gate metal layer Gate3, which is located on the side of the second interlayer dielectric layer ILD2 away from the second semiconductor material layer SML2; the passivation layer PVX, which is located on the side of the third gate metal layer Gate3 away from the second interlayer dielectric layer ILD2; the first signal line layer SD1 (which can be used as a third conductive layer), which is located on the side of the passivation layer PVX away from the third gate metal layer Gate3; the first planarization layer PLN1, which is located on the side of the first signal line layer SD1 away from the passivation layer PVX; the second signal line layer SD 2 (which can serve as the fourth conductive layer), which is located on the side of the first planarization layer PLN1 away from the first signal line layer SD1; the second planarization layer PLN2, which is located on the side of the second signal line layer SD2 away from the first planarization layer PLN1; the third signal line layer SD3 (for example: equivalent to the PEB layer in Figure 23A), which is located on the side of the second planarization layer PLN2 away from the second signal line layer SD2; the third planarization layer PLN3, which is located on the side of the third signal line layer SD3 away from the second planarization layer PLN2; and the anode layer AD, which is located on the side of the third planarization layer PLN3 away from the third signal line layer SD3. Among them, the first storage capacitor C1 includes a first electrode plate 71 and a third electrode plate 73 arranged opposite to each other, and the second storage capacitor C2 includes a second electrode plate 72 and a fourth electrode plate 74 arranged opposite to each other; the second electrode plate 72 of the second storage capacitor C2 is connected to the third electrode plate 73 of the first storage capacitor C1 through the first connecting hole v1, the second connecting hole v2, and the connecting line Cinl (that is, the second storage capacitor C2 and the first storage capacitor C1 form a series structure).

[0343] In one possible implementation, the multiple metal pattern blocks PEB may be located on the same layer. Alternatively, the multiple metal pattern blocks PEB may be located between the fourth conductive layer and the anode layer. Alternatively, the multiple metal pattern blocks PEB may be located on the layer where the third signal line layer SD3 is located.

[0344] In some possible embodiments, as shown in Figure 3, the display substrate further includes: a color filter layer CF located on the side of the light-emitting structure layer away from the driving circuit layer; the color filter layer includes a plurality of color resist portions CF0; the orthographic projection of the color resist portion CF0 on the substrate 101 has an overlapping area with the orthographic projection of the first anode portion ADA on the substrate 101.

[0345] In some possible embodiments, the shape and area of ​​the orthographic projection of the color resist portion CF0 on the substrate may be substantially the same as the shape and area of ​​the orthographic projection of the corresponding first anode portion ADA on the substrate; for example, referring to FIG. 20-FIG 22, FIG. 23A-FIG 23B, FIG. 24A-FIG 24C, and FIG. 25, the color resist portion CF0 The shape and area of ​​the orthographic projection on the substrate are approximately the same as the shape and area of ​​the corresponding first anode portion ADA's orthographic projection on the substrate; or, the shape and area of ​​the orthographic projection of the color resist portion CF0 on the substrate substrate may be approximately the same as the shape and area of ​​the corresponding sub-pixel opening's orthographic projection on the substrate, for example: the first overlapping region of some possible embodiments of the present disclosure may also be the orthographic projection of the sub-pixel opening corresponding to the color resist portion CF0 on the substrate, and the overlapping region of the orthographic projection of at least one of the plates of the corresponding at least one storage capacitor on the substrate; for example: referring to Figures 20-22, 23A-23B, 24A-24C, and 25, the shape and area of ​​the orthographic projection of the color resist portion CF0 on the substrate are approximately the same as the shape and area of ​​the corresponding sub-pixel opening (that is, the orthographic projection of ADA on the substrate in Figures 20-22, 23A-23B, 24A-24C, and 25 can be represented as the corresponding sub-pixel opening); or, the area of ​​the orthographic projection of the color resist portion CF0 on the substrate may be smaller than the area of ​​the orthographic projection of the corresponding first anode portion ADA on the substrate. For example, as shown in FIG19 , the shape and area of ​​the color resist portion CF0 projected on the substrate may be the same as the shape and area of ​​the corresponding overlapping region C10 , and may be smaller than the area of ​​the corresponding first anode portion ADA projected on the substrate.

[0346] In some possible embodiments, as shown in Figure 25, the display substrate further includes: a first black matrix layer BM1 located on the side of the color filter layer toward the light-emitting structure layer, and a second black matrix layer BM2 located on the side of the color filter layer CF away from the light-emitting structure layer 103; the orthographic projection of the second black matrix layer BM2 on the substrate 101 covers at least part of the boundary of the color resist portion CF0.

[0347] In the embodiment of the present disclosure, although the anode is made as flat as possible on the backplane, it may be difficult to avoid complete flatness. By making the display substrate also include a second black matrix layer BM2, and making the second black matrix layer BM2 cover at least a portion of the boundary of the color resist portion CF0, the light reflected by the mirror is prevented from entering other color sub-pixels, thereby preventing color separation and cross-color problems.

[0348] Full Display Camera (FDC) technology embeds the camera within the display area. To achieve high transmittance in the under-screen camera area and thus enable the camera function, the metal surface area is typically minimized. However, this reduction in metal surface area also reduces the luminous area of ​​the under-screen camera area, resulting in a difference in luminous area between the under-screen camera area and the normal display area (where the camera is not embedded). This leads to a difference in color mixing at the interface between the under-screen camera area and the normal display area.

[0349] In some possible embodiments, as shown in FIG26 , the display substrate includes: a first display area AA1, a second display area AA2, and a third display area AA3; wherein, the first display area AA1 may be a normal display area, the second display area AA2 may be provided with a fingerprint recognition device (i.e., a sensor area), and the third display area AA3 may be provided with a camera component (i.e., an FDC area); the area of ​​the first overlapping region of the first display area AA1 is greater than the area of ​​the first overlapping region of the third display area AA3; the area of ​​the first overlapping region of the second display area AA2 is greater than the area of ​​the first overlapping region of the third display area AA3. Optionally, the orthographic projection area of ​​the first anode portion of the first display area AA1 on the substrate is larger than the orthographic projection area of ​​the first anode portion of the third display area AA3 on the substrate, and the orthographic projection area of ​​the first anode portion of the second display area AA2 on the substrate is larger than the orthographic projection area of ​​the first anode portion of the third display area AA3 on the substrate. In the embodiment of the present disclosure, by making the area of ​​the first overlapping region of the first display area AA1 larger than the area of ​​the first overlapping region of the third display area AA3, and the area of ​​the first overlapping region of the second display area AA2 larger than the area of ​​the first overlapping region of the third display area AA3, the sizes of the first anode portions of different areas can be adapted.

[0350] In some possible embodiments, the orthographic projection area of ​​the first anode portion of the first display area on the substrate may be larger than the orthographic projection area of ​​the first anode portion of the second display area on the substrate; in another possible embodiment, the orthographic projection area of ​​the first anode portion of the first display area on the substrate may be approximately equal to the orthographic projection area of ​​the first anode portion of the second display area on the substrate.

[0351] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes the display substrate provided by the embodiment of the present disclosure.

[0352] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel provided by the embodiment of the present disclosure.

[0353] Based on the same inventive concept, the present disclosure also provides a method for manufacturing a display substrate as provided in the present disclosure, as shown in FIG27 , comprising:

[0354] Step S100: forming a driving circuit layer on one side of the substrate, wherein the driving circuit layer includes at least one storage capacitor; the storage capacitor includes two plates arranged opposite to each other;

[0355] Step S200: forming a light-emitting structure layer on a side of the driving circuit layer facing away from the substrate, the light-emitting structure layer comprising: a plurality of first anode portions; wherein the orthographic projection of at least one plate of at least one storage capacitor on the substrate has a first overlapping region with the orthographic projection of at least one first anode portion on the substrate, and the first overlapping region is an axisymmetric pattern.

[0356] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0357] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A display substrate, wherein, include: substrate; A driving circuit layer, located on one side of the substrate, includes: a plurality of pixel driving circuits; at least one pixel driving circuit among the plurality of pixel driving circuits includes: at least one storage capacitor; the storage capacitor includes two plates arranged opposite to each other; The light emitting structure layer is located on a side of the driving circuit layer facing away from the substrate, and includes an anode layer and a pixel definition layer; wherein the anode layer includes a plurality of anodes; the pixel definition layer includes a plurality of sub-pixel openings; at least one of the plurality of anodes includes a first anode portion located in at least one of the plurality of sub-pixel openings; The orthographic projection of at least one electrode plate in at least one storage capacitor on the substrate has a first overlapping region with the orthographic projection of at least one first anode portion on the substrate, and the first overlapping region is an axisymmetric pattern.

2. The display substrate according to claim 1, wherein, The orthographic projection of the plate close to the anode in the storage capacitor on the substrate and the orthographic projection of the first anode portion on the substrate have the first overlapping region, and the first overlapping region is an axisymmetric pattern.

3. The display substrate according to claim 1 or 2, wherein, The orthographic projection of the electrode plate on the substrate is an axisymmetric pattern, the orthographic projection of the first anode portion on the substrate is an axisymmetric pattern, and the symmetry axis of the electrode plate coincides with the symmetry axis of the first anode portion.

4. The display substrate according to any one of claims 1 to 3, wherein, An orthographic projection of at least one of the first anode portions on the substrate has the first overlapping region with the plate of at least one of the storage capacitors in the same pixel driving circuit.

5. The display substrate according to claim 4, wherein, The pixel driving circuit includes: a first storage capacitor and a second storage capacitor; the orthographic projection area of the first storage capacitor on the substrate is larger than the orthographic projection area of the second storage capacitor on the substrate; The orthographic projection of the first anode portion on the substrate is only in contact with the first storage capacitor and the first One of the two storage capacitors has the first overlapping region on an orthographic projection of the substrate.

6. The display substrate according to claim 5, wherein, The plurality of anodes include: a first anode, a second anode, and a third anode; the wavelength range of the outgoing light in the region where the first anode is located is greater than the wavelength range of the outgoing light in the region where the second anode is located; the wavelength range of the outgoing light in the region where the second anode is located is greater than the wavelength range of the outgoing light in the region where the third anode is located; The orthographic projection of the first anode portion of the second anode on the substrate has an overlapping area only with the orthographic projection of the second storage capacitor on the substrate; the orthographic projection of the first anode portion of the first anode on the substrate has an overlapping area only with the orthographic projection of the first storage capacitor on the substrate; the orthographic projection of the first anode portion of the third anode on the substrate has an overlapping area only with the orthographic projection of the first storage capacitor on the substrate.

7. The display substrate according to claim 4, wherein, The pixel driving circuit includes: a first storage capacitor and a second storage capacitor; the orthographic projection area of the first storage capacitor on the substrate is larger than the orthographic projection area of the second storage capacitor on the substrate; The orthographic projection of the first anode portion on the substrate has an overlapping area with the orthographic projections of the first storage capacitor and the second storage capacitor on the substrate.

8. The display substrate according to claim 7, wherein, The positive projection of the first anode portion on the substrate has a first capacitance overlapping region with the positive projection of the plate of the first storage capacitor on the substrate; The positive projection of the first anode portion on the substrate has a second capacitance overlapping region with the positive projection of the plate of the second storage capacitor on the substrate; the first overlapping region includes the first capacitance overlapping region and the second capacitance overlapping region; The area of the first capacitance overlapping region is larger than the area of the second capacitance overlapping region.

9. The display substrate according to claim 8, wherein, The area of the first capacitance overlapping region is 1.1 to 2.5 times the area of the second capacitance overlapping region.

10. The display substrate according to any one of claims 1-3, wherein, The positive projection of at least one of the first anode portions on the substrate has the first overlapping region with the plates of at least two of the storage capacitors in two adjacent pixel driving circuits.

11. The display substrate according to claim 1 or 2, wherein The plurality of anodes include: a first anode, a second anode, and a third anode; the range of the emission light band of the region where the first anode is located is larger than the range of the emission light band of the region where the second anode is located; the range of the emission light band of the region where the second anode is located is larger than the range of the emission light band of the region where the third anode is located; The first anode portion of the first anode includes: two first sub-anode portions arranged adjacent to each other along a first direction, and the two first sub-anode portions are symmetrically distributed; the first anode portion of the second anode includes: two second sub-anode portions arranged adjacent to each other along the first direction, and the two second sub-anode portions are symmetrically distributed; the first anode portion of the third anode includes: two third sub-anode portions arranged adjacent to each other along the first direction, and the two third sub-anode portions are symmetrically distributed.

12. The display substrate according to claim 11, wherein, The first anode and the second anode are arranged along a second direction; the first anode and the third anode are arranged along the first direction; The third sub-anode portion has two outer edges extending along the first direction, and the extension line of one of the outer edges has an overlapping region with the positive projection of the first sub-anode portion on the substrate, and the other outer edge has an overlapping region with the positive projection of the second sub-anode portion on the substrate.

13. The display substrate according to any one of claims 1 to 12, wherein, The display substrate further includes: a first power line whose main body extends along the second direction; the positive projection of the first power line on the substrate covers the positive projection of the first anode portion on the substrate.

14. The display substrate according to claim 13, wherein, The display substrate further includes: a plurality of metal pattern blocks; the positive projection of the metal pattern blocks on the substrate covers the positive projection of the first anode portion on the substrate.

15. The display substrate according to claim 14, wherein, The display substrate further includes: a plurality of connection portions; different metal pattern blocks are connected through the connection portions.

16. The display substrate according to any one of claims 1-15, wherein, The display substrate further includes: a color filter layer located on the side of the light-emitting structure layer away from the driving circuit layer; the color filter layer includes a plurality of color resist portions; the positive projection of the color resist portion on the substrate has an overlapping region with the positive projection of the first anode portion on the substrate.

17. The display substrate according to claim 16, wherein, The display substrate further includes: a first black matrix layer located on the side of the color filter layer facing the light-emitting structure layer, and a second black matrix layer located on the side of the color filter layer away from the light-emitting structure layer; The positive projection of the second black matrix layer on the substrate covers at least a part of the boundary of the color resist portion.

18. The display substrate according to any one of claims 1-17, wherein, The display substrate includes: a first display area, a second display area, and a third display area; a fingerprint recognition device is provided in the second display area, and a camera component is provided in the third display area; The area of the first overlapping region in the first display area is larger than the area of the first overlapping region in the third display area; the area of the first overlapping region in the second display area is larger than the area of the first overlapping region in the third display area.

19. A display device, wherein, It includes the display substrate according to any one of claims 1-18.

20. A method for manufacturing a display substrate, wherein, It includes: A driving circuit layer is formed on one side of the substrate, wherein the driving circuit layer includes at least one storage capacitor; the storage capacitor includes two oppositely arranged electrode plates; A light-emitting structure layer is formed on the side of the driving circuit layer away from the substrate, and the light-emitting structure layer includes: a plurality of first anode portions; wherein, the positive projection of at least one electrode plate of at least one of the storage capacitors on the substrate and the positive projection of at least one of the first anode portions on the substrate have a first overlapping region, and the first overlapping region is an axisymmetric pattern.

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