Dimming device and display device

Abstract

The invention provides a dimming device and a display device, which can perform dimming in halftone and can improve dimming performance. A dimming device includes: a dimming panel including a plurality of row electrodes extending in a first direction, a plurality of column electrodes extending in a second direction intersecting the first direction, and a dimming layer having a plurality of dimming regions divided into a matrix by the plurality of row electrodes and the plurality of column electrodes; and a dimming control device that performs control in which one of a plurality of mode voltages having a predetermined voltage waveform is applied to each of the plurality of row electrodes and the plurality of column electrodes in accordance with the color gradation of each of the plurality of dimming regions, and in each of a plurality of frame periods that constitute the repetition period and have different periods, the dimming region is configured to perform dimming on the plurality of row electrodes and the plurality of column electrodes in accordance with the color gradation of each of the plurality of dimming regions. The dimming control device selects a mode voltage to be applied to each of the plurality of row electrodes and the plurality of column electrodes in accordance with the color gradation of each of the plurality of dimming regions, the repetition period being a unit period for controlling the repetition of dimming.

Description

Technical Field

[0001] The present disclosure relates to a dimming device and a display device. Background Art

[0002] Conventionally, there is known a dimming device that can transmit or attenuate external light from the rear surface.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2021-26222

[0006] Patent Document 2: Japanese Patent Application Laid-Open No. 2021-184062 Summary of the Invention

[0007] Problems to be solved by the invention

[0008] Regarding such a dimming device, many proposals have been made for dimming using a halftone method using a frame rate control (FRC) method in a passive matrix.

[0009] However, there is no proposal for dimming in halftone using a driving method that can reduce the driving voltage to zero and having a matrix-shaped dimming area.

[0010] Therefore, the present disclosure provides a dimming device and a display device capable of performing dimming in halftones and improving dimming performance.

[0011] Solutions for solving problems

[0012] The dimming device involved in the present disclosure comprises: a dimming panel, which includes: a plurality of row electrodes, wherein the plurality of row electrodes extend along a first direction; a plurality of column electrodes, wherein the plurality of column electrodes extend along a second direction intersecting the first direction; and a dimming layer, which has a plurality of dimming areas divided into a matrix shape by a plurality of row electrodes and a plurality of column electrodes; and a dimming control device, which performs the following control: according to the color levels of the respective plurality of dimming areas, one of a plurality of pattern voltages of predetermined voltage waveforms is applied to the plurality of row electrodes and the plurality of column electrodes, respectively, wherein, during each frame period of a plurality of frame periods different from each other that constitute a repetition period, the dimming control device selects the pattern voltage applied to the plurality of row electrodes and the plurality of column electrodes according to the color levels of the respective plurality of dimming areas, wherein the repetition period represents a period as a repeated unit for controlling dimming.

[0013] Effects of the Invention

[0014] According to the dimming device and the display device according to the present disclosure, dimming can be performed in halftone and the dimming performance can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a block diagram schematically illustrating the configuration of a dimming system including the dimming device according to the first embodiment.

[0016] Figure 2 It is a perspective view showing a part of the structure of the dimming panel.

[0017] Figure 3 It is a top view of the column electrodes and row electrodes.

[0018] Figure 4 3 is a plan view showing a plurality of dimming areas divided by the dimming panel.

[0019] Figure 5 This is a diagram illustrating the correspondence between color gradation levels and relative on-periods.

[0020] Figure 6 This is a diagram explaining the relationship between the dimming mode and the on / off state of the dimming area in each frame.

[0021] Figure 7 This is a diagram explaining the mode voltage.

[0022] Figure 8 This is a timing chart (part 1) corresponding to an operation example of the first embodiment.

[0023] Figure 9 This is a timing chart (part 2) corresponding to the operation example of the first embodiment.

[0024] Figure 10 This is a timing chart corresponding to the operation example of the second row, second column to fourth column of the first embodiment.

[0025] Figure 11 This is an operation sequence diagram (Part 1) of the second embodiment.

[0026] Figure 12 This is an operation sequence diagram of the second embodiment (Part 2).

[0027] Figure 13 This is a block diagram schematically illustrating the configuration of a dimming system including a dimming device according to a third embodiment.

[0028] Figure 14 It is an operation explanation diagram of the third embodiment.

[0029] Figure 15 This is a schematic block diagram of the configuration of a display device to which the dimming device according to the first to third embodiments is applied. DETAILED DESCRIPTION

[0030] Hereinafter, a dimming device according to an embodiment will be described with reference to the drawings.

[0031] [1] First embodiment

[0032] Figure 1 This is a block diagram schematically illustrating the configuration of a dimming system including the dimming device according to the first embodiment.

[0033] The light control system 1 includes an analysis device 10 and a light control device 20 .

[0034] The analysis device 10 receives a dimming-related request command CMD from a host controller such as a personal computer. The request command CMD may be, for example, instruction data for the gradation distribution of external light in the dimming panel or image data corresponding to an image to be displayed when the dimming panel is used as a display device.

[0035] The analyzing device 10 analyzes the received request command CMD, generates a dimming signal SDM based on the analysis result, and supplies the dimming signal SDM to the dimming device 20 .

[0036] like Figure 1 As shown, the dimming device 20 includes a dimming panel 21 , a row electrode driving circuit 22 , a column electrode driving circuit 23 , a calculation circuit 24 , a reference voltage generating circuit 25 , and a timing generating circuit 26 .

[0037] Figure 2 It is a perspective view showing a part of the structure of the dimming panel.

[0038] like Figure 2 As shown, the dimming panel 21 includes a dimming layer 31 , a plurality of column electrodes EY1 - EY5 , and a plurality of row electrodes EX1 - EX3 .

[0039] The light-adjusting layer 31 extends in a substantially plate-like shape in the X and Y directions. The light-adjusting layer 31 includes, for example, a plate-like member 31 a in which light-adjusting liquid crystal 31 b is sealed.

[0040] exist Figure 2 In the example of , the +Z side of the light-adjusting layer 31 is the front surface, and the -Z side is the back surface. The +Z side surface of the box-shaped member 31a constitutes the front surface of the light-adjusting layer 31, and the -Z side surface of the member 31a constitutes the back surface of the light-adjusting layer 31.

[0041] The plurality of column electrodes EY1 to EY5 are arranged on the front surface side (+Z side) of the light-adjusting layer 31 .

[0042] The plurality of column electrodes EY1 to EY5 are provided on, for example, a substrate 32 disposed on the front surface of the light-adjusting layer 31. The substrate 32 may be bonded to the front surface of the light-adjusting layer 31 with an adhesive or the like. The substrate 32 is formed in a plate shape extending in the XY directions.

[0043] Each of the column electrodes EY1 to EY5 is formed of a transparent conductive material such as ITO, etc. The substrate 32 is formed of a transparent insulating resin, etc., for example.

[0044] Figure 3 It is a top view of the column electrodes and row electrodes.

[0045] like Figure 3 As shown in (a), on substrate 32, multiple column electrodes EY1-EY5 are insulated from each other by insulating portions 32a and 32b, and are arranged along the X direction. Thus, the column electrodes EY1-EY5 are arranged along the X direction along the front surface of the dimming layer 31. On substrate 32, each column electrode EY1-EY5 extends along the Y direction. The insulating portion 32a extends along the Y direction between the column electrodes EY1-EY5. The insulating portion 32b extends along the X direction and connects the +Y-side ends of the multiple insulating portions 32a.

[0046] Figure 2 The multiple row electrodes EX1 to EX3 shown are arranged on the -Z side of the dimming layer 31. The multiple row electrodes EX1 to EX3 can also be arranged on a substrate 33, which is arranged on the back side of the dimming layer 31. The multiple row electrodes EX1 to EX3 face the multiple column electrodes EY1 to EY5 so that the dimming layer 31 is located in between. The substrate 33 can also be bonded to the back side of the dimming layer 31 using an adhesive or the like. The substrate 33 extends in a plate-like shape in the XY directions. Each row electrode EX can be formed of a transparent conductive material such as ITO. The substrate 33 is formed, for example, from a transparent insulating resin.

[0047] like Figure 3 As shown in (b), on the substrate 33, multiple row electrodes EX1-EX3 are insulated from each other by insulating portions 33a and 33b, and are arranged along the Y direction. Consequently, the row electrodes EX1-EX3 are arranged along the Y direction along the back surface of the dimming layer 31. On the substrate 33, each row electrode EX1-EX3 extends along the X direction. The insulating portion 33a extends along the X direction between the row electrodes EX1-EX3. The insulating portion 33b extends along the Y direction and connects the +X-side ends of the multiple insulating portions 33a.

[0048] Figure 4 1 is a plan view showing a plurality of dimming areas divided by the dimming panel 2 .

[0049] exist Figure 2In the dimming layer 31 shown, the plurality of column electrodes EY1 to EY5 and the plurality of row electrodes EX1 to EX3 are divided into Figure 4 There are multiple dimming areas R(1,1) to R(3,5) as shown.

[0050] Hereinafter, an example is given to illustrate the correspondence between the column electrodes EY1 to EY5 and the row electrodes EX1 to EX3 and the dimming regions R( 1 , 1 ) to R( 3 , 5 ).

[0051] The dimming area R(1,1) is formed in the dimming layer 31 at the intersection of the row electrode EX1 and the column electrode EY1 when viewed from the Z direction. To the dimming area R(1,1), a pattern voltage VX1, one of a plurality of pattern voltages with predetermined voltage waveforms, is applied from the row electrode EX1 on the -Z side, and a pattern voltage VY1, one of a plurality of pattern voltages with predetermined voltage waveforms, is applied from the column electrode EY1 on the +Z side.

[0052] The dimming region R(1,2) is formed in the dimming layer 31 at the intersection of the row electrode EX1 and the column electrode EY2 when viewed from the Z direction. To the dimming region R(1,2), a pattern voltage VX1, one of a plurality of pattern voltages with predetermined voltage waveforms, is applied from the row electrode EX1 on the -Z side, and a pattern voltage VY2, one of a plurality of pattern voltages with predetermined voltage waveforms, is applied from the column electrode EY2 on the +Z side.

[0053] The dimming area R(1,3) is formed in the dimming layer 31 at the intersection of the row electrode EX1 and the column electrode EY3 when viewed from the Z direction. To the dimming area R(1,3), one of a plurality of pattern voltages with predetermined voltage waveforms, VX1, is applied from the row electrode EX1 on the -Z side, and one of a plurality of pattern voltages with predetermined voltage waveforms, VY3, is applied from the column electrode EY3 on the +Z side.

[0054] The dimming area R(1,4) is formed in the dimming layer 31 at the intersection of the row electrode EX1 and the column electrode EY4 when viewed from the Z direction. To the dimming area R(1,4), a pattern voltage VX1, one of a plurality of pattern voltages with predetermined voltage waveforms, is applied from the row electrode EX1 on the -Z side, and a pattern voltage VY4, one of a plurality of pattern voltages with predetermined voltage waveforms, is applied from the column electrode EY4 on the +Z side.

[0055] The dimming region R(1,5) is formed in the dimming layer 31 at the intersection of the row electrode EX1 and the column electrode EY5 when viewed from the Z direction. To the dimming region R(1,5), a pattern voltage VX1, one of a plurality of pattern voltages with predetermined voltage waveforms, is applied from the row electrode EX1 on the -Z side, and a pattern voltage VY5, one of a plurality of pattern voltages with predetermined voltage waveforms, is applied from the column electrode EY5 on the +Z side.

[0056] The dimming region R(2,1) is formed in the dimming layer 31 at the intersection of the row electrode EX2 and the column electrode EY1 when viewed from the Z direction. To the dimming region R(2,1), a pattern voltage VX2, one of a plurality of pattern voltages with predetermined voltage waveforms, is applied from the row electrode EX2 on the -Z side, and a pattern voltage VY1, one of a plurality of pattern voltages with predetermined voltage waveforms, is applied from the column electrode EY1 on the +Z side.

[0057] The dimming region R(3,1) is formed in the dimming layer 31 at the intersection of the row electrode EX3 and the column electrode EY1 when viewed from the Z direction. A pattern voltage VX3, one of a plurality of pattern voltages with predetermined voltage waveforms, is applied to the dimming region R(3,1) from the row electrode EX3 on the -Z side, and a pattern voltage VY1, one of a plurality of pattern voltages with predetermined voltage waveforms, is applied to the dimming region R(3,1) from the column electrode EY1 on the +Z side.

[0058] The dimming region R(3,5) is formed in the dimming layer 31 at the intersection of the row electrode EX3 and the column electrode EY5 when viewed from the Z direction. To the dimming region R(3,5), a pattern voltage VX3, one of a plurality of pattern voltages having a predetermined voltage waveform, is applied from the row electrode EX3 on the -Z side, and a pattern voltage VY5, one of a plurality of pattern voltages having a predetermined voltage waveform, is applied from the column electrode EY5 on the +Z side.

[0059] The same applies to the other dimming areas R(2,2) to R(2,5) and the dimming areas R(3,2) to R(3,4).

[0060] The row electrode driver circuit 22 is electrically connected to the plurality of row electrodes EX1-EX3. The row electrode driver circuit 22 drives each of the plurality of row electrodes EX1-EX3 using a reference voltage with a voltage waveform corresponding to a row control signal in synchronization with a clock signal. The row electrode driver circuit 22 can independently drive the plurality of row electrodes EX1-EX3. The row electrode driver circuit 22 selects one of a plurality (three in this embodiment) of pattern voltages (pattern voltages Va, Vb, and Vc in this embodiment) based on the row control signal.

[0061] Then, the row electrode driving circuit 22 supplies the selected pattern voltage to the row electrodes EX1 to EX3 in synchronization with the clock signal.

[0062] Similar to the row electrode driver circuit 22, the column electrode driver circuit 23 is electrically connected to the plurality of column electrodes EY1 to EY5. The column electrode driver circuit 23 drives each of the plurality of column electrodes EY1 to EY5 using a reference voltage with a voltage waveform corresponding to a column control signal in synchronization with a clock signal. The column electrode driver circuit 23 can independently drive the plurality of column electrodes EY1 to EY5. The column electrode driver circuit 23 selects one of a first reference voltage and a second reference voltage based on the column control signal. The column electrode driver circuit 23 can supply the selected reference voltage to the column electrodes EY1 to EY5 in synchronization with the clock signal.

[0063] The calculation circuit 24 is electrically connected between the analysis device 10 and the row electrode driver circuit 22 and the column electrode driver circuit 23. The calculation circuit 24 receives a dimming signal SDM from the analysis device 10. Multiple pattern voltages are preset in the dimming device 20. Alternatively, multiple pattern voltages may be preset in the calculation circuit 24, the row electrode driver circuit 22, and the column electrode driver circuit 23. The dimming signal SDM includes an instruction for specifying which of the multiple pattern voltages should be supplied to the multiple column electrodes EY1 to EY5, and an instruction for specifying which of the multiple pattern voltages should be supplied to the multiple row electrodes EX1 to EX3.

[0064] The arithmetic circuit 24 generates a column control signal corresponding to the dimming signal SDM in synchronization with the clock signal and supplies the column control signal to the column electrode driver circuit 23. Furthermore, the arithmetic circuit 24 generates a row control signal corresponding to the dimming signal SDM in synchronization with the clock signal and supplies the row control signal to the row electrode driver circuit 22. The column control signal includes an instruction for the pattern voltage to be supplied to each column electrode EY. The row control signal includes an instruction for the pattern voltage to be supplied to each row electrode EX.

[0065] The reference voltage generating circuit 25 is electrically connected to each of the row electrode driving circuit 22 and the column electrode driving circuit 23. The reference voltage generating circuit 25 generates a reference voltage and supplies the reference voltage to each of the row electrode driving circuit 22 and the column electrode driving circuit 23.

[0066] The reference voltage generation circuit 25 may generate a first reference voltage (= "H" level) and a second reference voltage (= "L" level). The reference voltage generation circuit 25 may generate the reference voltage using a bandgap voltage corresponding to the bandgap energy of a semiconductor (e.g., the forward voltage of a diode). The reference voltage generation circuit 25 may supply the first reference voltage and the second reference voltage to the row electrode driver circuit 22 and the column electrode driver circuit 23, respectively.

[0067] The timing generation circuit 26 is electrically connected to the row electrode driver circuit 22, the column electrode driver circuit 23, and the calculation circuit 24. The timing generation circuit 26 generates a clock signal and supplies the clock signal to each of the row electrode driver circuit 22, the column electrode driver circuit 23, and the calculation circuit 24.

[0068] Furthermore, the timing generation circuit 26 can also be configured to generate a clock signal using a reference clock signal from an oscillator.

[0069] In the following description, it is assumed that the dimming device 20 can display 5 color levels, and the state in which the external light is most transmitted in a dimming area is set to color level = 1, and the state in which the external light is most attenuated (or blocked) in a dimming area is set to color level = 0.

[0070] Furthermore, the dimming device 20 sets the state in which approximately 75% of the external light is transmitted relative to the amount of transmitted light at the color level = 1 to the color level = 3 / 4, sets the state in which approximately 50% of the external light is transmitted relative to the amount of transmitted light at the color level = 1 to the color level = 2 / 4, and sets the state in which approximately 25% of the external light is transmitted relative to the amount of transmitted light at the color level = 1 to the color level = 1 / 4.

[0071] Then, the dimming device 20 determines which of the gradation level = 0 to the gradation level = 1 to apply to each dimming area based on the dimming signal, and performs control.

[0072] Next, the operating principle of the embodiment will be described.

[0073] In the embodiment, frame rate control (FRC) is adopted. In order to express the color level of the intermediate color level in each dimming area, multiple frames with different periods are used to constitute a repetition period (in this embodiment, four frames of frame 0 to frame 3). The repetition period represents the period as a repeated unit for controlling the dimming.

[0074] Figure 5 This is a diagram illustrating the correspondence between color gradation levels and relative on-periods.

[0075] Here, the relative on period refers to the proportion of the period during which each dimming area is in the on state in a repeated period, when the on state represents the transmittance state of external light in each dimming area (equivalent to the color scale level = 1) and the off state represents the blocking state of external light (equivalent to the color scale level = 0).

[0076] More specifically, if Figure 5 As shown, when the length of one repetition period is 1, in the dimming area of ​​gradation level = 0, the length of the period in the on state is 0. That is, it means that there is no time in the on state in one repetition period.

[0077] Furthermore, when the gradation level is 1 / 4, the length of the period in the on state is 0.1, which means that the proportion of the on state in one repetition period is 10% (=0.1 / 1×100).

[0078] Furthermore, when the gradation level is 2 / 4, the length of the period in the on state is 0.2, which means that the proportion of the on state in one repetition period is 20% (=0.2 / 1×100).

[0079] Furthermore, when the gradation level is 3 / 4, the length of the period in the on state is 0.4, which means that the proportion of the on state in one repetition period is 40% (=0.4 / 1×100).

[0080] Furthermore, when the gradation level is 1, the length of the period in the on state is 1. That is, the on state is always maintained during one repetition period, and the ratio thereof is 100% (=1 / 1×100).

[0081] In other words, by changing the length of the dimming area in the on state in one repetition period, it is possible to express a gradation.

[0082] Figure 6 This diagram explains the relationship between the dimming mode and the on / off state of the dimming area in a frame.

[0083] Set to dimming mode PTN Figure 4 As shown, it is configured to correspond to 3×5 dimming zones.

[0084] Specifically, if Figure 6 As shown in (a), in the dimming mode PTN, Figure 4 The areas corresponding to the dimming regions R(1,1) to R(1,5), R(2,5), and R(3,5) are set to gradation level=1.

[0085] In addition, in the dimming mode PTN, Figure 4 The areas corresponding to the dimming regions R(2, 4) and R(3, 4) are set to a gradation level of 3 / 4.

[0086] In addition, in the dimming mode PTN, Figure 4 The areas corresponding to the dimming areas R(2, 3) and R(3, 3) are set to a gradation level of 2 / 4.

[0087] In addition, in the dimming mode PTN, Figure 4 The areas corresponding to the dimming areas R(2, 2) and R(3, 2) are set to gradation level = 1 / 4.

[0088] In addition, in the dimming mode PTN, Figure 4 The areas corresponding to the dimming regions R(2, 1) and R(3, 1) are set to gradation level = 0.

[0089] exist Figure 6 In the case of the dimming pattern PTN shown in (a), during the frame period of frame FM0, the dimming area with a gradation level of 1 is set to the on state, and the dimming area with a gradation level less than 1 is set to the off state.

[0090] In more detail, Figure 6 As shown in (b), Figure 4 The areas corresponding to the dimming areas R(1,1) to R(1,5), R(2,5) and R(3,5) shown are set to the on state, and the areas corresponding to the dimming areas R(2,1) to R(2,4) and R(3,1) to R(3,4) are set to the off state.

[0091] In addition, the period ratio of the frame period of the frame FM0 is set to 0.6.

[0092] exist Figure 6 In the dimming pattern PTN shown in (a), during the frame period of frame FM1, the dimming area with a gradation level of 3 / 4 or more is turned on, and the area with a gradation level of less than 3 / 4 is turned off.

[0093] In more detail, Figure 6 As shown in (c), Figure 4 The areas corresponding to the dimming areas R(1,1) to R(1,5), dimming areas R(2,4) to R(2,5), and dimming areas R(3,4) to R(3,5) are set to the on state, and the areas corresponding to the dimming areas R(2,1) to R(2,3) and dimming areas R(3,1) to R(3,3) are set to the off state.

[0094] In addition, the period ratio of the frame period of the frame FM1 is set to 0.2.

[0095] exist Figure 6 In the case of the dimming pattern PTN shown in (a), during the frame period of frame FM2, the dimming area with a gradation level of 2 / 4 or more is set to the on state, and the dimming area with a gradation level of less than 2 / 4 is set to the off state.

[0096] In more detail, Figure 6 As shown in (d), Figure 4 The areas corresponding to the dimming areas R(1,1) to R(1,5), dimming areas R(2,3) to R(2,5), and dimming areas R(3,3) to R(3,5) are set to the on state, and the areas corresponding to the dimming areas R(2,1) to R(2,2) and dimming areas R(3,1) to R(3,2) are set to the off state.

[0097] In addition, the period ratio of the frame period of the frame FM2 is set to 0.1.

[0098] exist Figure 6 In the case of the dimming mode PTN shown in (a), during the frame period of frame FM3, the dimming area with a color level of 1 / 4 or above is set to the on state, and the dimming area with a color level less than 1 / 4, that is, in this embodiment, the color level = 0 is set to the off state.

[0099] In more detail, Figure 6 As shown in (e), Figure 4 The areas corresponding to the dimming areas R(1,1) to R(1,5), dimming areas R(2,2) to R(2,5), and dimming areas R(3,2) to R(3,5) shown are set to the on state, and the areas corresponding to the dimming areas R(2,1) and R(3,1) are set to the off state.

[0100] In addition, the period ratio of the frame period of the frame FM3 is set to 0.1.

[0101] These results are, with Figure 4 The relative on-periods in the areas corresponding to the dimming areas R(1,1) to R(1,5), R(2,5) and R(3,5) shown are 1 in total, corresponding to the color gradation level=1.

[0102] In addition, in the dimming mode PTN, Figure 4The relative on-periods in the areas corresponding to the dimming areas R(2, 4) and the dimming areas R(3, 4) shown are 0.4 in total, corresponding to the tone level = 3 / 4.

[0103] In addition, in the dimming mode PTN, Figure 4 The relative on-periods in the areas corresponding to the dimming areas R(2, 3) and R(3, 3) shown are 0.2 in total, corresponding to the gradation level = 2 / 4.

[0104] In addition, in the dimming mode PTN, Figure 4 The relative on-periods in the regions corresponding to the dimming region R(2,2) and the dimming region R(3,2) shown are 0.1 in total, corresponding to the gradation level = 1 / 4.

[0105] In addition, in the dimming mode PTN, Figure 4 The relative on-periods in the regions corresponding to the dimming region R(2, 1) and the dimming region R(3, 1) are 0 in total, corresponding to the tone level=0.

[0106] As described above, in each dimming area, within a certain repetitive period (= a period equivalent to consecutive frames FM0 to FM3), the on state (transmitting state) and off state (shading state) in frames FM0 to FM3 are controlled in such a way that the relative on period becomes a relative on period equivalent to the color level corresponding to the dimming mode PTN, thereby performing halftone display.

[0107] Next, selection and application of a pattern voltage for realizing the dimming mode PTN will be described.

[0108] First, the mode voltage according to the embodiment will be described.

[0109] Figure 7 This is a diagram explaining the mode voltage.

[0110] In this embodiment, there are three types of mode voltages: mode voltage Va, mode voltage Vb, and mode voltage Vc.

[0111] Each of the pattern voltages Va to Vc has a divided period obtained by equally dividing each frame period of the frames FM0 to FM3 into three, and maintains a signal level (“H” level or “L” level) at least in each divided period.

[0112] In this case, the lengths of the respective frame periods of frames FM0 to FM3 are different. In the present embodiment, the ratio of the frame periods is as follows.

[0113] FM0: FM1: FM2: FM3=0.6:0.2:0.1:0.1

[0114] Here, each of the pattern voltages Va to Vc is a binary level signal, and is a combination of any values ​​of a high level “1” and a low level “0”.

[0115] exist Figure 7 In the case of the example, with respect to the mode voltage Va, in the first frame period PFM1, the signal levels from the front period side among the three periods (= the three sub-frame periods of the frame period PFM1. The same applies hereinafter) obtained by dividing the first frame period PFM1 into three equal parts are "1", "1", and the signal levels from the front period side among the three periods (= the three sub-frame periods of the frame period PFM2. The same applies hereinafter) obtained by dividing the second frame period PFM2 following the first frame period PFM1 into three equal parts are "0", "0", and "0".

[0116] In addition, regarding the mode voltage Vb, the signal levels from the front period side of the three periods obtained by dividing the first frame period PFM1 into three equal parts are "0", "0", and "1", and the signal levels from the front period side of the three periods obtained by dividing the second frame period PFM2 following the first frame period PFM1 into three equal parts are "1", "1", and "0".

[0117] In addition, regarding the mode voltage Vc, the signal level from the side of the first period among the three periods obtained by dividing the first frame period into three equal parts is "1", "0", "0", and the signal level from the side of the first period among the three periods obtained by dividing the second frame period following the first frame period into three equal parts is "0", "1", "1".

[0118] Furthermore, the effective values ​​of the pattern voltages Va to Vc are equal within a predetermined period (= two frame periods). That is, in this embodiment, the pattern voltages Va to Vc each have a signal level of "1" for one frame period and a signal level of "0" for one frame period during two frame periods.

[0119] Next, the operation of the embodiment will be described in detail.

[0120] In the following instructions, the Figure 6 The dimming mode PTN shown in (a) is Figure 6 (b)~ Figure 6 The operation of the states of frames FM0 to FM3 shown in (e) is shown.

[0121] Figure 8 This is a timing chart (part 1) corresponding to an operation example of the first embodiment.

[0122] (Period corresponding to frame FM0)

[0123] First, during a period corresponding to frame FM0 , the calculation circuit 24 applies the pattern voltage Vc to the row electrode EX1 , and applies the pattern voltage Vb to each of the row electrode EX2 and the row electrode EX3 .

[0124] Furthermore, the calculation circuit 24 applies the pattern voltage Vb to the column electrodes EY1 to EY4 and applies the pattern voltage Va to the column electrode EY5 .

[0125] As a result, the dimming regions R(1,1) to R(1,4) receive pattern voltages Vc from their corresponding row electrodes, and pattern voltages Vb from their corresponding column electrodes. Consequently, the dimming regions R(1,1) to R(1,4) are turned on for two-thirds of the frame period of frame FM0, and turned off for one-third of the frame period of frame FM0. Consequently, during the period corresponding to frame FM0, the dimming regions R(1,1) to R(1,4) are effectively turned on (transmitting light).

[0126] Furthermore, the dimming region R(1,5) receives a pattern voltage Vc from the corresponding row electrode and a pattern voltage Va from the corresponding column electrode. Therefore, the dimming region R(1,5) is turned on for two-thirds of the frame period of frame FM0 and turned off for one-third of the frame period of frame FM0. Consequently, during the period corresponding to frame FM0, the dimming region R(1,5) is effectively turned on (transmitting light).

[0127] Furthermore, the dimming regions R(2,5) and R(3,5) are applied with the pattern voltage Vb from the corresponding row electrodes and with the pattern voltage Va from the corresponding column electrodes. Therefore, the dimming regions R(2,5) and R(3,5) are turned on for two-thirds of the frame period of frame FM0 and turned off for one-third of the frame period of frame FM0, effectively turning on (transmitting light) the dimming regions R(2,5) and R(3,5).

[0128] Furthermore, the dimming regions R(2,5) and R(3,5) receive pattern voltages Vb from their corresponding row electrodes and Va from their corresponding column electrodes. Consequently, the dimming regions R(2,5) and R(3,5) are turned on for two-thirds of the frame period of frame FM0 and turned off for one-third of the frame period of frame FM0. Consequently, during the period corresponding to frame FM0, the dimming regions R(2,5) and R(3,5) are effectively turned on (transmitting light).

[0129] Furthermore, the dimming regions R(2,1) to R(2,4) and R(3,1) to R(3,4) have pattern voltages Vb applied to them from their corresponding row electrodes, and pattern voltages Vb applied to them from their corresponding column electrodes. Therefore, the dimming regions R(2,1) to R(2,4) and R(3,1) to R(3,4) are set to an OFF state throughout the entire frame period of frame FM0. Consequently, during the period corresponding to frame FM0, the dimming regions R(2,1) to R(2,4) and R(3,1) to R(3,4) are effectively in an OFF state (light-shielded state).

[0130] First, for easy understanding, the operation of the dimming area R( 1 , 1 ) to the dimming area R( 1 , 5 ) corresponding to the row electrode EX1 and the column electrodes EY1 to EY5 will be described.

[0131] (Period corresponding to frame FM1)

[0132] Next, during a period corresponding to the frame FM1, the calculation circuit 24 applies the pattern voltage Vc to the row electrode EX1, and applies the pattern voltage Vb to each of the row electrode EX2 and the row electrode EX3.

[0133] Furthermore, the calculation circuit 24 applies the pattern voltage Vb to the column electrodes EY1 to EY3 , and applies the pattern voltage Va to the column electrodes EY4 and EY5 .

[0134] As a result, the dimming regions R(1,1) to R(1,3) receive pattern voltages Vc from their corresponding row electrodes, and pattern voltages Vb from their corresponding column electrodes. Consequently, the dimming regions R(1,1) to R(1,3) are turned on for two-thirds of the frame period of frame FM1 and turned off for one-third of the frame period of frame FM1. Consequently, during the period corresponding to frame FM1, the dimming regions R(1,1) to R(1,3) are effectively turned on (transmitting light).

[0135] Furthermore, the dimming regions R(1,4) and R(1,5) receive pattern voltages Vc from their corresponding row electrodes and Va from their corresponding column electrodes. Consequently, the dimming regions R(1,4) and R(1,5) are turned on for two-thirds of the frame period of frame FM1 and turned off for one-third of the frame period of frame FM1. Consequently, during the period corresponding to frame FM1, the dimming regions R(1,4) and R(1,5) are effectively turned on (transmitting light).

[0136] Furthermore, the dimming regions R(2,4), R(2,5), R(3,4), and R(3,5) are applied with pattern voltage Vb from the corresponding row electrodes, and with pattern voltage Va from the corresponding column electrodes. Consequently, the dimming regions R(2,4), R(2,5), R(3,4), and R(3,5) are turned on for two-thirds of the frame period of frame FM1, and turned off for one-third of the frame period of frame FM1. Consequently, during the period corresponding to frame FM1, the dimming regions R(2,4), R(2,5), R(3,4), and R(3,5) are effectively turned on (transmitting light).

[0137] Furthermore, the dimming regions R(2,1) to R(2,3) and R(3,1) to R(3,3) have pattern voltages Vb applied to them from their corresponding row electrodes, and pattern voltages Vb applied to them from their corresponding column electrodes. Therefore, the dimming regions R(2,1) to R(2,3) and R(3,1) to R(3,3) are set to an OFF state throughout the entire frame period of frame FM1. Consequently, during the period corresponding to frame FM1, the dimming regions R(2,1) to R(2,3) and R(3,1) to R(3,3) are effectively in an OFF state (light-shielded state).

[0138] (Period corresponding to frame FM2)

[0139] Next, during a period corresponding to the frame FM2, the calculation circuit 24 applies the pattern voltage Vc to the row electrode EX1, and applies the pattern voltage Vb to each of the row electrode EX2 and the row electrode EX3.

[0140] Furthermore, the calculation circuit 24 applies the pattern voltage Vb to each of the column electrodes EY1 and EY2 , and applies the pattern voltage Va to each of the column electrodes EY3 to EY5 .

[0141] As a result, the dimming regions R(1,1) and R(1,2) receive pattern voltages Vc from their corresponding row electrodes, and pattern voltages Vb from their corresponding column electrodes. Consequently, the dimming regions R(1,1) and R(1,2) are turned on for two-thirds of the frame period of frame FM2, and turned off for one-third of the frame period of frame FM2. Consequently, during the period corresponding to frame FM2, the dimming regions R(1,1) and R(1,2) are effectively turned on (transmitting light).

[0142] Furthermore, dimming regions R(1,3) through R(1,5) receive pattern voltages Vc from their corresponding row electrodes, and pattern voltages Va from their corresponding column electrodes. Consequently, dimming regions R(1,3) through R(1,5) are turned on for two-thirds of the frame period of frame FM2 and turned off for one-third of the frame period of frame FM2. Consequently, during the period corresponding to frame FM2, dimming regions R(1,3) through R(1,5) are effectively turned on (transmitting light).

[0143] Furthermore, the dimming regions R(2,3) to R(2,5) and R(3,3) to R(3,5) receive pattern voltages Vb from their corresponding row electrodes, and pattern voltages Va from their corresponding column electrodes. Consequently, the dimming regions R(2,3) to R(2,5) and R(3,3) to R(3,5) are turned on for two-thirds of the frame period of frame FM2 and turned off for one-third of the frame period of frame FM2. Consequently, during the period corresponding to frame FM2, the dimming regions R(2,3) to R(2,5) and R(3,3) to R(3,5) are effectively turned on (transmitting light).

[0144] Furthermore, the dimming regions R(2,1), R(2,2), and R(3,1), R(3,2) are applied with pattern voltages Vb from their corresponding row electrodes, and with pattern voltages Vb from their corresponding column electrodes. Therefore, the dimming regions R(2,1), R(2,2), and R(3,1), R(3,2) are set to an OFF state throughout the entire frame period of frame FM2. Consequently, during the period corresponding to frame FM2, the dimming regions R(2,1), R(2,2), and R(3,1), R(3,2) are effectively in an OFF state (light-shielded state).

[0145] (Period corresponding to frame FM3)

[0146] Next, during a period corresponding to the frame FM3, the calculation circuit 24 applies the pattern voltage Vc to the row electrode EX1, and applies the pattern voltage Vb to each of the row electrode EX2 and the row electrode EX3.

[0147] Furthermore, the calculation circuit 24 applies the pattern voltage Vb to the column electrode EY1 and applies the pattern voltage Va to the column electrodes EY2 to EY5 .

[0148] As a result, the dimming region R(1,1) receives the pattern voltage Vc from the corresponding row electrode and the pattern voltage Vb from the corresponding column electrode. Consequently, the dimming region R(1,1) is turned on for two-thirds of the frame period of frame FM3 and turned off for one-third of the frame period of frame FM3. Consequently, during the period corresponding to frame FM3, the dimming region R(1,1) is effectively turned on (transmitting light).

[0149] Furthermore, dimming regions R(1,2) through R(1,5) receive pattern voltages Vc from their corresponding row electrodes, and pattern voltages Va from their corresponding column electrodes. Consequently, dimming regions R(1,2) through R(1,5) are turned on for two-thirds of the frame period of frame FM3 and turned off for one-third of the frame period of frame FM3. Consequently, during the period corresponding to frame FM3, dimming regions R(1,2) through R(1,5) are effectively turned on (transmitting light).

[0150] Furthermore, the dimming regions R(2,2) to R(2,5) and R(3,2) to R(3,5) receive pattern voltages Vb from their corresponding row electrodes, and pattern voltages Va from their corresponding column electrodes. Consequently, the dimming regions R(2,2) to R(2,5) and R(3,2) to R(3,5) are turned on for two-thirds of the frame period of frame FM3 and turned off for one-third of the frame period of frame FM3. Consequently, during the period corresponding to frame FM3, the dimming regions R(2,2) to R(2,5) and R(3,2) to R(3,5) are effectively turned on (transmitting light).

[0151] Furthermore, the dimming regions R(2,1) and R(3,1) receive pattern voltages Vb from their corresponding row electrodes and pattern voltages Vb from their corresponding column electrodes. Therefore, the dimming regions R(2,1) and R(3,1) are in an OFF state throughout the entire frame period of frame FM3. Consequently, during the period corresponding to frame FM3, the dimming regions R(2,1) and R(3,1) are effectively in an OFF state (light-shielded state).

[0152] Then, if the period during which dimming regions R(1,1) to R(1,5), R(2,5), and R(3,5) are in the on state (transmitting state) at the time when the processing of the above-mentioned consecutive frames FM0 to FM3 is completed, that is, the relative on period of dimming regions R(1,1) to R(1,5), R(2,5), and R(3,5) is set to "1" and the relative on period is calculated for each dimming region, the relative on period of dimming regions R(2,1) and R(3,1) is "0". In other words, dimming regions R(2,1) and R(3,1) are areas with a gradation level of 0.

[0153] Similarly, the relative on-periods of the dimming area R(2,2) and the dimming area R(3,2) are “0.1.” That is, the dimming area R(2,2) and the dimming area R(3,2) are areas with a gradation level of 1 / 4.

[0154] Furthermore, the relative on-periods of the dimming area R(2,3) and the dimming area R(3,3) are “0.2.” That is, the dimming area R(2,3) and the dimming area R(3,3) are areas with a gradation level of 2 / 4.

[0155] Furthermore, the relative on-periods of the dimming area R(2,4) and the dimming area R(3,4) are “0.4.” That is, the dimming area R(2,4) and the dimming area R(3,4) are areas with a gradation level of 3 / 4.

[0156] As described above, according to this embodiment, by controlling the length of the relative on period during the repetition period, half-tone display can be performed.

[0157] Figure 9 This is a timing chart (part 2) corresponding to the operation example of the first embodiment.

[0158] exist Figure 9 In the embodiment, the polarity inversion signal POL whose signal level is inverted every frame as shown in the graph (a) is input from the calculation circuit 24 to the row electrode driving circuit 22 and the column electrode driving circuit 23.

[0159] The polarity inversion signal POL is used to invert the polarity of the mode voltages Va, Vb, and Vc. When a DC component is applied to the dimming device, the contrast between the on state (light-transmitting state) and the off state (light-blocking state) in each dimming range may decrease. By inverting the polarity of the mode voltages Va, Vb, and Vc, the DC component can be eliminated.

[0160] exist Figure 9 In the figure, (b) to (d) are Figure 7The mode voltages Va, Vb, and Vc are shown.

[0161] First, the operation of the dimming device 20 during the frame period corresponding to the frame FM0 will be described.

[0162] As shown at time t1 , when the polarity inversion signal POL is at the “H” level, the frame period corresponding to the frame FM0 starts, and the mode voltages Va, Vb, and Vc are in a non-inverted state.

[0163] Regarding the pattern voltage of the first row applied to the row electrode EX1 during the frame period corresponding to the frame FM0 (=the period from time t1 to time t4), as shown in FIG. Figure 9 The mode voltage Vc is selected as shown in the graph (e) of FIG.

[0164] Similarly, the pattern voltage applied to the column electrode EY1 corresponding to the first column during the frame period (=the period from time t1 to time t4) corresponding to the frame FM0 is as follows: Figure 9 The mode voltage Vb is selected as shown in the graph (f) of FIG.

[0165] In addition, regarding the pattern voltage applied to the column electrode EY2 corresponding to the second column during the frame period corresponding to the frame FM0, as shown in FIG. Figure 9 The mode voltage Vb is selected as shown in the graph (g) of FIG.

[0166] In addition, regarding the pattern voltage applied to the column electrode EY3 corresponding to the third column during the frame period corresponding to the frame FM0, as shown in FIG. Figure 9 The mode voltage Vb is selected as shown in the graph (h) of FIG.

[0167] In addition, regarding the pattern voltage applied to the column electrode EY4 corresponding to the fourth column during the frame period corresponding to the frame FM0, as shown in FIG. Figure 9 The mode voltage Vb is selected as shown in the graph (i) of FIG.

[0168] In contrast, the pattern voltage of the fifth column applied to the column electrode EY5 corresponding to the fifth column during the frame period corresponding to the frame FM0 is as follows: Figure 9 The mode voltage Va is selected as shown in the graph (j) of FIG.

[0169] In the following description, the mode voltages Va, Vb, and Vc are assumed to have a high potential side voltage of VX (volts: for example, +3 volts) and a low potential side voltage of 0 (volts) in the non-inverted state. Furthermore, the mode voltages Va, Vb, and Vc are assumed to have a high potential side voltage of 0 (volts) and a low potential side voltage of -VX (volts: for example, -3 volts) in the inverted state.

[0170] By applying the above mode voltage, such as Figure 9As shown in graph (k) of FIG, a voltage corresponding to the potential difference between the pattern voltage Vc and the pattern voltage Vb is applied to the dimming area R(1,1) corresponding to the first row and first column via the row electrode EX1 and the column electrode EY1. Specifically, a voltage of -VX (volts) is applied from time t1 to time t2, a voltage of 0 (volts) is applied from time t2 to time t3, and a voltage of +VX (volts) is applied from time t3 to time t4.

[0171] In addition, if Figure 9 As shown in the graph (1) of FIG, a voltage corresponding to the potential difference between the mode voltage Vc and the mode voltage Vb is applied to the dimming area R(1,2) corresponding to the first row and second column via the row electrode EX1 and the column electrode EY2. Specifically, a voltage of -VX (volts) is applied from time t1 to time t2, a voltage of 0 (volts) is applied from time t2 to time t3, and a voltage of +VX (volts) is applied from time t3 to time t4.

[0172] In addition, if Figure 9 As shown in graph (m) of FIG, a voltage corresponding to the potential difference between the mode voltage Vc and the mode voltage Vb is applied to the dimming area R(1,3) corresponding to the first row and third column via the row electrode EX1 and the column electrode EY3. Specifically, a voltage of -VX (volts) is applied from time t1 to time t2, a voltage of 0 (volts) is applied from time t2 to time t3, and a voltage of +VX (volts) is applied from time t3 to time t4.

[0173] In addition, if Figure 9 As shown in the graph (n) of FIG, a voltage corresponding to the potential difference between the pattern voltage Vc and the pattern voltage Vb is applied to the dimming region R(1,4) corresponding to the 1st row and 4th column via the row electrode EX1 and the column electrode EY4. Specifically, a voltage of -VX (volts) is applied between time t1 and time t2, a voltage of 0 (volts) is applied between time t2 and time t3, and a voltage of +VX (volts) is applied between time t3 and time t4.

[0174] In addition, if Figure 9 As shown in the graph (o) of FIG, a voltage corresponding to the potential difference between the mode voltage Vc and the mode voltage Va is applied to the dimming area R(1,5) corresponding to the 1st row and 5th column via the row electrode EX1 and the column electrode EY5. That is, a voltage of 0 (volts) is applied between time t1 and time t2, a voltage of +VX (volts) is applied between time t2 and time t3, and a voltage of +VX (volts) is applied between time t3 and time t4.

[0175] Next, the operation during the frame period corresponding to the frame FM1 will be described.

[0176] When the polarity inversion signal POL is inverted and becomes “L” level at time t4 , the frame period corresponding to the frame FM1 starts, and the mode voltages Va, Vb, and Vc are in an inverted state.

[0177] Regarding the pattern voltage of the first row applied to the row electrode EX1 during the frame period corresponding to the frame FM1 (=the period from time t4 to time t7), as shown in FIG. Figure 9 As shown in the graph (e) of , the mode voltage Vc (inversion mode voltage Vc) is selected.

[0178] Similarly, regarding the pattern voltage applied to the column electrode EY1 corresponding to the first column during the frame period corresponding to the frame FM1, as shown in FIG. Figure 9 As shown in the graph (f) of , the mode voltage Vb (inversion mode voltage Vb) is selected.

[0179] In addition, regarding the pattern voltage applied to the column electrode EY2 corresponding to the second column during the frame period corresponding to the frame FM1, as shown in FIG. Figure 9 As shown in the graph (g) of , the mode voltage Vb (inversion mode voltage Vb) is selected.

[0180] In addition, regarding the pattern voltage applied to the column electrode EY3 corresponding to the third column during the frame period corresponding to the frame FM1, as shown in FIG. Figure 9 As shown in the graph (h) of , the mode voltage Vb (inversion mode voltage Vb) is selected.

[0181] In addition, regarding the pattern voltage applied to the column electrode EY4 corresponding to the fourth column during the frame period corresponding to the frame FM1, as shown in FIG. Figure 9 As shown in the graph (i) of , the mode voltage Va (inversion mode voltage Va) is selected.

[0182] Furthermore, regarding the pattern voltage of the fifth column applied to the column electrode EY5 corresponding to the fifth column during the frame period corresponding to the frame FM1, as shown in FIG. Figure 9 The mode voltage Va is selected as shown in the graph (j) of FIG.

[0183] By applying the above mode voltage, such as Figure 9 As shown in graph (k) of FIG, a voltage corresponding to the potential difference between the pattern voltage Vc and the pattern voltage Vb is applied to the dimming area R(1,1) corresponding to the first row and first column via the row electrode EX1 and the column electrode EY1. Specifically, a voltage of +VX (volts) is applied from time t4 to time t5, a voltage of 0 (volts) is applied from time t5 to time t6, and a voltage of -VX (volts) is applied from time t6 to time t7.

[0184] In addition, if Figure 9As shown in the graph (1) of FIG, a voltage corresponding to the potential difference between the mode voltage Vc and the mode voltage Vb is applied to the dimming area R(1,2) corresponding to the first row and second column via the row electrode EX1 and the column electrode EY2. Specifically, a voltage of +VX (volts) is applied from time t4 to time t5, a voltage of 0 (volts) is applied from time t5 to time t6, and a voltage of -VX (volts) is applied from time t6 to time t7.

[0185] In addition, if Figure 9 As shown in graph (m) of FIG, a voltage corresponding to the potential difference between the mode voltage Vc and the mode voltage Vb is applied to the dimming region R(1,3) corresponding to the first row and third column via the row electrode EX1 and the column electrode EY3. Specifically, a voltage of +VX (volts) is applied from time t4 to time t5, a voltage of 0 (volts) is applied from time t5 to time t6, and a voltage of -VX (volts) is applied from time t6 to time t7.

[0186] In addition, if Figure 9 As shown in the graph (n) of FIG, a voltage corresponding to the potential difference between the pattern voltage Vc and the pattern voltage Va is applied to the dimming region R(1,4) corresponding to the 1st row and 4th column via the row electrode EX1 and the column electrode EY4. Specifically, a voltage of 0 (volts) is applied from time t4 to time t5, a voltage of -VX (volts) is applied from time t5 to time t6, and a voltage of -VX (volts) is applied from time t6 to time t7.

[0187] In addition, if Figure 9 As shown in the graph (o) of FIG, a voltage corresponding to the potential difference between the mode voltage Vc and the mode voltage Va is applied to the dimming area R(1,5) corresponding to the 1st row and 5th column via the row electrode EX1 and the column electrode EY5. That is, a voltage of 0 (volts) is applied from time t4 to time t5, a voltage of -VX (volts) is applied from time t5 to time t6, and a voltage of -VX (volts) is applied from time t6 to time t7.

[0188] Next, the operation during the frame period corresponding to the frame FM2 will be described.

[0189] When the polarity inversion signal POL is inverted and becomes “H” level at time t7 , the frame period corresponding to the frame FM2 starts, and the mode voltages Va, Vb, and Vc are in the non-inverted state again.

[0190] Regarding the pattern voltage of the first row applied to the row electrode EX1 during the frame period corresponding to the frame FM2 (=the period from time t7 to time t10), as shown in FIG. Figure 9 The mode voltage Vc is selected as shown in the graph (e) of FIG.

[0191] Similarly, regarding the pattern voltage applied to the column electrode EY1 corresponding to the first column during the frame period corresponding to the frame FM2, as shown in FIG. Figure 9 The mode voltage Vb is selected as shown in the graph (f) of FIG.

[0192] In addition, regarding the pattern voltage applied to the column electrode EY2 corresponding to the second column during the frame period corresponding to the frame FM2, as shown in FIG. Figure 9 The mode voltage Vb is selected as shown in the graph (g) of FIG.

[0193] In addition, regarding the pattern voltage applied to the column electrode EY3 corresponding to the third column during the frame period corresponding to the frame FM2, as shown in FIG. Figure 9 The mode voltage Va is selected as shown in the graph (h) of FIG.

[0194] In addition, regarding the pattern voltage applied to the column electrode EY4 corresponding to the fourth column during the frame period corresponding to the frame FM2, as shown in FIG. Figure 9 The mode voltage Va is selected as shown in the graph (i) of FIG.

[0195] Furthermore, regarding the pattern voltage of the fifth column applied to the column electrode EY5 corresponding to the fifth column during the frame period corresponding to the frame FM2, as shown in FIG. Figure 9 The mode voltage Va is selected as shown in the graph (j) of FIG.

[0196] By applying the above mode voltage, such as Figure 9 As shown in graph (k) of FIG, a voltage corresponding to the potential difference between the mode voltage Vc and the mode voltage Vb is applied to the dimming area R(1,1) corresponding to the first row and first column via the row electrode EX1 and the column electrode EY1. Specifically, a voltage of -VX (volts) is applied from time t7 to time t8, a voltage of 0 (volts) is applied from time t8 to time t9, and a voltage of +VX (volts) is applied from time t9 to time t10.

[0197] In addition, if Figure 9 As shown in the graph (1) of FIG, a voltage corresponding to the potential difference between the mode voltage Vc and the mode voltage Vb is applied to the dimming area R(1,2) corresponding to the first row and second column via the row electrode EX1 and the column electrode EY2. Specifically, a voltage of -VX (volts) is applied from time t7 to time t8, a voltage of 0 (volts) is applied from time t8 to time t9, and a voltage of +VX (volts) is applied from time t9 to time t10.

[0198] In addition, if Figure 9As shown in graph (m) of FIG, a voltage corresponding to the potential difference between the pattern voltage Vc and the pattern voltage Va is applied to the dimming region R(1,3) corresponding to the first row and third column via the row electrode EX1 and the column electrode EY3. Specifically, a voltage of 0 (V) is applied between time t7 and time t8, and a voltage of +VX (V) is applied between time t8 and time t10.

[0199] In addition, if Figure 9 As shown in the graph (n) of FIG, a voltage corresponding to the potential difference between the pattern voltage Vc and the pattern voltage Va is applied to the dimming region R(1,4) corresponding to the first row and fourth column via the row electrode EX1 and the column electrode EY4. Specifically, a voltage of 0 (V) is applied between time t7 and time t8, and a voltage of +VX (V) is applied between time t8 and time t10.

[0200] In addition, if Figure 9 As shown in the graph (o) of FIG, a voltage corresponding to the potential difference between the pattern voltage Vc and the pattern voltage Va is applied to the dimming region R(1,5) corresponding to the 1st row and 5th column via the row electrode EX1 and the column electrode EY5. Specifically, a voltage of 0 (V) is applied between time t7 and time t8, and a voltage of +VX (V) is applied between time t8 and time t10.

[0201] Next, the operation during the frame period corresponding to the frame FM3 will be described.

[0202] When the polarity inversion signal POL is inverted and becomes “L” level at time t10 , the frame period corresponding to the frame FM3 starts, and the mode voltages Va, Vb, and Vc are inverted again.

[0203] Regarding the pattern voltage of the first row applied to the row electrode EX1 during the frame period corresponding to the frame FM3 (=the period from time t10 to time t13), as shown in FIG. Figure 9 As shown in the graph (e) of , the mode voltage Vc (inversion mode voltage Vc) is selected.

[0204] Similarly, regarding the pattern voltage applied to the column electrode EY1 corresponding to the first column during the frame period corresponding to the frame FM3, as shown in FIG. Figure 9 The mode voltage Vb is selected as shown in the graph (f) of FIG.

[0205] In addition, regarding the pattern voltage applied to the column electrode EY2 corresponding to the second column during the frame period corresponding to the frame FM3, as shown in FIG. Figure 9 The mode voltage Va is selected as shown in the graph (g) of FIG.

[0206] In addition, regarding the pattern voltage applied to the column electrode EY3 corresponding to the third column during the frame period corresponding to the frame FM3, as shown in FIG. Figure 9 The mode voltage Va is selected as shown in the graph (h) of FIG.

[0207] In addition, regarding the pattern voltage applied to the column electrode EY4 corresponding to the fourth column during the frame period corresponding to the frame FM3, as shown in FIG. Figure 9 The mode voltage Va is selected as shown in the graph (i) of FIG.

[0208] Furthermore, regarding the pattern voltage of the fifth column applied to the column electrode EY5 corresponding to the fifth column during the frame period corresponding to the frame FM3, as shown in FIG. Figure 9 The mode voltage Va is selected as shown in the graph (j) of FIG.

[0209] By applying the above mode voltage, such as Figure 9 As shown in graph (k) of FIG, a voltage corresponding to the potential difference between the pattern voltage Vc and the pattern voltage Vb is applied to the dimming region R(1,1) corresponding to the first row and first column via the row electrode EX1 and the column electrode EY1. Specifically, a voltage of +VX (volts) is applied from time t10 to time t11, a voltage of 0 (volts) is applied from time t11 to time t12, and a voltage of -VX (volts) is applied from time t12 to time t13.

[0210] In addition, if Figure 9 As shown in the graph (1) of FIG, a voltage corresponding to the potential difference between the pattern voltage Vc and the pattern voltage Va is applied to the dimming region R(1,2) corresponding to the first row and second column via the row electrode EX1 and the column electrode EY2. Specifically, a voltage of 0 (V) is applied between time t10 and time t11, and a voltage of -VX (V) is applied between time t11 and time t13.

[0211] In addition, if Figure 9 As shown in graph (m) of FIG, a voltage corresponding to the potential difference between the pattern voltage Vc and the pattern voltage Va is applied to the dimming region R(1,3) corresponding to the first row and third column via the row electrode EX1 and the column electrode EY3. Specifically, a voltage of 0 (V) is applied between time t10 and time t11, and a voltage of -VX (V) is applied between time t11 and time t13.

[0212] In addition, if Figure 9 As shown in the graph (n) of FIG, a voltage corresponding to the potential difference between the pattern voltage Vc and the pattern voltage Va is applied to the dimming region R(1,4) corresponding to the first row and fourth column via the row electrode EX1 and the column electrode EY4. Specifically, a voltage of 0 (V) is applied between time t10 and time t11, and a voltage of -VX (V) is applied between time t11 and time t13.

[0213] In addition, if Figure 9 As shown in the graph (o) of FIG, a voltage corresponding to the potential difference between the pattern voltage Vc and the pattern voltage Va is applied to the dimming region R(1,5) corresponding to the 1st row and 5th column via the row electrode EX1 and the column electrode EY5. Specifically, a voltage of 0 (V) is applied between time t10 and time t11, and a voltage of -VX (V) is applied between time t11 and time t13.

[0214] As a result of the above operation, all the dimming areas R(1,1) to R(1,5) have a gradation level of 1.

[0215] Next, the operations of the second and third rows of the first embodiment will be described.

[0216] In this case, Figure 10 This is a timing chart corresponding to the operation example of the second row, second column to fourth column of the first embodiment.

[0217] Here, since the operations of the second and third rows of the first embodiment are the same, only the operations of the second row will be described.

[0218] (Period corresponding to frame FM0)

[0219] First, during a period corresponding to the frame FM0 (time t1 to time t4 ), the calculation circuit 24 applies the pattern voltage Vb to the row electrode EX2 .

[0220] Furthermore, the calculation circuit 24 applies the pattern voltage Vb to the column electrodes EY1 to EY4 .

[0221] As a result, the dimming regions R(2,1) through R(2,4) receive pattern voltage Vb from the corresponding row electrodes EX2, and the pattern voltage Vb from the corresponding column electrodes EY1 through EY4. Consequently, during the entire frame period of frame FM0 (time t1 through time t4), the potential difference between the dimming regions R(2,1) through R(2,4) is 0 volts. Consequently, during the period corresponding to frame FM0, the dimming regions R(2,1) through R(2,4) are effectively in an off state (light-shielded).

[0222] Meanwhile, although not shown, dimming region R(2,5) receives a pattern voltage Vb from the corresponding row electrode EX2 and a pattern voltage Va from the corresponding column electrode EY5. Therefore, dimming region R(2,5) is turned on for two-thirds of the frame period of frame FM0 and turned off for one-third of the frame period of frame FM0. Thus, during the period corresponding to frame FM0, dimming region R(2,5) is effectively turned on (transmitting light).

[0223] (Period corresponding to frame FM1)

[0224] Next, during a period corresponding to the frame FM1 (time t4 to time t7 ), the calculation circuit 24 applies the pattern voltage Vb to the row electrode EX2 .

[0225] Furthermore, the calculation circuit 24 applies the pattern voltage Vb to the column electrodes EY1 to EY3 , and applies the pattern voltage Va to the column electrodes EY4 and EY5 .

[0226] As a result, the dimming regions R(2,1) through R(2,3) receive the pattern voltage Vb from the corresponding row electrodes EX2, and the pattern voltage Vb from the corresponding column electrodes EY1 through EY3. Consequently, the potential difference between the dimming regions R(2,1) through R(2,3) is 0 volts throughout the entire period corresponding to frame FM1 (time t1 through time t4). Consequently, during the period corresponding to frame FM1, the dimming regions R(2,1) through R(2,3) are effectively in an off state (light-shielded state).

[0227] On the other hand, although not shown, dimming regions R(2,4) and R(2,5) receive pattern voltage Vb from the corresponding row electrode EX2, and pattern voltage Va from the corresponding column electrode EY4 and column electrode EY5. Therefore, dimming regions R(2,4) and R(2,5) are turned on for two-thirds of the frame period of frame FM0, and turned off for one-third of the frame period of frame FM0. Consequently, during the period corresponding to frame FM1, dimming regions R(2,4) and R(2,5) are effectively turned on (transmitting light).

[0228] (Period corresponding to frame FM2)

[0229] Next, during a period corresponding to the frame FM2 (time t7 to time t10 ), the calculation circuit 24 applies the pattern voltage Vb to the row electrode EX2 .

[0230] Furthermore, the calculation circuit 24 applies the pattern voltage Vb to the column electrodes EY1 to EY2 and applies the pattern voltage Va to the column electrodes EY3 to EY5 .

[0231] As a result, the dimming regions R(2,1) and R(2,2) receive the pattern voltage Vb from the corresponding row electrodes EX2, and the pattern voltage Vb from the corresponding column electrodes EY1 and EY2. Consequently, the potential difference between the dimming regions R(2,1) and R(2,2) is 0 volts throughout the entire frame period of frame FM2 (time t7 to time t10). Consequently, during the period corresponding to frame FM2, the dimming regions R(1,1) and R(1,2) are effectively in an off state (light-shielded state).

[0232] On the other hand, during the period corresponding to frame FM2, although not shown, dimming areas R(2,3) through R(2,5) receive pattern voltage Vb from the corresponding row electrode EX2, and pattern voltage Va from the corresponding column electrode EY3 through EY5. Therefore, dimming areas R(2,3) through R(2,5) are turned on for two-thirds of the frame period of frame FM2 and turned off for one-third of the frame period of frame FM2. Therefore, during the period corresponding to frame FM2, dimming areas R(2,3) through R(2,5) are effectively turned on (transmitting light).

[0233] (Period corresponding to frame FM3)

[0234] Next, during a period corresponding to the frame FM3 (time t10 to time t13 ), the calculation circuit 24 applies the pattern voltage Vb to the row electrode EX2 .

[0235] Furthermore, the calculation circuit 24 applies the pattern voltage Vb to the column electrode EY1 and applies the pattern voltage Va to the column electrodes EY2 to EY5 .

[0236] As a result, the mode voltage Vb is applied to the dimming area R(2,1) from the corresponding row electrode EX2, and the mode voltage Vb is applied to the dimming area R(2,1) from the corresponding column electrode EY1. Therefore, the potential difference of the dimming area R(2,1) is 0 volts throughout the entire frame period of frame FM3, and the dimming area R(2,1) is effectively in the off state (light-shielded state).

[0237] On the other hand, the dimming areas R(2,2) to R(2,5) have the pattern voltage Vb applied from the corresponding row electrode EX2 and the pattern voltage Va applied from the corresponding column electrode EY2 to EY5.

[0238] Therefore, dimming areas R(2,2) to R(2,5) are turned on for two-thirds of the frame period of frame FM3 and turned off for one-third of the frame period of frame FM3. Therefore, during the period corresponding to frame FM3, dimming areas R(2,2) to R(2,5) are effectively turned on (transmitting light).

[0239] As a result of the above operation, the relative on-periods of the dimming area R(2, 1) and the dimming area R(3, 1) are 0, and the gradation level=0.

[0240] In addition, the relative on-period between the dimming area R(2, 2) and the dimming area R(3, 2) is 0.1, and the gradation level is 1 / 4.

[0241] In addition, the relative on-period between the dimming area R(2, 3) and the dimming area R(3, 3) is 0.2, and the gradation level is 2 / 4.

[0242] In addition, the relative on-period between the dimming area R(2, 4) and the dimming area R(3, 4) is 0.4, and the gradation level is 3 / 4.

[0243] In addition, the relative on-period of the dimming area R(2, 5) and the dimming area R(3, 5) is 1, and the gradation level=1.

[0244] As described above, according to the first embodiment, halftone display can be achieved without complicating control, and power consumption can be suppressed despite active matrix control, thereby improving dimming performance.

[0245] [2] Second embodiment

[0246] In the above-mentioned first embodiment, the dimming device performs dimming processing on frames FM0 to FM3 in units of frames, but the second embodiment is an embodiment in which dimming processing is performed on each of the multiple (3 in this second embodiment) subframes SF0 to SF2 that constitute each frame FM0 to FM3.

[0247] That is, in the second embodiment, the dimming device performs the dimming process on the four sub-frames SF0 included in the frames FM0 to FM3, and then performs the dimming process on the four sub-frames SF1 included in the frames FM0 to FM3.

[0248] Next, the dimming device performs a dimming process on the four subframes SF2 included in the frames FM0 to FM3 , and then performs a dimming process on the four subframes SF3 included in the frames FM0 to FM3 .

[0249] After the dimming process for the subframe SF3 is completed, the dimming device repeats the dimming process again starting from the subframe SF0.

[0250] Figure 11 This is an operation sequence diagram (Part 1) of the second embodiment.

[0251] First, regarding the operation of the second embodiment, the operation of the first column corresponding to the column electrode EY1 will be described.

[0252] (Period corresponding to subframe SF0)

[0253] During the period corresponding to the subframe SF0 (time t1 to time t5 ), the calculation circuit 24 applies the pattern voltage Vc to the row electrode EX1 .

[0254] Furthermore, the calculation circuit 24 applies the pattern voltage Vb to the column electrode EY1 during the period corresponding to the subframe SF0 .

[0255] As a result, the dimming region R(1,1) receives a pattern voltage Vc from the corresponding row electrode EX1 and a pattern voltage Vb from the corresponding column electrode EY1. Consequently, the potential difference of the dimming region R(1,1) is -VX volts throughout the entire duration of subframe SF0. ​​Consequently, during the duration corresponding to subframe SF0, the dimming region R(1,1) is effectively in the on state (light-transmitting state).

[0256] Furthermore, the calculation circuit 24 applies the pattern voltage Vb to the column electrode EY2 during the period from time t1 to time t4 in the period corresponding to the subframe SF0 , and applies the pattern voltage Va during the period from time t4 to time t5 .

[0257] As a result, the dimming region R(1,2) receives a pattern voltage Vc from the corresponding row electrode EX1 during the period corresponding to subframe SF0, a pattern voltage Vb from the corresponding column electrode EY2 during the period from time t1 to time t4, and a pattern voltage Va from the corresponding column electrode EY2 during the period from time t4 to time t5. Therefore, the potential difference during the period from time t1 to time t4 within subframe SF0 is -VX volts, and the potential difference during the period from time t4 to time t5 is 0 volts. Therefore, during the period corresponding to subframe SF0, the dimming region R(1,2) effectively remains in a state with a relative on-period of 0.9.

[0258] Furthermore, the calculation circuit 24 applies the pattern voltage Vb to the column electrode EY3 during the period from time t1 to time t3 in the period corresponding to the subframe SF0 , and applies the pattern voltage Va during the period from time t3 to time t5 .

[0259] As a result, the dimming region R(1,3) receives a pattern voltage Vc from the corresponding row electrode EX1 during the period corresponding to subframe SF0, a pattern voltage Vb from the corresponding column electrode EY3 during the period from time t1 to time t3, and a pattern voltage Va from the corresponding column electrode EY3 during the period from time t3 to time t5. Therefore, the potential difference during the period from time t1 to time t3 within subframe SF0 is -VX volts, and the potential difference during the period from time t3 to time t5 is 0 volts. Therefore, during the period corresponding to subframe SF0, the dimming region R(1,3) effectively remains in a state with a relative on-period of 0.8.

[0260] Furthermore, the calculation circuit 24 applies the pattern voltage Vb to the column electrode EY4 during the period from time t1 to time t2 in the period corresponding to the subframe SF0 , and applies the pattern voltage Va during the period from time t2 to time t5 .

[0261] As a result, during the period corresponding to subframe SF0 (time t1 to time t5), pattern voltage Vc is applied to dimming region R(1,4) from the corresponding row electrode EX1. During the period from time t1 to time t2, pattern voltage Vb is applied to the corresponding column electrode EY4. During the period from time t2 to time t5, pattern voltage Va is applied to the corresponding column electrode EY4. Therefore, during the period of subframe SF0 (time t1 to time t5), the potential difference between time t1 and time t2 is -VX volts, and the potential difference between time t2 and time t5 is 0 volts. Consequently, during the period corresponding to subframe SF0, dimming region R(1,4) effectively remains in a state with a relative on-period of 0.6.

[0262] Furthermore, the calculation circuit 24 applies the pattern voltage Va to the column electrode EY5 during the period corresponding to the sub-frame SF0 .

[0263] As a result, the dimming region R(1,5) receives the pattern voltage Vc from the corresponding row electrode EX1 and the pattern voltage Va from the corresponding column electrode EY5. Consequently, the potential difference remains at 0 volts throughout the entire duration of subframe SF0. ​​Consequently, during the duration of subframe SF0, the dimming region R(1,5) is effectively in an off state (light-shielded state).

[0264] (Period corresponding to subframe SF1)

[0265] During the period corresponding to the subframe SF1 (time t5 to time t9 ), the calculation circuit 24 also applies the pattern voltage Vc to the row electrode EX1 .

[0266] Furthermore, the calculation circuit 24 applies the pattern voltage Vb to the column electrode EY1 during the period corresponding to the subframe SF1 .

[0267] As a result, the dimming region R(1,1) receives a pattern voltage Vc from the corresponding row electrode EX1 and a pattern voltage Vb from the corresponding column electrode EY1. Consequently, the potential difference remains at 0 volts throughout subframe SF1. Consequently, during the period corresponding to subframe SF1, the dimming region R(1,1) is effectively in an off state (light-shielded state).

[0268] Furthermore, the calculation circuit 24 applies the pattern voltage Vb to the column electrode EY2 during the period from time t5 to time t8 in the period corresponding to the subframe SF1 , and applies the pattern voltage Va during the period from time t8 to time t9 .

[0269] As a result, the dimming region R(1,2) receives a pattern voltage Vc from the corresponding row electrode EX1 during the period corresponding to subframe SF1, a pattern voltage Vb from the corresponding column electrode EY2 during the period from time t5 to time t8, and a pattern voltage Va from the corresponding column electrode EY2 during the period from time t8 to time t9. Therefore, the potential difference between time t5 and time t8 in subframe SF1 is 0 volts, and the potential difference between time t8 and time t9 is +VX volts. Therefore, during the period corresponding to subframe SF1, the dimming region R(1,2) effectively remains in a state of 0.1 relative to the on-period.

[0270] Furthermore, the calculation circuit 24 applies the pattern voltage Vb to the column electrode EY3 during the period from time t5 to time t7 in the period corresponding to the subframe SF1 , and applies the pattern voltage Va during the period from time t7 to time t9 .

[0271] As a result, the dimming region R(1,3) receives pattern voltage Vc from the corresponding row electrode EX1 during the period corresponding to subframe SF1, pattern voltage Vb from the corresponding column electrode EY3 during the period from time t5 to time t7, and pattern voltage Va from the corresponding column electrode EY3 during the period from time t7 to time t9. Therefore, the potential difference between time t5 and time t7 within subframe SF1 is 0 volts, and the potential difference between time t7 and time t9 is +VX volts. Therefore, during the period corresponding to subframe SF1, the dimming region R(1,3) effectively remains in a state with a relative on-period of 0.2.

[0272] Furthermore, the calculation circuit 24 applies the pattern voltage Vb to the column electrode EY4 during the period from time t5 to time t6 in the period corresponding to the subframe SF1 , and applies the pattern voltage Va during the period from time t6 to time t9 .

[0273] Thus, during the period corresponding to subframe SF1, the dimming region R(1,4) receives a pattern voltage Vc from the corresponding row electrode EX1, a pattern voltage Vb from the corresponding column electrode EY4 from time t5 to time t6, and a pattern voltage Va from the corresponding column electrode EY4 from time t6 to time t9. Therefore, the potential difference between time t5 and time t6 in subframe SF1 is 0 volts, and the potential difference between time t6 and time t9 is +VX volts. Therefore, during the period corresponding to subframe SF1, the dimming region R(1,4) effectively remains in a state with a relative on-period of 0.4.

[0274] Furthermore, the calculation circuit 24 applies the pattern voltage Va to the column electrode EY5 during the period corresponding to the sub-frame SF1 .

[0275] As a result, the dimming region R(1,5) receives a pattern voltage Vc from the corresponding row electrode EX1 and a pattern voltage Va from the corresponding column electrode EY5. Consequently, the potential difference is +VX volts throughout subframe SF1. Consequently, during the period corresponding to subframe SF1, the dimming region R(1,5) is effectively in an on state (light-transmitting state).

[0276] (Period corresponding to subframe SF2)

[0277] During the period corresponding to the subframe SF2 (time t9 to time t13 ), the calculation circuit 24 also applies the pattern voltage Vc to the row electrode EX1 .

[0278] Furthermore, the calculation circuit 24 applies the pattern voltage Vb to the column electrode EY1 during a period corresponding to the sub-frame SF2 .

[0279] As a result, the dimming region R(1,1) receives a pattern voltage Vc from the corresponding row electrode EX1 and a pattern voltage Vb from the corresponding column electrode EY1. Consequently, the potential difference remains at +VX volts throughout subframe SF2. Consequently, during the period corresponding to subframe SF2, the dimming region R(1,1) is effectively in an on state (light-transmitting state).

[0280] Furthermore, the calculation circuit 24 applies the pattern voltage Vb to the column electrode EY2 during the period from time t9 to time t12 in the period corresponding to the subframe SF2 , and applies the pattern voltage Va during the period from time t12 to time t13 .

[0281] As a result, the dimming region R(1,2) receives a pattern voltage Vc from the corresponding row electrode EX1 during the period corresponding to subframe SF2, a pattern voltage Vb from the corresponding column electrode EY2 during the period from time t9 to time t12, and a pattern voltage Va from the corresponding column electrode EY2 during the period from time t12 to time t13. Therefore, the potential difference during subframe SF2 is +VX volts from time t9 to time t12, and +VX volts from time t12 to time t13. Therefore, during the period corresponding to subframe SF2, the dimming region R(1,2) is effectively in the on state (light-transmitting state).

[0282] Furthermore, the calculation circuit 24 applies the pattern voltage Vb to the column electrode EY3 during the period from time t9 to time t11 in the period corresponding to the subframe SF2 , and applies the pattern voltage Va during the period from time t11 to time t13 .

[0283] As a result, the dimming region R(1,3) receives a pattern voltage Vc from the corresponding row electrode EX1 during the period corresponding to subframe SF2, a pattern voltage Vb from the corresponding column electrode EY3 during the period from time t9 to time t11, and a pattern voltage Va from the corresponding column electrode EY3 during the period from time t11 to time t13. Therefore, the potential difference during subframe SF2 from time t9 to time t11 is +VX volts, and the potential difference during time t11 to time t13 is +VX volts. Therefore, during the period corresponding to subframe SF2, the dimming region R(1,3) is effectively in the on state (light-transmitting state).

[0284] Furthermore, the calculation circuit 24 applies the pattern voltage Vb to the column electrode EY4 during the period from time t9 to time t10 in the period corresponding to the subframe SF2 (time t9 to time t13 ), and applies the pattern voltage Va during the period from time t10 to time t13 .

[0285] As a result, the dimming region R(1,4) receives a pattern voltage Vc from the corresponding row electrode EX1 during the period corresponding to subframe SF2, a pattern voltage Vb from the corresponding column electrode EY4 during the period from time t9 to time t10, and a pattern voltage Va from the corresponding column electrode EY4 during the period from time t10 to time t13. Therefore, the potential difference between time t9 and time t10 in subframe SF2 is +VX volts, and the potential difference between time t10 and time t13 is +VX volts. Therefore, during the period corresponding to subframe SF2, the dimming region R(1,4) is effectively in the on state (light-transmitting state).

[0286] Furthermore, the calculation circuit 24 applies the pattern voltage Va to the column electrode EY5 during the period corresponding to the sub-frame SF2 .

[0287] As a result, the dimming region R(1,5) receives a pattern voltage Vc from the corresponding row electrode EX1 and a pattern voltage Va from the corresponding column electrode EY5. Consequently, the potential difference is +VX volts throughout subframe SF2. Consequently, during the period corresponding to subframe SF2, the dimming region R(1,5) is effectively in an on state (light-transmitting state).

[0288] (Period corresponding to subframe SF3)

[0289] In addition, regarding the period corresponding to subframe SF3 (time t13 to time t17), the period corresponding to subframe SF4 (time t17 to time t21), and the period corresponding to subframe SF5 (time t21 to time t25), these are waveforms obtained by simply reversing the signs of the mode voltages Va, Vb, and Vc and the sign of the potential difference in the periods corresponding to subframe SF0, subframe SF1, and subframe SF2, respectively, and therefore their detailed description is omitted.

[0290] Figure 12 This is an operation sequence diagram of the second embodiment (Part 2).

[0291] Next, the operation of the second column corresponding to the column electrode EX2 in the second embodiment will be described.

[0292] (Period corresponding to subframe SF0)

[0293] like Figure 12 As shown in the graph (e) of FIG. 2 , during the period corresponding to the subframe SF0 (time t1 to time t5 ), the calculation circuit 24 applies the pattern voltage Vb to the row electrode EX2 .

[0294] In addition, if Figure 12 As shown in the graph (f) of , the calculation circuit 24 applies the pattern voltage Vb to the column electrode EY2 from time t1 to time t4 in the period corresponding to the subframe SF0 , and applies the pattern voltage Va from time t4 to time t5 .

[0295] Thus, the dimming region R(2,2) is applied with the pattern voltage Vb from the corresponding row electrode EX2, and the pattern voltage Vb is applied from the corresponding column electrode EY2 from time t1 to time t4. Figure 12 As shown in the graph (g) of , the potential difference is 0 volt during the period from time t1 to time t4.

[0296] In addition, the mode voltage Va is applied to the dimming region R(2,2) from the corresponding column electrode EY2 from time t4 to time t5. Figure 12 As shown in the graph (g) of , the potential difference during the period from time t4 to time t5 is +VX volts. Therefore, during the period corresponding to subframe SF0, the dimming region R(2,2) effectively becomes a state with a relative on-period of 0.9.

[0297] In addition, if Figure 12 As shown in the graph (h) of , the calculation circuit 24 applies the pattern voltage Vb to the column electrode EY3 during the period from time t1 to time t3 in the period corresponding to the subframe SF0 , and applies the pattern voltage Va during the period from time t3 to time t5 .

[0298] As a result, the dimming region R(2,3) receives pattern voltage Vb from the corresponding row electrode EX2 during the period corresponding to subframe SF0, pattern voltage Vb from the corresponding column electrode EY3 during the period from time t1 to time t3, and pattern voltage Va from the corresponding column electrode EY3 during the period from time t3 to time t5. Therefore, the potential difference between time t1 and time t3 within subframe SF0 is 0 volts, and the potential difference between time t3 and time t5 is +VX volts. Therefore, during the period corresponding to subframe SF0, the dimming region R(2,3) effectively remains in a state with a relative on-period of 0.8.

[0299] In addition, if Figure 12 As shown in graph (j) of , the calculation circuit 24 applies the pattern voltage Vb to the column electrode EY4 during the period from time t1 to time t2 in the period corresponding to the subframe SF0 , and applies the pattern voltage Va during the period from time t2 to time t5 .

[0300] Thus, the dimming region R(2,4) receives the pattern voltage Vb from the corresponding row electrode EX2 during the period corresponding to the subframe SF0, receives the pattern voltage Vb from the corresponding column electrode EY4 during the period from time t1 to time t2, and receives the pattern voltage Va from the corresponding column electrode EY4 during the period from time t2 to time t5. Figure 12 As shown in graph (k), the potential difference between time t1 and time t2 in subframe SF0 is 0 volts, and the potential difference between time t2 and time t5 is +VX volts. Therefore, during the period corresponding to subframe SF0, the dimming region R(2,4) effectively becomes 0.6 relative to the on-period.

[0301] Although not shown, the calculation circuit 24 applies the pattern voltage Va to the column electrode EY5 during the period corresponding to the sub-frame SF0 .

[0302] As a result, the dimming region R(2,5) receives the pattern voltage Vb from the corresponding row electrode EX2 and the pattern voltage Va from the corresponding column electrode EY5. Consequently, the potential difference is +VX volts throughout the entire duration of subframe SF0. ​​Consequently, during the duration corresponding to subframe SF0, the dimming region R(2,5) is effectively in the on state (light-transmitting state).

[0303] (Period corresponding to subframe SF1)

[0304] In the second embodiment, the same operation as that of the subframe SF0 is performed also in the period corresponding to the subframe SF1 (time t5 to time t9 ), and therefore detailed description thereof will be omitted.

[0305] (Period corresponding to subframe SF2)

[0306] Next, the operation in subframe SF2 will be described.

[0307] like Figure 12 As shown in the graph (e) of FIG. 2 , during the period corresponding to the subframe SF2 (time t9 to time t13 ), the calculation circuit 24 applies the pattern voltage Vb to the row electrode EX2 .

[0308] In addition, if Figure 12 As shown in the graph (f) of , the calculation circuit 24 applies the pattern voltage Vb to the column electrode EY2 from time t9 to time t12 in the period corresponding to the subframe SF2, and applies the pattern voltage Va from time t12 to time t13.

[0309] Thus, the dimming region R(2,2) is applied with the pattern voltage Vb from the corresponding row electrode EX2, and the pattern voltage Vb is applied from the corresponding column electrode EY2 from time t9 to time t12. Figure 12 As shown in the graph (g) of , the potential difference is 0 volt during the period from time t9 to time t12.

[0310] In addition, the mode voltage Va is applied to the dimming region R(2,2) from the corresponding column electrode EY2 from time t12 to time t13. Figure 12 As shown in the graph (g) of , the potential difference is 0 V during the period from time t9 to time t12. Therefore, during the period corresponding to the subframe SF2, the dimming region R(2,2) is effectively in the off state (light shielding state).

[0311] In addition, if Figure 12 As shown in the graph (h) of , the calculation circuit 24 applies the pattern voltage Vb to the column electrode EY3 during the period from time t9 to time t11 in the period corresponding to the subframe SF2 , and applies the pattern voltage Va during the period from time t11 to time t13 .

[0312] As a result, the dimming region R(2,3) receives pattern voltage Vb from the corresponding row electrode EX2 during the period corresponding to subframe SF2, pattern voltage Vb from the corresponding column electrode EY3 during the period from time t9 to time t11, and pattern voltage Va from the corresponding column electrode EY3 during the period from time t11 to time t13. Therefore, the potential difference is 0 volts throughout the entire period of subframe SF2. Therefore, during the period corresponding to subframe SF2, the dimming region R(2,3) is effectively in an off state (light-shielded state).

[0313] In addition, if Figure 12 As shown in graph (j) of , the calculation circuit 24 applies the pattern voltage Vb to the column electrode EY4 during the period from time t9 to time t10 in the period corresponding to the subframe SF2 , and applies the pattern voltage Va during the period from time t10 to time t13 .

[0314] Thus, the dimming region R(2,4) receives the pattern voltage Vb from the corresponding row electrode EX2 during the period corresponding to the subframe SF2, receives the pattern voltage Vb from the corresponding column electrode EY4 during the period from time t9 to time t10, and receives the pattern voltage Va from the corresponding column electrode EY4 during the period from time t10 to time t13. Figure 12 As shown in the graph (k) of FIG, the potential difference is 0 V during the entire period of the subframe SF2. Therefore, during the period corresponding to the subframe SF2, the dimming region R(2,4) is effectively in an OFF state (light shielding state).

[0315] Although not shown, the calculation circuit 24 applies the pattern voltage Va to the column electrode EY5 during the period corresponding to the sub-frame SF2 .

[0316] As a result, the dimming region R(2,5) receives the pattern voltage Vb from the corresponding row electrode EX2 and the pattern voltage Va from the corresponding column electrode EY5. Consequently, the potential difference is +VX volts throughout the entire duration of subframe SF2. Consequently, the dimming region R(2,5) is effectively in the on state (light-transmitting state) during the duration of subframe SF2.

[0317] (Period corresponding to subframe SF3)

[0318] In addition, regarding the period corresponding to subframe SF3 (time t13 to time t17), the period corresponding to subframe SF4 (time t17 to time t21), and the period corresponding to subframe SF5 (time t21 to time t25), these are waveforms obtained by simply reversing the signs of the mode voltages Va, Vb, and Vc and the sign of the potential difference in the periods corresponding to subframe SF0, subframe SF1, and subframe SF2, respectively, and therefore their detailed description is omitted.

[0319] As described above, also in the control of the second embodiment, the same operation as that of the first embodiment can be performed.

[0320] [3] Third embodiment

[0321] In the above first and second embodiments, the case where the frame periods of frames FM0 to FM3 in the repetition period are constant is described, but the speed of the on / off action of the dimming area of ​​the dimming panel 21 constituting the dimming device 20 changes according to the temperature. Therefore, if the ambient temperature changes, the same color level display may not always be possible.

[0322] Therefore, in the third embodiment, a temperature detection circuit 50 for detecting the ambient temperature is provided, so that a constant gradation display can be always performed in accordance with the ambient temperature.

[0323] Figure 13 This is a block diagram schematically illustrating the configuration of a dimming system including a dimming device according to a third embodiment.

[0324] exist Figure 13 In, with Figure 1 The same parts are denoted by the same reference numerals, and reference is made to the detailed description thereof.

[0325] The light control system 1A according to the third embodiment includes a temperature detection circuit 50 , and the temperature detection circuit 50 outputs temperature data STH corresponding to the detected ambient temperature to the calculation circuit 24 .

[0326] Figure 14 It is an operation explanation diagram of the third embodiment.

[0327] exist Figure 14 In FIG. 5 , the vertical axis represents the relative ratio of each frame period of frames FM0 to FM3 to the repetition period.

[0328] exist Figure 14 In the figure, the area with constant relative ratios indicated by the upper and lower arrows is a temperature area (normal temperature area) corresponding to the case where the ratio of frame period FM0 to frame FM3 adopted in the above-mentioned first and second embodiments is FM0:FM1:FM2:FM3=0.6:0.2:0.1:0.1.

[0329] In a temperature region where the temperature is lower than the normal temperature region (in Figure 14 In the area on the left side in the middle), the operation circuit 24 controls by reducing the ratio of the frame period of frame FM0 and increasing the ratio of the frame period of frame FM1 to frame FM3, thereby effectively enabling the same halftone display as in the normal temperature area.

[0330] On the other hand, in a temperature region where the temperature is higher than the normal temperature region (in Figure 14 In the area on the right side), the operation circuit 24 controls by increasing the ratio of the frame period of frame FM0 and reducing the ratio of the frame period of frame FM1 to frame FM3, thereby effectively enabling the same halftone display as in the normal temperature area.

[0331] As a result, according to the third embodiment, even if the ambient temperature of the place where the light control device 20 is installed changes, a constant halftone display can be always performed.

[0332] The same effect can be achieved by extending the repetition period, but the possibility of flickering increases. Therefore, the third embodiment adopts a method of changing the ratio of frame periods while keeping the repetition period constant.

[0333] The above description adopts a configuration in which only the ratio of the frame periods is changed. However, in addition to this, the voltage applied to the dimming area can be varied to enable constant halftone display.

[0334] [4] Fourth embodiment

[0335] In addition, if Figure 15 As shown, the dimming device 20 according to the first to third embodiments can also be applied to the display device 100 .

[0336] Figure 15 This is a schematic block diagram of the configuration of a display device to which the dimming device according to the first to third embodiments is applied.

[0337] The display device 100 includes an analysis device 10 , a transparent display 101 , and a dimming device 20 .

[0338] The dimming device 20 is any one of the dimming devices 20 according to the first to third embodiments.

[0339] The analysis device 10 is Figure 1 The analyzing device 10 shown has the same structure, but is preferably configured to perform analysis most suitable for the transparent display 101.

[0340] In the transparent display 101, unit areas having transparent regions and light-emitting regions are arranged two-dimensionally. Multiple light-emitting pixels (e.g., R pixels, G pixels, and B pixels) are arranged in each light-emitting region. The light-emitting colors of the R pixels, G pixels, and B pixels correspond to red (R), green (G), and blue (B), respectively. As a result, the transparent display 101 can display images or directly transmit external light from the back.

[0341] The analyzing device 10 receives a request command CMD related to image display and dimming from the upper controller, analyzes the request corresponding to the request command CMD to generate an image signal SGR and supplies the image signal SGR to the transparent display 101, and generates a dimming signal SDM and supplies the dimming signal SDM to the dimming device 20.

[0342] The transparent display 101 displays a predetermined image on a display screen according to the image signal SGR. Here, the image is not limited to pictures, photos, etc., but also includes character strings, etc.

[0343] The dimming device 20 independently sets the plurality of dimming regions R to a light-transmitting state, a light-blocking state, or a halftone state according to the dimming signal SDM.

[0344] As a result, in the image displayed on the transparent display 101 , the image corresponding to the region in which the dimming device 20 is set to the light-transmitting state is displayed in the original color.

[0345] Furthermore, among the images displayed on the transparent display 101 , the image corresponding to the region where the dimming device is set to the light-shielding state is displayed darkly and is hardly visible.

[0346] Furthermore, in the image displayed on the transparent display 101, the image corresponding to the area in which the dimming device is set to a halftone state is displayed brighter or darker than other areas according to its halftone, so that the area displaying the image that the user wants to pay attention to can be made more conspicuous than other areas or displayed in a flashing manner, or conversely, the area displaying the image containing information that is not necessarily needed can be made less conspicuous than other areas that the user wants to pay attention to.

[0347] While several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways and can be omitted, replaced, or modified without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention and are also included within the invention set forth in the claims and their equivalents.

Claims

1. A dimming device comprising: A dimming panel comprising: a plurality of row electrodes extending along a first direction; a plurality of column electrodes extending along a second direction intersecting the first direction; and a dimming layer located between the plurality of row electrodes and the plurality of column electrodes, having a plurality of dimming areas divided into a matrix by the plurality of row electrodes and the plurality of column electrodes; as well as A dimming control device performs the following control: applying one of a plurality of pattern voltages having predetermined voltage waveforms to the plurality of row electrodes and the plurality of column electrodes according to the color scales of the plurality of dimming areas, In which, during each frame period of a plurality of frame periods different from each other that constitute a repetition period, the dimming control device selects a pattern voltage to be applied to the plurality of row electrodes and the plurality of column electrodes respectively according to the color levels of the respective plurality of dimming areas, wherein the repetition period represents a period as a repeated unit for controlling dimming.

2. The dimming device according to claim 1, wherein: The dimming control device controls each of the frame periods constituting the repetitive period so that the polarity of the pattern voltage applied during the frame period is reversed between the even-numbered frame periods and the odd-numbered frame periods.

3. The dimming device according to claim 1, wherein: The pattern voltages are binary signals, and are set to have the same effective value.

4. The dimming device according to claim 1, wherein: The pattern of the difference voltage between two pattern voltages selected for one dimming area and applied during one frame period is set to transition between a voltage that puts the dimming area in a light-shielding state and a voltage that puts the dimming area in a light-transmitting state.

5. The dimming device according to claim 4, wherein: The voltage for setting the dimming area in the light-shielding state is 0 volt. The dimming device according to claim 1 , wherein: The dimming control device receives a dimming signal and generates a column control signal and a row control signal according to the dimming signal, wherein the dimming signal is used to specify the mode voltage to be applied to the plurality of column electrodes among the plurality of mode voltages, and to specify the mode voltage to be supplied to the plurality of row electrodes among the plurality of mode voltages. The dimming device further comprises: a column electrode driving circuit configured to drive the plurality of column electrodes according to the column control signal; and The row electrode driving circuit drives the plurality of row electrodes according to the row control signal.

7. The dimming device according to claim 6, wherein: The plurality of frame periods include a first frame period and a second frame period in which the polarity of the voltage waveform is reversed with respect to the polarity of the voltage waveform in the first frame period. The dimming control device further generates a polarity signal indicating the polarity of the plurality of frame periods. The column electrode driving circuit drives the plurality of column electrodes according to the column control signal and the polarity signal. The row electrode driving circuit drives the plurality of row electrodes according to the row control signal and the polarity signal.

8. The dimming device according to claim 6, wherein: A reference voltage generating circuit is further provided, the reference voltage generating circuit generating a reference voltage and supplying the reference voltage to each of the column electrode driving circuit and the row electrode driving circuit.

9. The dimming device according to claim 1, wherein: The plurality of frame periods include frame periods having different lengths from one another.

10. The dimming device according to claim 4, wherein: The dimming control device controls the ratio of the lengths of the periods during which the respective dimming areas are in the light-transmitting state in the repetition period to perform a half-tone display. The dimming device according to claim 1 , wherein: The dimming control device changes the ratio of the lengths of the plurality of frame periods in the repetition period according to the ambient temperature.

12. A display device comprising: transparent displays; and A dimming device is disposed on the back side of the transparent display and is capable of controlling the transmittance of light. in, The dimming device includes a dimming panel. The dimming panel has: a plurality of row electrodes extending along a first direction; a plurality of column electrodes extending along a second direction intersecting the first direction; a dimming layer having a plurality of dimming areas divided into a matrix shape by the plurality of row electrodes and the plurality of column electrodes; as well as A dimming control device performs the following control: applying one of a plurality of pattern voltages having predetermined voltage waveforms to the plurality of row electrodes and the plurality of column electrodes according to the color scales of the plurality of dimming areas, During each frame period of a plurality of frame periods different from each other that constitute a repetition period, the dimming control device selects a pattern voltage to be applied to the plurality of row electrodes and the plurality of column electrodes respectively according to the color levels of the respective plurality of dimming areas, wherein the repetition period represents a period as a repetitive unit for controlling dimming.

Images