Pixel circuit, display panel and display device

Abstract

The application provides a pixel circuit, a display panel and a display device. The pixel circuit comprises a pixel electrode, a data line, a gate scanning line, a first thin film transistor, a second thin film transistor and a control wire. The first thin film transistor is used for controlling whether to input a data signal to the pixel electrode. The second thin film transistor is used for switching an effective channel length of the first thin film transistor. The first end of the second thin film transistor is electrically connected with the active layer of the first thin film transistor. In response to the second thin film transistor being closed, the effective channel length of the first thin film transistor is a first channel length. In response to the second thin film transistor being opened, the effective channel length of the first thin film transistor is a second channel length. The first channel length is greater than the second channel length. The pixel circuit can improve the on-state current while reducing the off-state current, greatly improve the ratio of the on-state current to the off-state current, and thus improve the display contrast and the image quality.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a pixel circuit, a display panel and a display device. BACKGROUND

[0002] In a display panel, a thin film transistor (TFT) is a core device for controlling pixel switching, and its performance directly determines the display quality of the display panel.

[0003] Among them, the performance of the thin film transistor is mainly determined by the on-state current, the off-state current and the on-off ratio (the ratio of the on-state current to the off-state current). For example, the larger the on-state current, the higher the pixel charging efficiency; the smaller the off-state current, the lower the leakage current, and the higher the display contrast; the on-off ratio needs to meet a certain value to ensure normal display of the pixel at different gray scale voltages.

[0004] However, in a conventional thin film transistor, increasing the on-state current will cause the off-state current to increase synchronously, making it difficult to simultaneously optimize the on-state current and the off-state current, thereby limiting the on-off ratio and adversely affecting the display quality. SUMMARY

[0005] The pixel circuit, the display panel and the display device provided by the present application aim to solve the problem that the on-state current and the off-state current of the thin film transistor in the existing pixel circuit are difficult to be simultaneously optimized, thereby adversely affecting the display quality.

[0006] To solve the above technical problems, one technical solution adopted by the present application is to provide a pixel circuit, comprising:

[0007] a pixel electrode for driving a pixel;

[0008] a data line for transmitting a data signal;

[0009] a gate scanning line for transmitting a scanning signal;

[0010] a first thin film transistor for controlling whether to input a data signal to the pixel electrode; the first thin film transistor comprises an active layer, a first end and a second end electrically connected to the active layer, and a control end; wherein the first end of the first thin film transistor is electrically connected to the pixel electrode, and the second end of the first thin film transistor is electrically connected to the data line; the control end of the first thin film transistor is electrically connected to the gate scanning line;

[0011] A second thin-film transistor is used to switch the effective channel length of the first thin-film transistor; the second thin-film transistor includes a first terminal, a second terminal, and a control terminal; the first terminal of the second thin-film transistor is electrically connected to the active layer of the first thin-film transistor; the second terminal of the second thin-film transistor is electrically connected to the data line.

[0012] The control trace is electrically connected to the control terminal of the second thin-film transistor.

[0013] In response to the second thin-film transistor being turned off, the pixel electrode can transfer charge from the first end of the first thin-film transistor to the second end of the first thin-film transistor, and the effective channel length of the first thin-film transistor is the first channel length.

[0014] In response to the second thin-film transistor being turned on, the data line can transmit data signals from the first terminal of the second thin-film transistor to the first terminal of the first thin-film transistor; the effective channel length of the first thin-film transistor is the second channel length; wherein the first channel length is greater than the second channel length.

[0015] In one specific embodiment, the first end of the second thin-film transistor is disposed between the first end and the second end of the first thin-film transistor;

[0016] Wherein, the first channel length is the distance between the first end and the second end of the first thin-film transistor; the second channel length is the distance between the first end of the first thin-film transistor and the first end of the second thin-film transistor.

[0017] In one specific embodiment, the length of the first channel is greater than or equal to 7 micrometers and less than or equal to 50 micrometers;

[0018] The length of the second channel is greater than or equal to 1 micrometer and less than or equal to 10 micrometers.

[0019] In one specific embodiment, the second thin-film transistor is turned off in response to the control line inputting a low potential to the control terminal of the second thin-film transistor;

[0020] In response to the control line inputting a high potential to the control terminal of the second thin-film transistor, the second thin-film transistor is turned on.

[0021] In one specific embodiment, the high-potential triggering time of the gate scan line lags behind the high-potential triggering time of the control trace, and the lag time is a first preset time;

[0022] The low-potential triggering time of the control trace lags behind the low-potential triggering time of the gate scan line, and the lag time is a second preset time.

[0023] In one specific embodiment, the low-potential triggering time of the gate scan line lags behind the high-potential triggering time of the data line, and the lag time is a third preset time.

[0024] The low-potential trigger time of the data line lags behind the low-potential trigger time of the gate scan line, and the lag time is a fourth preset time.

[0025] In one specific embodiment, the second preset time is greater than the fourth preset time.

[0026] In one specific embodiment, the first end of the first thin-film transistor is disposed in the same layer as the second end of the first thin-film transistor and the first end of the second thin-film transistor;

[0027] The first end and the second end of the first thin-film transistor are respectively connected to the opposite sides of the active layer of the first thin-film transistor; the first end of the second thin-film transistor is connected to the central region of the active layer of the first thin-film transistor.

[0028] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide a display panel, including the pixel circuits as described in any of the above.

[0029] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide a display device, including a display panel as described in any of the above claims.

[0030] The beneficial effects of this application's embodiments are as follows: Unlike existing technologies, this application provides a pixel circuit, a display panel, and a display device. The pixel circuit includes a pixel electrode, a data line, a gate scan line, a first thin-film transistor (TFT), a second TFT, and control traces. The first TFT controls whether to input a data signal to the pixel electrode. The first TFT includes an active layer, a first terminal and a second terminal electrically connected to the active layer, and a control terminal. The first terminal of the first TFT is electrically connected to the pixel electrode, and the second terminal is electrically connected to the data line. The control terminal of the first TFT is electrically connected to the gate scan line. The second TFT is used to switch the effective channel length of the first TFT. The second TFT includes a first terminal, a second terminal, and a control terminal. The first terminal of the second TFT is electrically connected to the active layer of the first TFT. The second terminal of the second TFT is electrically connected to the data line. The control traces are electrically connected to the control terminal of the second TFT. In this dual-mode operation, in response to the second thin-film transistor being off, the pixel electrode can transfer charge from the first terminal of the first thin-film transistor to the second terminal of the first thin-film transistor, where the effective channel length of the first thin-film transistor is the same as the first channel length. In response to the second thin-film transistor being on, the data line can transmit data signals from the first terminal of the second thin-film transistor to the first terminal of the first thin-film transistor, where the effective channel length of the first thin-film transistor is the same as the second channel length, and the first channel length is greater than the second channel length. By electrically connecting the first terminal of the second thin-film transistor to the active layer of the first thin-film transistor, the second thin-film transistor can switch the drain of the first thin-film transistor, thereby dynamically adjusting the effective channel length of the first thin-film transistor. This allows for a shorter second channel length during pixel charging to increase the on-state current, significantly improving pixel charging efficiency. After charging is complete, a longer first channel length is used to reduce the off-state current, effectively reducing leakage current. This dual-mode operation significantly increases the ratio of on-state current to off-state current, thereby improving display contrast and image quality. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the pixel circuit provided in an embodiment of this application;

[0032] Figure 2 for Figure 1 The equivalent circuit diagram of the pixel circuit shown;

[0033] Figure 3 for Figure 1 The equivalent circuit diagram of the pixel circuit during the holding phase is shown.

[0034] Figure 4 for Figure 1 The equivalent circuit diagram of the pixel circuit during the charging stage is shown.

[0035] Figure 5 for Figure 1 The charging timing diagram of the pixel circuit shown is shown.

[0036] Figure 6 for Figure 1 The pixel circuit shown is a cross-sectional view along line AA.

[0037] Figure 7 A simplified structural diagram of a display panel provided in one embodiment of this application;

[0038] Figure 8 This is a simplified structural diagram of a display device provided in an embodiment of this application.

[0039] Explanation of icon numbers:

[0040] 100 - Display panel; 10 - Pixel circuit; 1 - Pixel electrode; 2 - Data line; 3 - Gate scan line; 4 - First thin-film transistor; 5 - Second thin-film transistor; 6 - Control trace; 41 - First terminal of the first thin-film transistor; 42 - Second terminal of the first thin-film transistor; 43 - Control terminal of the first thin-film transistor; 44 - Active layer; 45 - Substrate; 46 - Gate insulating layer; 51 - First terminal of the second thin-film transistor; 52 - Second terminal of the second thin-film transistor; 53 - Control terminal of the second thin-film transistor. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0042] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0043] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0044] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0045] See Figures 1-6 , Figure 1 This is a schematic diagram of the pixel circuit provided in an embodiment of this application; Figure 2 for Figure 1 The equivalent circuit diagram of the pixel circuit shown; Figure 3 for Figure 1 The equivalent circuit diagram of the pixel circuit during the holding phase is shown. Figure 4 for Figure 1 The equivalent circuit diagram of the pixel circuit during the charging stage is shown. Figure 5 for Figure 1 The charging timing diagram of the pixel circuit shown is shown. Figure 6 for Figure 1 The pixel circuit shown is a cross-sectional view along line AA.

[0046] This application provides a pixel circuit 10 for driving pixels in a display panel to emit light to display an image. For example... Figure 1As shown, the pixel circuit 10 may include a pixel electrode 1, a data line 2, a gate scan line 3, a first thin-film transistor 4, a second thin-film transistor 5, and a control line 6.

[0047] In this configuration, pixel electrode 1 is used to drive pixel light emission. Multiple rows of gate scan lines 3 and multiple columns of data lines 2 are arranged alternately; the gate scan lines 3 are used to transmit scan signals to activate the first thin-film transistor 4 of the corresponding row or column of pixels, allowing data signals to be written to that row of pixels. The data lines 2 are used to transmit data signals to write data signals to the pixels of the corresponding column or row. The gate scan lines 3 and data lines 2 cooperate to write data signals into the storage capacitor of a specific pixel.

[0048] The first thin-film transistor 4 is used to control whether to input a data signal to the pixel electrode 1. Specifically, the first thin-film transistor 4 may include an active layer 44, a first terminal 41 and a second terminal 42 of the first thin-film transistor electrically connected to the active layer 44, and a control terminal 43 of the first thin-film transistor; specifically, the first terminal 41 of the first thin-film transistor is electrically connected to the pixel electrode 1, the second terminal 42 of the first thin-film transistor is electrically connected to the data line 2, and the control terminal 43 of the first thin-film transistor is electrically connected to the gate scan line 3.

[0049] In this design, the first terminal 41 of the first thin-film transistor (TFT) can be the source, the second terminal 42 of the first TFT can be the drain, and the control terminal 43 of the first TFT can be the gate. After the gate scan line 3 inputs a scan signal to the gate of the first TFT 4 and turns on the first TFT 4, the data signal transmitted by the data line 2 can be output to the corresponding pixel electrode 1 through the first TFT 4, thereby writing the data signal into the corresponding storage capacitor.

[0050] Of course, in other embodiments, the first terminal 41 of the first thin-film transistor can also be the drain, and the second terminal 42 of the first thin-film transistor can be the source.

[0051] The second thin-film transistor 5 is used to switch the effective channel length of the first thin-film transistor 4. Specifically, the second thin-film transistor 5 includes a first terminal 51, a second terminal 52, and a control terminal 53; wherein the first terminal 51 of the second thin-film transistor is electrically connected to the active layer 44 of the first thin-film transistor 4; and the second terminal 52 of the second thin-film transistor is electrically connected to the data line 2.

[0052] The control trace 6 is electrically connected to the control terminal 53 of the second thin-film transistor to control the turning on and off of the second thin-film transistor 5. Specifically, the control trace 6 can be arranged parallel to the gate scan line 3.

[0053] In this design, the first terminal 51 of the second thin-film transistor (TFT) can be the source, the second terminal 52 can be the drain, and the control terminal 53 can be the gate. After the control line 6 inputs a control signal to the gate of the second TFT and turns on the second TFT, the data signal transmitted by the data line 2 is input from the drain of the second TFT, then output from the source of the second TFT to the active layer 44 of the first TFT, and then output through the active layer 44 of the first TFT to the corresponding pixel electrode 1, thereby writing the data signal into the corresponding storage capacitor.

[0054] Combination Figure 2 and Figure 3 In response to the second thin-film transistor 5 being turned off, the first terminal 51 and the second terminal 52 of the second thin-film transistor are not connected; the pixel electrode 1 can only transfer charge to the second terminal 42 of the first thin-film transistor through the first terminal 41 of the first thin-film transistor, forming a leakage current; at this time, the effective channel length of the first thin-film transistor 4 is the first channel length L1.

[0055] In other words, when the second thin-film transistor 5 is turned off, the first terminal 41 of the first thin-film transistor serves as the source of the first thin-film transistor 4, and the second terminal 42 of the first thin-film transistor serves as the drain of the first thin-film transistor 4.

[0056] Combination Figure 2 and Figure 4 In response to the second thin-film transistor 5 being turned on, the first terminal 51 and the second terminal 52 of the second thin-film transistor are connected; the data line 2 can transmit data signals to the first terminal 41 of the first thin-film transistor through the first terminal 51 of the second thin-film transistor, forming an on-state current. At this time, the effective channel length of the first thin-film transistor 4 is the second channel length L2.

[0057] In other words, when the second thin-film transistor 5 is turned on, the first terminal 41 of the first thin-film transistor serves as the source of the first thin-film transistor 4, and the first terminal 51 of the second thin-film transistor serves as the drain of the first thin-film transistor 4.

[0058] Specifically, the first channel length L1 is greater than the second channel length L2. It can be understood that a longer channel length reduces the leakage current when the first thin-film transistor 4 is off, while a shorter channel length increases the on-state current of the first thin-film transistor 4.

[0059] Thus, by electrically connecting the first terminal 51 of the second thin-film transistor to the active layer 44 of the first thin-film transistor 4, the second thin-film transistor 5 can switch the drain of the first thin-film transistor 4, thereby dynamically adjusting the effective channel length of the first thin-film transistor 4. During the pixel charging stage, a shorter second channel length L2 is used to increase the on-state current, significantly improving pixel charging efficiency. After charging is complete, a longer first channel length L1 is used to reduce the off-state current, effectively reducing leakage current. This dual-mode operation significantly increases the ratio of on-state current to off-state current, thereby improving display contrast and image quality.

[0060] like Figure 1 As shown, in a specific embodiment, the first end 51 of the second thin-film transistor is disposed between the first end 41 of the first thin-film transistor and the second end 42 of the first thin-film transistor, so as to change the effective channel length of the first thin-film transistor 4 by controlling the conduction state of the second thin-film transistor 5.

[0061] During the pixel retention phase, the second thin-film transistor 5 is turned off, and the first end 51 and the second end 52 of the second thin-film transistor are not connected. The effective channel length of the first thin-film transistor 4 is the first channel length L1, which is determined by the distance from the first end 41 of the first thin-film transistor to the second end 52 of the second thin-film transistor. That is, the first channel length L1 is the distance between the first end 41 and the second end 42 of the first thin-film transistor.

[0062] During the pixel charging phase, the second thin-film transistor 5 is turned on, and its first terminal 51 and second terminal 52 are connected. It can be understood that when the data line 2 is connected to the first terminal 41 of the first thin-film transistor via the first terminal 51 and the second terminal 52 of the second thin-film transistor, the current is mainly transmitted through the second thin-film transistor 5, which is equivalent to short-circuiting the second terminal 42 of the first thin-film transistor. At this time, the effective channel length of the first thin-film transistor 4 is the second channel length L2, which is determined by the distance between the first terminal 41 of the first thin-film transistor and the first terminal 51 of the second thin-film transistor; that is, the second channel length L2 is the distance between the first terminal 41 of the first thin-film transistor and the first terminal 51 of the second thin-film transistor.

[0063] Thus, by dynamically adjusting the channel length of the first thin-film transistor 4, a smaller second channel length L2 is used during the pixel charging stage to increase the on-state current and ensure charging efficiency; while during the holding stage, a larger first channel length L1 is used to reduce the off-state current. This effectively improves the switching ratio, allowing the first thin-film transistor 4 to significantly reduce leakage current while maintaining high driving capability, thereby improving the stability and contrast of the panel display.

[0064] Specifically, the first channel length L1 is greater than or equal to 7 micrometers and less than or equal to 50 micrometers. It can be understood that the larger the effective channel length of the thin-film transistor, the greater its resistance; during the holding phase when the first thin-film transistor 4 is off, a larger first channel length results in a larger resistance in the leakage current path, thereby effectively reducing the off-state current of the first thin-film transistor 4 and improving the contrast and stability of the display image.

[0065] Specifically, the length L1 of the first channel can be any value among 7 micrometers, 15 micrometers, 20 micrometers, 30 micrometers, and 50 micrometers.

[0066] The second channel length L2 is greater than or equal to 1 micrometer and less than or equal to 10 micrometers. It can be understood that the smaller the effective channel length of a thin-film transistor (TFT), the lower its carrier migration resistance and the larger its on-state current. During the charging phase when both the first TFT 4 and the second TFT 5 are turned on, the smaller second channel length results in lower carrier migration resistance, effectively increasing the on-state current of the first TFT 4. This provides a higher current drive capability during the charging phase, ensuring fast and stable pixel charging.

[0067] Specifically, the second channel length L2 can be any value among 1 micrometer, 2 micrometers, 5 micrometers, 8 micrometers, and 10 micrometers.

[0068] Combination Figure 2 and Figure 5 In response to a low potential input to the control terminal 53 of the second thin-film transistor via control line 6, the second thin-film transistor 5 turns off; in response to a high potential input to the control terminal 53 of the second thin-film transistor via control line 6, the second thin-film transistor 5 turns on. By adjusting the switching state of the second thin-film transistor 5 via control line 6, the effective channel length of the first thin-film transistor 4 can be dynamically changed, allowing a smaller channel length to increase the on-state current during the charging phase and a larger channel length to reduce leakage current during the turn-off phase.

[0069] Specifically, taking the pixel circuit 10 corresponding to the pixel in the nth row and mth column as an example, such as... Figure 5 As shown, Gout_n is the scan signal of the gate scan line 3 in the nth row, Control_n is the control signal of the control line 6 in the nth row, and Data_m is the data signal of the data line 2 in the mth column.

[0070] The nth row gate scan line 3 is used to provide a potential signal to the control terminal 43 of the first thin film transistor corresponding to the nth row pixel; the nth row control line 6 is used to provide a potential signal to the control terminal 53 of the second thin film transistor corresponding to the nth row pixel; the mth column data line 2 is used to provide a potential signal to the first thin film transistor 4 corresponding to the mth column pixel.

[0071] The second thin-film transistor 5 can specifically be an N-type semiconductor thin-film transistor. When the potential is low, the second thin-film transistor 5 corresponding to the nth row pixel is in the off state. The source and drain of the first thin-film transistor 4 correspond to the first terminal 41 and the second terminal 42 of the first thin-film transistor, respectively. The effective channel length of the first thin-film transistor 4 is the first channel length L1.

[0072] When the potential is high, the second thin-film transistor 5 corresponding to the nth row pixel is in the on state. The source and drain of the first thin-film transistor 4 correspond to the first terminal 41 of the first thin-film transistor and the first terminal 51 of the second thin-film transistor, respectively. The effective channel length of the first thin-film transistor 4 is the second channel length L2.

[0073] Continue reading Figure 5 In a specific embodiment, the high-potential triggering time of the gate scan line 3 lags behind the high-potential triggering time of the control line 6 by a first preset time T1; and the low-potential triggering time of the control line 6 lags behind the low-potential triggering time of the gate scan line 3 by a second preset time T2. This ensures that the conduction time of the second thin-film transistor 5 completely covers the conduction time of the first thin-film transistor 4, thereby preventing the turning on and off of the second thin-film transistor 5 from affecting the normal operating timing of the first thin-film transistor 4.

[0074] Specifically, the control line 6 in the nth row inputs a high-level signal to the gate of the corresponding second thin-film transistor 5 to turn on the second thin-film transistor 5 in the nth row; after the first preset time T1, the gate scan line 3 in the nth row inputs a high-level signal to the gate of the corresponding first thin-film transistor 4 to turn on the first thin-film transistor 4 in the nth row.

[0075] The gate scan line 3 in the nth row inputs a low-level signal to the gate of the corresponding first thin-film transistor 4 to turn off the first thin-film transistor 4 in the nth row; after a second preset time T2, the control line 6 in the nth row inputs a low-level signal to the gate of the corresponding second thin-film transistor 5 to turn off the second thin-film transistor 5 in the nth row. In this way, it is ensured that the effective channel length of the first thin-film transistor 4 in the nth row is the second channel length L2 during the turn-on time period.

[0076] In a specific embodiment, the low-potential triggering time of the gate scan line 3 lags behind the high-potential triggering time of the data line 2 by a third preset time T3; and the low-potential triggering time of the data line 2 lags behind the low-potential triggering time of the gate scan line 3 by a fourth preset time T4. This ensures that the data signal is fully written into the storage capacitor while preventing fluctuations in the pixel voltage due to the incomplete shutdown of the first thin-film transistor 4.

[0077] Specifically, the data line 2 in the m-th column inputs a high-level signal to the drain of the corresponding first thin-film transistor 4 to write a data signal to the corresponding storage capacitor through the first thin-film transistor 4; after the third preset time T3, the gate scan line 3 in the n-th row inputs a low-level signal to the gate of the corresponding first thin-film transistor 4 to turn off the first thin-film transistor 4 in the n-th row.

[0078] It is understandable that during the data signal writing process, the first thin-film transistor 4 can only be turned off after the gate has fully stabilized during the high potential period. If the gate is turned off too early (low potential), the data signal will not be fully written, resulting in insufficient pixel charging and uneven display brightness or color deviation. Therefore, turning off the first thin-film transistor 4 after the data line 2 inputs a high level for a third preset time T3 ensures that the data signal is fully written to the storage capacitor.

[0079] The gate scan line 3 in the nth row inputs a low-level signal to the gate of the corresponding first thin-film transistor 4 to turn off the first thin-film transistor 4 in the nth row; after the fourth preset time T4, the data line 2 in the mth column inputs a low-level signal to the drain of the corresponding first thin-film transistor 4 to complete the charging stage.

[0080] It is understandable that after the gate is turned off (low potential), the first thin-film transistor 4 is disconnected, and the storage capacitor enters a floating state. If data line 2 becomes low potential before or at the same time as the gate is turned off, the voltage of data line 2 may pull down the pixel voltage through the first thin-film transistor 4, which is not yet fully turned off, resulting in write voltage distortion. Therefore, data line 2 needs to switch to a low potential only after the gate is turned off for a fourth preset time T4 (i.e., the gate is completely turned off) to avoid interference with the current pixel.

[0081] In a specific embodiment, the second preset time T2 is greater than the fourth preset time T4; that is, the time when the control line 6 in the nth row inputs a low-level signal to the gate of the corresponding second thin-film transistor 5 lags behind the time when the data line 2 in the mth column inputs a low-level signal to the drain of the corresponding first thin-film transistor 4. In other words, the time when the gate of the second thin-film transistor 5 is turned off lags behind the time when the data line 2 stops charging, so as to ensure that the process of turning off the control signal after the pixel charging is completed will not interfere with the normal operation of the data line 2, thereby ensuring the integrity of the charging process.

[0082] See Figure 6In a specific embodiment, the first end 41 of the first thin-film transistor (TFT) is disposed in the same layer as the second end 42 of the first TFT and the first end 51 of the second TFT. The first end 41 and the second end 42 of the first TFT overlap with opposite sides of the active layer 44 of the first TFT 4. The first end 51 of the second TFT overlaps with the central region of the active layer 44 of the first TFT 4. This allows for the simultaneous fabrication of the source and drain metal layers of the second TFT, thereby reducing the number of process steps.

[0083] Specifically, the first thin-film transistor 4 may further include a substrate 45 and a gate insulating layer 46. The control terminal 43 (gate) of the first thin-film transistor is disposed on one side surface of the substrate 45; the gate insulating layer 46 covers the side surface of the gate away from the substrate 45, as well as the portion of the substrate 45 not covered by the gate.

[0084] An active layer 44 is disposed on the surface of the gate insulating layer 46 away from the gate. The source of the first thin-film transistor 4 overlaps with one side of the active layer 44, and the drain of the first thin-film transistor 4 overlaps with the other side of the active layer 44. The distance L1 between the source and drain of the first thin-film transistor 4 is the first channel length. The source of the second thin-film transistor 5 is disposed between the source and drain of the first thin-film transistor 4 and overlaps with the active layer 44 of the first thin-film transistor 4. The distance L2 between the source of the second thin-film transistor 5 and the drain of the first thin-film transistor 4 is the second channel length. In this way, the effective channel length of the first thin-film transistor 4 can be controlled by controlling the conduction of the second thin-film transistor 5.

[0085] This application provides a pixel circuit 10, which includes a pixel electrode 1, a data line 2, a gate scan line 3, a first thin-film transistor 4, a second thin-film transistor 5, and a control line 6. The first thin-film transistor 4 controls whether to input a data signal to the pixel electrode 1. The first thin-film transistor 4 includes an active layer 44, a first terminal 41 and a second terminal 42 electrically connected to the active layer 44, and a control terminal 43. The first terminal 41 is electrically connected to the pixel electrode 1, the second terminal 42 is electrically connected to the data line 2, and the control terminal 43 is electrically connected to the gate scan line 3. The second thin-film transistor 5 is used to switch the effective channel length of the first thin-film transistor 4. The second thin-film transistor 5 includes a first terminal 51, a second terminal 52, and a control terminal 53. The first terminal 51 is electrically connected to the active layer 44 of the first thin-film transistor 4; the second terminal 52 is electrically connected to the data line 2; and the control line 6 is electrically connected to the control terminal 53. In this configuration, in response to the second thin-film transistor 5 being off, the pixel electrode 1 can transfer charge from the first terminal 41 of the first thin-film transistor to the second terminal 42 of the first thin-film transistor, and the effective channel length of the first thin-film transistor 4 is the first channel length. In response to the second thin-film transistor 5 being on, the data line 2 can transmit data signals from the first terminal 51 of the second thin-film transistor to the first terminal 41 of the first thin-film transistor, and the effective channel length of the first thin-film transistor 4 is the second channel length; wherein the first channel length is greater than the second channel length. By electrically connecting the first terminal 51 of the second thin-film transistor to the active layer 44 of the first thin-film transistor 4, the second thin-film transistor 5 can switch the drain of the first thin-film transistor 4, thereby dynamically adjusting the effective channel length of the first thin-film transistor 4. This allows for the use of a shorter second channel length during the pixel charging stage to increase the on-state current, significantly improving pixel charging efficiency; after charging is complete, a longer first channel length is used to reduce the off-state current, effectively reducing leakage current. This dual-mode operation significantly increases the ratio of on-state current to off-state current, thereby improving display contrast and image quality.

[0086] See Figure 7 , Figure 7This is a simplified structural diagram of a display panel 100 provided in one embodiment of this application. This application also provides a display panel 100 for displaying images; the display panel 100 may include the pixel circuit 10 involved in any of the above embodiments. Specifically, the display panel 100 may include a driving substrate (not shown), the driving substrate including a driving circuit layer (not shown), and the pixel circuit 10 disposed in the driving circuit layer. This display panel 100 can increase the on-state current while reducing the off-state current, significantly increasing the ratio of on-state current to off-state current, thereby improving display contrast and image quality.

[0087] See Figure 8 , Figure 8 This is a simplified structural diagram of a display device provided in one embodiment of this application. This application also provides a display device including the display panel 100 provided in the above embodiment. This display device can increase the on-state current while decreasing the off-state current, significantly increasing the ratio of on-state current to off-state current, thereby improving display contrast and image quality. This display device can be a product or component with display functionality, such as a mobile phone, tablet computer, laptop computer, or television. The display device also includes a motherboard, control circuitry, etc., whose structures are the same as or similar to those of existing display devices; please refer to the prior art for details, which will not be repeated here.

[0088] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A pixel circuit, characterized by comprising: The pixel circuit comprises: a pixel electrode for driving a pixel; a data line for transmitting a data signal; a gate scanning line for transmitting a scanning signal; a first thin film transistor for controlling whether to input the data signal to the pixel electrode; the first thin film transistor comprises an active layer, a first end and a second end electrically connected with the active layer, and a control end; wherein the first end of the first thin film transistor is electrically connected with the pixel electrode, and the second end of the first thin film transistor is electrically connected with the data line; the control end of the first thin film transistor is electrically connected with the gate scanning line; a second thin film transistor for switching an effective channel length of the first thin film transistor; the second thin film transistor comprises a first end, a second end and a control end; the first end of the second thin film transistor is electrically connected with the active layer of the first thin film transistor; the second end of the second thin film transistor is electrically connected with the data line; a control wire electrically connected with the control end of the second thin film transistor; wherein, in response to the second thin film transistor being closed, the pixel electrode can transmit electric charges to the second end of the first thin film transistor through the first end of the first thin film transistor, and the effective channel length of the first thin film transistor is a first channel length; in response to the second thin film transistor being opened, the data line can transmit the data signal to the first end of the first thin film transistor through the first end of the second thin film transistor; the effective channel length of the first thin film transistor is a second channel length; wherein the first channel length is greater than the second channel length.

2. The pixel circuit according to claim 1, wherein: the first end of the second thin film transistor is arranged between the first end and the second end of the first thin film transistor; wherein the first channel length is the distance between the first end and the second end of the first thin film transistor; and the second channel length is the distance between the first end of the first thin film transistor and the first end of the second thin film transistor.

3. The pixel circuit according to claim 2, wherein: the first channel length is greater than or equal to 7 microns and less than or equal to 50 microns; the second channel length is greater than or equal to 1 micron and less than or equal to 10 microns.

4. The pixel circuit according to claim 1, wherein: in response to the control wire inputting a low potential to the control end of the second thin film transistor, the second thin film transistor is closed; in response to the control wire inputting a high potential to the control end of the second thin film transistor, the second thin film transistor is opened.

5. The pixel circuit according to claim 4, wherein: the high potential trigger time of the gate scanning line lags behind the high potential trigger time of the control wire, and the lag time is a first preset time; the low potential trigger time of the control wire lags behind the low potential trigger time of the gate scanning line, and the lag time is a second preset time.

6. The pixel circuit according to claim 5, wherein: the low potential trigger time of the gate scanning line lags behind the high potential trigger time of the data line, and the lag time is a third preset time. The low potential triggering moment of the data line lags behind the low potential triggering moment of the gate scanning line, and the lag time is a fourth preset time.

7. The pixel circuit of claim 6, wherein, The second preset time is greater than the fourth preset time.

8. The pixel circuit of claim 2, wherein, The first end of the first thin film transistor is arranged in the same layer as the second end of the first thin film transistor and the first end of the second thin film transistor. The first end and the second end of the first thin film transistor are respectively overlapped with opposite sides of the active layer of the first thin film transistor; and the first end of the second thin film transistor is overlapped with a central region of the active layer of the first thin film transistor.

9. A display panel, characterized by, A display panel comprising the pixel circuit of any one of claims 1-8.

10. A display device, characterized by comprising: A display panel comprising the pixel circuit of claim 9.

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