Display device

Abstract

A display device is provided, the display device including: a display panel; a pixel in a display area of the display panel; a plurality of circuit boards connected to the non-display area of the display panel; and a plurality of driving circuits on the circuit boards, in which each of the plurality of circuit boards includes a group terminal connected to a pad of the non-display area, the group terminal includes a plurality of terminals adjacent to each other in a corresponding circuit board, and the group terminals of at least two circuit boards have different widths.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0043461 filed on March 29, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] An aspect of some embodiments of the present disclosure relates to a display device. Background Art

[0003] Organic light-emitting diode (OLED) displays are self-luminous and, unlike liquid crystal displays (LCDs), generally do not require a separate light source, resulting in relatively reduced thickness and weight. OLED displays are also attracting attention as next-generation displays for televisions, monitors, and portable electronic devices due to their high-quality features, such as relatively low power consumption, high brightness, and high response speed.

[0004] As the resolution of display devices increases, they include more data lines. Consequently, more driver circuits and circuit boards may be required to drive the data lines. Consequently, as the resolution of display devices increases, the gaps between circuit boards and the spacing between circuit board terminals may inevitably decrease because a large number of driver circuits are attached to the limited area of ​​the display panel.

[0005] Alignment marks located between the circuit boards are used to check alignment between the circuit boards. When the gap between the circuit board terminals is reduced as described above, there may be insufficient area for placement of alignment marks, which may make it difficult to form the alignment marks. In this case, the circuit boards may become misaligned. Furthermore, the reduced spacing between the circuit board terminals may cause misalignment between the circuit board terminals and the display panel pads (also known as "solder pads").

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background technology and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the Invention

[0007] Aspects of some embodiments of the present disclosure relate to a display device, for example, to a display device that can minimize misalignment of a circuit board at high resolution.

[0008] Aspects of some embodiments of the present disclosure include a display device that can minimize or reduce misalignment of a circuit board at high resolution.

[0009] According to some disclosed embodiments, a display device includes: a display panel; pixels in a display area of ​​the display panel; a plurality of circuit boards connected to a non-display area of ​​the display panel; and a plurality of driving circuits on the circuit boards, wherein each of the plurality of circuit boards includes a group terminal connected to a pad of the non-display area, the group terminals including a plurality of terminals adjacent to each other in the corresponding circuit boards, and the group terminals of at least two circuit boards have different widths.

[0010] According to some embodiments, the plurality of circuit boards includes: a first outermost circuit board; a second outermost circuit board; and an intermediate circuit board between the first outermost circuit board and the second outermost circuit board.

[0011] According to some embodiments, the group terminals of at least one of the first outermost circuit board and the second outermost circuit board have a different width than the group terminals of the intermediate circuit board.

[0012] According to some embodiments, a width of the group terminals of the middle circuit board is smaller than a width of the group terminals of at least one of the first outermost circuit board and the second outermost circuit board.

[0013] According to some embodiments, the display device further includes a first alignment mark between adjacent circuit boards.

[0014] According to some embodiments, the first alignment mark is between the first outermost circuit board and the middle circuit board.

[0015] According to some embodiments, a distance between any one of the facing sides of the first outermost circuit board and the middle circuit board and the center of the first alignment mark is equal to a distance between the other of the facing sides and the center of the first alignment mark.

[0016] According to some embodiments, the distance between any one of the facing sides of the outermost terminal of the first outermost circuit board near the first alignment mark and the outermost terminal of the middle circuit board near the first alignment mark and the center of the first alignment mark is different from the distance between the other one of the facing sides and the center of the first alignment mark.

[0017] According to some embodiments, any one of the facing sides is a side of the outermost terminals of the first outermost circuit board, and the other one of the facing sides is a side of the outermost terminals of the middle circuit board.

[0018] According to some embodiments, the first alignment mark is between the second outermost circuit board and the middle circuit board.

[0019] According to some embodiments, a distance between any one of the facing sides of the second outermost circuit board and the middle circuit board and the center of the first alignment mark is equal to a distance between the other of the facing sides and the center of the first alignment mark.

[0020] According to some embodiments, the distance between any one of the facing sides of the outermost terminal of the second outermost circuit board near the first alignment mark and the outermost terminal of the intermediate circuit board near the first alignment mark and the center of the first alignment mark is different from the distance between the other one of the facing sides and the center of the first alignment mark.

[0021] According to some embodiments, any one of the facing sides is a side of the outermost terminal of the second outermost circuit board, the other one of the facing sides is a side of the outermost terminal of the middle circuit board, and the distance between any one of the facing sides and the center of the first alignment mark is greater than the distance between the other one of the facing sides and the center of the first alignment mark.

[0022] According to some embodiments, the intermediate circuit board includes a first intermediate circuit board and a second intermediate circuit board, and the first alignment mark is between the first intermediate circuit board and the second intermediate circuit board.

[0023] According to some embodiments, a distance between any one of the facing sides of the first and second middle circuit boards and the center of the first alignment mark is equal to a distance between the other of the facing sides and the center of the first alignment mark.

[0024] According to some embodiments, the distance between any one of the facing sides of the outermost terminal of the first intermediate circuit board near the first alignment mark and the outermost terminal of the second intermediate circuit board near the first alignment mark and the center of the first alignment mark is equal to the distance between the other one of the facing sides and the center of the first alignment mark.

[0025] According to some embodiments, at least two of the circuit boards have different widths.

[0026] According to some embodiments, circuit boards having groups of terminals of different widths have different widths.

[0027] According to some embodiments, a circuit board including a group of terminals having a larger width has a larger width than a circuit board including a group of terminals having a smaller width.

[0028] According to some embodiments, the display device further includes a fan-out line connected to one side of each of the pads and the pixel.

[0029] According to some embodiments, the display device further includes a dummy line connected to the other side of each of the pads.

[0030] According to some embodiments, the display device further includes a second alignment mark between adjacent dummy lines.

[0031] According to some embodiments, the second alignment mark is on the same layer as the active layer of the pixel.

[0032] According to some embodiments, the second alignment mark has a triangular shape.

[0033] According to some embodiments, a plurality of group pads including adjacent pads among the pads are connected to a plurality of group terminals.

[0034] According to some embodiments, the second alignment mark includes a plurality of alignment marks, and the plurality of alignment marks are close to an imaginary center line that passes through a portion of the stack pad corresponding to half the width of the stack pad and extends parallel to the pad along a direction in which the pad extends.

[0035] According to some embodiments, when the total number of pads included in the group pad is an odd number, the imaginary center line is located at the center of the center pad at the center of the group pad, and the plurality of alignment marks are on both sides of the imaginary line connected to the center pad.

[0036] According to some embodiments, when the total number of pads included in the group pad is an even number, a plurality of alignment marks are on both sides of an nth imaginary line on the left side of the imaginary center line, where n is a natural number less than k / 2, and k is the total number of pads included in the group pad.

[0037] According to some embodiments, when the total number of pads included in the group pad is an even number, a plurality of alignment marks are on both sides of an nth imaginary line on the right side of an imaginary center line, where n is a natural number less than k / 2, and k is the total number of pads included in the group pad.

[0038] According to some embodiments, the second alignment mark includes a plurality of alignment marks on both sides of the dummy line with the dummy line interposed therebetween, and each of the plurality of alignment marks has a triangular shape.

[0039] According to some embodiments, the pads include an outermost group of pads connected to a first outermost circuit board and a middle group of pads connected to a middle circuit board, and a distance between any one of the facing sides of the pads included in the outermost group of pads and the pads included in the middle group of pads and the center of the first alignment mark is different from a distance between the other of the facing sides and the center of the first alignment mark.

[0040] According to some embodiments, a distance between any one of the facing sides and the center of the first alignment mark is greater than a distance between the other one of the facing sides and the center of the first alignment mark.

[0041] According to some embodiments, the gaps between adjacent circuit boards are equal.

[0042] However, aspects of the embodiments of the present disclosure are not limited to the aspects specifically described herein. The above and other aspects of the embodiments of the present disclosure will become more apparent to those skilled in the art by referring to the detailed description of the present disclosure given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] These and / or other aspects will become apparent and more readily understood through the following description of the embodiments with reference to the accompanying drawings, in which: Figure 1 is a plan view of a display device according to some embodiments; Figure 2 yes Figure 1 a plan view of a display panel; Figure 3 yes Figure 1 an enlarged view of portion A1; Figure 4 yes Figure 1 an enlarged view of portion A2; Figure 5 yes Figure 2 an enlarged view of portion A3; Figure 6 yes Figure 2 An enlarged view of part A4; Figure 7 is a circuit diagram of a pixel of a display device according to some embodiments; Figure 8 is a cross-sectional view of a display device according to some embodiments; Figure 9 yes Figure 2 an enlarged view of portion A5; Figure 10 It is along Figure 9 A sectional view taken along line II'; Figure 11 It is along Figure 9 A sectional view taken along line II-II'; Figure 12 It is along Figure 9 A sectional view taken along line III-III'; Figure 13 It is along Figure 9 A sectional view taken along line IV-IV'; Figure 14 is a diagram illustrating a position of a fifth alignment mark when the number of pads in a pad group is an odd number according to some embodiments; and Figure 15 is a diagram illustrating a position of a fifth alignment mark when the number of pads in a pad group is an even number, according to some embodiments. DETAILED DESCRIPTION

[0044] Aspects of some embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which aspects of some embodiments of the invention are shown. However, the present invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art.

[0045] It will also be understood that when a layer is referred to as being "on" another layer or substrate, the layer can be directly on the other layer or substrate, or intervening layers may also be present. Throughout the specification, like reference numerals refer to like components. In the drawings, the thickness of layers and regions are exaggerated for clarity.

[0046] Although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms may be used to distinguish one element from another. Therefore, without departing from the teachings of one or more embodiments, the first element discussed below may be referred to as the second element. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first," "second," etc. may also be used herein to distinguish elements of different categories or groups. For the sake of simplicity, the terms "first," "second," etc. may respectively represent "first category (or first group)," "second category (or second group)," etc.

[0047] The features of the various embodiments of the present disclosure may be combined in part or in whole. As will be clearly understood by those skilled in the art, various interactions and operations are technically feasible. The various embodiments may be practiced individually or in combination.

[0048] Hereinafter, aspects of some embodiments will be described with reference to the accompanying drawings.

[0049] Figure 1 is a plan view of a display device 100 according to some embodiments. Figure 2 yes Figure 1 For example, Figure 2 Shown Figure 1 components other than the data driver DD.

[0050] Reference Figure 1 and Figure 2Display device 100 is a device for displaying moving or still images. Display device 100 can be used as a display screen in portable electronic devices (such as mobile phones, smartphones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic organizers, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile personal computers (UMPCs)) as well as various products (such as televisions, notebook computers, monitors, billboards, and Internet of Things (IoT) devices). These are presented as examples only, and display device 100 can also be applied to other electronic devices.

[0051] The display device 100 may be a light-emitting display device, such as an organic light-emitting diode display device including an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, or an ultra-small light-emitting display device including ultra-small light-emitting diodes (such as micro- or nano-sized light-emitting diodes). However, the embodiments of the present disclosure are not limited thereto. For example, the display device 100 may also be a type of display device other than a light-emitting display device. An embodiment in which the display device 100 is a light-emitting display device (e.g., an organic light-emitting diode display device) will be disclosed in more detail below.

[0052] The display device 100 may include a display panel 110, and a gate driver GD, an emission driver ED, and a data driver DD that supply driving signals to the pixels PX of the display panel 110. Here, the pixels PX may be located in a display area DA of the display panel 110, the gate driver GD and the emission driver ED may be located in a non-display area NDA of the display panel 110, and the data driver DD may be connected to the non-display area NDA of the display panel 110 through a circuit board.

[0053] The display device 100 may further include a power supply unit and a timing controller. The power supply unit may supply power voltage to the pixels PX, the gate driver GD, the emission driver ED, and the data driver DD. The timing controller may control the operation of the first gate driver GD1, the second gate driver GD2, the first emission driver ED1, the second emission driver ED2, and the data driver DD.

[0054] The display panel 110 may have a rectangular shape in a plan view (eg, a view perpendicular or orthogonal to a display surface of the display panel 110). Figure 1 and Figure 2 The horizontal length of the display panel 110 is longer than the vertical length, but the shape of the display panel 110 is not limited thereto. For example, the display panel 110 may also have a shape in which the vertical length is longer than the horizontal length, or may have a square shape. The display panel 110 may include angled corners or rounded (rounded) corners.

[0055] The planar shape of the display panel 110 is not limited to the quadrilateral shape shown, and other shapes may also be applied. For example, the display panel 110 may have a polygonal shape other than a quadrilateral, a circular shape, an elliptical shape, an irregular shape, or other shapes in plan view.

[0056] The display panel 110 may be provided as a rigid panel that is substantially non-deformable, or may be provided as a flexible panel that can be folded, bent, or rolled in at least a portion without damaging the display panel 110. The display panel 110 may be provided in the display device 100 in an unbent state or in a partially bent state.

[0057] The display panel 110 may include a display area DA and a non-display area NDA.

[0058] A plurality of pixels PX may be located in the display area DA. The pixels PX may display an image. The pixels PX may be connected to a gate line GL, an emission control line EML, a data line DL, and a power line. The gate line GL and the emission control line EML may extend along a first direction DR1, and the data line DL may extend along a second direction DR2.

[0059] The non-display area NDA may be located around the display area DA (eg, in the periphery of the display area DA or outside the footprint of the display area DA). According to some embodiments, the non-display area NDA may surround the display area DA.

[0060] The display area DA may have various shapes according to various embodiments. For example, the display area DA may have a quadrilateral shape, a polygonal shape other than a quadrilateral shape, a circular shape, an elliptical shape, an irregular shape, or other shapes. According to some embodiments, the display area DA may have a shape that matches or matches the shape of the display panel 110.

[0061] like Figure 2 As shown in , the non-display area NDA may include a pad area PA where a plurality of pads PD are positioned. For example, the pad area PA may be located in the non-display area NDA (eg, lower non-display area) positioned below the display area DA. The pads PD may be arranged along a first direction DR1.

[0062] The gate driver GD and the emission driver ED may be located in the non-display area NDA. For example, the gate driver GD may include a first gate driver GD1 and a second gate driver GD2, and the emission driver ED may include a first emission driver ED1 and a second emission driver ED2. Here, the first gate driver GD1 and the first emission driver ED1 may be located in the non-display area NDA (e.g., the left non-display area) located to the left of the display area DA, and the second gate driver GD2 and the second emission driver ED2 may be located in the non-display area NDA (e.g., the right non-display area) located to the right of the display area DA.

[0063] The gate driver GD may drive the gate lines GL. For example, each of the first gate driver GD1 and the second gate driver GD2 may supply a gate signal to the gate lines GL. The gate lines GL may be connected to the first gate driver GD1 and the second gate driver GD2. For example, one side of each gate line GL may be electrically connected to the first gate driver GD1, and the other side of each gate line GL may be electrically connected to the second gate driver GD2.

[0064] The emission driver ED may drive the emission control lines EML. For example, each of the first emission driver ED1 and the second emission driver ED2 may supply an emission control signal to the emission control lines EML. The emission control lines EML may be connected to the first emission driver ED1 and the second emission driver ED2. For example, one side of each emission control line EML may be electrically connected to the first emission driver ED1, and the other side of each emission control line EML may be electrically connected to the second emission driver ED2.

[0065] like Figure 1 and Figure 2 As shown in FIG, the circuit boards CB1 to CB5 can be electrically connected to the display panel 110 via the pads PD. The circuit boards CB1 to CB5 may include a first circuit board CB1, a second circuit board CB2, a third circuit board CB3, a fourth circuit board CB4, and a fifth circuit board CB5. According to some embodiments, the first circuit board CB1 to the fifth circuit board CB5 may be connected to at least one of the timing controller and the power supply unit via another circuit board or a connector. According to some embodiments, each of the circuit boards CB1 to CB5 may be, but is not limited to, a printed circuit board (PCB) such as a flexible printed circuit board (FPCB) and a rigid printed circuit board, or a flexible film such as a chip on film (COF).

[0066] The gaps between adjacent circuit boards (e.g., in the first direction DR1) may be equal. For example, the gaps between the first circuit board CB1 and the second circuit board CB2, the gaps between the second circuit board CB2 and the third circuit board CB3, the gaps between the third circuit board CB3 and the fourth circuit board CB4, and the gaps between the fourth circuit board CB4 and the fifth circuit board CB5 may be equal.

[0067] Each of the circuit boards CB1 to CB5 may include a group of terminals (or group bumps). For example, the first circuit board CB1 may include a first group of terminals BP1, the second circuit board CB2 may include a second group of terminals BP2, the third circuit board CB3 may include a third group of terminals BP3, the fourth circuit board CB4 may include a fourth group of terminals BP4, and the fifth circuit board CB5 may include a fifth group of terminals BP5.

[0068] The first terminal group BP1 may include a plurality of first terminals (or bumps) C1, P1, and D1 positioned adjacent to each other in the first circuit board CB1. The second terminal group BP2 may include a plurality of second terminals P2 and D2 positioned adjacent to each other in the second circuit board CB2. The third terminal group BP3 may include a plurality of third terminals P3 and D3 positioned adjacent to each other in the third circuit board CB3. The fourth terminal group BP4 may include a plurality of fourth terminals P4 and D4 positioned adjacent to each other in the fourth circuit board CB4. The fifth terminal group BP5 may include a plurality of fifth terminals C2, P5, and D5 positioned adjacent to each other in the fifth circuit board CB5. Although five circuit boards CB1 to CB5 are disclosed in the current embodiment, the number of circuit boards is not limited thereto.

[0069] The data driver DD may include a plurality of drive circuits DDC1 to DDC5 (hereinafter referred to as data drive circuits) arranged along a first direction DR1. For example, the data driver DD may include a first data drive circuit DDC1 mounted on a first circuit board CB1, a second data drive circuit DDC2 mounted on a second circuit board CB2, a third data drive circuit DDC3 mounted on a third circuit board CB3, a fourth data drive circuit DDC4 mounted on a fourth circuit board CB4, and a fifth data drive circuit DDC5 mounted on a fifth circuit board CB5. Each of the data drive circuits DDC1 to DDC5 may include, for example, an integrated circuit.

[0070] Each of the data driving circuits DDC1 to DDC5 may be electrically connected to the pads PD of the display panel 110 through one of the circuit boards CB1 to CB5. For example, the first data driving circuit DDC1 may be electrically connected to the first pads C11, P11, and D11 of the display panel 110 through the first terminals C1, P1, and D1 of the first circuit board CB1, the second data driving circuit DDC2 may be electrically connected to the second pads P22 and D22 of the display panel 110 through the second terminals P2 and D2 of the second circuit board CB2, the third data driving circuit DDC3 may be electrically connected to the third pads P33 and D33 of the display panel 110 through the third terminals P3 and D3 of the third circuit board CB3, the fourth data driving circuit DDC4 may be electrically connected to the fourth pads P44 and D44 of the display panel 110 through the fourth terminals P4 and D4 of the fourth circuit board CB4, and the fifth data driving circuit DDC5 may be electrically connected to the fifth pads C22, P55, and D55 of the display panel 110 through the fifth terminals C2, P5, and D5 of the fifth circuit board CB5.

[0071] The data lines DL may be connected to the data driver DD. For example, the data lines DL may be divided and connected to the data driving circuits DDC1 to DDC5. According to some embodiments, the data lines DL may include a plurality of first data lines connected to the first data driving circuit DDC1, a plurality of second data lines connected to the second data driving circuit DDC2, a plurality of third data lines connected to the third data driving circuit DDC3, a plurality of fourth data lines connected to the fourth data driving circuit DDC4, and a plurality of fifth data lines connected to the fifth data driving circuit DDC5.

[0072] The first terminals C1, P1, and D1 (e.g., first group of terminals BP1) may include a plurality of first control terminals C1, a plurality of first power terminals P1, and a plurality of first data terminals D1 arranged along a first direction DR1 on a first circuit board CB1. The first control terminals C1 may be connected to a timing controller located on another circuit board (hereinafter referred to as an external circuit board). The first power terminals P1 may be connected to a power supply unit located on the external circuit board. The first data terminals D1 may be connected to a first data drive circuit DDC1.

[0073] The second terminals P2 and D2 (e.g., second group of terminals BP2) may include a plurality of second power terminals P2 and a plurality of second data terminals D2 arranged along a first direction DR1 in a second circuit board CB2. The second power terminals P2 may be connected to a power supply unit located on an external circuit board. The second data terminals D2 may be connected to a second data drive circuit DDC2.

[0074] The third terminals P3 and D3 (e.g., third group terminals BP3) may include a plurality of third power terminals P3 and a plurality of third data terminals D3 arranged along a first direction DR1 in a third circuit board CB3. The third power terminals P3 may be connected to a power supply unit located on an external circuit board. The third data terminals D3 may be connected to a third data drive circuit DDC3.

[0075] The fourth terminals P4 and D4 (e.g., fourth group terminals BP4) may include a plurality of fourth power terminals P4 and a plurality of fourth data terminals D4 arranged along a first direction DR1 in a fourth circuit board CB4. The fourth power terminals P4 may be connected to a power supply unit located on an external circuit board. The fourth data terminals D4 may be connected to a fourth data drive circuit DDC4.

[0076] The fifth terminals C2, P5, and D5 (e.g., the fifth group of terminals BP5) may include a plurality of second control terminals C2, a plurality of fifth power terminals P5, and a plurality of fifth data terminals D5 arranged along a first direction DR1 on a fifth circuit board CB5. The second control terminals C2 may be connected to a timing controller located on an external circuit board. The fifth power terminals P5 may be connected to a power supply unit located on an external circuit board. The fifth data terminals D5 may be connected to a fifth data drive circuit DDC5.

[0077] The first terminals C1, P1 and D1 of the above-mentioned first circuit board CB1, the second terminals P2 and D2 of the second circuit board CB2, the third terminals P3 and D3 of the third circuit board CB3, the fourth terminals P4 and D4 of the fourth circuit board CB4, and the fifth terminals C2, P5 and D5 of the fifth circuit board CB5 can be respectively connected to the first pads C11, P11 and D11, the second pads P22 and D22, the third pads P33 and D33, the fourth pads P44 and D44, and the fifth pads C22, P55 and D55.

[0078] The first terminals C1, P1, and D1 can be electrically connected to the first pads C11, P11, and D11 directly or via a connecting member (such as a conductive ball). The second terminals P2 and D2 can be electrically connected to the second pads P22 and D22 directly or via a connecting member (such as a conductive ball). The third terminals P3 and D3 can be electrically connected to the third pads P33 and D33 directly or via a connecting member (such as a conductive ball). The fourth terminals P4 and D4 can be electrically connected to the fourth pads P44 and D44 directly or via a connecting member (such as a conductive ball). The fifth terminals C2, P5, and D5 can be electrically connected to the fifth pads C22, P55, and D55 directly or via a connecting member (such as a conductive ball).

[0079] The first pads C11, P11, and D11 may include a plurality of first control pads C11, a plurality of first power pads P11, and a plurality of first data pads D11 arranged along a first direction DR1 in the pad area PA of the display panel 110. The first control pads C11 may be connected to the first control terminal C1, respectively. Furthermore, the first control pads C11 may be connected to the first gate driver GD1 and the first emission driver ED1. The first power pads P11 may be connected to the first power terminal P1, respectively. Furthermore, the first power pads P11 may be connected to the first gate driver GD1, the first emission driver ED1, and the pixels PX. The first data pads D11 may be connected to the first data terminals D1, respectively. Furthermore, the first data pads D11 may be connected to the first data lines, respectively.

[0080] The second pads P22 and D22 may include a plurality of second power pads P22 and a plurality of second data pads D22 arranged along the first direction DR1 in the pad area PA of the display panel 110. The second power pads P22 may be connected to the second power terminals P2, respectively. Furthermore, the second power pads P22 may be connected to the pixels PX, and the second data pads D22 may be connected to the second data terminals D2, respectively. Furthermore, the second data pads D22 may be connected to the second data lines, respectively.

[0081] The third pads P33 and D33 may include a plurality of third power pads P33 and a plurality of third data pads D33 arranged along the first direction DR1 in the pad area PA of the display panel 110. The third power pads P33 may be connected to the third power terminal P3, respectively. Furthermore, the third power pads P33 may be connected to the pixels PX, and the third data pads D33 may be connected to the third data terminal D3, respectively. Furthermore, the third data pads D33 may be connected to the third data lines, respectively.

[0082] The fourth pads P44 and D44 may include a plurality of fourth power pads P44 and a plurality of fourth data pads D44 arranged along the first direction DR1 in the pad area PA of the display panel 110. The fourth power pads P44 may be connected to the fourth power terminals P4, respectively. Furthermore, the fourth power pads P44 may be connected to the pixels PX. The fourth data pads D44 may be connected to the fourth data terminals D4, respectively. Furthermore, the fourth data pads D44 may be connected to the fourth data lines, respectively.

[0083] The fifth pads C22, P55, and D55 may include a plurality of second control pads C22, a plurality of fifth power pads P55, and a plurality of fifth data pads D55 arranged along the first direction DR1 in the pad area PA of the display panel 110. The second control pads C22 may be connected to the second control terminal C2, respectively. Furthermore, the second control pads C22 may be connected to the second gate driver GD2 and the second emission driver ED2. The fifth power pads P55 may be connected to the fifth power terminal P5, respectively. Furthermore, the fifth power pads P55 may be connected to the pixels PX. The fifth data pads D55 may be connected to the fifth data terminal D5, respectively. Furthermore, the fifth data pads D55 may be connected to the fifth data line, respectively.

[0084] The above-mentioned first control pad C11 and the first gate driver GD1 may be electrically connected to each other through corresponding fan-out lines FL, and the other first control pads C11 and the first emission driver ED1 may be electrically connected to each other through corresponding fan-out lines FL.

[0085] The above-mentioned second control pad C22 and second gate driver GD2 may be electrically connected to each other through corresponding fan-out lines FL, and other second control pads C22 and second emission drivers ED2 may be electrically connected to each other through corresponding fan-out lines FL.

[0086] The first to fifth data pads D11 , D22 , D33 , D44 , and D55 may be electrically connected to the first to fifth data lines through corresponding fan-out lines FL.

[0087] The gate timing control signal, emission timing control signal, gate clock signal, emission clock signal, gate start signal, emission start signal, high potential voltage, and low potential voltage from the timing controller can be supplied to the first gate driver GD1 and the first emission driver ED1 through the first control terminal C1 of the first circuit board CB1 and the first control pad C11 of the display panel 110. For example, the gate timing control signal, gate clock signal, gate start signal, high potential voltage, and low potential voltage can be supplied to the first gate driver GD1, and the emission timing control signal, emission clock signal, emission start signal, high potential voltage, and low potential voltage can be supplied to the first emission driver ED1. The power supply signal from the power supply unit can be supplied to the first gate driver GD1, the first emission driver ED1, and the pixel PX through the first power supply terminal P1 of the first circuit board CB1 and the first power supply pad P11 of the display panel 110. The power supply signal may include, for example, a driving voltage VD (see Figure 7 ), common voltage VS (see Figure 7 ), the first initialization voltage VI1 (see Figure 7 ), the second initialization voltage VI2 (see Figure 7 ) and bias voltage VB (see Figure 7The data signal from the first data driving circuit DDC1 may be supplied to the first data line through the first data terminal D1 of the first circuit board CB1 and the first data pad D11 of the display panel 110 , respectively.

[0088] The power signal from the power supply unit can be supplied to the pixel PX through the second power terminal P2 of the second circuit board CB2 and the second power pad P22 of the display panel 110. The data signal from the second data driving circuit DDC2 can be supplied to the second data line through the second data terminal D2 of the second circuit board CB2 and the second data pad D22 of the display panel 110, respectively.

[0089] A power signal from the power supply unit may be supplied to the pixel PX through the third power terminal P3 of the third circuit board CB3 and the third power pad P33 of the display panel 110. A data signal from the third data driving circuit DDC3 may be supplied to the third data line through the third data terminal D3 of the third circuit board CB3 and the third data pad D33 of the display panel 110, respectively.

[0090] A power signal from the power supply unit can be supplied to the pixel PX through the fourth power terminal P4 of the fourth circuit board CB4 and the fourth power pad P44 of the display panel 110. A data signal from the fourth data driving circuit DDC4 can be supplied to the fourth data line through the fourth data terminal D4 of the fourth circuit board CB4 and the fourth data pad D44 of the display panel 110, respectively.

[0091] The gate timing control signal, the emission timing control signal, the gate clock signal, the emission clock signal, the high potential voltage, and the low potential voltage from the timing controller may be supplied to the second gate driver GD2 and the second emission driver ED2 through the second control terminal C2 of the fifth circuit board CB5 and the second control pad C22 of the display panel 110. For example, the gate timing control signal, the gate clock signal, the high potential voltage, and the low potential voltage may be supplied to the second gate driver GD2, and the emission timing control signal, the emission clock signal, the high potential voltage, and the low potential voltage may be supplied to the second emission driver ED2.

[0092] The power signal from the power supply unit can be supplied to the second gate driver GD2, the second emission driver ED2, and the pixel PX via the fifth power terminal P5 of the fifth circuit board CB5 and the fifth power pad P55 of the display panel 110. The data signal from the fifth data drive circuit DDC5 can be supplied to the fifth data line via the fifth data terminal D5 of the fifth circuit board CB5 and the fifth data pad D55 of the display panel 110. The high potential voltage can be greater than the driving voltage, and the low potential voltage can be less than the common voltage.

[0093] like Figure 1 As shown in , the width W1 of the first group of terminals BP1 including the first terminals C1, P1, and D1 (hereinafter referred to as the first group terminal width W1) can be defined as a dimension in the arrangement direction (e.g., the first direction DR1) of the first terminals C1, P1, and D1. For example, the first group terminal width W1 can be defined as the distance between an outer side (hereinafter referred to as the first outer side) of a first terminal (e.g., the outermost first control terminal C1 among the first control terminals C1) located at one edge of the first circuit board CB1 and an outer side (hereinafter referred to as the second outer side) of a first terminal (e.g., the outermost first power terminal P1 among the first power terminals P1) located at another edge of the first terminals C1, P1, and D1 of the first circuit board CB1. Here, the first outer side may be positioned close to a first side of the first circuit board CB1 that intersects a side (e.g., a lower side) of the display panel 110, and the second outer side may be positioned or arranged close to a second side of the first circuit board CB1 that intersects a side (e.g., a lower side) of the display panel 110. That is, the second side may face the first side.

[0094] Similarly, the width W2 of the second group of terminals BP2, including the second terminals P2 and D2 (hereinafter referred to as the second group terminal width W2), can be defined as the dimension in the arrangement direction of the second terminals P2 and D2 (e.g., the first direction DR1). The width W3 of the third group of terminals BP3, including the third terminals P3 and D3 (hereinafter referred to as the third group terminal width W3), can be defined as the dimension in the arrangement direction of the third terminals P3 and D3 (e.g., the first direction DR1). The width W4 of the fourth group of terminals BP4, including the fourth terminals P4 and D4 (hereinafter referred to as the fourth group terminal width W4), can be defined as the dimension in the arrangement direction of the fourth terminals P4 and D4 (e.g., the first direction DR1). The width W5 of the fifth group of terminals BP5, including the fifth terminals C2, P5, and D5 (hereinafter referred to as the fifth group terminal width W5), can be defined as the dimension in the arrangement direction of the fifth terminals C2, P5, and D5 (e.g., the first direction DR1).

[0095] According to some embodiments, at least two circuit boards may have different group terminal widths. For example, a circuit board other than the outermost circuit board among the circuit boards may have a group terminal width smaller than that of the outermost circuit board. Here, the outermost circuit boards may be defined as a first outermost circuit board and a second outermost circuit board, respectively, and the circuit board (or multiple circuit boards) between the first outermost circuit board and the second outermost circuit board may be defined as an intermediate circuit board. In this case, the group terminal width of the intermediate circuit board may be smaller than the group terminal width of the first outermost circuit board (or the second outermost circuit board). According to some embodiments, the first outermost circuit board may be the first circuit board CB1, the second outermost circuit board may be the fifth circuit board CB5, and the intermediate circuit board may be at least one of the second circuit board CB2 to the fourth circuit board CB4. For example, as Figure 1 As shown in FIG, the second terminal group width W2 of the second circuit board CB2 may be smaller than the first terminal group width W1 of the first circuit board CB1.

[0096] According to some embodiments, the width of the first and second outermost circuit board terminals may be equal. For example, the first terminal group width W1 of the first circuit board CB1 and the fifth terminal group width W5 of the fifth circuit board CB5 may be equal.

[0097] According to some embodiments, the terminal group widths of the intermediate circuit boards may be equal. For example, the second terminal group width W2 of the second circuit board CB2, the third terminal group width W3 of the third circuit board CB3, and the fourth terminal group width W4 of the fourth circuit board CB4 may be equal to each other.

[0098] like Figure 2 As shown in , the width W11 of the first group of pads PD1 including the first pads C11, P11, and D11 (hereinafter referred to as the first group pad width W11) can be defined as a dimension in the arrangement direction of the first pads C11, P11, and D11 (e.g., the first direction DR1). For example, the first group pad width W11 can be defined as the distance between the outer side (hereinafter referred to as the left side) of a first pad located at one edge among the first pads C11, P11, and D11 (e.g., the outermost first control pad C11 among the first control pads C11) and the outer side (hereinafter referred to as the right side) of a first pad located at the other edge among the first pads C11, P11, and D11 (e.g., the outermost first power pad P11 among the first power pads P11). Here, the left side can be positioned close to the first side of the first circuit board CB1 that intersects the side (e.g., the lower side) of the display panel 110, and the right side can be positioned close to the second side of the first circuit board CB1 that intersects the side (e.g., the lower side) of the display panel 110.

[0099] Similarly, the width W22 of the second group of pads PD2 including the second pads P22 and D22 (hereinafter, referred to as the second group pad width W22) can be defined as the dimension in the arrangement direction of the second pads P22 and D22 (e.g., the first direction DR1). The width W33 of the third group of pads PD3 including the third pads P33 and D33 (hereinafter, referred to as the third group pad width W33) can be defined as the dimension in the arrangement direction of the third pads P33 and D33 (e.g., the first direction DR1). The width W44 of the fourth group of pads PD4 including the fourth pads P44 and D44 (hereinafter, referred to as the fourth group pad width W44) can be defined as the dimension in the arrangement direction of the fourth pads P44 and D44 (e.g., the first direction DR1). A width W55 of the fifth group pad PD5 including the fifth pads C22 , P55 , and D55 (hereinafter, referred to as a fifth group pad width W55 ) may be defined as a dimension in an arrangement direction (eg, first direction DR1 ) of the fifth pads C22 , P55 , and D55 .

[0100] According to some embodiments, at least two group pads may have different group pad widths. For example, group pads other than the outermost group pad among the group pads may have a group pad width smaller than that of the outermost group pad. Here, the outermost group pads may be defined as the first outermost group pad and the second outermost group pad, respectively, and the group pad between the first outermost group pad and the second outermost group pad may be defined as the middle group pad. In this case, the group pad width of the middle group pad may be smaller than the group pad width of the first outermost group pad (or the second outermost group pad). According to some embodiments, the first outermost group pad may be the first group pad PD1, the second outermost group pad may be the fifth group pad PD5, and the middle group pad may be at least one of the second group pad PD2 to the fourth group pad PD4. For example, as Figure 2 As shown in FIG, the second pad group width W22 of the second group of pads PD2 may be smaller than the first pad group width W11 of the first group of pads PD1.

[0101] According to some embodiments, the pad widths of the first and second outermost groups of pads may be equal. For example, the first pad width W11 of the first group of pads PD1 and the fifth pad width W55 of the fifth group of pads PD5 may be equal.

[0102] According to some embodiments, the widths of the middle pad groups may be equal. For example, the second pad group width W22 of the second pad group PD2, the third pad group width W33 of the third pad group PD3, and the fourth pad group width W44 of the fourth pad group PD4 may be equal to each other.

[0103] According to some embodiments, corresponding groups of terminals and pads may have the same width. For example, the first group of terminals BP1 of the first circuit board CB1 and the first group of pads PD1 stacked by the first circuit board CB1 may have the same width. In other words, the first group of terminal widths W1 and the first group of pad widths W11 may be equal. Similarly, the second group of terminal widths W2 may be equal to the second group of pad widths W22, the third group of terminal widths W3 may be equal to the third group of pad widths W33, the fourth group of terminal widths W4 may be equal to the fourth group of pad widths W44, and the fifth group of terminal widths W5 may be equal to the fifth group of pad widths W55.

[0104] According to some embodiments, corresponding group terminals and group pads may have different widths. For example, the first group terminals BP1 of the first circuit board CB1 and the first group pads PD1 stacked by the first circuit board CB1 may have different widths. According to some embodiments, the first group terminal width W1 may be greater than the first group pad width W11. Similarly, the second group terminal width W2 may be greater than the second group pad width W22, the third group terminal width W3 may be greater than the third group pad width W33, the fourth group terminal width W4 may be greater than the fourth group pad width W44, and the fifth group terminal width W5 may be greater than the fifth group pad width W55. In other words, when the group terminal width and the group pad width correspond to each other, the group terminal width may be greater than the group pad width.

[0105] At least one alignment mark (also referred to as an "alignment key") may be located in the non-display area NDA. For example, a first alignment mark AK1, a second alignment mark AK2, a third alignment mark AK3, and a fourth alignment mark AK4 may be located in the non-display area NDA. For example, the first alignment mark AK1 may be located between the first and second circuit boards CB1 and CB2, which are adjacent to each other in the first direction DR1, in the non-display area NDA. The second alignment mark AK2 may be located between the second and third circuit boards CB2 and CB3, which are adjacent to each other in the first direction DR1, in the non-display area NDA. The third alignment mark AK3 may be located between the third and fourth circuit boards CB3 and CB4, which are adjacent to each other in the first direction DR1, in the non-display area NDA. The fourth alignment mark AK4 may be located between the fourth and fifth circuit boards CB4 and CB5, which are adjacent to each other in the first direction DR1, in the non-display area NDA. The first to fourth alignment marks AK1 to AK4 may be marks used for aligning the circuit boards CB1 to CB5 with the display panel 110. The circuit boards CB1 to CB5 may be aligned with the display panel 110 using the first to fourth alignment marks AK1 to AK4. In addition, whether the circuit boards CB1 to CB5 and the display panel 110 are accurately aligned with each other can be checked by the first to fourth alignment marks AK1 to AK4. Each of the first to fourth alignment marks AK1 to AK4 may have, for example, a cross shape.

[0106] Figure 3 yes Figure 1 An enlarged view of portion A1.

[0107] like Figure 3 As shown in FIG, the first circuit board CB1 and the second circuit board CB2 having different group terminal widths may be aligned based on the first alignment mark AK1.

[0108] Among the sides of the first circuit board CB1, sides that are positioned opposite to each other in the first direction DR1 and intersect (or overlap) with the side SS110 (e.g., the lower side) of the display panel 110 may be defined as a first side SS1 and a second side SS2 of the first circuit board CB1, respectively. In this case, the second side SS2 of the first circuit board CB1 may be positioned close to the first alignment mark AK1.

[0109] Among the sides of the second circuit board CB2, sides that are positioned opposite to each other in the first direction DR1 and intersect (or overlap) with the side SS110 (e.g., the lower side) of the display panel 110 may be respectively defined as a third side SS3 and a fourth side SS4 of the second circuit board CB2. In this case, the third side SS3 of the second circuit board CB2 may be positioned close to the first alignment mark AK1.

[0110] The facing sides (e.g., sides facing each other in the first direction DR1) of the first and second circuit boards CB1 and CB2, which have different terminal group widths and are positioned adjacent to each other, can be spaced the same distance from the first alignment mark AK1 in the first direction DR1. This same distance refers to the distance between each side and the center of the first alignment mark AK1 in the first direction DR1. In other words, the sides of the circuit boards positioned adjacent to (or facing) each other, with the first alignment mark AK1 positioned therebetween, can be spaced the same distance from the first alignment mark AK1. For example, the distance ds1 between the first alignment mark AK1 and the second side SS2 of the first circuit board CB1 can be equal to the distance ds2 between the first alignment mark AK1 and the third side SS3 of the second circuit board CB2. In other words, when an imaginary line passing through the center of the first alignment mark AK1 and extending parallel to the second side SS2 is defined as the alignment line LL1, the distance ds1 between the alignment line LL1 and the second side SS2 (e.g., the distance in the first direction DR1) can be equal to the distance ds2 between the alignment line LL1 and the third side SS3 (e.g., the distance in the first direction DR1).

[0111] In a first circuit board CB1 and a second circuit board CB2 having different terminal group widths and positioned adjacent to each other, the distance ds3 between one of the facing sides of the outermost terminal of the first circuit board CB1 near the first alignment mark AK1 and the outermost terminal of the second circuit board CB2 near the first alignment mark AK1 and the first alignment mark AK1 may be different from the distance ds4 between the other of the facing sides and the first alignment mark AK1. For example, among the first terminals C1, P1, and D1 of the first circuit board CB1, the terminal located at the outermost position of the first circuit board CB1 so as to be close to the first alignment mark AK1 may be defined as the first outermost terminal of the first circuit board CB1. Furthermore, among the second terminals P2 and D2 of the second circuit board CB2 having a different terminal group width than the first circuit board CB1, the terminal located at the outermost position of the second circuit board CB2 so as to be close to the first alignment mark AK1 may be defined as the second outermost terminal of the second circuit board CB2. In this case, the first and second outermost terminals may be located at different distances from the first alignment mark AK1. For example, the distance ds3 between the first alignment mark AK1 and the first outermost terminal of the first circuit board CB1 can be different from the distance ds4 between the first alignment mark AK1 and the second outermost terminal of the second circuit board CB2. In other words, the distance ds3 between the alignment line LL1 and the first outermost terminal (or the outer side SS22 of the first outermost terminal) (e.g., the distance in the first direction DR1) can be different from the distance ds4 between the alignment line LL1 and the second outermost terminal (or the outer side SS33 of the second outermost terminal) (e.g., the distance in the first direction DR1). For example, the distance ds3 between the first outermost terminal of the first circuit board CB1, which has a relatively large terminal group width, and the first alignment mark AK1 can be greater than the distance ds4 between the second outermost terminal of the second circuit board CB2, which has a relatively small terminal group width, and the first alignment mark AK1.

[0112] Likewise, facing sides (eg, sides facing each other in the first direction DR1 ) of the fourth and fifth circuit boards CB4 and CB5 having different group terminal widths and positioned adjacent to each other may be the same distance in the first direction DR1 from the fourth alignment mark AK4 therebetween.

[0113] Likewise, a distance between the fourth alignment mark AK4 and an outermost terminal of the fifth circuit board CB5 close to the fourth alignment mark AK4 may be greater than a distance between the fourth alignment mark AK4 and an outermost terminal of the fourth circuit board CB4 close to the fourth alignment mark AK4.

[0114] The above-mentioned first group terminal width W1 of the first circuit board CB1 can be defined as the distance between the outer side SS11 of the first terminal (for example, the first control terminal C1) located at the outermost position on one side of the first circuit board CB1 and the outer side SS22 of the first terminal (for example, the first power terminal P1) located at the outermost position on the other side of the first circuit board CB1.

[0115] Similarly, the above-mentioned second group terminal width W2 of the second circuit board CB2 can be defined as the distance between the outer side SS33 of the second terminal (e.g., the second power terminal P2) located at the outermost position on one side of the second circuit board CB2 and the outer side SS44 of the second terminal (e.g., the second power terminal P2) located at the outermost position on the other side of the second circuit board CB2.

[0116] At least two of the circuit boards CB1 to CB5 may have different widths. For example, the circuit board with a relatively large group of terminal widths may have a larger width. In other words, the width of the outermost circuit board may be greater than the width of the middle circuit board. For example, the width W10 of the first circuit board CB1 may be greater than the width W20 of the second circuit board CB2. Here, the width of the circuit board may be the dimension in the first direction DR1. For example, Figure 3 As shown in FIG, the width W10 of the first circuit board CB1 may be the distance between the first side SS1 of the first circuit board CB1 and the second side SS2 of the first circuit board CB1, and the width W20 of the second circuit board CB2 may be the distance between the third side SS3 of the second circuit board CB2 and the fourth side SS4 of the second circuit board CB2. Similarly, the width W50 of the fifth circuit board CB5 may be greater than the width W40 of the fourth circuit board CB4.

[0117] At least two of the intermediate circuit boards may have the same width. For example, the width W20 of the second circuit board CB2, the width W30 of the third circuit board CB3, and the width W40 of the fourth circuit board CB4 may be the same.

[0118] Regardless of the width of the circuit board, the widths of the data driving circuits DDC1 to DDC5 may be the same. For example, the widths of the first data driving circuit DDC1, the second data driving circuit DDC2, the third data driving circuit DDC3, the fourth data driving circuit DDC4, and the fifth data driving circuit DDC5 may be equal to each other. Here, the width of the data driving circuit may be a dimension in the first direction DR1.

[0119] Figure 4 yes Figure 1 An enlarged view of portion A2 of FIG.

[0120] like Figure 4As shown in FIG, the third circuit board CB3 and the fourth circuit board CB4 having the same group terminal width can be aligned based on the third alignment mark AK3.

[0121] Among the sides of the third circuit board CB3, sides that are positioned opposite to each other in the first direction DR1 and intersect (or overlap) with the side SS110 (e.g., the lower side) of the display panel 110 may be defined as a first side SS5 and a second side SS6 of the third circuit board CB3, respectively. In this case, the second side SS6 of the third circuit board CB3 may be positioned close to the third alignment mark AK3.

[0122] Among the sides of the fourth circuit board CB4, sides that are arranged opposite to each other in the first direction DR1 and intersect (or overlap) with the side SS110 (e.g., the lower side) of the display panel 110 may be respectively defined as a third side SS7 and a fourth side SS8 of the fourth circuit board CB4. In this case, the third side SS7 of the fourth circuit board CB4 may be positioned close to the third alignment mark AK3.

[0123] The facing sides (e.g., sides facing each other in the first direction DR1) of the third and fourth circuit boards CB3 and CB4, which have the same terminal group width and are positioned adjacent to each other, can be located at the same distance from the third alignment mark AK3. In other words, the sides of the circuit boards that are adjacent to (or facing each other) and between which the third alignment mark AK3 is positioned can be located at the same distance from the third alignment mark AK3. For example, the distance ds5 between the third alignment mark AK3 and the second side SS6 of the third circuit board CB3 can be equal to the distance ds6 between the third alignment mark AK3 and the third side SS7 of the fourth circuit board CB4. In other words, when an imaginary line passing through the center of the third alignment mark AK3 and extending parallel to the second side SS6 is defined as the alignment line LL11, the distance ds5 between the alignment line LL11 and the second side SS6 (e.g., the distance in the first direction DR1) can be equal to the distance ds6 between the alignment line LL11 and the third side SS7 (e.g., the distance in the first direction DR1). The aforementioned distances ds1, ds2, ds5, and ds6 can all be the same or different.

[0124] In addition, among the third terminals P3 and D3 of the third circuit board CB3, the terminal located at the outermost position of the third circuit board CB3 and close to the third alignment mark AK3 can be defined as the first outermost terminal of the third circuit board CB3. Among the fourth terminals P4 and D4 of the fourth circuit board CB4 having the same group terminal width as the third circuit board CB3, the terminal located at the outermost position of the fourth circuit board CB4 and close to the third alignment mark AK3 can be defined as the second outermost terminal of the fourth circuit board CB4. In this case, the first outermost terminal and the second outermost terminal can be arranged at the same distance from the third alignment mark AK3. For example, the distance ds7 between the third alignment mark AK3 and the first outermost terminal of the third circuit board CB3 can be equal to the distance ds8 between the third alignment mark AK3 and the second outermost terminal of the fourth circuit board CB4. In other words, the distance ds7 (e.g., the distance in the first direction DR1) between the alignment line LL11 and the first outermost terminal (or the outer side SS66 of the first outermost terminal) can be equal to the distance ds8 (e.g., the distance in the first direction DR1) between the alignment line LL11 and the second outermost terminal (or the outer side SS77 of the second outermost terminal). For example, the distance ds7 between the first outermost terminal of the third circuit board CB3 and the third alignment mark AK3 can be equal to the distance ds8 between the second outermost terminal of the fourth circuit board CB4 and the third alignment mark AK3.

[0125] Likewise, facing sides (eg, sides facing each other in the first direction DR1 ) of the second and third circuit boards CB2 and CB3 having the same group terminal width and positioned adjacent to each other may be at the same distance from the second alignment mark AK2 therebetween.

[0126] Likewise, the distance between the second alignment mark AK2 and the outermost terminal of the second circuit board CB2 adjacent to the second alignment mark AK2 may be equal to the distance between the second alignment mark AK2 and the outermost terminal of the third circuit board CB3 adjacent to the second alignment mark AK2 .

[0127] The above-mentioned third group terminal width W3 of the third circuit board CB3 can be defined as the distance between the outer side SS55 of the third terminal located at the outermost position on one side of the third circuit board CB3 (for example, the third power terminal P3 at the left end) and the outer side SS66 of the third terminal located at the outermost position on the other side of the third circuit board CB3 (for example, the third power terminal P3 at the right end).

[0128] Similarly, the above-mentioned fourth group terminal width W4 of the fourth circuit board CB4 can be defined as the distance between the outer side SS77 of the fourth terminal located at the outermost position on one side of the fourth circuit board CB4 (for example, the fourth power terminal P4 at the left end) and the outer side SS88 of the fourth terminal located at the outermost position on the other side of the fourth circuit board CB4 (for example, the fourth power terminal P4 at the right end).

[0129] At least two of the circuit boards may have the same width. For example, circuit boards with the same group terminal width may have the same width. For example, the width of the first circuit board CB1 and the width of the fifth circuit board CB5 may be equal to each other. In addition, the width of the second circuit board CB2, the width of the third circuit board CB3, and the width of the fourth circuit board CB4 may be equal to each other. Here, the width of the circuit board may be the dimension in the first direction DR1. As in Figure 4 In the example shown in , the distance between the first side SS5 of the third circuit board CB3 and the second side SS6 of the third circuit board CB3 may be equal to the distance between the third side SS7 of the fourth circuit board CB4 and the fourth side SS8 of the fourth circuit board CB4.

[0130] A circuit board with a relatively large terminal width may have a larger width. For example, the width of the first circuit board CB1 may be greater than the width of the second circuit board CB2. Here, the width of the circuit board may be the dimension in the first direction DR1. For example, as in Figure 3 In the example shown in , the width of the first circuit board CB1 can be the distance between the first side SS1 of the first circuit board CB1 and the second side SS2 of the first circuit board CB1, and the width of the second circuit board CB2 can be the distance between the third side SS3 of the second circuit board CB2 and the fourth side SS4 of the second circuit board CB2.

[0131] According to some embodiments, the width of the group terminals of the middle circuit board (e.g., the second circuit board CB2) (e.g., the second group terminal width W2) is smaller than the width of the group terminals of the outermost circuit board (e.g., the first circuit board CB1) (e.g., the first group terminal width W1). Therefore, the distance between the group terminals of adjacent circuit boards (e.g., Figure 3 The sum of ds3 and ds4 in ) can be increased, and the distance between the group pads corresponding to the group terminals is correspondingly increased (for example, Figure 2 (The distance between the first pad P11 at the right edge and the second pad P22 at the left edge of the circuit board CB1 is increased). Therefore, the distance between the group pads PD1 to PD5 can be increased, thereby ensuring a sufficient margin area for placing the first to fourth alignment marks AK1 to AK4. Therefore, the alignment between the circuit boards CB1 to CB5 can be easily checked, and thus, misalignment between the circuit boards CB1 to CB5 can be minimized.

[0132] Figure 5 yes Figure 2 An enlarged view of portion A3.

[0133] The outermost group pad and the middle group pad adjacent to the outermost group pad may have different distances from the alignment mark therebetween in the first direction DR1. Figure 5 As shown in FIG, a distance ds10 between an alignment line LL1 passing through the center of the first alignment mark AK1 and the second group pad PD2 in the first direction DR1 can be smaller than a distance ds9 between the alignment line LL1 and the first group pad PD1 in the first direction DR1. For example, the first power pad P11 of the first group pad PD1 and the second power pad P22 of the second group pad PD2 face each other, with the first alignment mark AK1 positioned between the first power pad P11 and the second power pad P22. Therefore, a distance ds10 between the alignment line LL1 of the first alignment mark AK1 and the outer side SS20 of the second power pad P22 in the first direction DR1 can be smaller than a distance ds9 between the alignment line LL1 and the outer side SS10 of the first power pad P11 in the first direction DR1. Here, the outer side SS10 of the first power pad P11 and the outer side SS20 of the second power pad P22 can face each other in the first direction DR1, with the first alignment mark AK1 positioned between the outer side SS10 of the first power pad P11 and the outer side SS20 of the second power pad P22.

[0134] Likewise, a distance between an alignment line passing through the center of the fourth alignment mark AK4 and the fourth group pad PD4 in the first direction DR1 may be smaller than a distance between an alignment line passing through the center of the fourth alignment mark AK4 and the fifth group pad PD5 in the first direction DR1.

[0135] Figure 6 yes Figure 2 An enlarged view of part A4.

[0136] The middle group pads may be spaced the same distance from the alignment mark between them in the first direction DR1. Figure 6As shown in FIG, a distance ds11 in the first direction DR1 between an alignment line LL11 passing through the center of the third alignment mark AK3 and the third group pad PD3 can be equal to a distance ds12 in the first direction DR1 between the alignment line LL11 and the fourth group pad PD4. For example, the third power pad P33 of the third group pad PD3 and the fourth power pad P44 of the fourth group pad PD4 can face each other, with the third alignment mark AK3 positioned between the third power pad P33 and the fourth power pad P44. Therefore, a distance ds11 in the first direction DR1 between the alignment line LL11 of the third alignment mark AK3 and the outer side SS15 of the third power pad P33 can be equal to a distance ds12 in the first direction DR1 between the alignment line LL11 and the outer side SS25 of the fourth power pad P44. Here, outer sides SS15 and SS25 of the third and fourth power pads P33 and P44 may face each other in the first direction DR1 with the third align mark AK3 interposed therebetween.

[0137] Likewise, a distance between an alignment line passing through the center of the second alignment mark AK2 and the second group pad PD2 in the first direction DR1 may be equal to a distance between an alignment line passing through the center of the second alignment mark AK2 and the third group pad PD3 in the first direction DR1.

[0138] Figure 7 is a circuit diagram of a pixel PX of the display device 100 according to some embodiments. For example, Figure 7 Can be Figure 1 The circuit diagram of the pixel PX. Figure 7 Various components in a pixel PX according to some embodiments are shown, but as will be understood by those skilled in the art, embodiments according to the present disclosure are not limited thereto, and according to various embodiments, the pixel PX may include additional components or fewer components without departing from the spirit and scope of the embodiments according to the present disclosure.

[0139] like Figure 7 As shown in the figure, the pixel PX can be connected to the first gate line GWL, the second gate line GCL, the third gate line GIL, the fourth gate line EBL, the emission control line EML, the data line DL, the driving voltage line VDL, the common voltage line VSL, the first initialization voltage line VIL1, the second initialization voltage line VIL2 and the bias voltage line VBL.

[0140] The pixel PX may include a pixel circuit PC and a light emitting element LEL. The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 and a capacitor Cst.

[0141] The first transistor T1 may include a gate electrode, a source electrode, and a drain electrode. The first transistor T1 may control a source-drain current (hereinafter, referred to as a driving current) according to a data voltage applied to the gate electrode. The driving current (e.g., Isd) flowing through the channel region of the first transistor T1 may be proportional to the square of the difference between the voltage (Vgs) between the source and gate electrodes of the first transistor T1 and the threshold voltage (Vth) (Isd=k×(Vgs-Vth)). 2 ), where k is a proportionality coefficient determined by the structure and physical characteristics of the first transistor T1, Vgs is the source-gate voltage of the first transistor T1, and Vth is the threshold voltage of the first transistor T1.

[0142] The light emitting element LEL may emit light in response to the received driving current (Isd). The amount of light emitted from the light emitting element LEL or the brightness of the light emitting element LEL may be proportional to the magnitude of the driving current (Isd).

[0143] The light-emitting element LEL may be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer positioned between the first and second electrodes. In another example, the light-emitting element LEL may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor positioned between the first and second electrodes. In another example, the light-emitting element LEL may be a quantum dot light-emitting element including a first electrode, a second electrode, and a quantum dot light-emitting layer positioned between the first and second electrodes. In another example, the light-emitting element LEL may be a micro light-emitting diode.

[0144] A first electrode of the light-emitting element LEL may be electrically connected to a fourth node N4. The first electrode of the light-emitting element LEL may be connected to a drain electrode of the sixth transistor T6 and a source electrode of the seventh transistor T7 through the fourth node N4. A second electrode of the light-emitting element LEL may be connected to a common voltage line VSL. The second electrode of the light-emitting element LEL may receive a common voltage VS (e.g., a low potential voltage) from the common voltage line VSL.

[0145] The second transistor T2 can be turned on by the first gate signal GW of the first gate line GWL to electrically connect the data line DL and the first node N1, which is the source electrode of the first transistor T1. The second transistor T2 turned on by the first gate signal GW can supply a data voltage to the first node N1. The second transistor T2 can have a gate electrode electrically connected to the first gate line GWL, a source electrode electrically connected to the data line DL, and a drain electrode electrically connected to the first node N1.

[0146] The third transistor T3 can be turned on by the second gate signal GC of the second gate line GCL to electrically connect the second node N2, which serves as the drain electrode of the first transistor T1, and the third node N3, which serves as the gate electrode of the first transistor T1. The third transistor T3 can be connected between the third node N3 and the second node N2. For example, the third transistor T3 can have a gate electrode electrically connected to the second gate line GCL, a source electrode electrically connected to the third node N3, and a drain electrode electrically connected to the second node N2. The third transistor T3 can be turned on by the second gate signal GC of the second gate line GCL to electrically connect the second node N2, which serves as the drain electrode of the first transistor T1, and the third node N3, which serves as the gate electrode of the first transistor T1. The third transistor T3 can be a dual-gate transistor having two gate electrodes (e.g., a gate electrode and a counter-gate electrode). The gate electrode and the counter-gate electrode can be located on different layers so as to face each other.

[0147] The fourth transistor T4 can be turned on by the third gate signal GI of the third gate line GIL to electrically connect the third node N3, which serves as the gate electrode of the first transistor T1, to the first initialization voltage line VIL1. The fourth transistor T4 can be connected in series between the third node N3 and the first initialization voltage line VIL1. For example, the fourth transistor T4 can have a gate electrode electrically connected to the third gate line GIL, a source electrode electrically connected to the third node N3, and a drain electrode electrically connected to the first initialization voltage line VIL1. The fourth transistor T4 can be a dual-gate transistor. The first initialization voltage line VIL1 can transmit the first initialization voltage VI1.

[0148] The fifth transistor T5 can be turned on by the emission control signal EM of the emission control line EML to electrically connect the driving voltage line VDL and the first node N1 serving as the source electrode of the first transistor T1. The fifth transistor T5 may have a gate electrode electrically connected to the emission control line EML, a source electrode electrically connected to the driving voltage line VDL, and a drain electrode electrically connected to the first node N1.

[0149] The sixth transistor T6 can be turned on by the emission control signal EM of the emission control line EML to electrically connect the second node N2, which is the drain electrode of the first transistor T1, and the fourth node N4, which is the first electrode of the light emitting element LEL. The sixth transistor T6 can have a gate electrode electrically connected to the emission control line EML, a source electrode electrically connected to the second node N2, and a drain electrode electrically connected to the fourth node N4.

[0150] When the fifth transistor T5 , the first transistor T1 , and the sixth transistor T6 are all turned on, a driving current may be supplied to the light emitting element LEL.

[0151] The seventh transistor T7 can be turned on by a fourth gate signal EB of the fourth gate line EBL to electrically connect the fourth node N4, which serves as the first electrode of the light-emitting element LEL, to the second initialization voltage line VIL2. The seventh transistor T7, turned on by the fourth gate signal EB, can discharge the first electrode of the light-emitting element LEL to the second initialization voltage VI2. The seventh transistor T7 can have a gate electrode electrically connected to the fourth gate line EBL, a source electrode electrically connected to the fourth node N4, and a drain electrode electrically connected to the second initialization voltage line VIL2. The second initialization voltage line VIL2 can transmit the second initialization voltage VI2.

[0152] The eighth transistor T8 can be turned on by a fourth gate signal EB of the fourth gate line EBL to electrically connect the bias voltage line VBL to the first node N1, which serves as the source electrode of the first transistor T1. The eighth transistor T8, turned on by the fourth gate signal EB, can supply the bias voltage VB to the first node N1. The eighth transistor T8 can improve the hysteresis of the first transistor T1 by supplying the bias voltage VB to the source electrode of the first transistor T1. The eighth transistor T8 can have a gate electrode electrically connected to the fourth gate line EBL, a source electrode electrically connected to the bias voltage line VBL, and a drain electrode electrically connected to the first node N1.

[0153] Each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may include a silicon-based active layer. For example, each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be a p-type transistor including an active layer made of low-temperature polycrystalline silicon (LTPS). An active layer made of low-temperature polycrystalline silicon can have high electron mobility and excellent conduction characteristics. Therefore, the display device 100 including transistors with excellent conduction characteristics can stably and efficiently drive the pixel PX. Each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can output current flowing into the source electrode to the drain electrode based on the gate low voltage applied to the gate electrode.

[0154] Each of the third transistor T3 and the fourth transistor T4 may be an n-type transistor including an oxide-based active layer. The transistor including the oxide-based active layer may have a coplanar structure in which the gate electrode is located at the top. The transistor including the oxide-based active layer may output current flowing into the drain electrode to the source electrode based on a gate high voltage applied to the gate electrode.

[0155] The capacitor Cst may be electrically connected between the third node N3, which is the gate electrode of the first transistor T1, and the driving voltage line VDL. For example, a first electrode of the capacitor Cst may be electrically connected to the third node N3, and a second electrode of the capacitor Cst may be electrically connected to the driving voltage line VDL. Thus, a potential difference between the driving voltage line VDL and the gate electrode of the first transistor T1 may be maintained.

[0156] Figure 8 is a cross-sectional view of a display device 100 according to some embodiments.

[0157] like Figure 8 As shown in FIG, the display device 100 may include a substrate SUB, a barrier layer BR, a thin film transistor layer TFTL, a light emitting element layer EMTL, and an encapsulation layer ENC. The barrier layer BR, the thin film transistor layer TFTL, the light emitting element layer EMTL, and the encapsulation layer ENC may be sequentially positioned on the substrate SUB along a third direction DR3.

[0158] The substrate SUB may be a rigid substrate or a flexible substrate that can be bent, folded, or rolled. The substrate SUB may be made of an insulating material such as glass, quartz, or a polymer resin. The polymer material may be, for example, polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl compound, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or a combination thereof. Alternatively, the substrate SUB may include a metal material.

[0159] like Figure 8 As shown in FIG, a barrier layer BR may be located on a substrate SUB. The barrier layer BR may be disposed on the entire surface of the substrate SUB. The barrier layer BR may be a layer for protecting the transistors T1 to T8 of the thin film transistor layer TFTL and the light emitting layer EL of the light emitting element layer EMTL from moisture introduced through the substrate SUB, which is susceptible to moisture penetration.

[0160] The barrier layer BR may be composed of a plurality of inorganic layers alternately stacked. For example, the barrier layer BR may be a multilayer (e.g., a first barrier layer BR1 and a second barrier layer BR2) in which one or more inorganic layers selected from silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, and aluminum oxide layers are alternately stacked.

[0161] like Figure 8As shown in FIG, the first pattern layer may be located on the blocking layer BR. For example, the light blocking layer BML may be located on the blocking layer BR. The light blocking layer BML may be located on the blocking layer BR to cover the overlapping region (e.g., the first channel region CH1) between the first gate electrode GE1 and the first active layer ACT1. In other words, the light blocking layer BML may be located on the blocking layer BR to overlap the first channel region CH1 of the first transistor T1 serving as the driving transistor.

[0162] The light-blocking layer BML can be made of, for example, a metal material such as chromium (Cr) or molybdenum (Mo), or can be made of black ink or black dye. When the light-blocking layer BML is made of a metal material, it can receive static power. Therefore, the light-blocking layer BML is not electrically floating, and the electrical characteristics of the transistor (e.g., the first transistor T1) on the light-blocking layer BML can be stabilized.

[0163] like Figure 8 As shown in FIG, the buffer layer BF may be located on the light blocking layer BML. The buffer layer BF may be disposed on the entire surface of the substrate SUB on which the blocking layer BR is disposed. The buffer layer BF may be a layer for protecting the transistors T1 to T8 of the thin film transistor layer TFTL and the light emitting layer EL of the light emitting element layer EMTL from moisture introduced through the substrate SUB, which is susceptible to moisture penetration.

[0164] The buffer layer BF may be composed of a plurality of inorganic layers alternately stacked. For example, the buffer layer BF may be a multilayer (e.g., a first buffer layer BF1 and a second buffer layer BF2) in which one or more inorganic layers selected from silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, and aluminum oxide layers are alternately stacked.

[0165] The second pattern layer may be located on the buffer layer BF. For example, the first active layer ACT1 may be located on the buffer layer BF. Figure 8 As shown in , the first active layer ACT1 may include a first channel region CH1 of the first transistor T1, a second electrode E12 of the first transistor T1, a first electrode E61 of the sixth transistor T6, a second electrode E62 of the sixth transistor T6, and a sixth channel region CH6 of the sixth transistor T6.

[0166] The first active layer ACT1 may be an active layer made of low temperature polysilicon (LTPS).

[0167] The first gate insulating layer GTI1 may be located on the second pattern layer. Figure 8 As shown in , the first gate insulating layer GTI1 may be positioned on the first active layer ACT1. Here, the first gate insulating layer GTI1 may be disposed on the entire surface of the substrate SUB on which the first active layer ACT1 is positioned.

[0168] The first gate insulating layer GTI1 may include tetraethyl orthosilicate (TEOS), silicon nitride (SiN x For example, the first gate insulating layer GTI1 may have a double-layer structure in which a silicon nitride layer having a thickness of 40 nm and a tetraethyl orthosilicate layer having a thickness of 80 nm are sequentially stacked.

[0169] The third pattern layer may be located on the first gate insulating layer GTI1. For example, the second gate electrode, the first gate electrode GE1, the eighth gate electrode, the emission control line EML, the fifth gate electrode, and the sixth gate electrode GE6 may be located on the first gate insulating layer GTI1.

[0170] Figure 8 An example is shown in which the first gate electrode GE1, the sixth gate electrode GE6, and the emission control line EML are located on the first gate insulating layer GTI1. The first gate electrode GE1 may be located on the first gate insulating layer GTI1 to overlap the first channel region CH1 of the first active layer ACT1. The emission control line EML and the sixth gate electrode GE6 may be located on the first gate insulating layer GTI1 to overlap the sixth channel region CH6 of the first active layer ACT1.

[0171] The third pattern layer may include at least one of molybdenum (Mo), copper (Cu), aluminum, and titanium (Ti), or may be a single layer or multiple layers. For example, the first gate electrode GE1 may be a three-layer structure including a titanium layer, an aluminum layer, and a titanium layer sequentially located on the first gate insulating layer GTI1 along the third direction DR3.

[0172] The second gate insulating layer GTI2 may be located on the third pattern layer. Figure 8 As shown in , the second gate insulating layer GTI2 may be located on the first gate electrode GE1, the sixth gate electrode GE6, and the emission control line EML. Here, the second gate insulating layer GTI2 may be arranged on the entire surface of the substrate SUB on which the first gate electrode GE1, the sixth gate electrode GE6, and the emission control line EML are disposed.

[0173] The second gate insulating layer GTI2 may include the same material and structure as the first gate insulating layer GTI1 described above.

[0174] The fourth pattern layer may be located on the second gate insulating layer GTI2. For example, the fourth pair of gate electrodes, the third pair of gate electrodes GEb3, and the capacitor electrode CPE may be located on the second gate insulating layer GTI2. Figure 8An example is shown in which the capacitor electrode CPE and the third pair of gate electrodes GEb3 are located on the second gate insulating layer GTI2. The capacitor electrode CPE may be located on the second gate insulating layer GTI2 to overlap the first gate electrode GE1. A capacitor Cst may be formed between the capacitor electrode CPE and the first gate electrode GE1.

[0175] The fourth pattern layer may have the same material or structure as the third pattern layer.

[0176] The first interlayer insulating layer ITL1 may be located on the fourth pattern layer. Figure 8 As shown in FIG, the first interlayer insulating layer ITL1 may be located on the capacitor electrode CPE and the third pair of gate electrodes GEb3. Here, the first interlayer insulating layer ITL1 may be located on the entire surface of the substrate SUB on which the capacitor electrode CPE and the third pair of gate electrodes GEb3 are disposed.

[0177] The first interlayer insulating layer ITL1 may include an inorganic layer (eg, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer). The first interlayer insulating layer ITL1 may include a plurality of inorganic layers.

[0178] The fifth pattern layer may be located on the first interlayer insulating layer ITL1. For example, the second active layer ACT2 may be located on the first interlayer insulating layer ITL1. Figure 8 As shown in FIG, the second active layer ACT2 may be located on the first interlayer insulating layer ITL1 to overlap the third pair of gate electrodes GEb3. The second active layer ACT2 may include a first electrode E31 of the third transistor T3, a second electrode E32 of the third transistor T3, and a third channel region CH3 of the third transistor T3. The third channel region CH3 of the second active layer ACT2 may overlap the third pair of gate electrodes GEb3.

[0179] The second active layer ACT2 may be an oxide-based active layer. For example, the second active layer ACT2 may be an oxide semiconductor including indium gallium zinc oxide (IGZO) or indium gallium zinc tin oxide (IGZTO).

[0180] The third gate insulating layer GTI3 may be located on the fifth pattern layer. Figure 8 As shown in FIG, the third gate insulating layer GTI3 may be positioned on the second active layer ACT2. The third gate insulating layer GTI3 may be disposed on the entire surface of the substrate SUB on which the second active layer ACT2 is positioned.

[0181] The third gate insulating layer GTI3 may have the same material and structure as the first gate insulating layer GTI1 described above.

[0182] The sixth pattern layer may be located on the third gate insulating layer GTI3. For example, the fourth gate electrode and the third gate electrode GE3 may be located on the third gate insulating layer GTI3.

[0183] Figure 8 An example is shown in which the third gate electrode GE3 is located on the third gate insulating layer GTI3. The third gate electrode GE3 may overlap the third channel region CH3 of the second active layer ACT2.

[0184] The sixth pattern layer may have the same material or structure as the third pattern layer.

[0185] The second interlayer insulating layer ITL2 may be located on the sixth pattern layer. Figure 8 As shown in FIG, the second interlayer insulating layer ITL2 may be located on the third gate electrode GE3. The second interlayer insulating layer ITL2 may be located on the entire surface of the substrate SUB on which the third gate electrode GE3 is disposed.

[0186] The second interlayer insulating layer ITL2 may have the same material and structure as those of the above-described first interlayer insulating layer ITL1 .

[0187] The seventh pattern layer may be located on the second interlayer insulating layer ITL2. For example, the first initialization voltage line VIL1 (see Figure 7 ), the third gate line GIL (see Figure 7 ), data connection electrode, first gate line GWL (see Figure 7 ), the second gate line GCL (see Figure 7 ), gate connection electrode GCE, active connection electrode ACE, bias voltage line VBL, capacitor connection electrode, lower pixel connection electrode PCEa, fourth gate line EBL (see Figure 7 ) and the second initialization voltage line VIL2 (see Figure 7 ) may be located on the second interlayer insulating layer ITL2.

[0188] Figure 8An example is shown in which the gate connection electrode GCE, the active connection electrode ACE, the bias voltage line VBL, and the lower pixel connection electrode PCEa are located on the second interlayer insulating layer ITL2. The lower pixel connection electrode PCEa can be connected to the second electrode E62 of the sixth transistor T6 via a first contact hole CT1 that penetrates the second interlayer insulating layer ITL2, the third gate insulating layer GTI3, the first interlayer insulating layer ITL1, the second gate insulating layer GTI2, and the first gate insulating layer GTI1. The active connection electrode ACE can be connected to the second electrode E12 of the first transistor T1 and the first electrode E61 of the sixth transistor T6 via a second contact hole CT2 that penetrates the second interlayer insulating layer ITL2, the third gate insulating layer GTI3, the first interlayer insulating layer ITL1, the second gate insulating layer GTI2, and the first gate insulating layer GTI1. In addition, the active connection electrode ACE can be connected to the second electrode E32 of the third transistor T3 via a fifth contact hole CT5 that penetrates the second interlayer insulating layer ITL2 and the third gate insulating layer GTI3. The gate connection electrode GCE may be connected to the first gate electrode GE1 through a hole 40 penetrating the second interlayer insulating layer ITL2, the third gate insulating layer GTI3, the first interlayer insulating layer ITL1, the capacitor electrode CPE, and a third contact hole CT3 of the second gate insulating layer GTI2. Furthermore, the gate connection electrode GCE may be connected to the first electrode E31 of the third transistor T3 through a fourth contact hole CT4 penetrating the second interlayer insulating layer ITL2 and the third gate insulating layer GTI3.

[0189] The seventh pattern layer may have the same material or structure as the third pattern layer.

[0190] The first planarization layer VA1 may be located on the seventh pattern layer. For example, the first planarization layer VA1 may be located on the gate connection electrode GCE, the active connection electrode ACE, the bias voltage line VBL, and the lower pixel connection electrode PCEa. The first planarization layer VA1 may be arranged on the entire surface of the substrate SUB on which the gate connection electrode GCE, the active connection electrode ACE, the bias voltage line VBL, and the lower pixel connection electrode PCEa are disposed.

[0191] The first planarization layer VA1 may include an organic layer such as an acryl resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0192] The eighth pattern layer may be located on the first planarization layer VA1. For example, the first data line, the driving voltage line VDL, and the upper pixel connection electrode PCEb may be located on the first planarization layer VA1. Figure 8 An example is shown in which the driving voltage line VDL and the upper pixel connection electrode PCEb are located on the first planarization layer VA1.

[0193] The upper pixel link electrode PCEb may be connected to the lower pixel link electrode PCEa through a sixth contact hole CT6 penetrating the first planarization layer VA1 .

[0194] The eighth pattern layer may have the same material or structure as the third pattern layer.

[0195] The second planarization layer VA2 may be located on the eighth pattern layer. For example, the second planarization layer VA2 may be located on the driving voltage line VDL and the upper pixel connection electrode PCEb. The second planarization layer VA2 may be arranged on the entire surface of the substrate SUB on which the driving voltage line VDL and the upper pixel connection electrode PCEb are disposed.

[0196] The second planarization layer VA2 may have the same material and structure as the first planarization layer VA1 described above.

[0197] The ninth pattern layer may be located on the second planarization layer VA2. Figure 8 As shown in FIG, the light emitting element layer EMTL including the ninth pattern layer may be located on the second planarization layer VA2. Figure 8 As shown in FIG, the pixel electrode PE may be formed as a ninth pattern layer on the second planarization layer VA2. The pixel electrode PE may be connected to the upper pixel connection electrode PCEb through a seventh contact hole CT7 penetrating the second planarization layer VA2.

[0198] In addition to the ninth pattern layer, the light emitting element layer EMTL may further include a light emitting layer EL, a common electrode CM, and a bank PDL (or a pixel defining layer).

[0199] The light-emitting element LEL may include a pixel electrode PE, a light-emitting layer EL, and a common electrode CM. The emission area EA is a region in which the pixel electrode PE, the light-emitting layer EL, and the common electrode CM are sequentially stacked, so that holes from the pixel electrode PE and electrons from the common electrode CM recombine with each other in the light-emitting layer EL to emit light. In this case, the pixel electrode PE may be the anode of the light-emitting element LEL, and the common electrode CM may be the cathode of the light-emitting element LEL.

[0200] In a top emission structure in which light is emitted from the light-emitting layer EL toward the common electrode CM, the pixel electrode PE may be formed as a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or, in order to increase reflectivity, may be formed as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO / Al / ITO), an APC alloy, or a stacked structure of an APC alloy and indium tin oxide (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0201] A bank PDL (or pixel defining layer) may define the emission area EA of the pixel PX. To this end, the bank PDL may be located on the second planarization layer VA2 to expose a portion of the pixel electrode PE. The bank PDL may cover the edge of the pixel electrode PE. The bank PDL may be located in a seventh contact hole CT7 that penetrates the second planarization layer VA2. Therefore, the seventh contact hole CT7 that penetrates the second planarization layer VA2 may be filled with the bank PDL. The bank PDL may be made of an organic layer (such as an acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin).

[0202] like Figure 8 As shown in FIG, the spacer SPC may be located on the bank PDL. The spacer SPC may support a mask during the process of manufacturing the light emitting layer EL. The spacer SPC may be made of an organic layer (such as an acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin).

[0203] The light-emitting layer EL may be formed on the pixel electrode PE. The light-emitting layer EL may include an organic material to emit light of a certain color (e.g., a set color or a predetermined color). For example, the light-emitting layer EL may include a hole transport layer, an organic material layer, and an electron transport layer. The organic material layer may include a host and a dopant. The organic material layer may include a material that emits light (e.g., a predetermined light) and may be formed using a phosphorescent material or a fluorescent material.

[0204] The above-mentioned light-emitting element LEL can be provided for each pixel PX. For example, the first pixel PX may include a first light-emitting element, the second pixel PX may include a second light-emitting element, and the third pixel PX may include a third light-emitting element. The first light-emitting element, the second light-emitting element, and the third light-emitting element may provide light of different colors. For example, the first light-emitting element may emit light of a first color, the second light-emitting element may emit light of a second color, and the third light-emitting element may emit light of a third color.

[0205] For example, the organic material layer of the first light-emitting layer of the first emission region emitting light of the first color may be a phosphorescent material including a host material and a dopant, wherein the host material includes carbazole biphenyl (CBP) or 1,3-bis(carbazol-9-yl) (mCP), and the dopant includes any one or more of bis(1-phenylisoquinolinolato) iridium acetylacetonate (PIQIr(acac)), bis(1-phenylquinolinolato) iridium acetylacetonate (PQIr(acac)), tris(1-phenylquinolinolato) iridium (PQIr), and platinum octaethylporphyrin (PtOEP). Alternatively, the organic material layer of the first light-emitting layer of the first emission region may be a fluorescent material including PBD:Eu(DBM)3(Phen) or perylene. However, the present disclosure is not limited thereto.

[0206] The organic material layer of the second light-emitting layer of the second emission region emitting light of the second color may be a phosphorescent material including a host material and a dopant material, wherein the host material includes CBP or mCP, and the dopant material includes Ir(ppy)3 (fa-tris(2-phenylpyridine)iridium). Alternatively, the organic material layer of the second light-emitting layer of the second emission region emitting light of the second color may be a fluorescent material including tris(8-hydroxyquinolinyl)aluminum (Alq3). However, the present disclosure is not limited thereto.

[0207] The organic material layer of the third light emitting layer of the third emission region emitting light of the third color may be a phosphorescent material including a host material including CBP or mCP and a dopant material including (4,6-F2ppy)2Irpic or L2BD111. However, the present disclosure is not limited thereto.

[0208] The common electrode CM may be located on the first, second, and third light-emitting layers (e.g., EL). The common electrode CM may cover the first, second, and third light-emitting layers. The common electrode CM may be a common layer commonly located on the first to third light-emitting layers. A covering layer may be formed on the common electrode CM.

[0209] In a top-emission structure, the common electrode (CM) can be made of a light-transmitting transparent conductive material (TCO), such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. When the common electrode (CM) is made of a semi-transmissive conductive material, the microcavity can increase light output efficiency.

[0210] The encapsulation layer ENC may be formed on the light-emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic layer TFE1 and TFE3 to prevent or reduce the penetration of contaminants such as oxygen or moisture into the light-emitting element layer EMTL. Additionally, the encapsulation layer ENC may include at least one organic layer to protect the light-emitting element layer EMTL from foreign matter such as dust. For example, the encapsulation layer ENC may include a first encapsulation inorganic layer TFE1, an encapsulation organic layer TFE2, and a second encapsulation inorganic layer TFE3.

[0211] A first encapsulating inorganic layer TFE1 may be located on the common electrode CM, an encapsulating organic layer TFE2 may be located on the first encapsulating inorganic layer TFE1, and a second encapsulating inorganic layer TFE3 may be located on the encapsulating organic layer TFE2. Each of the first encapsulating inorganic layer TFE1 and the second encapsulating inorganic layer TFE3 may be a multilayer structure in which one or more inorganic layers selected from silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, and aluminum oxide layers are alternately stacked. The encapsulating organic layer TFE2 may be an organic layer (such as an acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin).

[0212] Figure 9 yes Figure 2 An enlarged view of portion A5. Figure 10 It is along Figure 9 A cross-sectional view taken along line II'. Figure 11 It is along Figure 9 A sectional view taken along line II-II'. Figure 12 It is along Figure 9 A cross-sectional view taken along line III-III'.

[0213] Figure 9 Four first pads (eg, four first data pads D11 ) are shown. For example, the four first data pads D11 may be first data pads D11 connected to different first data lines.

[0214] One side of each first data pad D11 can be connected to a fan-out line FL, and the other side of each first data pad D11 can be connected to a dummy line DML. For example, each first data pad D11 can be connected to the fan-out line FL via a first connection electrode CNE1 and to the dummy line DML via a second connection electrode CNE2. The dummy line DML can be part of a test line used to transmit test signals during the manufacturing process of the display device 100. For example, after the process of testing the display device 100 using the test line is completed, the test line can be cut during a scribing process. Therefore, the dummy line DML can be part of the cut test line.

[0215] The fan-out line FL and the dummy line DML may be located on the first gate insulating layer GTI1 , and may be made of the same material as the third pattern layer.

[0216] The first connection electrode CNE1 may be located on the fan-out line FL, and the second connection electrode CNE2 may be located on the dummy line DML. For example, the first connection electrode CNE1 may be located on the second interlayer insulating layer ITL2 to overlap the fan-out line FL, and the second connection electrode CNE2 may be located on the second interlayer insulating layer ITL2 to overlap the dummy line DML. The first connection electrode CNE1 may be connected to the fan-out line FL via first and second contact holes CT11 and CT22 that penetrate the second interlayer insulating layer ITL2, the third gate insulating layer GTI3, the first interlayer insulating layer ITL1, and the second gate insulating layer GTI2. The second connection electrode CNE2 may be connected to the dummy line DML via third and fourth contact holes CT33 and CT44 that penetrate the second interlayer insulating layer ITL2, the third gate insulating layer GTI3, the first interlayer insulating layer ITL1, and the second gate insulating layer GTI2. The first and second connection electrodes CNE1 and CNE2 may both be made of the same material as the seventh pattern layer described above.

[0217] Each first data pad D11 may be located on the first connection electrode CNE1 and the second connection electrode CNE2. For example, each first data pad D11 may be located on the first connection electrode CNE1 and the second connection electrode CNE2 so as to overlap with the first connection electrode CNE1 and the second connection electrode CNE2. Each first data pad D11 may be directly connected to (or in direct contact with) the first connection electrode CNE1 and the second connection electrode CNE2. The first data pad D11 may be made of the same material as the eighth pattern layer described above.

[0218] The second planarization layer VA2 may be located on the first data pads D11. The second planarization layer VA2 may have a pad contact hole PCH that exposes at least a portion of each first data pad D11. For example, the pad contact hole PCH may penetrate the second planarization layer VA2. The aforementioned terminals (for example, the first data terminal D1) may be connected to each first data pad D11 through the pad contact hole PCH. For example, the first data terminal D1 may be electrically connected to each first data pad D11 through an anisotropic conductive layer located on the pad contact hole PCH.

[0219] On the other hand, the fifth alignment mark AK5 may be located in the non-display area NDA. For example, the fifth alignment mark AK5 may be located in the non-display area NDA between adjacent dummy lines DML. The fifth alignment mark AK5 may be a mark used for alignment between the circuit boards CB1 to CB5 and the display panel 110. For example, the fifth alignment mark AK5 may be a mark used for alignment between the terminals C1, P1, D1, P2, D2, P3, D3, P4, D4, P5, D5, and C2 of the circuit boards CB1 to CB5 and the pads C11, P11, D11, P22, D22, P33, D33, P44, D44, P55, D55, and C22 of the display panel 110. By using the fifth alignment mark AK5, the terminals C1, P1, D1, P2, D2, P3, D3, P4, D4, P5, D5, and C2 can be aligned with the pads C11, P11, D11, P22, D22, P33, D33, P44, D44, P55, D55, and C22. In addition, by using the fifth alignment mark AK5, it can be checked whether the terminals C1, P1, D1, P2, D2, P3, D3, P4, D4, P5, D5, and C2 are accurately aligned with the pads C11, P11, D11, P22, D22, P33, D33, P44, D44, P55, D55, and C22. The fifth alignment mark AK5 can have, for example, a triangular shape.

[0220] The fifth alignment mark AK5 may be located on both sides of the dummy line DML. For example, a plurality of fifth alignment marks AK5 may be arranged opposite each other with the dummy line DML interposed therebetween. The fifth alignment mark AK5 located on one side of the dummy line DML and the fifth alignment mark AK5 located on the other side of the dummy line DML may be symmetrical with respect to the dummy line DML therebetween.

[0221] The fifth alignment mark AK5 may be located on the buffer layer BF. For example, the fifth alignment mark AK5 may be located between the second buffer layer BF2 and the first gate insulating layer GTI1. The fifth alignment mark AK5 may be made of the same material as the second pattern layer described above. For example, the fifth alignment mark AK5 may be made of the same material as the first active layer ACT1 described above. Specifically, the fifth alignment mark AK5 may be made of the same material as the first electrode E61 of the first active layer ACT1. The fifth alignment mark AK5 may be observed from the back side of the substrate SUB. Figure 13 It is along Figure 9 A sectional view taken along line IV-IV'.

[0222] Figure 13 The display device 100 and Figure 9 The difference between the above-described display device 100 and the fan-out line FL is that the fan-out line FL is located on the second gate insulating layer GTI2. This difference will be mainly described below.

[0223] like Figure 13 As shown in FIG, the fan-out line FL may be located on the second gate insulating layer GTI2. For example, the fan-out line FL may be made of the same material as the fourth pattern layer.

[0224] like Figure 13 As shown in , adjacent fan-out lines FL can be located in different layers. For example, one of the adjacent fan-out lines FL can be made of the third pattern layer, and the other can be made of the fourth pattern layer. In other words, when the fan-out line FL made of the third pattern layer is defined as the first fan-out line and the fan-out line FL made of the fourth pattern layer is defined as the second fan-out line, the first fan-out line and the second fan-out line can be alternately arranged along the first direction DR1.

[0225] Figure 14 is a diagram illustrating a position of the fifth alignment mark AK5 when the number of pads in a pad group is an odd number, according to some embodiments.

[0226] Figure 14 An example is shown in which one group of pads (e.g., the first group of pads PD1) includes five pads PD10, PD20, PD30, PD40, and PD50. Here, a first dummy line DML1 may be connected to the first pad PD10, a second dummy line DML2 may be connected to the second pad PD20, a third dummy line DML3 may be connected to the third pad PD30, a fourth dummy line DML4 may be connected to the fourth pad PD40, and a fifth dummy line DML5 may be connected to the fifth pad PD50.

[0227] like Figure 14 As shown in , the fifth alignment mark AK5 may be located near an imaginary center line CTL1 that passes through a portion of the first group pads PD1 corresponding to half of the first group pad width W11 of the first group pads PD1 and extends parallel to the pads (e.g., the third pads PD30) along the second direction DR2 (e.g., the direction in which the pads extend). For example, as Figure 14As shown in FIG, when the total number of pads PD10, PD20, PD30, PD40, and PD50 included in the first pad group PD1 is an odd number (e.g., five), the imaginary center line CTL1 may be located at the center of the third pad PD30, which is positioned at the center of the first pad group PD1. Here, the fifth alignment mark AK5 may be located on both sides of the third dummy line DML3 connected to the third pad PD30. For example, the fifth alignment marks AK5 may face each other in the first direction DR1, with the third dummy line DML3 interposed therebetween. In other words, three of the fifth alignment marks AK5 may be located between the second dummy line DML2 and the third dummy line DML3, and another three of the fifth alignment marks AK5 may be located between the third dummy line DML3 and the fourth dummy line DML4.

[0228] Figure 15 is a diagram illustrating a position of the fifth alignment mark AK5 when the number of pads in a pad group is an even number, according to some embodiments.

[0229] Figure 15 An example is shown in which one of the pad groups (e.g., the first pad group PD1) includes six pads PD10, PD20, PD30, PD40, PD50, and PD60. Here, a first dummy line DML1 may be connected to the first pad PD10, a second dummy line DML2 may be connected to the second pad PD20, a third dummy line DML3 may be connected to the third pad PD30, a fourth dummy line DML4 may be connected to the fourth pad PD40, a fifth dummy line DML5 may be connected to the fifth pad PD50, and a sixth dummy line DML6 may be connected to the sixth pad PD60.

[0230] like Figure 15 As shown in , the fifth alignment mark AK5 may be located near an imaginary center line CTL2 that passes through a portion of the first group pads PD1 corresponding to half of the first group pad width W11 of the first group pads PD1 and extends parallel to the pads (e.g., the third pad PD30) along the second direction DR2 (e.g., the direction in which the pads extend). For example, as Figure 15As shown in FIG, when the total number of pads PD10, PD20, PD30, PD40, PD50, and PD60 included in the first pad group PD1 is an even number (e.g., six), the imaginary center line CTL2 may be located between the third pad PD30 and the fourth pad PD40, which are located at the center of the first pad group PD1. Here, the fifth alignment mark AK5 may be located on both sides of the third dummy line DML3, which is located to the left of the imaginary center line CTL2 (e.g., in the opposite direction of the first direction DR1 (hereinafter referred to as the first opposite direction)). For example, the fifth alignment marks AK5 may face each other in the first direction DR1, with the third dummy line DML3 interposed therebetween. In other words, three of the fifth alignment marks AK5 may be located between the imaginary center line CTL2 (or the fourth dummy line DML4) and the third dummy line DML3, and another three of the fifth alignment marks AK5 may be located between the third dummy line DML3 and the second dummy line DML2.

[0231] In another embodiment, when the total number of pads PD10, PD20, PD30, PD40, PD50, and PD60 included in the first pad group PD1 is an even number as described above, the fifth alignment mark AK5 may be located on both sides of the fourth dummy line DML4, which is located to the right of the imaginary center line CTL2 (e.g., in the first direction DR1). For example, the fifth alignment marks AK5 may face each other in the first direction DR1, with the fourth dummy line DML4 interposed therebetween. In other words, three of the fifth alignment marks AK5 may be located between the imaginary center line CTL2 (or the third dummy line DML3) and the fourth dummy line DML4, and another three of the fifth alignment marks AK5 may be located between the fourth dummy line DML4 and the fifth dummy line DML5.

[0232] According to some embodiments, when the total number of pads PD10, PD20, PD30, PD40, PD50, and PD60 included in the first pad group PD1 is an even number as described above, the fifth alignment mark AK5 may be located on both sides of the n-th imaginary line on the left side (e.g., the first reverse direction) of the imaginary center line CTL2, or may be located on both sides of the n-th imaginary line on the right side (e.g., the first direction DR1) of the imaginary center line CTL2. Here, n may be a natural number (e.g., a natural number less than k / 2), where k may be the total number of pads included in one pad group. For example, as Figure 15 As shown in , when the first group of pads PD1 includes a total of 6 pads PD10, PD20, PD30, PD40, PD50 and PD60, k is 3 (=6 / 2), and therefore, n can be 1 or 2 (k is 6, and therefore, n can be 1 or 2 which is smaller than 3 (=6 / 2)).

[0233] In the display device according to some embodiments of the present disclosure, misalignment of the circuit board may be minimized or reduced at high resolution.

[0234] However, the features of the embodiments according to the present disclosure are not limited to the features specifically described herein. The above and other features of the embodiments according to the present disclosure will become more apparent to those skilled in the art by referring to the appended claims and their equivalents.

[0235] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the disclosed embodiments without departing substantially from the principles of the invention. Therefore, the disclosed embodiments of the present disclosure are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A display device, comprising: Display panel; Pixels, in a display area of ​​the display panel; a plurality of circuit boards connected to the non-display area of ​​the display panel; as well as A plurality of driving circuits are provided on the circuit board. Each of the plurality of circuit boards includes a group terminal connected to the pad of the non-display area, the group terminal includes a plurality of terminals adjacent to each other in the corresponding circuit board, and the group terminals of at least two circuit boards have different widths.

2. The display device according to claim 1, wherein The plurality of circuit boards include: a first outermost circuit board; a second outermost circuit board; and An intermediate circuit board is located between the first outermost circuit board and the second outermost circuit board.

3. The display device according to claim 2, wherein: The group terminals of at least one of the first outermost circuit board and the second outermost circuit board have a different width from the group terminals of the intermediate circuit board.

4. The display device according to claim 3, wherein A width of the group of terminals of the intermediate circuit board is smaller than a width of the group of terminals of the at least one of the first outermost circuit board and the second outermost circuit board. 5 . The display device according to claim 3 , further comprising a first alignment mark between adjacent circuit boards. The display device according to claim 5 , wherein: The first alignment mark is between the first outermost circuit board and the middle circuit board.

7. The display device according to claim 6, wherein: A distance between any one of the facing sides of the first outermost circuit board and the middle circuit board and a center of the first alignment mark is equal to a distance between the other of the facing sides and the center of the first alignment mark.

8. The display device according to claim 6, wherein: The distance between any one of the facing sides of the outermost terminal of the first outermost circuit board near the first alignment mark and the outermost terminal of the intermediate circuit board near the first alignment mark and the center of the first alignment mark is different from the distance between the other one of the facing sides and the center of the first alignment mark.

9. The display device according to claim 8, wherein The either one of the facing sides is a side of the outermost terminals of the first outermost circuit board, and the other one of the facing sides is a side of the outermost terminals of the intermediate circuit board.

10. The display device according to claim 5, wherein The first alignment mark is between the second outermost circuit board and the middle circuit board.

11. The display device according to claim 10, wherein: A distance between any one of the facing sides of the second outermost circuit board and the middle circuit board and the center of the first alignment mark is equal to a distance between the other of the facing sides and the center of the first alignment mark.

12. The display device according to claim 10, wherein: The distance between any one of the facing sides of the outermost terminal of the second outermost circuit board close to the first alignment mark and the outermost terminal of the intermediate circuit board close to the first alignment mark and the center of the first alignment mark is different from the distance between the other one of the facing sides and the center of the first alignment mark.

13. The display device according to claim 12, wherein: Any one of the facing sides is the side of the outermost terminal of the second outermost circuit board, the other one of the facing sides is the side of the outermost terminal of the intermediate circuit board, and the distance between any one of the facing sides and the center of the first alignment mark is greater than the distance between the other one of the facing sides and the center of the first alignment mark.

14. The display device according to claim 5, wherein The intermediate circuit board includes a first intermediate circuit board and a second intermediate circuit board, and the first alignment mark is between the first intermediate circuit board and the second intermediate circuit board.

15. The display device according to claim 14, wherein A distance between any one of the facing sides of the first and second intermediate circuit boards and a center of the first alignment mark is equal to a distance between the other of the facing sides and the center of the first alignment mark.

16. The display device according to claim 14, wherein: The distance between any one of the facing sides of the outermost terminal of the first intermediate circuit board close to the first alignment mark and the outermost terminal of the second intermediate circuit board close to the first alignment mark and the center of the first alignment mark is equal to the distance between the other one of the facing sides and the center of the first alignment mark.

17. The display device according to claim 1, wherein At least two of the circuit boards have different widths.

18. The display device according to claim 17, wherein: The circuit boards having groups of terminals of different widths have different widths.

19. The display device according to claim 18, wherein A circuit board including a group of terminals having a larger width has a larger width than a circuit board including a group of terminals having a smaller width. 20 . The display device of claim 1 , further comprising a fan-out line connected to one side of each of the pads and the pixel.

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