Display device

Abstract

Each pixel of a display device according to an embodiment of the present invention comprises: a first transistor; a second transistor connected to a first gate of the first transistor and a data line; a third transistor connected to a first gate of the first transistor and a first voltage line; a first capacitor including a first electrode connected to a first gate of the first transistor and a second electrode connected to a second terminal of the first transistor; and a second capacitor including a first electrode connected to the first voltage line and a second electrode connected to the second terminal of the first transistor, in which the first electrode of the second capacitor and the first voltage line are arranged in the same layer.

Description

Technical Field

[0001] One or more embodiments relate to a pixel and a display device including the pixel. Background Art

[0002] The applications of display devices have recently diversified. In addition, as display devices have become thinner and lighter, their scope of use has increased.

[0003] Given that display devices are used in various ways, various methods may be used to design the shape of the display devices, and the number of functions that can be connected or linked to the display devices is increasing. Summary of the Invention

[0004] Technical issues One or more embodiments include a display device with improved display quality. However, aspects of the embodiments are not limited thereto, and the above-described features do not limit the scope of the disclosed embodiments.

[0005] Technical solutions to the problem According to one or more embodiments, a display device includes a plurality of pixels, wherein each of the plurality of pixels includes: a first transistor including a first terminal, a second terminal, a first gate, and a second gate connected to the second terminal; a second transistor connected to the first gate of the first transistor and a data line; a third transistor connected to the first gate of the first transistor and a first voltage line; a fourth transistor connected to the first terminal and the second voltage line of the first transistor; a first capacitor including a first electrode connected to the first gate of the first transistor and a second electrode connected to the second terminal of the first transistor; and a second capacitor including a first electrode connected to the first voltage line and a second electrode connected to the second terminal of the first transistor. The first electrode of the second capacitor and the first voltage line are provided on the same layer.

[0006] A second electrode of the second capacitor may be connected to the second gate of the first transistor.

[0007] The first electrode of the first capacitor may include an upper electrode and a lower electrode, the upper electrode and the first gate of the first transistor may be provided in the same layer, the lower electrode and the first electrode of the second capacitor may be provided in the same layer, and the lower electrode may be connected to the upper electrode.

[0008] During one frame, the gate signal may be supplied to the gate of the third transistor once, and the gate signal may be supplied to the gate of the fourth transistor two or more times.

[0009] Each of the multiple pixels may further include: a fifth transistor connected to the second terminal of the first transistor and the third voltage line; a sixth transistor connected to the second terminal of the first transistor and the light emitting diode; and a seventh transistor connected to the light emitting diode and the fourth voltage line, and the same gate signal may be supplied to the gate of the fifth transistor and the gate of the seventh transistor.

[0010] A timing at which the gate signal is applied to the gate of the fourth transistor may be earlier than a timing at which the gate signal is applied to the gate of the sixth transistor.

[0011] Each of the multiple pixels may further include: a fifth transistor connected to the second terminal of the first transistor and the third voltage line; a sixth transistor connected to the second terminal of the first transistor and the light emitting diode; and a seventh transistor connected to the light emitting diode and the fourth voltage line, and the gate signal supplied to the gate of the fifth transistor may be different from the gate signal supplied to the gate of the seventh transistor.

[0012] During one frame, the gate signal may be supplied to the gate of the fifth transistor once, and the gate signal may be supplied to the gate of the seventh transistor two or more times.

[0013] A frame may include a first scanning period and a second scanning period, the first scanning period including a first non-emission period and a first emission period, and the second scanning period including a second non-emission period and a second emission period. Each of the plurality of pixels may further include a fifth transistor connected to the second terminal of the first transistor and a third voltage line. The first non-emission period may include: a writing period, in which a first gate signal is applied to the gate of the second transistor during the writing period; a first period, before the writing period, in which a second gate signal is applied to the gate of the fifth transistor during the first period, and a third gate signal is applied to the gate of the third transistor during the first period; and a second period, between the writing period and the first period, in which a third gate signal is applied to the gate of the third transistor during the second period, and a fourth gate signal is applied to the gate of the fourth transistor during the second period.

[0014] The second non-emission period may include a third period in which the second gate signal is applied to the gate of the fifth transistor.

[0015] According to one or more embodiments, a display device includes a plurality of pixels, wherein each of the plurality of pixels includes: a first transistor including a first terminal, a second terminal, a first gate, and a second gate connected to the second terminal; a second transistor connected to the first gate of the first transistor and a data line; a third transistor connected to the first gate of the first transistor and a first voltage line; a fourth transistor connected to the first terminal and the second voltage line of the first transistor; a fifth transistor connected to the second terminal of the first transistor and a light-emitting diode; a first capacitor including a first electrode connected to the first gate of the first transistor and a second electrode connected to the second terminal of the first transistor; and a second capacitor including a first electrode connected to the first voltage line and a second electrode connected to the second terminal of the first transistor. A gate signal is applied to the gate of the fourth transistor at a timing prior to a gate signal being applied to the gate of the fifth transistor.

[0016] A second electrode of the second capacitor may be connected to the second gate of the first transistor.

[0017] The first electrode of the first capacitor may include an upper electrode and a lower electrode, the upper electrode and the first gate of the first transistor may be provided in the same layer, the lower electrode and the first electrode of the second capacitor may be provided in the same layer, and the lower electrode may be connected to the upper electrode.

[0018] During one frame, the gate signal may be supplied to the gate of the third transistor once, and the gate signal may be supplied to the gate of the fourth transistor two or more times.

[0019] Each of the plurality of pixels may further include: a sixth transistor connected to the second terminal of the first transistor and the third voltage line; and a seventh transistor connected to the light emitting diode and the fourth voltage line. The same gate signal may be supplied to the gate of the sixth transistor and the gate of the seventh transistor.

[0020] Each of the plurality of pixels may further include: a sixth transistor connected to the second terminal of the first transistor and the third voltage line; and a seventh transistor connected to the light emitting diode and the fourth voltage line. A gate signal supplied to the gate of the sixth transistor may be different from a gate signal supplied to the gate of the seventh transistor.

[0021] During one frame, the gate signal may be supplied to the gate of the sixth transistor once, and the gate signal may be supplied to the gate of the seventh transistor two or more times.

[0022] According to one or more embodiments, a display device includes a plurality of pixels, wherein each of the plurality of pixels includes: a first transistor including a first terminal, a second terminal, a first gate, and a second gate connected to the second terminal; a second transistor connected to the first gate of the first transistor and a data line; a third transistor connected to the first gate of the first transistor and a first voltage line; a fourth transistor connected to the first terminal and the second voltage line of the first transistor; a first capacitor including a first electrode connected to the first gate of the first transistor and a second electrode connected to the second terminal of the first transistor; a second capacitor including a first electrode connected to the second voltage line and a second electrode connected to the second terminal of the first transistor; and a third capacitor including a first electrode connected to the second terminal of the first transistor and a second electrode connected to an electrode of a light emitting diode.

[0023] Each of the plurality of pixels may further include: a fifth transistor connected to the second terminal of the first transistor and a third voltage line; a sixth transistor connected to the second terminal of the first transistor and a light-emitting diode; and a seventh transistor connected to the light-emitting diode and a fourth voltage line. The same gate signal may be supplied to the gate of the fifth transistor and the gate of the seventh transistor. The gate signal may be applied to the gate of the fourth transistor before the gate signal is applied to the gate of the sixth transistor.

[0024] According to an embodiment, each of the plurality of pixels may further include: a fifth transistor connected to the second terminal of the first transistor and the third voltage line; a sixth transistor connected to the second terminal of the first transistor and the light-emitting diode; and a seventh transistor connected to the light-emitting diode and the fourth voltage line. The gate signal supplied to the gate of the fifth transistor may be different from the gate signal supplied to the gate of the seventh transistor. The timing of applying the gate signal to the gate of the fourth transistor may be earlier than the timing of applying the gate signal to the gate of the sixth transistor.

[0025] According to one or more embodiments, a display device includes a plurality of pixels, wherein each pixel of the plurality of pixels includes: a first transistor including a first terminal, a second terminal, a first gate, and a second gate connected to the second terminal; a second transistor connected to the first gate of the first transistor and a data line; a third transistor connected to the first gate of the first transistor and a first voltage line; a fourth transistor connected to the first terminal and the second voltage line of the first transistor; a fifth transistor connected to the second terminal of the first transistor and a first electrode of a light-emitting diode; a first capacitor including a first electrode connected to the first gate of the first transistor and a second electrode connected to the second terminal of the first transistor; and a second capacitor including a first electrode connected to the second terminal of the first transistor and a second electrode connected to the second electrode of the light-emitting diode.

[0026] A first electrode of the second capacitor may be connected to the second gate of the first transistor.

[0027] The first electrode of the first capacitor may include an upper electrode and a lower electrode, the upper electrode and the first gate of the first transistor are disposed in the same layer, the lower electrode and the first electrode of the second capacitor are disposed in the same layer, and the lower electrode is connected to the upper electrode.

[0028] During one frame, the gate signal may be supplied to the gate of the third transistor once, and the gate signal may be supplied to the gate of the fourth transistor two or more times.

[0029] Each of the plurality of pixels may further include: a sixth transistor connected to the second terminal of the first transistor and the third voltage line; and a seventh transistor connected to the first electrode of the light emitting diode and the fourth voltage line. The same gate signal may be supplied to the gate of the sixth transistor and the gate of the seventh transistor.

[0030] A timing at which the gate signal is applied to the gate of the fourth transistor may be earlier than a timing at which the gate signal is applied to the gate of the fifth transistor.

[0031] Each of the multiple pixels may further include: a sixth transistor connected to the second terminal of the first transistor and the third voltage line; and a seventh transistor connected to the first electrode of the light emitting diode and the fourth voltage line, and the gate signal supplied to the gate of the sixth transistor may be different from the gate signal supplied to the gate of the seventh transistor.

[0032] During one frame, the gate signal is supplied to the gate of the sixth transistor once, and the gate signal may be supplied to the gate of the seventh transistor two or more times.

[0033] A frame may include a first scanning period and a second scanning period, the first scanning period including a first non-emission period and a first emission period, and the second scanning period including a second non-emission period and a second emission period. Each of the plurality of pixels further includes a sixth transistor connected to the second terminal of the first transistor and a third voltage line. The first non-emission period may include: a writing period, in which a first gate signal is applied to the gate of the second transistor during the writing period; a first period, before the writing period, in which a second gate signal is applied to the gate of the sixth transistor during the first period, and a third gate signal is applied to the gate of the third transistor during the first period; and a second period, between the writing period and the first period, in which a third gate signal is applied to the gate of the third transistor during the second period, and a fourth gate signal is applied to the gate of the fourth transistor during the second period.

[0034] The second non-emission period may include a third period in which the second gate signal is applied to the gate of the sixth transistor.

[0035] Advantageous Effects of the Invention According to the embodiment, a display device capable of improving display quality can be provided. Of course, the scope of the disclosure is not limited thereto. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1a and Figure 1b is a schematic plan view of a display device according to an embodiment.

[0037] Figure 2 is a schematic block diagram of a display device according to an embodiment.

[0038] Figure 3a and Figure 3b is a conceptual diagram for explaining a method of driving a display device according to a driving frequency.

[0039] Figure 4 is a schematic diagram of an equivalent circuit of a pixel according to an embodiment.

[0040] Figures 5 to 7 is shown for explanation Figure 4 Schematic diagram of the pixel operation signals.

[0041] Figure 8 is a schematic diagram of an equivalent circuit of a pixel according to a comparative example.

[0042] Figure 9 is a schematic diagram showing the operation of the fourth gate signal applied to the Figure 8 FIG. 1 is a diagram showing a change in the first driving voltage when the pixel is turned on.

[0043] Figure 10 is a schematic diagram of a layout of an emission area of ​​a pixel according to an embodiment.

[0044] Figures 11 to 19 It is shown layer by layer Figure 4 A schematic plan view (or layout diagram) of the arrangement of elements of a pixel.

[0045] Figure 20 yes Figure 19 A schematic cross-sectional view taken along line II'.

[0046] Figure 21 yes Figure 19 A schematic cross-sectional view taken along line II-II'.

[0047] Figure 22 is a schematic diagram of an equivalent circuit of a pixel according to an embodiment.

[0048] Figure 23 and Figure 24 is shown for explanation Figure 22 Schematic diagram of the pixel operation signals.

[0049] Figures 25 to 27 is a schematic diagram of an equivalent circuit of a pixel according to an embodiment.

[0050] Figures 28a to 29b is a schematic cross-sectional view of the structure of a display element according to an embodiment.

[0051] Figure 30 is a schematic cross-sectional view of a structure of a pixel of a display device according to an embodiment. DETAILED DESCRIPTION

[0052] A display device according to a disclosed embodiment includes a plurality of pixels, wherein each of the plurality of pixels includes: a first transistor including a first terminal, a second terminal, a first gate, and a second gate connected to the second terminal; a second transistor connected to the first gate of the first transistor and a data line; a third transistor connected to the first gate of the first transistor and a first voltage line; a fourth transistor connected to the first terminal and the second voltage line of the first transistor; a first capacitor including a first electrode connected to the first gate of the first transistor and a second electrode connected to the second terminal of the first transistor; and a second capacitor including a first electrode connected to the first voltage line and a second electrode connected to the second terminal of the first transistor. The first electrode of the second capacitor and the first voltage line are provided on the same layer.

[0053] Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals represent like elements throughout. In this regard, the embodiments may have different forms and should not be construed as limited to the descriptions set forth herein. Therefore, the embodiments will be described below solely with reference to the drawings to explain the described aspects.

[0054] The term "and / or" includes all combinations of one or more that can be defined by the associated construction. For example, "A and / or B" can be understood to mean "A, B, or A and B." For the purposes of this disclosure, the phrase "at least one of A and B" can be interpreted as only A, only B, or any combination of A and B. In addition, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z.

[0055] Since the disclosure allows for various changes and numerous embodiments, specific embodiments will be illustrated in the drawings and described in detail in the written description. Hereinafter, the effects and features of the disclosure and methods for achieving them will be more fully described with reference to the drawings, in which embodiments of the disclosure are shown. However, the disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein.

[0056] It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0057] As used herein, singular forms such as “a” and “an” are intended to include plural forms as well, unless the context clearly indicates otherwise.

[0058] It will also be understood that the terms “comprises” and / or “comprising” used herein specify the presence of stated features or elements, but do not preclude the presence or addition of one or more other features or elements.

[0059] It will be understood that when a layer, region or element is referred to as being “formed on” another layer, region or element, it can be directly or indirectly formed on the other layer, region or element. That is, for example, intervening layers, regions or elements may be present.

[0060] For the convenience of explanation, the size of the elements in the drawings may be exaggerated or reduced. For example, since the size and thickness of the elements in the drawings are arbitrarily shown for the convenience of explanation, the following embodiments are not limited thereto.

[0061] When X and Y are said to be connected, this may include cases where X and Y are electrically connected, cases where X and Y are functionally connected, and cases where X and Y are physically connected. When X and Y are said to be connected to each other, this may indicate that X and Y are directly connected to each other or that X and Y are indirectly connected to each other. Here, X and Y may be objects (e.g., devices, apparatuses, circuits, wiring, electrodes, terminals, conductive layers, layers, etc.). Therefore, the connection is not limited to a predetermined connection relationship (e.g., a connection relationship shown in the drawings or detailed description) and may include other connection relationships not shown in the drawings or detailed description.

[0062] The case where X and Y are electrically connected to each other may include, for example, a case where X and Y are directly electrically connected to each other or a case where at least one device capable of electrically connecting X and Y (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, etc.) is connected between X and Y.

[0063] The terms "on" or "turned on" used in conjunction with the state of an element may refer to the activated state of the element, while "off" or "turned off" may refer to the inactivated state of the element. "On" or "turned on" used in conjunction with a signal received by an element may refer to the signal used to activate the element, while "off" or "turned off" used in conjunction with a signal received by an element may refer to the signal used to deactivate the element. An element can be activated by a high-level voltage or a low-level voltage. For example, a P-channel transistor (P-type transistor) is activated by a low-level voltage, while an N-channel transistor (N-type transistor) is activated by a high-level voltage. Therefore, it should be understood that the "on" voltage of a P-type transistor and the "on" voltage of an N-type transistor have opposite (high and low) voltage levels.

[0064] In this specification, any signal that is supplied may refer to a supplied on-voltage or turn-on voltage (eg, a high-level voltage), and any signal that is not supplied may refer to a supplied off-voltage (eg, a low-level voltage).

[0065] In the following embodiments, the x-direction, y-direction, and z-direction are not limited to directions along the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the x-direction, y-direction, and z-direction can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0066] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one skilled in the art to which the disclosure belongs. It will also be understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the relevant art and the context of the disclosure, and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0067] The display device according to the embodiment may be implemented as an electronic device such as a smartphone, a mobile phone, a smart watch, a navigation device, a game console, a TV, an in-vehicle information device, a notebook computer, a laptop computer, a tablet computer, a personal media player (PMP), or a personal digital assistant (PDA). The electronic device may be flexible.

[0068] Figure 1a and Figure 1b is a schematic diagram of a display device 10 according to an embodiment. Figure 2 is a schematic block diagram of a display device 10 according to an embodiment. Figure 3a and Figure 3b is a schematic conceptual diagram for explaining a method of driving a display device according to a driving frequency.

[0069] Reference Figure 1a and Figure 1b , the display device 10 may include a display area DA displaying an image and a peripheral area PA surrounding the display area DA. The display area DA may be completely surrounded by the peripheral area PA.

[0070] When the display area DA is viewed in a plan view, the display area DA may have a rectangular shape. According to another embodiment, the display area DA may have a polygonal shape (e.g., a triangular shape, a pentagonal shape, or a hexagonal shape), a circular shape, an elliptical shape, an irregular shape, etc. The display area DA may have a shape with rounded corners. According to an embodiment, as Figure 1a As shown in , the display device 10 may have a display area DA having a shape in which the length in the x direction is greater than the length in the y direction. According to another embodiment, as Figure 1b As shown in , the display device 10 may have a display area DA having a shape in which a length in the y direction is greater than a length in the x direction.

[0071] Reference Figure 2 The display device 10 according to the embodiment may include a pixel portion 11 , a gate driving circuit 13 , a data driving circuit 15 , a power supply circuit 17 and / or a controller 19 .

[0072] The pixel portion 11 may be included in the display area DA. Various conductive lines for transmitting electrical signals applied to the display area DA, external circuits electrically connected to the pixel circuits, and pads (also referred to as "pads") to which a printed circuit board (PCB) or a driver integrated circuit (IC) chip is attached may be located in the peripheral area PA. For example, the gate driver circuit 13, the data driver circuit 15, the power supply circuit 17, and the controller 19 may be included in the peripheral area PA.

[0073] like Figure 2 As shown in FIG, gate lines GL, data lines DL, and pixels PX connected to the gate lines GL and the data lines DL may be provided in the display area DA. The pixels PX may be arranged in a stripe configuration, a PenTile configuration, or a similar configuration. TM Structure, Diamond Pixel TM The pixels PX may be arranged in any of various configurations, such as a lattice structure and a mosaic structure, to display an image. Each pixel PX may include an organic light-emitting diode (OLED) as a display element (light-emitting device), and the organic light-emitting diode OLED may be connected to a pixel circuit. The pixel circuit may include a transistor and at least one capacitor. Each pixel PX may emit, for example, red, green, blue, or white light via the organic light-emitting diode OLED. Each pixel PX may be connected to at least one corresponding gate line among the gate lines GL and at least one corresponding data line among the data lines DL.

[0074] Each gate line GL may extend in the x-direction (row direction) and may be connected to pixels PX located in the same row. Each gate line GL may transmit a gate signal to pixels PX located in the same row. Each data line DL may extend in the y-direction (column direction) and may be connected to pixels PX located in the same column. Each data line DL may transmit a data signal to pixels PX located in the same column in synchronization with the gate signal.

[0075] According to an embodiment, the peripheral area PA may be a non-display area in which no pixels PX are disposed. According to another embodiment, a portion of the peripheral area PA may be implemented as the display area DA. For example, the pixels PX may be disposed at at least one corner of the peripheral area PA and may overlap the gate drive circuit 13. Thus, dead space may be reduced, and the display area DA may be expanded.

[0076] The gate drive circuit 13 may be connected to the gate lines GL, may generate gate signals based on the control signals GCS from the controller 19, and may sequentially supply the gate signals to the gate lines GL. The gate lines GL may be electrically connected to the gates of the transistors included in the pixels PX. The gate signals may be gate control signals for controlling the on and off operations of the transistors having gates connected to the gate lines GL. The gate signals may be square wave signals including an on-voltage for turning on the transistors and an off-voltage for turning off the transistors. Depending on the embodiment, the on-voltage may be a high-level voltage (a first-level voltage) or a low-level voltage (a second-level voltage).

[0077] Despite Figure 2 Pixel PX is shown as being connected to gate line GL, but this is an example, and pixel PX may be connected to two or more gate lines, and gate drive circuit 13 may supply two or more gate signals whose turn-on voltages are applied at different timings to gate lines corresponding to the two or more gate signals. For example, pixel PX may be connected to a first gate line, a second gate line, a third gate line, a fourth gate line, a fifth gate line, and a sixth gate line, and gate drive circuit 13 may apply a first gate signal GW, a second gate signal GI, a third gate signal GR, a fourth gate signal EM, and a fifth gate signal EMB to the first gate line, the second gate line, the third gate line, the fourth gate line, and the fifth gate line, respectively.

[0078] The data driving circuit 15 may be connected to the data line DL and may supply a data signal to the data line DL according to a control signal DCS from the controller 19. The data signal supplied to the data line DL may be supplied to the pixel PX to which the gate signal has been supplied. The data driving circuit 15 may convert the input image data DATA having a grayscale input from the controller 19 into a data signal in a voltage form or a current form. Figure 2 An example is shown in which the data driving circuit 15 outputs the data signal Vdata in the form of a voltage.

[0079] The power supply circuit 17 can generate the voltages necessary to drive the pixel PX in response to a control signal PCS from the controller 19. The power supply circuit 17 can generate a first drive voltage ELVDD and a second drive voltage ELVSS, and supply them to the pixel PX. The first drive voltage ELVDD can be a high-level voltage supplied to the first electrode (e.g., pixel electrode or anode) of the display element included in the pixel PX. The second drive voltage ELVSS can be a low-level voltage supplied to the second electrode (e.g., counter electrode or cathode) of the display element included in the pixel PX. The power supply circuit 17 can generate a reference voltage Vref, a first initialization voltage Vint, and a second initialization voltage Vaint, and supply them to the pixel PX.

[0080] The voltage level of the first driving voltage ELVDD may be higher than the voltage level of the second driving voltage ELVSS. The voltage level of the reference voltage Vref may be lower than the voltage level of the first driving voltage ELVDD. The voltage level of the first initialization voltage Vint may be lower than the voltage level of the second driving voltage ELVSS. The voltage level of the second initialization voltage Vaint may be higher than the voltage level of the first initialization voltage Vint. The voltage level of the second initialization voltage Vaint may be substantially equal to or higher than the voltage level of the second driving voltage ELVSS.

[0081] The controller 19 may generate control signals GCS, DCS, and PCS based on signals input from the outside, and may supply them to the gate driving circuit 13, the data driving circuit 15, and / or the power supply circuit 17. The control signal GCS output to the gate driving circuit 13 may include a clock signal and a gate start signal. The control signal DCS output to the data driving circuit 15 may include a source start signal and a clock signal.

[0082] The display device 10 may include a display panel, and the display panel may include a substrate. Pixels PX may be disposed in a display area DA of the substrate. During the process of forming transistors constituting the pixel circuit in the display area DA of the substrate, part or all of the gate driver circuit 13 may be directly formed in the peripheral area PA of the substrate. The data driver circuit 15, the power supply circuit 17, and the controller 19 may each be formed as a separate IC chip, or may be formed as a single IC chip and disposed on a flexible printed circuit board (FPCB) electrically connected to a pad disposed on one side of the substrate. According to another embodiment, the data driver circuit 15, the power supply circuit 17, and the controller 17 may be disposed directly on the substrate using a chip-on-glass (COG) method or a chip-on-plastic (COP) method.

[0083] According to an embodiment, the transistors included in the pixel circuit may be N-type oxide thin film transistors. According to another embodiment, the transistors included in the pixel circuit may be P-type silicon thin film transistors. According to another embodiment, some of the transistors included in the pixel circuit may be N-type oxide thin film transistors, while other transistors included in the pixel circuit may be P-type silicon thin film transistors.

[0084] An N-type oxide thin-film transistor may be a low-temperature polycrystalline oxide (LTPO) thin-film transistor in which the active pattern (semiconductor layer) comprises an oxide. However, this is merely an example, and N-type transistors are not limited thereto. For example, the active pattern (semiconductor layer) included in an N-type transistor may comprise an inorganic semiconductor (e.g., amorphous silicon or polycrystalline silicon) or an organic semiconductor. A P-type silicon thin-film transistor may be a thin-film transistor in which the active pattern (semiconductor layer) comprises amorphous silicon, or a low-temperature polycrystalline silicon (LTPS) thin-film transistor in which the active pattern (semiconductor layer) comprises polycrystalline silicon.

[0085] The display device 10 can support a variable refresh rate (VRR). The refresh rate can be the frequency at which the data signal Vdata is actually written to the driver transistor of the pixel PX. It can also be referred to as the screen refresh rate or screen reproduction rate and can represent the number of image frames reproduced in one second. Depending on the embodiment, the refresh rate can be the output frequency of the gate driver circuit 13 and / or the data driver circuit 15. The frequency corresponding to the refresh rate can be the driving frequency. The display device 10 can adjust the output frequency of the gate driver circuit 13 and the corresponding output frequency of the data driver circuit 15 according to the driving frequency. A display device 10 that supports VRR can operate while varying the driving frequency within a range from a maximum driving frequency to a minimum driving frequency. For example, at a refresh rate of approximately 60 Hz, the gate signal from the gate driver circuit 13 for writing the data signal Vdata can be supplied to each horizontal line (row) 60 times per second. The display device 10 can display images while varying the driving frequency according to the refresh rate.

[0086] According to the driving frequency, one frame 1F may include a first scanning period AS and one or more second scanning periods SS. Figure 3a As shown in FIG, in the display device 10 operating at a driving frequency of AHz, one frame 1F may include one first scanning period AS and one second scanning period SS. Figure 3b As shown in , in a display device 10 operating at a driving frequency of BHz lower than a driving frequency of AHz, one frame 1F may include one first scanning period AS and two or more second scanning periods SS. As the driving frequency decreases, one frame 1F may become longer. According to another embodiment, one frame 1F may include only one first scanning period AS.

[0087] The first scan period AS can be defined as an address scan period during which the data signal Vdata is written to the pixel PX in response to the first gate signal GW, and the pixel PX can emit light according to the data signal Vdata. The operation of writing the data signal Vdata from the data line DL to the pixel PX can also be referred to as a data programming operation. The second scan period SS can be defined as a self-scan period during which the first gate signal GW is not applied to the pixel PX and the data signal Vdata is not written to the pixel PX. During the second scan period SS, the data signal Vdata written to the first scan period AS can be maintained, and the pixel PX can emit light according to the maintained data signal Vdata. The length of the second scan period SS can be substantially equal to the length of the first scan period AS.

[0088] Figure 4 is a schematic diagram of an equivalent circuit of a pixel PX according to an embodiment. Figures 5 to 7 is shown for explanation Figure 4 Schematic diagram of the operation signals of the pixel PX.

[0089] Reference Figure 4 Pixel PX may include an organic light-emitting diode (OLED) as a display element and a pixel circuit PC connected to the organic light-emitting diode (OLED). Pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, as well as a first capacitor C1 and a second capacitor C2. The first transistor T1 may be a driving transistor that outputs a driving current corresponding to a data signal Vdata, and the second transistors T2 through T7 may be switching transistors that transmit signals. The first terminal (first electrode) and the second terminal (second electrode) of each of the first through seventh transistors T1 through T7 may be a source or a drain, depending on the respective voltages of the first and second terminals. For example, depending on the respective voltages of the first and second terminals, the first terminal may be a drain and the second terminal may be a source, or the first terminal may be a source and the second terminal may be a drain. The node to which the first gate of the first transistor T1 is connected may be defined as a first node N1, and the node to which the second terminal of the first transistor T1 is connected may be defined as a second node N2.

[0090] The pixel PX may be connected to a first gate line GWL transmitting a first gate signal GW, a second gate line GIL transmitting a second gate signal GI, a third gate line GRL transmitting a third gate signal GR, a fourth gate line EML transmitting a fourth gate signal EM, a fifth gate line EMBL transmitting a fifth gate signal EMB, and a data line DL transmitting a data signal Vdata. Because light emission of the pixel PX is controlled by the fourth gate signal EM and the fifth gate signal EMB, the fourth gate signal EM and the fifth gate signal EMB may be referred to as emission control signals, and the fourth gate line EML and the fifth gate line EMBL may be referred to as emission control lines.

[0091] The pixel PX may also be connected to a driving voltage line PL transmitting a first driving voltage ELVDD, a reference voltage line VRL transmitting a reference voltage Vref, a first initialization voltage line VL1 transmitting a first initialization voltage Vint, and a second initialization voltage line VL2 transmitting a second initialization voltage Vaint.

[0092] The first transistor T1 may be connected between the driving voltage line PL and the second node N2. The first transistor T1 may include a gate, a first terminal, and a second terminal connected to the second node N2. The gate of the first transistor T1 may include a first gate connected to the first node N1 and a second gate connected to the second node N2. The first gate and the second gate may be arranged to face each other at different layers. For example, the first gate and the second gate of the first transistor T1 may be positioned to face each other, with the semiconductor layer interposed between the first gate and the second gate.

[0093] The first gate of the first transistor T1 can be connected to the second terminal of the second transistor T2, the first terminal of the third transistor T3, and the first capacitor C1. The second gate of the first transistor T1 can be connected to the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The first terminal of the first transistor T1 can be connected to the driving voltage line PL via the fifth transistor T5, and the second terminal can be connected to the pixel electrode of the organic light emitting diode OLED via the sixth transistor T6. The second terminal of the first transistor T1 can be connected to the first terminal of the fourth transistor T4, the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The first transistor T1 can receive the data signal Vdata according to the switching operation of the second transistor T2 and can control the amount of driving current flowing to the organic light emitting diode OLED.

[0094] The second transistor T2 (data write transistor) can be connected between the data line DL and the first gate of the first transistor T1. The second transistor T2 may include a gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1. The second terminal of the second transistor T2 may be connected to the first gate of the first transistor T1, the first terminal of the third transistor T3, and the first capacitor C1. The second transistor T2 can be turned on by the first gate signal GW transmitted to the first gate line GWL to electrically connect the data line DL to the first node N1. The second transistor T2 can then transmit the data signal Vdata received via the data line DL to the first node N1.

[0095] The third transistor T3 (first initialization transistor) may be connected between the first gate of the first transistor T1 and the reference voltage line VRL. The third transistor T3 may include a gate connected to the third gate line GRL, a first terminal connected to the first node N1, and a second terminal connected to the reference voltage line VRL. The first terminal of the third transistor T3 may be connected to the first gate of the first transistor T1, the second terminal of the second transistor T2, and the first capacitor C1. The third transistor T3 may be turned on by a third gate signal GR received via the third gate line GRL to transmit the reference voltage Vref received via the reference voltage line VRL to the first node N1.

[0096] The fourth transistor T4 (second initialization transistor) may be connected between the first transistor T1 and the first initialization voltage line VL1. The fourth transistor T4 may include a gate connected to the second gate line GIL, a first terminal connected to the second node N2, and a second terminal connected to the first initialization voltage line VL1. The first terminal of the fourth transistor T4 may be connected to the second terminal of the first transistor T1, the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The fourth transistor T4 may be turned on by a second gate signal GI received via the second gate line GIL to transmit the first initialization voltage Vint received via the first initialization voltage line VL1 to the second node N2.

[0097] A fifth transistor T5 (a first emission control transistor) may be connected between the driving voltage line PL and the first transistor T1. The fifth transistor T5 may include a gate connected to a fourth gate line EML, a first terminal connected to the driving voltage line PL, and a second terminal connected to the first terminal of the first transistor T1. The fifth transistor T5 may be turned on or off based on a fourth gate signal EM received via the fourth gate line EML.

[0098] The sixth transistor T6 (second emission control transistor) may be connected between the first transistor T1 and the organic light emitting diode OLED. The sixth transistor T6 may be connected between the second node N2 and the third node N3. The sixth transistor T6 may include a gate connected to the fifth gate line EMBL, a first terminal connected to the second node N2, and a second terminal connected to the third node N3. The first terminal of the sixth transistor T6 may be connected to the second terminal of the first transistor T1, the first terminal of the fourth transistor T4, the first capacitor C1, and the second capacitor C2. The second terminal of the sixth transistor T6 may be connected to the first terminal of the seventh transistor T7 and the pixel electrode of the organic light emitting diode OLED. The sixth transistor T6 may be turned on or off based on a fifth gate signal EMB received via the fifth gate line EMBL.

[0099] A seventh transistor T7 (third initialization transistor) may be connected between the organic light emitting diode OLED and the second initialization voltage line VL2. The seventh transistor T7 may be connected between the sixth transistor T6 and the second initialization voltage line VL2. The seventh transistor T7 may include a gate connected to the second gate line GIL, a first terminal connected to the third node N3, and a second terminal connected to the second initialization voltage line VL2. The first terminal of the seventh transistor T7 may be connected to the second terminal of the sixth transistor T6 and the pixel electrode of the organic light emitting diode OLED. The seventh transistor T7 may be turned on by a second gate signal GI received via the second gate line GIL to transmit the second initialization voltage Vaint received via the second initialization voltage line VL2 to the third node N3.

[0100] The first capacitor C1 may be connected between the first gate of the first transistor T1 and the second terminal of the first transistor T1. The first electrode of the first capacitor C1 may be connected to the first node N1, and the second electrode of the first capacitor C1 may be connected to the second node N2. The first electrode of the first capacitor C1 may be connected to the first gate of the first transistor T1, the second terminal of the second transistor T2, and the first terminal of the third transistor T3. The second electrode of the first capacitor C1 may be connected to the second terminal and the gate of the first transistor T1, the second electrode of the second capacitor C2, the first terminal of the fourth transistor T4, and the first terminal of the sixth transistor T6. The first capacitor C1, as a storage capacitor, may store a voltage corresponding to the threshold voltage of the first transistor T1 and the data signal Vdata.

[0101] The second capacitor C2 may be connected between the reference voltage line VRL and the second node N2. A first electrode of the second capacitor C2 may be connected to the reference voltage line VRL. A second electrode of the second capacitor C2 may be connected to the second terminal and the second gate of the first transistor T1, the second electrode of the first capacitor C1, the first terminal of the fourth transistor T4, and the first terminal of the sixth transistor T6. The capacitance of the first capacitor C1 may be greater than that of the second capacitor C2.

[0102] The organic light emitting diode OLED may be connected to the first transistor T1 via the sixth transistor T6. The organic light emitting diode OLED may include a pixel electrode (anode) connected to the third node N3 and a counter electrode (cathode) facing the pixel electrode. The counter electrode may receive the second driving voltage ELVSS. The counter electrode may be a common electrode shared by all pixels PX.

[0103] According to the embodiment, Figure 5As shown in FIG, the pixel PX can operate in one first scanning period AS and one second scanning period SS during one frame 1F. Most of the first scanning period AS and the second scanning period SS can be emission periods. The voltage levels of the first gate signal GW, the second gate signal GI, the third gate signal GR, the fourth gate signal EM, and the fifth gate signal EMB applied to the pixel PX in the first scanning period AS and the second scanning period SS can be different.

[0104] like Figure 6 As shown in , the first scanning period AS may include a first non-emission period ND1 in which the pixel PX does not emit light and a first emission period DD1 in which the pixel PX emits light. The first non-emission period ND1 may include a first period P1, a second period P2, a third period P3, and a fourth period P4.

[0105] Each of the first gate signal GW, the second gate signal GI, the third gate signal GR, the fourth gate signal EM, and the fifth gate signal EMB may have a high-level voltage (a first-level voltage) in some periods and a low-level voltage (a second-level voltage) in some periods. The high-level voltage may be a turn-on voltage for turning on a transistor, and the low-level voltage may be a turn-off voltage for turning off a transistor.

[0106] The first period P1 may be a first initialization period for initializing the first and second nodes N1 and N2 connected to the first transistor T1, and the third node N3 connected to the pixel electrode of the organic light emitting diode OLED. During the first period P1, a second gate signal GI having a turn-on voltage may be supplied (applied) to the second gate line GIL. A third gate signal GR having a turn-on voltage may be supplied to the third gate line GRL. The first, fourth, and fifth gate signals GW, EM, and EMB may be supplied as turn-off voltages. The timing of applying the turn-on voltage to the third gate signal GR may be delayed by a period (e.g., a predetermined or selectable period) from the timing of applying the turn-on voltage to the second gate signal GI.

[0107] The fourth transistor T4 and the seventh transistor T7 can be turned on by the second gate signal GI, and the third transistor T3 can be turned on by the third gate signal GR. The second node N2 (e.g., the second terminal of the first transistor T1) can be initialized to the first initialization voltage Vint via the turned-on fourth transistor T4. The first node N1 (e.g., the first gate electrode of the first transistor T1) can be initialized to the reference voltage Vref via the turned-on third transistor T3. The third node N3 (e.g., the pixel electrode of the organic light emitting diode OLED) can be initialized to the second initialization voltage Vaint via the turned-on seventh transistor T7. The first capacitor C1 and the second capacitor C2 can be initialized via the turned-on third transistor T3 and the turned-on fourth transistor T4.

[0108] The second period P2 may be a compensation period for compensating for the threshold voltage of the first transistor T1. During the second period P2, the third gate signal GR having a turn-on voltage may be supplied to the third gate line GRL, and the fourth gate signal EM may be supplied to the fourth gate line EML. The first gate signal GW, the second gate signal GI, and the fifth gate signal EMB may be supplied as turn-off voltages.

[0109] The third transistor T3 can be turned on by the third gate signal GR, and the fifth transistor T5 can be turned on by the fourth gate signal EM. Therefore, by supplying the reference voltage Vref to the first node N1 and the first drive voltage ELVDD to the first terminal of the first transistor T1, the first transistor T1 can be turned on. When the voltage at the second terminal of the first transistor T1 substantially reaches the difference (Vref-Vth) between the reference voltage Vref and the threshold voltage (Vth) of the first transistor T1, the first transistor T1 can be turned off. By storing a voltage corresponding to the threshold voltage (Vth) of the first transistor T1 in the first capacitor C1, the threshold voltage (Vth) of the first transistor T1 can be compensated.

[0110] The third period P3 may be a write period in which the data signal Vdata is supplied to the pixel. During the third period P3, the first gate signal GW having a turn-on voltage may be supplied to the first gate line GWL. According to an embodiment, the turn-on voltage of the first scan signal GW may have a width of approximately two horizontal periods 2H. The second gate signal GI, the third gate signal GR, the fourth gate signal EM, and the fifth gate signal EMB may be supplied as a turn-off voltage.

[0111] The second transistor T2 can be turned on by the first gate signal GW, and the turned-on second transistor T2 can transmit the data signal Vdata from the data line DL to the first node N1 (e.g., to the first gate of the first transistor T1). Therefore, the voltage of the first node N1 can change from the reference voltage Vref to a voltage corresponding to the data signal Vdata. In this case, the voltage of the second node N2 can also change in response to the change in the voltage of the first node N1. The voltage of the second node N2 can be a voltage (Vref-Vth+α×(Vdata-Vref)) that changes according to the capacitance ratio (α=C1 / (C1+C2)) between the first capacitor C1 and the second capacitor C2. Therefore, the first capacitor C1 can be charged with a voltage corresponding to the threshold voltage (Vth) of the first transistor T1 and the data signal Vdata.

[0112] The fourth period P4 may be a second initialization period for initializing the connection of the second terminal of the first transistor T1 to the second node N2 and the pixel electrode of the organic light emitting diode OLED to the third node N3. The fourth period P4 is after data writing and before the first emission period DD1. During the fourth period P4, the second gate signal GI having a turn-on voltage may be supplied (applied) to the second gate line GIL. The first gate signal GW, the third gate signal GR, the fourth gate signal EM, and the fifth gate signal EMB may be supplied as turn-off voltages.

[0113] The fourth transistor T4 and the seventh transistor T7 can be turned on by the second gate signal GI. The first initialization voltage Vint can be transmitted to the second terminal of the first transistor T1 through the turned-on fourth transistor T4. The second initialization voltage Vaint can be transmitted to the pixel electrode of the organic light emitting diode OLED through the turned-on seventh transistor T7.

[0114] When displaying low grayscales (e.g., grayscale values ​​of 11 to 31), variations in brightness may occur or may result due to residual voltage in the organic light-emitting diode (OLED). By initializing the third node N3 during a fourth period P4 after data writing and before pixel emission, variations in brightness of the organic light-emitting diode (OLED) can be minimized when displaying low grayscales, thereby further improving image quality. A voltage different from the first initialization voltage Vint (e.g., a voltage higher than the first initialization voltage Vint) can be used as the second initialization voltage Vaint to minimize the period of time during which the pixel electrode voltage varies, thereby minimizing screen flicker.

[0115] The first emission period DD1 may be a period during which the organic light emitting diode OLED emits light. In the first emission period DD1, a fourth gate signal EM having a turn-on voltage may be supplied to the fourth gate line EML, and a fifth gate signal EMB having a turn-on voltage may be supplied to the fifth gate line EMBL. The first gate signal GW, the second gate signal GI, and the third gate signal GR may be turn-off voltages.

[0116] During the first emission period DD1, the fifth transistor T5 may be turned on by the fourth gate signal EM, and the first driving voltage ELVDD may be supplied to the first terminal of the first transistor T1 through the turned-on fifth transistor T5. The first transistor T1 may output a driving current having a magnitude corresponding to a voltage corresponding to the data signal Vdata stored in the first capacitor C1 (e.g., a voltage (Vgs-Vth) obtained by subtracting a threshold voltage (Vth) of the first transistor T1 from a gate-source voltage (Vgs)) (Id∝(Vgs-Vth) 2 ). Drive current (Id∝(Vgs-Vth) 2 ) may flow in the organic light emitting diode OLED through the sixth transistor T6 turned on by the fifth gate signal EMB, and the organic light emitting diode OLED may emit light having brightness corresponding to the magnitude of the driving current.

[0117] like Figure 7 As shown in FIG, the second scanning period SS may include a second non-emission period ND2 in which the pixel PX does not emit light and a second emission period DD2 in which the pixel PX emits light. The second non-emission period ND2 may include a fifth period P5 and a sixth period P6. The second scanning period SS may not include a compensation period corresponding to the second period P2 of the first scanning period AS and a writing period corresponding to the third period P3 of the first scanning period AS.

[0118] Each of the first, second, third, fourth, and fifth gate signals GW, GI, GR, EM, and EMB may have a high level voltage (first level voltage) in some periods and may have a low level voltage (second level voltage) in some periods.

[0119] The fifth period P5 may be a third initialization period for initializing the third node N3 connected to the pixel electrode of the organic light emitting diode OLED. The fifth period P5 may correspond to the first period P1 of the first scanning period AS. During the fifth period P5, the second gate signal GI having an on-voltage may be supplied to the second gate line GIL. The first gate signal GW, the third gate signal GR, the fourth gate signal EM, and the fifth gate signal EMB may be supplied with an off-voltage. The fourth transistor T4 and the seventh transistor T7 may be turned on by the second gate signal GI. The second node N2 (e.g., the second terminal of the first transistor T1) may be initialized to the first initialization voltage Vint by the turned-on fourth transistor T4. The third node N3 (e.g., the pixel electrode of the organic light emitting diode OLED) may be initialized to the second initialization voltage Vaint by the turned-on seventh transistor T7.

[0120] The sixth period P6 may be a fourth initialization period for initializing the third node N3 connected to the pixel electrode of the organic light emitting diode OLED. The sixth period P6 precedes the second emission period DD2. The sixth period P6 may correspond to the fourth period P4 of the first scanning period AS. During the sixth period P6, the second gate signal GI having an on-voltage may be supplied to the second gate line GIL. The first gate signal GW, the third gate signal GR, the fourth gate signal EM, and the fifth gate signal EMB may be supplied with off-voltages. The fourth transistor T4 and the seventh transistor T7 may be turned on by the second gate signal GI. The second node N2 (e.g., the second terminal of the first transistor T1) may be initialized to the first initialization voltage Vint by the turned-on fourth transistor T4. The third node N3 (e.g., the pixel electrode of the organic light emitting diode OLED) may be initialized to the second initialization voltage Vaint by the turned-on seventh transistor T7.

[0121] The second emission period DD2 may be a period during which the organic light emitting diode OLED emits light. The second emission period DD2 may correspond to the first emission period DD1 of the first scanning period AS. In the second emission period DD2, a fourth gate signal EM having a turn-on voltage may be supplied to the fourth gate line EML, and a fifth gate signal EMB having a turn-on voltage may be supplied to the fifth gate line EMBL. The first gate signal GW, the second gate signal GI, and the third gate signal GR may be turn-off voltages.

[0122] During the second emission period DD2, the fifth transistor T5 may be turned on by the fourth gate signal EM, and the first drive voltage ELVDD may be supplied to the first terminal of the first transistor T1 through the turned-on fifth transistor T5. The first transistor T1 may output a drive current having a magnitude corresponding to the voltage stored in the first capacitor C1 (corresponding to the data signal Vdata). The drive current may flow through the organic light emitting diode OLED via the sixth transistor T6 turned on by the fifth gate signal EMB, and the organic light emitting diode OLED may emit light having a brightness corresponding to the magnitude of the drive current. The data signal Vdata stored in the first capacitor C1 during the second emission period DD2 may be the data signal supplied to the pixel and maintained during the third period P3 of the first scan period AS.

[0123] When the first initialization voltage Vint and the second initialization voltage Vaint are applied to the second node N2 and the third node N3 (e.g., the first and second terminals of the sixth transistor T6) in the fourth and sixth periods P4 and P6, when the turn-on voltages of the fourth gate signal EM and the fifth gate signal EMB are applied at the same timing, the voltage of the third node N3 may change to a voltage lower than the second initialization voltage Vaint due to the voltage difference between the first and second terminals of the sixth transistor T6. Therefore, by initializing the third node N3 with the second initialization voltage Vaint, which is higher than the first initialization voltage Vint, a flicker phenomenon may be minimized. According to an embodiment, in each of the first emission period DD1 and the second emission period DD2, the turn-on voltage application timing of the fifth gate signal EMB may be delayed by a time period DT (e.g., a predetermined or selectable time period) from the turn-on voltage application timing of the fourth gate signal EM. After first applying the turn-on voltage of the fourth gate signal EM to increase the voltage level of the voltage applied to the first terminal of the sixth transistor T6, the voltage difference between the first terminal and the second terminal of the sixth transistor T6 can be reduced by applying the turn-on voltage of the fifth gate signal EMB, thereby minimizing the voltage fluctuation of the third node N3 and minimizing the flicker phenomenon.

[0124] According to an embodiment, by initializing the pixel electrode twice in the second scanning period SS similar to the first scanning period AS, even when one or more second scanning periods SS are included in one frame, luminance deviation according to driving speed may be minimized.

[0125] In the above embodiment, by performing threshold voltage compensation and data writing to the drive transistor once during a single frame, the first and third gate signals GW and GR can be supplied only during the first scanning period AS. The second, fifth, and sixth gate signals EMB can be supplied during each of the first scanning period AS and the second scanning period SS. In other words, during a single frame, the period of each of the first and third gate signals GW and GR can be one cycle, and the period of each of the second, fourth, and fifth gate signals EMB can be two cycles. The fourth gate signal EM can be supplied during the compensation period P2 of the first scanning period AS and not during the period corresponding to the compensation period P2 of the second scanning period SS. However, considering that the fourth gate signal EM is an emission control signal, the fourth gate signal EM can be supplied during the first emission period DD1 of the first scanning period AS and the second emission period DD2 of the second scanning period SS, and thus can be interpreted as having a period of two cycles during a single frame.

[0126] The first gate signal GW can be supplied to the pixel at intervals of one cycle during one frame by being supplied to the pixel only once in the third period P3 of the first scanning period AS. The second gate signal GI can be supplied to the pixel at intervals of two cycles in one frame by being supplied to the pixel twice in the first period P1 and the fourth period P4 of the first scanning period AS and twice in the fifth period P5 and the sixth period P6 of the second scanning period SS. The third gate signal GR can be supplied to the pixel at intervals of one cycle in one frame by being continuously supplied to the pixel only once in the first period P1 and the second period P2 of the first scanning period AS. The fourth gate signal EM can be supplied to the pixel at intervals of two cycles in one frame by being supplied to the pixel once in the first emission period DD1 of the first scanning period AS and once in the second emission period DD2 of the second scanning period SS. The case where the fourth gate signal EM is supplied in the second period P2 of the first scanning period AS will be omitted here. The fifth gate signal EMB may be supplied to the pixel at intervals of two cycles in one frame by being supplied to the pixel once in the first emission period DD1 of the first scanning period AS and once in the second emission period DD2 of the second scanning period SS.

[0127] According to another embodiment, the fourth period P4 of the first scanning period AS and the sixth period P6 of the second scanning period SS may be omitted. In this case, the second gate signal GI may be supplied to the pixel once in the first period P1 of the first scanning period AS and once in the fifth period P5 of the second scanning period SS. Thus, the second gate signal GI may be supplied to the pixel at intervals of two cycles in one frame.

[0128] Figures 5 to 7 FIG. 4 shows an embodiment in which one frame includes one first scanning period AS and one second scanning period SS, and the fourth gate signal EM is applied to the pixel at intervals of two cycles in one frame. Figure 3b As shown in , in an embodiment where one frame includes one first scanning period AS and two or more second scanning periods SS, the third gate signal GR can be understood as being supplied to the pixel at intervals of one cycle in one frame, and the fourth gate signal EM can be understood as being supplied to the pixel at intervals of three cycles or more in one frame.

[0129] Figure 8 is a schematic diagram of an equivalent circuit of a pixel PX′ according to a comparative example. Figure 9 is a schematic diagram showing the fourth gate signal EM applied to the Figure 8 FIG. 1 is a diagram showing a change in the first driving voltage ELVDD when the pixel PX′ is shown in FIG.

[0130] exist Figure 8 In the pixel circuit PC' of the pixel PX' shown in FIG, the second capacitor C2' may be connected between the driving voltage line PL and the second node N2. Figure 6 and Figure 7 As shown in , the fourth gate signal EM can be sequentially applied to the display area DA from the first row to the last row during one frame. When the fourth gate signal EM is applied as an on-voltage, the first driving voltage ELVDD decreases, while when the fourth gate signal EM is applied as an off-voltage, the first driving voltage ELVDD increases. When the fourth gate signal EM is applied as an on-voltage to a pixel PX' displaying white, the decrease in the first driving voltage ELVDD is large, while when the fourth gate signal EM is applied as an on-voltage to a pixel PX' displaying black, the decrease in the first driving voltage ELVDD is small.

[0131] Figure 9 FIG. 2 shows a variation of the first driving voltage ELVDD measured for the entire display area DA with time t when the fourth gate signal EM is applied at intervals of two cycles during one frame. Figure 9As shown in FIG, when the fourth gate signal EM is applied at intervals of two cycles during a frame, voltage variations in the first driving voltage ELVDD may occur in the middle of a frame. Consequently, each pixel PX' in the display area DA may be affected by the decrease and increase of the first driving voltage ELVDD depending on the operating state, potentially causing image unevenness (mura). For example, if the first driving voltage ELVDD has a decreasing slope, pixels PX' in the second half of the second period P2 (e.g., before the third gate signal GR transitions from an on-voltage to an off-voltage) may appear dark due to the decrease in the voltage at the second terminal of the first transistor T1 caused by the voltage variation of the second capacitor C2'. If the first driving voltage ELVDD has a rising slope, pixels PX' before the third period P3 (e.g., before the fourth gate signal EM reaches the off-voltage and before the first gate signal GW is applied as an on-voltage) may appear bright due to the increase in the voltage at the second terminal of the first transistor T1 caused by the voltage variation of the second capacitor C2'.

[0132] In the pixel PX according to the embodiment, the second capacitor C2 may be connected to the reference voltage line VRL instead of the driving voltage line PL, and the third gate signal GR may be provided at intervals of one cycle during one frame, so the voltage of the reference voltage line VRL to which the third transistor T3 is connected may not change in the middle of one frame, thereby minimizing the occurrence of mura.

[0133] Figure 10 is a schematic diagram of a layout of an emission area of ​​a pixel according to an embodiment.

[0134] Reference Figure 10 The display area DA defined on the substrate 100 may include pixel regions in which rows and columns intersect each other and in which pixel circuits are provided. Depending on the embodiment, a unit pixel region may be defined that includes two or more pixel regions adjacent to each other in the x-direction. For example, the unit pixel region PCAu may include a first pixel region PCA1, a second pixel region PCA2, and / or a third pixel region PCA3 adjacent to each other in the x-direction.

[0135] The pixels PX disposed in the display area DA may include a first pixel PX1 emitting light of a first color, a second pixel PX2 emitting light of a second color, and a third pixel PX3 emitting light of a third color. For example, the first pixel PX1 may be a red pixel, the second pixel PX2 may be a green pixel, and the third pixel PX3 may be a blue pixel. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may be repeated according to a specific pattern in the x- and y-directions. Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a pixel circuit and an organic light emitting diode (OLED) electrically connected to the pixel circuit.

[0136] The first pixel area PCA1 may be an area where the pixel circuit of the first pixel PX1 is disposed. The second pixel area PCA2 may be an area where the pixel circuit of the second pixel PX2 is disposed. The third pixel area PCA3 may be an area where the pixel circuit of the third pixel PX3 is disposed. The organic light emitting diode OLED may be disposed above the pixel circuit. The organic light emitting diode OLED may be disposed directly above the pixel circuit connected to the organic light emitting diode OLED so as to overlap the connected pixel circuit, or may be disposed so as to overlap a portion of the pixel circuit of another pixel disposed in a column or row that is offset relative to and adjacent to the connected pixel circuit.

[0137] Figure 10 The pixel electrode 211 and the emission area EA of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 are shown. In the emission area EA, the emission layer of the organic light emitting diode OLED can be disposed. The emission area EA can be defined by the opening of the pixel defining layer described below. Because the emission layer is disposed on the pixel electrode 211, Figure 10 The arrangement of the emission areas shown in FIG. 1 may represent an arrangement of pixel electrodes or an arrangement of pixels.

[0138] The emission area EA may have a shape such as a polygon (such as a rectangle or an octagon), a circle, or an ellipse. Examples of the polygon may include a shape whose corners (vertices) are rounded.

[0139] like Figure 10 As shown in , the emission area EA of the first pixel PX1 and the emission area EA of the second pixel PX2 may be disposed adjacent to each other in the y direction, and the emission area EA of the third pixel PX3 may be disposed adjacent to the emission area EA of the first pixel PX1 and the emission area EA of the second pixel PX2 in the x direction. Therefore, the emission area EA of the first pixel PX1 and the emission area EA of the second pixel PX2 may be alternately arranged in the y direction along the imaginary straight line IL1, and the emission area EA of the third pixel PX3 may be repeatedly arranged in the y direction along the imaginary straight line IL2.

[0140] The respective lengths of the emission areas EA of the first pixel PX1, the second pixel PX2, and the third pixel PX3 in the x-direction may be the same as or different from their respective lengths in the y-direction. For example, the emission areas EA of the first pixel PX1 and the second pixel PX2 may have a square shape, while the emission area EA of the third pixel PX3 may have a rectangular shape having a longer side in the y-direction. The length of the emission area EA of the third pixel PX3 in the y-direction may be substantially equal to or greater than the sum of the lengths of the emission areas EA of the first pixel PX1 and the second pixel PX2 in the y-direction.

[0141] The emission area EA of the first pixel PX1, the emission area EA of the second pixel PX2, and the emission area EA of the third pixel PX3 may have the same area (size) or different areas (sizes). According to an embodiment, the emission area EA of the third pixel PX3 may have a larger area than the emission area EA of the first pixel PX1. The emission area EA of the third pixel PX3 may have a larger area than the emission area EA of the second pixel PX2. The emission area EA of the first pixel PX1 may have an area substantially equal to the area of ​​the emission area EA of the second pixel PX2.

[0142] Figures 11 to 19 It is shown layer by layer Figure 4 Schematic plan view of the arrangement of elements of a pixel. Figure 14 part of Figure 15 is a schematic plan view of elements of the first pixel area PCA1. Figure 20 yes Figure 19 A schematic cross-sectional view taken along line II'. Figure 21 yes Figure 19 A schematic cross-sectional view taken along line II-II'.

[0143] According to an embodiment, different second initialization voltages Vaint may be supplied to the first pixel, the second pixel, and the third pixel, taking into account their emission characteristics. For example, the pixel circuit of the first pixel may be connected to the 2-1 initialization voltage line VL21, and the pixel circuit of the second pixel and the pixel circuit of the third pixel may be connected to the 2-2 initialization voltage line VL22. The second initialization voltage supplied to the 2-1 initialization voltage line VL21 may be different from the second initialization voltage supplied to the 2-2 initialization voltage line VL22.

[0144] The same elements may be provided in corresponding layers of the first pixel area PCA1, the second pixel area PCA2, and the third pixel area PCA3. Hereinafter, for ease of illustration and description, identification symbols may be assigned to elements of the pixel circuit provided in the first pixel area PCA1, and the first pixel area PCA1 will be focused on and described. The description of the same elements is substantially the same and applies to elements of the second pixel area PCA2 and the third pixel area PCA3. Figure 20 and Figure 21 The cross-sectional view may be a cross-sectional view of the first pixel area PCA1. Figures 11 to 21 To describe Figure 20 and Figure 21 .

[0145] The substrate 100 may include a glass material, a ceramic material, a metal material, or a material having flexible or bendable properties. The substrate 100 may have a single-layer structure of an organic layer or a multi-layer structure of an organic layer and an inorganic layer. For example, the substrate 100 may have a stacked structure of a first base layer / a barrier layer / a second base layer. Each of the first base layer and the second base layer may be an organic layer including a polymer resin. The first base layer and the second base layer may include a transparent polymer resin. The barrier layer may be a barrier layer that prevents penetration of external foreign matter and may include a material such as silicon nitride (SiN x ) or silicon oxide (SiO x ) of a single layer or multiple layers of inorganic materials.

[0146] Reference Figure 11 , a first conductive layer may be provided on the substrate 100. The first conductive layer may include a reference voltage line VRL, a first electrode layer and / or a first driving voltage line PLh. According to another embodiment, a barrier layer may be further provided between the substrate 100 and the first conductive layer.

[0147] The reference voltage line VRL may extend in the x-direction and may be arranged throughout the first, second, and third pixel areas PCA1, PCA2, and PCA3.

[0148] The first driving voltage line PLh may include a main line PLm1 extending in the x-direction and a protruding line PLp extending and protruding from the main line PLm1 in the y-direction. The main line PLm1 of the first driving voltage line PLh may extend across the first pixel area PCA1, the second pixel area PCA2, and the third pixel area PCA3. The protruding line PLp may be provided in each pixel area so as to be adjacent to the boundary of an adjacent pixel area.

[0149] The first electrode layer may include a third electrode C13 of the first capacitor C1 and a first electrode C21 of the second capacitor C2, which are spaced apart from each other. The third electrode C13 of the first capacitor C1 may be configured as an island type. The first electrode C21 of the second capacitor C2 may be connected to a reference voltage line VRL. The first electrode C21 of the second capacitor C2 may be connected to the reference voltage line VRL via a connection portion CP. The first electrodes C21 of the second capacitors C2 in the first pixel area PCA1, the second pixel area PCA2, and the third pixel area PCA3 may be connected to each other. According to an embodiment, the first electrode C21 of the second capacitor C2, the connection portion CP, and the reference voltage line VRL may be integral with each other and may be provided on the same layer. The connection portion CP may be provided in one of the first pixel area PCA1, the second pixel area PCA2, and the third pixel area PCA3 (e.g., in the third pixel area PCA3).

[0150] According to an embodiment, the first conductive layer may further include a repair line RL. The repair line RL may extend in the x-direction and may be arranged throughout the first pixel area PCA1, the second pixel area PCA2, and the third pixel area PCA3.

[0151] The first insulating layer 111 may be provided on the substrate 100 while covering the first conductive layer, and the second conductive layer may be provided on the first insulating layer 111. Figure 12 As shown in , the second conductive layer may include a second electrode layer, a lower first gate line GWL1 , a first initialization voltage line VL1 , and a 2-2 nd initialization voltage line VL22 .

[0152] The second electrode layer can be configured as an island. A portion of the second electrode layer can serve as the second gate electrode G12, which serves as the lower gate electrode (bottom gate electrode) of the first transistor T1. Another portion of the second electrode layer can serve as the second electrode C12 of the first capacitor C1, and another portion of the second electrode layer can serve as the second electrode C22 of the second capacitor C2. The second electrode C12 of the first capacitor C1 can overlap with the third electrode C13 of the first capacitor C1. The second electrode C22 of the second capacitor C2 can overlap with the first electrode C21 of the second capacitor C2. An opening SOP1 can be defined in the second electrode layer.

[0153] The first initialization voltage line VL1 and the 2-2 initialization voltage line VL22 may each extend in the x-direction and may be disposed in the first, second, and third pixel areas PCA1, PCA2, and PCA3.

[0154] The second insulating layer 112 may be provided on the first insulating layer 111 while covering the second conductive layer, and the semiconductor layer ACT may be provided on the second insulating layer 112. The semiconductor layer ACT may include amorphous silicon, polycrystalline silicon, or an organic semiconductor material (such as an oxide semiconductor). Figure 13 As shown in FIG, the semiconductor layer ACT may include a first semiconductor layer ACT1, a second semiconductor layer ACT2, a third semiconductor layer ACT3, and a fourth semiconductor layer ACT4. The semiconductor layer ACT may include a channel region of each of the first to seventh transistors T1 to T7, and a source region and a drain region on the sides (e.g., both sides) of the channel region. In some embodiments, the source region or the drain region may be interpreted as the source electrode or the drain electrode of the transistor.

[0155] Reference Figure 15 The first semiconductor layer ACT1 may include the source region S1 and drain region D1 of the first transistor T1, and the source region S5 and drain region D5 of the fifth transistor T5. The second semiconductor layer ACT2 may include the source region S2 and drain region D2 of the second transistor T2, and the source region S3 and drain region D3 of the third transistor T3. The third semiconductor layer ACT3 may include the source region S6 and drain region D6 of the sixth transistor T6, and the source region S7 and drain region D7 of the seventh transistor T7. The fourth semiconductor layer ACT4 may include the source region S4 and drain region D4 of the fourth transistor T4.

[0156] A width (length in the x direction) of the channel region of the first transistor T1 in the third pixel area PCA3 may be greater than a width of the channel region of the first transistor T1 in each of the first and second pixel areas PCA1 and PCA2 .

[0157] In a comparative example in which the second capacitor C2 and the reference voltage line VRL are provided in different layers, a connection electrode serving as a bridge for connecting the first electrode C21 of the second capacitor C2 to the reference voltage line VRL may be required, and a space may be required for forming a contact hole for connecting the connection electrode to the reference voltage line VRL.

[0158] According to the embodiment, Figure 15 and Figure 20 As shown in FIG, since the first electrode C21 of the second capacitor C2 and the reference voltage line VRL are provided in the same layer, the wiring arrangement space can be reduced, thereby increasing the resolution and increasing the capacitance of the second capacitor C2.

[0159] The third insulating layer 113 may be provided on the second insulating layer 112 while covering the semiconductor layer ACT, and the third conductive layer may be provided on the third insulating layer 113. Figure 14As shown in FIG, the third conductive layer may include a third electrode layer and gate electrodes G2 to G7 of the second to seventh transistors T2 to T7. The third conductive layer may also include a first gate line GWL2, a second gate line GIL, a third gate line GRL, a fourth gate line EML, a fifth gate line EMBL, and a 2-1st initialization voltage line VL21. The third conductive layer may also include connecting electrodes 121 and 122. In the third insulating layer 113, only the region overlapping the third conductive layer may remain, and the remaining regions may be removed.

[0160] The third electrode layer may be configured in an island shape, and an opening SOP2 may be defined in the third electrode layer. A portion of the third electrode layer may be the first gate electrode G11, which serves as the upper gate electrode (top gate electrode) of the first transistor T1. Another portion of the third electrode layer may be the first electrode C11 of the first capacitor C1. The first electrode C11 of the first capacitor C1 may overlap with the second electrode C12 and the third electrode C13 of the first capacitor C1. The first electrode C11 of the first capacitor C1 may contact and be electrically connected to the third electrode C13 of the first capacitor C1 through a contact hole 21 that passes through the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113. The contact hole 21 may be located in the opening SOP1 of the second electrode C12 of the first capacitor C1. The first capacitor C1 may include the third electrode C13, the second electrode C12, and the first electrode C11, sequentially arranged in the z-direction on the substrate 100. The first electrode C11 and the third electrode C13 may be electrically connected to each other.

[0161] The upper first, second, third, GRL, fourth, and fifth gate lines GWL2, GIL, GRL, EML, EMBL, and 2-1st initialization voltage line VL21 may each extend in the x-direction and may be arranged throughout the first, second, and third pixel areas PCA1, PCA2, and PCA3.

[0162] The upper first gate line GWL2 may overlap the lower first gate line GWL1 and may be electrically connected to the lower first gate line GWL1 through a contact hole 24 passing through the second insulating layer 112 and the third insulating layer 113. The first gate line GWL may have a two-layer structure including the lower first gate line GWL1 and the upper first gate line GWL2 disposed at different layers.

[0163] Gate electrodes G1 to G7 of the first to seventh transistors T1 to T7 may overlap a channel region of the semiconductor layer ACT.

[0164] Reference Figure 15The first gate electrode G11 of the first transistor T1 may be configured as an island type. The first gate electrode G11 of the first transistor T1 may overlap the first semiconductor layer ACT1. The first gate electrode G11 of the first transistor T1 may overlap the second gate electrode G12. The gate electrode G2 of the second transistor T2 may be configured as an island type. The gate electrode G2 of the second transistor T2 may overlap the second semiconductor layer ACT2. The gate electrode G3 of the third transistor T3 may be a portion of the third gate line GRL that intersects (overlaps) the second semiconductor layer ACT2. The gate electrode G4 of the fourth transistor T4 may be a portion of the second gate line GIL that intersects (overlaps) the fourth semiconductor layer ACT4. The gate electrode G5 of the fifth transistor T5 may be a portion of the fourth gate line EML that intersects (overlaps) the first semiconductor layer ACT1. The gate electrode G6 of the sixth transistor T6 may be a portion of the fifth gate line EMBL that intersects (overlaps) the third semiconductor layer ACT3. The gate electrode G7 of the seventh transistor T7 may be a portion of the second gate line GIL that intersects (overlaps) the third semiconductor layer ACT3.

[0165] The connection electrode 121 may be electrically connected to the reference voltage line VRL through a contact hole 22 passing through the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113. The connection electrode 122 may be electrically connected to the first driving voltage line PLh through a contact hole 23 passing through the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113.

[0166] The fourth insulating layer 114 may be provided on the third conductive layer while covering the third conductive layer, and the fourth conductive layer may be provided on the fourth insulating layer 114. In the region from which the third insulating layer 113 has been removed, the fourth insulating layer 114 may be provided on the second insulating layer 112 to contact the upper surface of the second insulating layer 112. Figure 16 As shown in FIG, the fourth conductive layer may include data lines DL and connecting electrodes 131, 132, 133, 134, 135, 136, 137 and 138. For ease of illustration and description, Figure 16 Only the fourth conductive layer is shown.

[0167] The data line DL may be disposed to extend in the y direction in each pixel region and may be electrically connected to the drain region D2 of the second transistor T2 through a contact hole 31 passing through the fourth insulating layer 114 .

[0168] One end of the connection electrode 131 may be electrically connected to the gate electrode G2 of the second transistor T2 through a contact hole 32 passing through the fourth insulating layer 114 , and the other end of the connection electrode 131 may be electrically connected to the upper first gate line GWL2 through a contact hole 33 passing through the fourth insulating layer 114 .

[0169] The connection electrode 132 may be electrically connected to the source region S3 of the third transistor T3 through a contact hole 34 passing through the fourth insulating layer 114, and may be electrically connected to the connection electrode 121 through a contact hole 35 passing through the fourth insulating layer 114. Therefore, the source region S3 of the third transistor T3 may be electrically connected to the reference voltage line VRL.

[0170] One end of the connection electrode 133 can be electrically connected to the third electrode layer via a contact hole 36 passing through the fourth insulating layer 114, and thus can be electrically connected to the first gate electrode G11 of the first transistor T1. The other end of the connection electrode 133 can be electrically connected to the source region S2 of the second transistor T2 and the drain region D3 of the third transistor T3 via a contact hole 37 passing through the fourth insulating layer 114.

[0171] The connection electrode 134 may include a first region 134a overlapping the third electrode layer and a second region 134b protruding and extending in the y direction from the first region 134a. The connection electrode 134 may electrically connect the source region S1 of the first transistor T1 to the fourth and sixth transistors T4 and T6.

[0172] The first region 134a of the connecting electrode 134 can be electrically connected to the source region S1 of the first transistor T1 via a contact hole 38 passing through the fourth insulating layer 114. The first region 134a of the connecting electrode 134 can be electrically connected to the second electrode layer via a contact hole 39 passing through the second insulating layer 112 and the fourth insulating layer 114, and thus can be electrically connected to the second gate electrode G12 of the first transistor T1, the second electrode C12 of the first capacitor C1, and the second electrode C22 of the second capacitor C2. Contact holes 38 and 39 can be positioned in the opening SOP2 of the third electrode layer. The second region 134b of the connecting electrode 134 can be electrically connected to the drain region D6 of the sixth transistor T6 via a contact hole 40 passing through the fourth insulating layer 114. The second region 134b of the connecting electrode 134 can be electrically connected to the drain region D4 of the fourth transistor T4 via a contact hole 41 passing through the fourth insulating layer 114.

[0173] The connection electrode 135 may be electrically connected to the connection electrode 122 through a contact hole 43 passing through the fourth insulating layer 114, and may be electrically connected to the drain region D5 of the fifth transistor T5 through a contact hole 42 passing through the fourth insulating layer 114. Therefore, the drain region D5 of the fifth transistor T5 may be electrically connected to the first driving voltage line PLh.

[0174] One end of the connection electrode 136 may be electrically connected to the source region S6 of the sixth transistor T6 through a contact hole 44 passing through the fourth insulating layer 114. The other end of the connection electrode 136 may overlap a portion of the repair line RL. The other end of the connection electrode 136 may be insulated from the repair line RL and may be electrically connected to the repair line RL in the event that a defect occurs in a pixel circuit later disposed in the corresponding pixel region.

[0175] The connection electrode 137 may be electrically connected to the source region S4 of the fourth transistor T4 through a contact hole 45 passing through the fourth insulating layer 114 , and may be connected to the first initialization voltage line VL1 through a contact hole 46 passing through the fourth insulating layer 114 .

[0176] The connection electrode 138 may be electrically connected to the source region S7 of the seventh transistor T7 through a contact hole 47 passing through the fourth insulating layer 114, and may be connected to the second initialization voltage line VL2 through a contact hole 48 passing through the fourth insulating layer 114. According to an embodiment, the connection electrode 138 disposed in the first pixel area PCA1 may be electrically connected to the 2-1st initialization voltage line VL21 through a contact hole 48a, and the connection electrodes 138 disposed in the second pixel area PCA2 and the third pixel area PCA3 may be electrically connected to the 2-2nd initialization voltage line VL22 through contact holes 48b, respectively.

[0177] The fifth insulating layer 115 may be disposed on the fourth insulating layer 114 while covering the fourth conductive layer, and the fifth conductive layer may be disposed on the fifth insulating layer 115. Figures 17a to 17c As shown in , the fifth conductive layer may include vertical conductive lines and connecting electrodes 141. Figures 17a to 17c , for ease of illustration and description, only the fifth conductive layer and some of the conductive layers thereunder are shown.

[0178] The connection electrode 141 may be electrically connected to the connection electrode 136 through a contact hole 51 passing through the fifth insulating layer 115 , and may be electrically connected to the source region S6 of the sixth transistor T6 .

[0179] The vertical conductive lines may include a second drive voltage line PLv, a vertical initialization voltage line, a common voltage line EL, and a vertical reference voltage line VRLv. The vertical initialization voltage lines may include a first vertical initialization voltage line VL1v, a 2-1st vertical initialization voltage line VL21v, and a 2-2nd vertical initialization voltage line VL22v. The second drive voltage line PLv, the vertical initialization voltage line, the common voltage line EL, and the vertical reference voltage line VRLv may all extend in the y-direction and may be spaced apart from each other in the x-direction in the first, second, and third pixel areas PCA1, PCA2, and PCA3.

[0180] For each unit pixel area PCAu, the second driving voltage line PLv, one of the vertical initialization voltage lines, the common voltage line EL, and the vertical reference voltage line VRLv may be sequentially and repeatedly arranged in the x-direction. For each unit pixel area PCAu, one of the first vertical initialization voltage line VL1v, the 2-1st vertical initialization voltage line VL21v, and the 2-2nd vertical initialization voltage line VL22v may be arranged in the first pixel area PCA1 and the second pixel area PCA2. For example, the vertical conductive lines may be arranged in the x-direction in the order of the second driving voltage line PLv, the first vertical initialization voltage line VL1v, the common voltage line EL, the vertical reference voltage line VRLv, the second driving voltage line PLv, the 2-1st vertical initialization voltage line VL21v, the common voltage line EL, the vertical reference voltage line VRLv, the second driving voltage line PLv, the 2-2nd vertical initialization voltage line VL22v, the common voltage line EL, and the vertical reference voltage line VRLv.

[0181] Figure 17a An example is shown in which the second driving voltage line PLv, the first vertical initialization voltage line VL1v, the common voltage line EL, and the vertical reference voltage line VRLv are sequentially disposed in the x direction in the unit pixel area PCAu.

[0182] The second driving voltage line PLv may be disposed in the first pixel area PCA1. The second driving voltage line PLv may include a main line PLm2 extending in the y-direction, and a first region 145a, a second region 146a, and a third region 147a, each of which protrudes and extends from the main line PLm2 in the x-direction. The main line PLm2 may overlap the data line DL located in the first pixel area PCA1. The first region 145a may overlap the first gate line GWL and the reference voltage line VRL. An extension of the first region 145a may overlap the first initialization voltage line VL1, the 2-1st initialization voltage line VL21, and the 2-2nd initialization voltage line VL22 in a pixel area adjacent to the first pixel area PCA1 in the +y direction. The second region 146a may overlap the first transistor T1, the first capacitor C1, and the second capacitor C2. The third region 147a may overlap the first initialization voltage line VL1, the 2-1st initialization voltage line VL21, and the 2-2nd initialization voltage line VL22. The extension of the third region 147a may overlap the first gate line GWL and the reference voltage line VRL located in a pixel region adjacent to the first pixel region PCA1 in the -y direction. The second region 146a of the second driving voltage line PLv may be electrically connected to the connection electrode 135 of the first pixel region PCA1 via a contact hole 52 passing through the fifth insulating layer 115. Thus, the second driving voltage line PLv may be electrically connected to the first driving voltage line PLh. The driving voltage lines PL may have a mesh structure in the display area DA by including the first driving voltage line PLh and the second driving voltage line PLv.

[0183] The first vertical initialization voltage line VL1v may be disposed in the first pixel area PCA1 and the second pixel area PCA2. The first vertical initialization voltage line VL1v may include a main line VL1vm extending in the y-direction and a first region 145b, a second region 146b, a third region 147b, and a fourth region 148b, each of which protrudes and extends from the main line VL1vm in the x-direction. The first region 145b, the third region 147b, and the fourth region 148b may be located in the first pixel area PCA1, and the second region 146b may be located in the first pixel area PCA1 and the second pixel area PCA2.

[0184] The main line VL1vm may overlap the data line DL located in the second pixel area PCA2. The first region 145b may overlap the first gate line GWL and the reference voltage line VRL located in the first pixel area PCA1. An extension of the first region 145b may overlap the first initialization voltage line VL1, the 2-1st initialization voltage line VL21, and the 2-2nd initialization voltage line VL22 located in the pixel area adjacent to the first pixel area PCA1 in the +y direction. The second region 146b may overlap the first transistor T1, the first capacitor C1, and the second capacitor C2 located in the first and second pixel areas PCA1 and PCA2. The third region 147b may overlap the first initialization voltage line VL1, the 2-1st initialization voltage line VL21, and the 2-2nd initialization voltage line VL22 located in the first pixel area PCA1. An extension of the third region 147b may overlap the first gate line GWL and the reference voltage line VRL located in the pixel area adjacent to the first pixel area PCA1 in the -y direction.

[0185] The fourth region 148b may be positioned between the second region 146b and the third region 147b and may be electrically connected to the connection electrode 137 positioned in the first pixel area PCA1 through a contact hole 53 passing through the fifth insulating layer 115. Thus, the first vertical initialization voltage line VL1v may be electrically connected to the first initialization voltage line VL1, and the first initialization voltage line VL1 may have a mesh structure in the display area DA.

[0186] Figure 17b and Figure 17c The shapes of the connection electrode 138 and / or the vertical initialization voltage line may be different from Figure 16 and Figure 17a , and / or the shape of the connection electrode 138 and / or the vertical initialization voltage line shown in FIG.

[0187] like Figure 17b As shown in FIG, the 2-2nd vertical initialization voltage line VL22v can be provided in the first pixel region PCA1 and the second pixel region PCA2 of the unit pixel region PCAu. The 2-2nd vertical initialization voltage line VL22v can include a main line VL22vm extending in the y direction and a first region 145b, a second region 146b, a third region 147b, and a fourth region 148b, each of which protrudes and extends from the main line VL22vm in the x direction. The first region 145b and the third region 147b can be located in the first pixel region PCA1, the fourth region 148b can be located in the second pixel region PCA2, and the second region 146b can be located in the first pixel region PCA1 and the second pixel region PCA2.

[0188] The main line VL22vm may overlap the data line DL located in the second pixel area PCA2. The first region 145b may overlap the first gate line GWL and the reference voltage line VRL located in the first pixel area PCA1. An extension of the first region 145b may overlap the first initialization voltage line VL1, the 2-1st initialization voltage line VL21, and the 2-2nd initialization voltage line VL22 located in the pixel area adjacent to the first pixel area PCA1 in the +y direction. The second region 146b may overlap the first transistor T1, the first capacitor C1, and the second capacitor C2 located in the first and second pixel areas PCA1 and PCA2. The third region 147b may overlap the first initialization voltage line VL1, the 2-1st initialization voltage line VL21, and the 2-2nd initialization voltage line VL22 located in the first pixel area PCA1. An extension of the third region 147b may overlap the first gate line GWL and the reference voltage line VRL located in the pixel area adjacent to the first pixel area PCA1 in the -y direction.

[0189] The fourth region 148b can be electrically connected to the connection electrode 138 positioned in the second pixel area PCA2 through the contact hole 53 passing through the fifth insulating layer 115. The connection electrode 138 of the second pixel area PCA2 can be electrically connected to the 2-2nd initialization voltage line VL22 through the contact hole 48b. Therefore, the 2-2nd vertical initialization voltage line VL22v can be electrically connected to the 2-2nd initialization voltage line VL22, and the 2-2nd initialization voltage line VL22 can have a mesh structure in the display area DA.

[0190] like Figure 17c As shown in FIG, the 2-1st vertical initialization voltage line VL21v can be provided in the first pixel region PCA1 and the second pixel region PCA2 of the unit pixel region PCAu. The 2-1st vertical initialization voltage line VL21v can include a main line VL21vm extending in the y direction and a first region 145b, a second region 146b, a third region 147b, and a fourth region 148b, each of which protrudes and extends from the main line VL21vm in the x direction. The first region 145b, the third region 147b, and the fourth region 148b can be located in the first pixel region PCA1, and the second region 146b can be located in the first pixel region PCA1 and the second pixel region PCA2.

[0191] The main line VL21vm may overlap the data line DL located in the second pixel area PCA2. The first region 145b may overlap the first gate line GWL and the reference voltage line VRL located in the first pixel area PCA1. An extension of the first region 145b may overlap the first initialization voltage line VL1, the 2-1st initialization voltage line VL21, and the 2-2nd initialization voltage line VL22 located in the pixel area adjacent to the first pixel area PCA1 in the +y direction. The second region 146b may overlap the first transistor T1, the first capacitor C1, and the second capacitor C2 located in the first and second pixel areas PCA1 and PCA2. The third region 147b may overlap the first initialization voltage line VL1, the 2-1st initialization voltage line VL21, and the 2-2nd initialization voltage line VL22 located in the first pixel area PCA1. An extension of the third region 147b may overlap the first gate line GWL and the reference voltage line VRL located in the pixel area adjacent to the first pixel area PCA1 in the -y direction.

[0192] The fourth region 148b may be positioned between the second region 146b and the third region 147b and may be electrically connected to the connection electrode 138 positioned in the first pixel area PCA1 via a contact hole 53 passing through the fifth insulating layer 115. The connection electrode 138 of the first pixel area PCA1 may be electrically connected to the 2-1st initialization voltage line VL21 via the contact hole 48a. Thus, the 2-1st vertical initialization voltage line VL21v may be electrically connected to the 2-1st initialization voltage line VL21, and the 2-1st initialization voltage line VL21 may have a mesh structure in the display area DA.

[0193] A common voltage line EL may be provided in the second and third pixel areas PCA2 and PCA3. The common voltage line EL may extend in the y-direction and may include a first region 145c having a first width in the x-direction, a second region 146c having a second width smaller than the first width, and a third region 147c having the first width. The first, second, and third regions 145c and 146c may overlap with the data line DL located in the third pixel area PCA3. The first region 145c may overlap with the first gate line GWL, the reference voltage line VRL, and the third gate line GRL located in the second and third pixel areas PCA2 and PCA3. The third region 147c may overlap with the first transistor T1, the first capacitor C1, the second capacitor C2, the fourth gate line EML, the fifth gate line EMBL, the second gate line GIL, the first initialization voltage line VL1, the 2-1st initialization voltage line VL21, and the 2-2nd initialization voltage line VL22 located in the first and second pixel areas PCA1 and PCA2.

[0194] A vertical reference voltage line VRLv may be provided in the third pixel area PCA3. The vertical reference voltage line VRLv may include a main line VRLvm extending in the y-direction, and a first region 145d, a second region 146d, and a third region 147d, each of which protrudes and extends from the main line VRLvm in the x-direction. The first region 145d may overlap the first gate line GWL and the third gate line VRL. An extension of the first region 145d may overlap the first initialization voltage line VL1, the 2-1st initialization voltage line VL21, and the 2-2nd initialization voltage line VL22 in a pixel area adjacent to the third pixel area PCA3 in the +y-direction. The second region 146d may overlap the first transistor T1, the first capacitor C1, and the second capacitor C2. The third region 147d may overlap the first initialization voltage line VL1, the 2-1st initialization voltage line VL21, and the 2-2nd initialization voltage line VL22. The extension of the third region 147d may overlap the first gate line GWL and the reference voltage line VRL located in a pixel region adjacent to the third pixel region PCA3 in the -y direction. The first region 146d of the vertical reference voltage line VRLv may be electrically connected to the connection electrode 132 via a contact hole 54 passing through the fifth insulating layer 115. Thus, the vertical reference voltage line VRLv may be electrically connected to the reference voltage line VRL, and the reference voltage line VRL may have a mesh structure in the display area DA.

[0195] The connection electrodes 121 , 122 , 131 , 132 , 133 , 134 , 135 , 136 , 137 , 138 , and 141 of each of the first to third pixel areas PCA1 , PCA2 , and PCA3 may have different shapes depending on the positions of wirings arranged in the pixel areas.

[0196] The sixth insulating layer 116 may be disposed on the fifth insulating layer 115 while covering the fifth conductive layer, and as shown in FIG. Figure 18 As shown in FIG, an organic light emitting diode OLED as a display element may be disposed on the sixth insulating layer 116 . Figure 18 Shows the settings Figure 17a The organic light emitting diode on the unit pixel area shown in FIG.

[0197] According to an embodiment, the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114 may be inorganic insulating layers, and the fifth insulating layer 115 and the sixth insulating layer 116 may be organic insulating layers. The inorganic insulating layer may include an inorganic material including oxide or nitride. For example, the inorganic insulating layer may include silicon oxide (SiO2), silicon nitride (SiN x), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2). The organic insulating layer may include at least one of an organic material such as acryl, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO).

[0198] Figure 19 Shown as Figure 18 Each organic light emitting diode OLED may include a pixel electrode 211 , an opposing electrode 215 , and an emission layer 213 a positioned between the pixel electrode 211 and the opposing electrode 215 . Figure 19 The pixel electrode 211 and the emission layer 213 a of the first pixel PX1 , the pixel electrode 211 and the emission layer 213 b of the second pixel PX2 , and the pixel electrode 211 and the emission layer 213 c of the third pixel PX3 are shown. Figure 20 and Figure 21 An organic light emitting diode OLED including a pixel electrode 211 of a first pixel PX1 , an emission layer 213 a , and an opposing electrode 215 is shown.

[0199] The pixel electrode 211 may be connected to the pixel circuit by being electrically connected to the lower connection electrode through the contact hole 61 of the sixth insulating layer 116. Figure 19 , the pixel electrode 211 of the first pixel PX1 can be electrically connected to the first transistor T1 by being electrically connected to the connection electrode 141 provided in the first pixel area PCA1. The pixel electrode 211 of the second pixel PX2 can be electrically connected to the first transistor T1 by being electrically connected to the connection electrode 141 provided in the second pixel area PCA2. The pixel electrode 211 of the third pixel PX3 can be electrically connected to the first transistor T1 by being electrically connected to the connection electrode 141 provided in the third pixel area PCA3.

[0200] According to an embodiment, the pixel electrode 211 of the first pixel PX1 and the pixel electrode 211 of the second pixel PX2 may overlap with the pixel circuit of the first pixel area PCA1 and may be arranged adjacent to each other in the y direction. The pixel electrode 211 of the third pixel PX3 may overlap with the pixel circuits of the second pixel area PCA2 and the third pixel area PCA3. For example, each of the pixel electrode 211 of the first pixel PX1 and the pixel electrode 211 of the second pixel PX2 may have an approximately square shape, while the pixel electrode 211 of the third pixel PX3 may have a rectangular shape with a longer side in the y direction.

[0201] A pixel defining layer 117 covering an edge of the pixel electrode 211 may be disposed on the sixth insulating layer 116. An opening 117OP exposing a portion of the pixel electrode 211 and defining an emission region may be defined in the pixel defining layer 117. The pixel defining layer 117 may be a single-layer organic insulating layer or multiple organic insulating layers and / or a single-layer or multiple inorganic insulating layers.

[0202] The opposing electrode 215 may be integrally formed to correspond to the organic light emitting diode OLED included in the display area DA.

[0203] Figure 22 is a schematic diagram of an equivalent circuit PCa of a pixel PXa according to an embodiment. Figure 23 and Figure 24 is shown for explanation Figure 22 Schematic diagram of the operation signals of the pixel PXa.

[0204] Figure 22 The pixel PXa and Figure 4 The pixel PX of FIG. 1 may be different in that the gate of the seventh transistor T7 is connected to the sixth gate line GBL for supplying the sixth gate signal GB. Figure 2 In the display device 10 shown in , a sixth gate line GBL may be further provided in the pixel portion 11 , and the gate driving circuit 13 may further generate a sixth gate signal GB.

[0205] like Figure 23 and Figure 24 As shown in FIG, the pixel PXa can operate in one first scanning period AS and one second scanning period SS during one frame 1F. Figures 4 to 7 The differences in the operation of the pixel PX are described.

[0206] like Figure 23 As shown in , the first scanning period AS may include a first non-emission period ND1 in which the pixel PXa does not emit light and a first emission period DD1 in which the pixel PXa emits light. The first non-emission period ND1 may include a first period P1, a second period P2, a third period P3, and a fourth period P4.

[0207] During a first period P1, a second gate signal GI having a turn-on voltage may be supplied (applied) to the second gate line GIL, and a sixth gate signal GB having a turn-on voltage may be supplied to the sixth gate line GBL. A third gate signal GR having a turn-on voltage may be supplied to the third gate line GRL. The fourth transistor T4 may be turned on by the second gate signal GI, and the third transistor T3 may be turned on by the third gate signal GR. The second terminal of the first transistor T1 may be initialized to a first initialization voltage Vint by the turned-on fourth transistor T4. The first gate of the first transistor T1 may be initialized to a reference voltage Vref by the turned-on third transistor T3. The seventh transistor T7 may be turned on by the sixth gate signal GB, and the pixel electrode of the organic light emitting diode OLED may be initialized to a second initialization voltage Vaint by the turned-on seventh transistor T7.

[0208] During the second period P2, a third gate signal GR having a turn-on voltage may be supplied to the third gate line GRL, and a fourth gate signal EM may be supplied to the fourth gate line EML. The third transistor T3 may be turned on by the third gate signal GR, and the fifth transistor T5 may be turned on by the fourth gate signal EM. Therefore, the threshold voltage (Vth) of the first transistor T1 may be compensated by storing a voltage corresponding to the threshold voltage (Vth) of the first transistor T1 in the first capacitor C1.

[0209] During the third period P3, a first gate signal GW having a turn-on voltage may be supplied to the first gate line GWL. The second transistor T2 may be turned on by the first gate signal GW, and the turned-on second transistor T2 may transmit the data signal Vdata from the data line DL to the first gate of the first transistor T1. Therefore, the first capacitor C1 may be charged with a voltage corresponding to the threshold voltage (Vth) of the first transistor T1 and the data signal Vdata.

[0210] During a fourth period P4, a second gate signal GI having a turn-on voltage may be supplied (applied) to the second gate line GIL, and a sixth gate signal GB having a turn-on voltage may be supplied to the sixth gate line GBL. The fourth transistor T4 may be turned on by the second gate signal GI, and the first initialization voltage Vint may be transmitted to the second terminal of the first transistor T1 via the turned-on fourth transistor T4. The seventh transistor T7 may be turned on by the sixth gate signal GB, and the second initialization voltage Vaint may be transmitted to the pixel electrode of the organic light emitting diode OLED via the turned-on seventh transistor T7.

[0211] During the first emission period DD1, a fourth gate signal EM having a turn-on voltage may be supplied to the fourth gate line EML, and a fifth gate signal EMB having a turn-on voltage may be supplied to the fifth gate line EMBL. The fifth transistor T5 may be turned on by the fourth gate signal EM, and the first drive voltage ELVDD may be supplied to the first terminal of the first transistor T1 through the turned-on fifth transistor T5. The sixth transistor T6 may be turned on by the fifth gate signal EMB, and the first transistor T1 may output a drive current having a magnitude corresponding to a voltage corresponding to the data signal Vdata stored in the first capacitor C1, and the organic light emitting diode OLED may emit light having a brightness corresponding to the magnitude of the drive current.

[0212] like Figure 24 As shown in , the second scanning period SS may include a second non-emission period ND2 in which the pixel PXa does not emit light and a second emission period DD2 in which the pixel PXa emits light. The second non-emission period ND2 may include a fifth period P5 and a sixth period P6. The second scanning period SS may not include a compensation period corresponding to the second period P2 of the first scanning period AS and a writing period corresponding to the third period P3 of the first scanning period AS.

[0213] During the fifth period P5, a sixth gate signal GB having a turn-on voltage may be supplied to the sixth gate line GBL. The seventh transistor T7 may be turned on by the sixth gate signal GB, and the pixel electrode of the organic light emitting diode OLED may be initialized to the second initialization voltage Vaint by the turned-on seventh transistor T7.

[0214] During the sixth period P6, a sixth gate signal GB having a turn-on voltage may be supplied to the sixth gate line GBL. The seventh transistor T7 may be turned on by the sixth gate signal GB, and the pixel electrode of the organic light emitting diode OLED may be initialized to the second initialization voltage Vaint by the turned-on seventh transistor T7.

[0215] During the second emission period DD2, a fourth gate signal EM having a turn-on voltage may be supplied to the fourth gate line EML, and a fifth gate signal EMB having a turn-on voltage may be supplied to the fifth gate line EMBL. The fifth transistor T5 may be turned on by the fourth gate signal EM, and the first drive voltage ELVDD may be supplied to the first terminal of the first transistor T1 through the turned-on fifth transistor T5. The sixth transistor T6 may be turned on by the fifth gate signal EMB, and the first transistor T1 may output a drive current having a magnitude corresponding to the voltage stored in the first capacitor C1 (e.g., the data signal Vdata), and the organic light emitting diode OLED may emit light having a brightness corresponding to the magnitude of the drive current. The data signal Vdata stored in the first capacitor C1 during the second emission period DD2 may be the data signal supplied to the pixel and maintained during the third period P3 of the first scan period AS.

[0216] In each of the first emission period DD1 and the second emission period DD2, the turn-on voltage application timing of the fifth gate signal EMB may be delayed from the turn-on voltage application timing of the fourth gate signal EM by a time period DT (eg, a predetermined or selectable time period). Figures 22 to 24 In an embodiment, by initializing the pixel electrode in the fifth and sixth periods P5 and P6 of the second scanning period SS, which correspond to periods before and after the compensation period of the first scanning period AS, luminance deviation according to driving speed can be minimized even when one or more second scanning periods SS are included in a frame. By initializing the drive transistor only in the first scanning period AS, the occurrence of spots (mura) caused by a voltage drop of the first initialization voltage of the screen can be minimized.

[0217] exist Figures 22 to 24 In an embodiment, during one frame, the first gate signal GW, the second gate signal GI, and the third gate signal GR may be supplied only in the first scanning period AS, and the sixth gate signal GB may be supplied in the first scanning period AS and the second scanning period SS. The fourth gate signal EM and the fifth gate signal EMB may be supplied in the first scanning period AS and the second scanning period SS. In other words, during one frame, the period of each of the first gate signal GW, the second gate signal GI, and the third gate signal GR may be one cycle, and the period of each of the fourth gate signal EM, the fifth gate signal EMB, and the sixth gate signal GB may be two cycles.

[0218] According to another embodiment, the fourth period P4 of the first scanning period AS and the sixth period P6 of the second scanning period SS may be omitted.

[0219] Although not shown in the drawings, according to another embodiment, in addition to the reference voltage line VRL, the second capacitor C2 may be connected to a conductive line to which a voltage supplied at intervals of one cycle during one frame is applied or a conductive line having no voltage fluctuation during one frame. For example, the second capacitor C2 may be connected between the first initialization voltage line VL1 and the second node N2, or between the second initialization voltage line VL2 and the second node N2. Alternatively, according to another embodiment, as Figure 25 As shown in FIG, in the pixel PX″, the second capacitor C2 may be connected between the common voltage line EL to which the second driving voltage ELVSS is applied and the second node N2.

[0220] Figure 26 and Figure 27 Schematic diagrams of equivalent circuits PCb and PCc of pixels PXb and PXc according to an embodiment.

[0221] Figure 26 The pixel PXb is Figure 4 The pixel PX of the embodiment may be different in at least that: the second capacitor C2 is connected between the driving voltage line PL and the second node N2, and the third capacitor C3 is added between the second node N2 and the third node N3. The first electrode of the third capacitor C3 may be connected to the second node N2, and the second electrode of the third capacitor C3 may be connected to the third node N3. The second electrode of the third capacitor C3 may be provided on the first electrode of the third capacitor C3 and may be electrically connected to the pixel electrode of the organic light emitting diode OLED. According to an embodiment, the first electrode of the third capacitor C3 is connected to the second electrode C22 of the second capacitor C2 (see Figure 20 ) can be provided on the same layer, and the second electrode of the third capacitor C3 can be the semiconductor layer of the sixth transistor T6 (eg, Figure 13 A portion of the third semiconductor layer ACT3).

[0222] Even when the voltage of the second node N2 varies according to the variation of the first driving voltage ELVDD, the third capacitor C3 may be provided between the second node N2 and the third node N3, so that the voltage of the second node N2 may be compensated by the parasitic capacitor Coled of the organic light emitting diode OLED.

[0223] Figure 26 The pixel PXb shown in FIG can be in a frame period Figure 6 The first scanning period AS and Figure 7 The system operates in one or more second scanning periods SS.

[0224] Figure 27 The pixel PXc is Figure 26The pixel PXb may be different at least in that the gate of the seventh transistor T7 is connected to a sixth gate line GBL for supplying a sixth gate signal GB. Figure 27 The pixel PXc shown in FIG can be Figure 23 The first scanning period AS and Figure 24 The system operates in one or more second scanning periods SS.

[0225] Figures 28a to 29b is a schematic cross-sectional view of the structure of a display element according to an embodiment.

[0226] The organic light emitting diode OLED as a display element according to the embodiment may include a pixel electrode 211 , an opposing electrode 215 , and an intermediate layer 213 between the pixel electrode 211 (first electrode, anode) and the opposing electrode 215 (second electrode, cathode).

[0227] The pixel electrode 211 may include a light-transmitting conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). The pixel electrode 211 may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound of these materials. For example, the pixel electrode 211 may have a multilayer structure of ITO / Ag / ITO.

[0228] The counter electrode 215 may be disposed on the intermediate layer 213. The counter electrode 215 may include a metal, alloy, electrically conductive compound, or any combination thereof, all having a low work function. For example, the counter electrode 215 may include lithium (Li), silver (Ag), magnesium (Mg), aluminum (Al), aluminum-lithium (Al-Li), calcium (Ca), magnesium-indium (Mg-In), magnesium-silver (Mg-Ag), ytterbium (Yb), silver-ytterbium (Ag-Yb), ITO, IZO, or any combination thereof. The counter electrode 215 may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode.

[0229] The intermediate layer 213 may include a low-molecular or high-molecular organic material that emits light of a specific color. In addition to various organic materials, the intermediate layer 213 may also include metal-containing compounds (such as organometallic compounds), inorganic materials (such as quantum dots), etc.

[0230] According to an embodiment, the intermediate layer 213 may include an emission layer and a first functional layer and a second functional layer below and above the emission layer, respectively. The first functional layer may include a hole transport layer HTL, or may include a hole transport layer HTL and a hole injection layer HIL. The second functional layer may include an electron transport layer ETL and / or an electron injection layer EIL. The first functional layer or the second functional layer may be omitted. The first functional layer and the second functional layer may be integrated with each other to correspond to the organic light emitting diode OLED included in the display area DA.

[0231] According to embodiments, the intermediate layer 213 may include two or more emission portions sequentially stacked one above the other between the pixel electrode 211 and the counter electrode 215, and a charge generation layer (CGL) disposed between the two emission portions. When the intermediate layer 213 includes the emission portion and the charge generation layer (CGL), the organic light emitting diode (OLED) may be a tandem light emitting device. The organic light emitting diode (OLED) may improve color purity and luminous efficiency by having a stacked structure of emission portions.

[0232] The emission portion may include an emission layer and a first functional layer and a second functional layer below and above the emission layer, respectively. The charge generation layer (CGL) may include a negative charge generation layer and a positive charge generation layer. The luminous efficiency of an organic light-emitting diode (OLED), which is a tandem light-emitting device including an emission layer, may be further improved by the negative charge generation layer and the positive charge generation layer.

[0233] The negative charge generation layer may be an n-type charge generation layer. The negative charge generation layer may supply electrons. The negative charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material. The positive charge generation layer may be a p-type charge generation layer. The positive charge generation layer may supply holes. The positive charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material.

[0234] According to the embodiment, Figure 28aAs shown in , the organic light emitting diode OLED may include a first emission unit EU1 and a second emission unit EU2 stacked sequentially on each other, the first emission unit EU1 including a first emission layer EML1, and the second emission unit EU2 including a second emission layer EML2. The charge generation layer CGL may be placed between the first emission unit EU1 and the second emission unit EU2. For example, the organic light emitting diode OLED may include a pixel electrode 211, a first emission layer EML1, a charge generation layer CGL, a second emission layer EML2, and a counter electrode 215 sequentially stacked on each other. The first functional layer and the second functional layer may be respectively arranged below and above the first emission layer EML1. The first functional layer and the second functional layer may be respectively arranged below and above the second emission layer EML2. The first emission layer EML1 may be a blue emission layer, and the second emission layer EML2 may be a yellow emission layer.

[0235] According to the embodiment, Figure 28b As shown in , the organic light emitting diode OLED may include a first emission unit EU1 and a third emission unit EU3, each including a first emission layer EML1, and a second emission unit EU2 including a second emission layer EML2. The first charge generation layer CGL1 may be arranged between the first emission unit EU1 and the second emission unit EU2, and the second charge generation layer CGL2 may be arranged between the second emission unit EU2 and the third emission unit EU3. For example, the organic light emitting diode OLED may include a pixel electrode 211, a first emission layer EML1, a first charge generation layer CGL1, a second emission layer EML2, a second charge generation layer CGL2, a first emission layer EML1, and a counter electrode 215 sequentially stacked on each other. The first functional layer and the second functional layer may be arranged below and above the first emission layer EML1, respectively. The first functional layer and the second functional layer may be arranged below and above the second emission layer EML2, respectively. The first emission layer EML1 may be a blue emission layer, and the second emission layer EML2 may be a yellow emission layer.

[0236] According to an embodiment, in the organic light emitting diode OLED, in addition to the second emission layer EML2, the second emission unit EU2 may further include a third emission layer EML3 and / or a fourth emission layer EML4 disposed below and / or above the second emission layer EML2 so as to directly contact the second emission layer EML2. "Direct contact" may mean that no other layer is disposed between the second emission layer EML2 and the third emission layer EML3 and / or between the second emission layer EML2 and the fourth emission layer EML4. The third emission layer EML3 may be a red emission layer, and the fourth emission layer EML4 may be a green emission layer.

[0237] For example, Figure 28cAs shown in , the organic light emitting diode OLED may include a pixel electrode 211, a first emission layer EML1, a first charge generation layer CGL1, a third emission layer EML3, a second emission layer EML2, a second charge generation layer CGL2, a first emission layer EML1, and an opposing electrode 215 sequentially stacked on each other. As another example, as Figure 28d As shown in the figure, the organic light emitting diode OLED may include a pixel electrode 211, a first emission layer EML1, a first charge generation layer CGL1, a third emission layer EML3, a second emission layer EML2, a fourth emission layer EML4, a second charge generation layer CGL2, a first emission layer EML1 and a counter electrode 215 sequentially stacked on each other.

[0238] Figure 29a It shows Figure 28c A schematic cross-sectional view of an example of an organic light-emitting diode, Figure 29b It shows Figure 28d Schematic cross-sectional view of an example of an organic light emitting diode.

[0239] Reference Figure 29a The organic light emitting diode OLED may include a first emission unit EU1, a second emission unit EU2, and a third emission unit EU3 sequentially stacked on each other. A first charge generation layer CGL1 may be disposed between the first emission unit EU1 and the second emission unit EU2, and a second charge generation layer CGL2 may be disposed between the second emission unit EU2 and the third emission unit EU3. Each of the first charge generation layer CGL1 and the second charge generation layer CGL2 may include a negative charge generation layer nCGL and a positive charge generation layer pCGL.

[0240] The first emission unit EU1 may include a blue emission layer BEML. The first emission unit EU1 may further include a hole injection layer HIL and a hole transport layer HTL between the pixel electrode 211 and the blue emission layer BEML. According to an embodiment, a p-doped layer may be further included between the hole injection layer HIL and the hole transport layer HTL. The p-doped layer may be formed by doping the hole injection layer HIL with a p-type dopant material. According to an embodiment, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may be further included between the blue emission layer BEML and the hole transport layer HTL. The blue light auxiliary layer may improve the luminous efficiency of the blue emission layer BEML. The blue light auxiliary layer may improve the luminous efficiency of the blue emission layer BEML by adjusting the hole charge balance. The electron blocking layer may prevent electrons from being injected into the hole transport layer HTL. The buffer layer may compensate for the resonance distance according to the wavelength of light emitted by the emission layer.

[0241] The second emission unit EU2 may include a yellow emission layer YEML and a red emission layer REML directly contacting the yellow emission layer YEML below the yellow emission layer YEML. The second emission unit EU2 may also include a hole transport layer HTL between the positive charge generation layer pCGL of the first charge generation layer CGL1 and the red emission layer REML, and may also include an electron transport layer ETL between the yellow emission layer YEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0242] The third emission unit EU3 may include a blue emission layer BEML. The third emission unit EU3 may also include a hole transport layer HTL between the positive charge generation layer pCGL of the second charge generation layer CGL2 and the blue emission layer BEML. The third emission unit EU3 may also include an electron transport layer ETL and an electron injection layer EIL between the blue emission layer BEML and the counter electrode 215. The electron transport layer ETL may be a single layer or a multilayer. According to an embodiment, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may be further included between the blue emission layer BEML and the hole transport layer HTL. At least one of a hole blocking layer and a buffer layer may also be included between the blue emission layer BEML and the electron transport layer ETL. The hole blocking layer may prevent holes from being injected into the electron transport layer ETL.

[0243] In addition to the stacked structure of the second emission unit EU2, Figure 29b The organic light emitting diode OLED shown in Figure 29a The organic light emitting diode OLED shown in FIG. Figure 29b The second emission unit EU2 may include a yellow emission layer YEML, a red emission layer REML directly contacting the yellow emission layer YEML below the yellow emission layer YEML, and a green emission layer GEML directly contacting the yellow emission layer YEML above the yellow emission layer YEML. The second emission unit EU2 may further include a hole transport layer HTL between the positive charge generation layer pCGL of the first charge generation layer CGL1 and the red emission layer REML, and may further include an electron transport layer ETL between the green emission layer GEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0244] Figure 30 is a schematic cross-sectional view of a structure of a pixel of a display device according to an embodiment.

[0245] Reference Figure 30The display device may include pixels. The pixels may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a pixel electrode 211, an opposing electrode 215, and an intermediate layer 213. According to an embodiment, the first pixel PX1 may be a red pixel, the second pixel PX2 may be a green pixel, and the third pixel PX3 may be a blue pixel. Each pixel may include an organic light emitting diode (OLED) as a display element, and the organic light emitting diode OLED of each pixel may be electrically connected to the pixel circuit.

[0246] The pixel electrode 211 may be independently included in the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 .

[0247] The intermediate layer 213 of the organic light emitting diode OLED of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a first emission unit EU1 and a second emission unit EU2 sequentially stacked on each other, and a charge generation layer CGL between the first emission unit EU1 and the second emission unit EU2. The charge generation layer may include a negative charge generation layer nCGL and a positive charge generation layer pCGL. The charge generation layer CGL may be a common layer continuously formed in the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0248] The first emission unit EU1 of the first pixel PX1 may include a hole injection layer HIL, a hole transport layer HTL, a red emission layer REML, and an electron transport layer ETL sequentially stacked on the pixel electrode 211. The first emission unit EU1 of the second pixel PX2 may include a hole injection layer HIL, a hole transport layer HTL, a green emission layer GEML, and an electron transport layer ETL sequentially stacked on the pixel electrode 211. The first emission unit EU1 of the third pixel PX3 may include a hole injection layer HIL, a hole transport layer HTL, a blue emission layer BEML, and an electron transport layer ETL sequentially stacked on the pixel electrode 211. Each of the hole injection layer HIL, the hole transport layer HTL, and the electron transport layer ETL of the first emission unit EU1 may be a common layer continuously formed in the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0249] The second emission unit EU2 of the first pixel PX1 may include a hole transport layer HTL, an auxiliary layer AXL, a red emission layer REML, and an electron transport layer ETL sequentially stacked on the charge generation layer CGL. The second emission unit EU2 of the second pixel PX2 may include a hole transport layer HTL, a green emission layer GEML, and an electron transport layer ETL sequentially stacked on the charge generation layer CGL. The second emission unit EU2 of the third pixel PX3 may include a hole transport layer HTL, a blue emission layer BEML, and an electron transport layer ETL sequentially stacked on the charge generation layer CGL. Each of the hole transport layer HTL and the electron transport layer ETL of the second emission unit EU2 may be a common layer continuously formed in the first pixel PX1, the second pixel PX2, and the third pixel PX3. According to an embodiment, at least one of a hole blocking layer and a buffer layer may be included between the emission layer and the electron transport layer ETL in the second emission unit EU2 of the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0250] The thickness H1 of the red emission layer REML, the thickness H2 of the green emission layer GEML, and the thickness H3 of the blue emission layer BEML can be determined based on the resonance distance. The auxiliary layer AXL is a layer added to adjust the resonance distance and can include a resonance-assisting material. For example, the auxiliary layer AXL and the hole transport layer HTL can include the same material.

[0251] exist Figure 30 In the embodiment, only the first pixel PX1 may include the auxiliary layer AXL. However, the embodiment is not limited thereto. For example, the auxiliary layer AXL may be included in at least one of the first pixel PX1, the second pixel PX2, and the third pixel PX3 to adjust the resonance distance of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0252] The display device may further include a capping layer 217 disposed outside the counter electrode 215. The capping layer 217 may be used to improve luminous efficiency based on the principle of constructive interference. Thus, the light extraction efficiency of the organic light emitting diode (OLED) may be increased, thereby improving the luminous efficiency of the organic light emitting diode (OLED).

[0253] While the disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the claims.

Claims

1. A display device, comprising: Multiple pixels, Each of the plurality of pixels comprises: a first transistor comprising a first terminal, a second terminal, a first gate, and a second gate connected to the second terminal; a second transistor connected to the first gate of the first transistor and a data line; a third transistor connected to the first gate of the first transistor and a first voltage line; a fourth transistor connected to the first terminal of the first transistor and a second voltage line; a first capacitor including a first electrode connected to the first gate of the first transistor and a second electrode connected to the second terminal of the first transistor; and a second capacitor including a first electrode connected to the first voltage line and a second electrode connected to the second terminal of the first transistor, and The first electrode of the second capacitor and the first voltage line are disposed on the same layer.

2. The display device according to claim 1, wherein The second electrode of the second capacitor is connected to the second gate of the first transistor.

3. The display device according to claim 1, wherein The first electrode of the first capacitor includes an upper electrode and a lower electrode, The upper electrode and the first gate of the first transistor are arranged on the same layer, The lower electrode and the first electrode of the second capacitor are provided on the same layer, and The lower electrode is connected to the upper electrode. The display device according to claim 1 , wherein: During one frame, a gate signal is supplied to the gate of the third transistor once, and a gate signal is supplied to the gate of the fourth transistor two or more times.

5. The display device according to claim 1, wherein Each pixel of the plurality of pixels further comprises: a fifth transistor connected to the second terminal of the first transistor and a third voltage line; a sixth transistor connected to the second terminal of the first transistor and a light emitting diode; and a seventh transistor connected to the light emitting diode and a fourth voltage line, and The same gate signal is supplied to the gate of the fifth transistor and the gate of the seventh transistor. The display device according to claim 5 , wherein: A gate signal is applied to the gate of the fourth transistor at a timing prior to a gate signal being applied to the gate of the sixth transistor.

7. The display device according to claim 1, wherein Each pixel of the plurality of pixels further comprises: a fifth transistor connected to the second terminal of the first transistor and a third voltage line; a sixth transistor connected to the second terminal of the first transistor and a light emitting diode; and a seventh transistor connected to the light emitting diode and a fourth voltage line, and A gate signal supplied to the gate of the fifth transistor is different from a gate signal supplied to the gate of the seventh transistor.

8. The display device according to claim 7, wherein During one frame, a gate signal is supplied to the gate of the fifth transistor once, and a gate signal is supplied to the gate of the seventh transistor two or more times.

9. The display device according to claim 1, wherein One frame includes a first scanning period and a second scanning period, the first scanning period includes a first non-transmission period and a first transmission period, and the second scanning period includes a second non-transmission period and a second transmission period. Each of the plurality of pixels further includes a fifth transistor connected to the second terminal of the first transistor and a third voltage line, and The first non-emission period includes: a writing period, in which a first gate signal is applied to the gate of the second transistor; a first period, before the writing period, in which a second gate signal is applied to the gate of the fifth transistor in the first period, and a third gate signal is applied to the gate of the third transistor in the first period; and a second period, between the writing period and the first period, in which the third gate signal is applied to the gate of the third transistor in the second period, and a fourth gate signal is applied to the gate of the fourth transistor in the second period.

10. The display device according to claim 9, wherein The second non-emission period includes a third period in which the second gate signal is applied to the gate of the fifth transistor.

11. A display device, comprising: Multiple pixels, Each of the plurality of pixels comprises: a first transistor comprising a first terminal, a second terminal, a first gate, and a second gate connected to the second terminal; a second transistor connected to the first gate of the first transistor and a data line; a third transistor connected to the first gate of the first transistor and a first voltage line; a fourth transistor connected to the first terminal of the first transistor and a second voltage line; a fifth transistor connected to the second terminal of the first transistor and the light emitting diode; a first capacitor including a first electrode connected to the first gate of the first transistor and a second electrode connected to the second terminal of the first transistor; and a second capacitor including a first electrode connected to the first voltage line and a second electrode connected to the second terminal of the first transistor, and A gate signal is applied to the gate of the fourth transistor at a timing prior to a gate signal being applied to the gate of the fifth transistor.

12. The display device according to claim 11, wherein The second electrode of the second capacitor is connected to the second gate of the first transistor.

13. The display device according to claim 11, wherein The first electrode of the first capacitor includes an upper electrode and a lower electrode, The upper electrode and the first gate of the first transistor are arranged on the same layer, The lower electrode and the first electrode of the second capacitor are provided on the same layer, and The lower electrode is connected to the upper electrode.

14. The display device according to claim 11, wherein During one frame, a gate signal is supplied to the gate of the third transistor once, and a gate signal is supplied to the gate of the fourth transistor two or more times.

15. The display device according to claim 11, wherein Each pixel of the plurality of pixels further comprises: a sixth transistor connected to the second terminal of the first transistor and a third voltage line; and a seventh transistor connected to the light emitting diode and a fourth voltage line, and The same gate signal is supplied to the gate of the sixth transistor and the gate of the seventh transistor.

16. The display device according to claim 11, wherein Each pixel of the plurality of pixels further comprises: a sixth transistor connected to the second terminal of the first transistor and a third voltage line; and a seventh transistor connected to the light emitting diode and a fourth voltage line, and A gate signal supplied to the gate of the sixth transistor is different from a gate signal supplied to the gate of the seventh transistor.

17. The display device according to claim 16, wherein During one frame, a gate signal is supplied to the gate of the sixth transistor once, and a gate signal is supplied to the gate of the seventh transistor two or more times.

18. A display device, comprising: Multiple pixels, Each of the plurality of pixels comprises: a first transistor comprising a first terminal, a second terminal, a first gate, and a second gate connected to the second terminal; a second transistor connected to the first gate of the first transistor and a data line; a third transistor connected to the first gate of the first transistor and a first voltage line; a fourth transistor connected to the first terminal of the first transistor and a second voltage line; a first capacitor comprising a first electrode connected to the first gate of the first transistor and a second electrode connected to the second terminal of the first transistor; a second capacitor including a first electrode connected to the second voltage line and a second electrode connected to the second terminal of the first transistor; and A third capacitor includes a first electrode connected to the second terminal of the first transistor and a second electrode connected to one electrode of the light emitting diode.

19. The display device according to claim 18, wherein Each pixel of the plurality of pixels further comprises: a fifth transistor connected to the second terminal of the first transistor and a third voltage line; a sixth transistor connected to the second terminal of the first transistor and the light emitting diode; and a seventh transistor connected to the light emitting diode and a fourth voltage line, The same gate signal is supplied to the gate of the fifth transistor and the gate of the seventh transistor, and A gate signal is applied to the gate of the fourth transistor at a timing prior to a gate signal being applied to the gate of the sixth transistor.

20. The display device according to claim 1, wherein Each pixel of the plurality of pixels further comprises: a fifth transistor connected to the second terminal of the first transistor and a third voltage line; a sixth transistor connected to the second terminal of the first transistor and the light emitting diode; and a seventh transistor connected to the light emitting diode and a fourth voltage line, A gate signal supplied to the gate of the fifth transistor is different from a gate signal supplied to the gate of the seventh transistor, and A gate signal is applied to the gate of the fourth transistor at a timing prior to a gate signal being applied to the gate of the sixth transistor.

21. A display device, comprising: Multiple pixels, Each of the plurality of pixels comprises: a first transistor comprising a first terminal, a second terminal, a first gate, and a second gate connected to the second terminal; a second transistor connected to the first gate of the first transistor and a data line; a third transistor connected to the first gate of the first transistor and a first voltage line; a fourth transistor connected to the first terminal of the first transistor and a second voltage line; a fifth transistor connected to the second terminal of the first transistor and the first electrode of the light emitting diode; a first capacitor including a first electrode connected to the first gate of the first transistor and a second electrode connected to the second terminal of the first transistor; and A second capacitor includes a first electrode connected to the second terminal of the first transistor and a second electrode connected to the second electrode of the light emitting diode.

22. The display device according to claim 21, wherein The first electrode of the second capacitor is connected to the second gate of the first transistor.

23. The display device according to claim 21, wherein The first electrode of the first capacitor includes an upper electrode and a lower electrode, The upper electrode and the first gate of the first transistor are arranged on the same layer, The lower electrode and the first electrode of the second capacitor are provided on the same layer, and The lower electrode is connected to the upper electrode.

24. The display device according to claim 21, wherein During one frame, a gate signal is supplied to the gate of the third transistor once, and a gate signal is supplied to the gate of the fourth transistor two or more times.

25. The display device according to claim 21, wherein Each pixel of the plurality of pixels further comprises: a sixth transistor connected to the second terminal of the first transistor and a third voltage line; and a seventh transistor connected to the first electrode of the light emitting diode and a fourth voltage line, and The same gate signal is supplied to the gate of the sixth transistor and the gate of the seventh transistor.

26. The display device according to claim 21, wherein A gate signal is applied to the gate of the fourth transistor at a timing prior to a gate signal being applied to the gate of the fifth transistor.

27. The display device according to claim 21, wherein Each pixel of the plurality of pixels further comprises: a sixth transistor connected to the second terminal of the first transistor and a third voltage line; and a seventh transistor connected to the first electrode of the light emitting diode and a fourth voltage line, and A gate signal supplied to the gate of the sixth transistor is different from a gate signal supplied to the gate of the seventh transistor.

28. The display device according to claim 27, wherein During one frame, a gate signal is supplied to the gate of the sixth transistor once, and a gate signal is supplied to the gate of the seventh transistor two or more times.

29. The display device according to claim 21, wherein One frame includes a first scanning period and a second scanning period, the first scanning period includes a first non-transmission period and a first transmission period, and the second scanning period includes a second non-transmission period and a second transmission period. Each of the plurality of pixels further includes a sixth transistor connected to the second terminal of the first transistor and a third voltage line, and The first non-emission period includes: a writing period, in which a first gate signal is applied to the gate of the second transistor; a first period, before the writing period, in which a second gate signal is applied to the gate of the sixth transistor in the first period, and a third gate signal is applied to the gate of the third transistor in the first period; and a second period, between the writing period and the first period, in which the third gate signal is applied to the gate of the third transistor in the second period, and a fourth gate signal is applied to the gate of the fourth transistor in the second period.

30. The display device according to claim 29, wherein The second non-emission period includes a third period in which the second gate signal is applied to the gate of the sixth transistor.

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