Display panel and display device

Abstract

The invention provides a display panel and a display device.The display panel comprises a first substrate, a first conducting layer, a second conducting layer, a shielding layer and a first electrode layer, the first conducting layer, the second conducting layer, the shielding layer and the first electrode layer are stacked on the first substrate, the first conducting layer comprises a shielding signal line, the second conducting layer comprises a data line, the shielding layer comprises a shielding part, and the first electrode layer comprises a pixel electrode; the shielding layer is arranged between the second conductive layer and the first electrode layer, the shielding layer is electrically connected with the shielding signal line through the via hole, the shielding layer is used for shielding an electric field between the data line and the pixel electrode, and the shielding layer is made of the transparent conductive material and has higher light transmittance, so that the aperture opening ratio of the display panel can be increased, and the display effect of the display panel is improved. Therefore, light leakage caused by deflection of liquid crystals near the data lines can be prevented while the penetration rate of the display panel can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous development of LCD technology, wide viewing angles, low energy consumption, and high charge rates have become important performance indicators for measuring product advancement. Although thin-film transistor liquid crystal display panels have a higher charge rate than other display panels, the increasing popularity of LCD panels has led most consumers to prefer larger and brighter panels, driving the rapid development of the display panel industry.

[0003] As the concept of global carbon neutrality becomes a trend, the power consumption requirements for display panels are becoming increasingly stringent. In order to reduce the energy consumption of display panels, it is necessary to improve the transmittance of display panels. At present, a metal shielding layer is usually provided between the data line and the pixel electrode of the display panel to shield the electric field generated between the data line and the pixel electrode, and prevent the liquid crystal near the data line from deflecting and causing light leakage. However, since the metal shielding layer and the data line are not light-transmitting, the aperture ratio of the display panel is relatively low, which makes it difficult to improve the transmittance of the display panel.

[0004] Therefore, it is necessary to provide a display panel and a display device to improve this defect. Summary of the Invention

[0005] Embodiments of the present application provide a display panel and a display device, which can improve the transmittance of the display panel.

[0006] In order to achieve the above-mentioned objective, according to a first aspect of the present application, a display panel is provided, comprising:

[0007] a first substrate,

[0008] A first conductive layer, disposed on the first substrate, comprising a shielding signal line;

[0009] a second conductive layer disposed on the first conductive layer, wherein the second conductive layer includes a data line;

[0010] a shielding layer disposed on the second conductive layer, wherein the shielding layer comprises a transparent conductive material and includes a shielding portion, and the shielding portion overlaps the data line in a thickness direction of the display panel; and

[0011] A first electrode layer is provided on the shielding layer, wherein the first electrode layer includes a plurality of pixel electrodes;

[0012] Wherein, the display panel is provided with a via hole, and the shielding portion is electrically connected to the shielding signal line through the via hole.

[0013] Optionally, the display panel has a display area, and at least one via hole is disposed in the display area.

[0014] Optionally, the first conductive layer includes a plurality of scan lines, the plurality of scan lines are arranged to intersect with the plurality of data lines to define a plurality of pixel areas in the display area, and the via holes are arranged in the pixel areas.

[0015] Optionally, the plurality of pixel areas include a first pixel area having the via hole, the plurality of pixel electrodes include a first pixel electrode located in the first pixel area, the display panel further includes a first transistor located in the first pixel area, the second conductive layer includes a first connecting portion located in the first pixel area, and a source of the first transistor is electrically connected to the first pixel electrode via the first connecting portion;

[0016] Wherein, the via hole is arranged between the first connecting portion and the scan line.

[0017] Optionally, the first connecting portion includes:

[0018] a first connecting sub-portion extending along an extending direction of the scanning line;

[0019] a second connecting sub-portion, overlapping with the first pixel electrode in a thickness direction of the display panel and connected to the first pixel electrode;

[0020] The second connecting sub-portion is connected to a side of the first connecting sub-portion away from the scan line.

[0021] Optionally, the plurality of pixel areas include a plurality of first pixel areas, the plurality of first pixel areas include a first-first pixel area, and the plurality of via holes include a first via hole located in the first-first pixel area;

[0022] The display panel further includes a first conductive electrode, which is disposed on the shielding layer and is connected to the shielding portion through the first via hole.

[0023] Optionally, the display panel includes an organic insulating layer, the organic insulating layer is disposed on the shielding layer, the first conductive electrode is disposed on the organic insulating layer, and the first via hole penetrates the organic insulating layer to expose a portion of the shielding portion.

[0024] Optionally, the plurality of first pixel regions include first and second pixel regions, and the plurality of via holes include second via holes provided in the first and second pixel regions;

[0025] Wherein, the first conductive electrode is connected to the shielding signal line through the second via hole.

[0026] Optionally, the display panel includes:

[0027] a gate insulating layer, disposed on the first conductive layer, and the second conductive layer is disposed on the gate insulating layer;

[0028] a passivation layer disposed on the second conductive layer, and a shielding layer disposed on the passivation layer; and

[0029] an organic insulating layer, disposed on the shielding layer;

[0030] The second via hole penetrates the organic insulating layer, the passivation layer and the gate insulating layer to expose a portion of the shielding signal line.

[0031] Optionally, the shielding layer includes a plurality of the shielding parts, the plurality of vias include a plurality of the first vias and a plurality of the second vias, and the plurality of the shielding parts are electrically connected to the shielding signal lines through the corresponding first vias, the second vias and the first conductive electrodes to form a grid structure.

[0032] Optionally, the plurality of pixel areas further include a second pixel area, and the first-first pixel area, the first-second pixel area and the second pixel area are arranged along an extending direction of the scan line;

[0033] At least one second pixel region is disposed between the first-first pixel region and the first-second pixel region.

[0034] Optionally, the plurality of pixel electrodes further include a second pixel electrode located in the second pixel area, and a length of the first pixel electrode in the extending direction of the data line is smaller than a length of the second pixel electrode in the extending direction of the data line.

[0035] Optionally, a distance between the first pixel electrode and the scan line in the extending direction of the data line is greater than a distance between the second pixel electrode and the scan line in the extending direction of the data line.

[0036] Optionally, the display panel further includes a second transistor located in the second pixel area, the second conductive layer includes a second connecting portion, and a source of the second transistor is electrically connected to the second pixel electrode through the second connecting portion;

[0037] The second connecting portion includes a third connecting sub-portion and a fourth connecting sub-portion, the third connecting sub-portion extends along the extension direction of the scan line, and the fourth connecting sub-portion is connected to a side of the third connecting sub-portion close to the scan line.

[0038] Optionally, the first connecting portion includes a first connecting sub-portion and a second connecting sub-portion, and the distance between the second connecting sub-portion and the scan line in the extending direction of the data line is greater than the distance between the fourth connecting sub-portion and the scan line in the extending direction of the data line.

[0039] Optionally, the first conductive electrode is provided in the same layer as the first electrode layer and is made of the same material as the first electrode layer.

[0040] Optionally, the display panel includes a display area and a non-display area arranged around the display area, and at least one via hole is arranged in the non-display area.

[0041] Optionally, a plurality of via holes are provided in the non-display area, the plurality of via holes include a third via hole and a fourth via hole located in the non-display area, and the shielding layer includes a shielding connection portion located in the non-display area and connected to the shielding portion;

[0042] The display panel further includes a second conductive electrode located in the non-display area, and the shielding connection portion is electrically connected to the shielding signal line through the second conductive electrode, the third via hole, and the fourth via hole.

[0043] Optionally, the display panel includes:

[0044] a gate insulating layer, disposed on the first conductive layer, wherein the first conductive layer is disposed on the gate insulating layer;

[0045] a passivation layer disposed on the second conductive layer, and a shielding layer disposed on the passivation layer; and

[0046] an organic insulating layer, disposed on the shielding layer;

[0047] The third via hole penetrates the organic insulating layer to expose a portion of the shielding connection portion; the fourth via hole penetrates the organic insulating layer, the passivation layer and the gate insulating layer to expose a portion of the shielding signal line.

[0048] Optionally, the plurality of vias include a plurality of third vias and a plurality of fourth vias, and the shielding connection portion is connected to the shielding signal line through the second conductive electrode, at least two of the third vias, and at least two of the fourth vias.

[0049] Optionally, the second conductive electrode is provided in the same layer as the first electrode layer and is made of the same material as the first electrode layer.

[0050] According to a second aspect of the present application, a display device is provided, comprising the display panel as described above.

[0051] In the display panel of the embodiment of the present application, a shielding layer is arranged between the second conductive layer and the first electrode layer, and the shielding layer is electrically connected to the shielding signal line through a via, so that the shielding layer can be used to shield the electric field between the data line and the pixel electrode. Since the material of the shielding layer is a transparent conductive material with higher light transmittance, the aperture ratio of the display panel can be improved, thereby improving the transmittance of the display panel while preventing the liquid crystal near the data line from being deflected and causing light leakage.

[0052] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0054] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same drawing numbers represent the same parts in the following description.

[0055] Figure 1 A top view of a first display panel provided in an embodiment of the present application;

[0056] Figure 2 A schematic diagram of pixel arrangement in a display area of ​​a display panel provided in an embodiment of the present application;

[0057] Figure 3 A schematic diagram of a first pixel region of a display panel provided in an embodiment of the present application;

[0058] Figure 4 A schematic diagram of the film layer structure of a first pixel region of a display panel provided in an embodiment of the present application;

[0059] Figure 5 Schematic diagrams of first and second pixel regions of a display panel provided in an embodiment of the present application;

[0060] Figure 6 Schematic diagram of the film layer structure of the first and second pixel regions of the display panel provided in an embodiment of the present application;

[0061] Figure 7 A top view of a second display panel provided in an embodiment of the present application;

[0062] Figure 8 A partial schematic diagram of a non-display area of ​​a second display panel provided in an embodiment of the present application;

[0063] Figure 9 A top view of a third display panel provided in an embodiment of the present application;

[0064] Figure 10 A schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0065] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0066] An embodiment of the present application provides a display panel, including a first substrate, a first conductive layer, a second conductive layer, a shielding layer and a first electrode layer, wherein the first conductive layer is arranged on the first substrate, the first conductive layer includes a shielding signal line, the second conductive layer is arranged on the first conductive layer, the second conductive layer includes a data line, the shielding layer is arranged on the second conductive layer, the material of the shielding layer includes a transparent conductive material, the shielding layer includes a shielding portion, the shielding portion overlaps with the data line in the thickness direction of the display panel, the first electrode layer is arranged on the shielding layer, the first electrode layer includes a pixel electrode, the display panel is provided with a via, and the shielding portion is electrically connected to the shielding signal line through the via.

[0067] In an embodiment of the present application, a shielding layer is provided between the second conductive layer and the first electrode layer, and the shielding layer is electrically connected to the shielding signal line through a via, so that the shielding layer can be used to shield the electric field between the data line and the pixel electrode. Since the material of the shielding layer is a transparent conductive material with a higher light transmittance, the aperture ratio of the display panel can be increased, thereby improving the transmittance of the display panel while preventing the liquid crystal near the data line from being deflected and causing light leakage.

[0068] Combine Figure 1 As shown, Figure 1 This is a top view of the first display panel provided in an embodiment of the present application. The display panel 100 includes a display area AA and a non-display area NA disposed around the display area AA. The display area AA is used to display images and may include multiple data lines, multiple scan lines, and multiple pixel areas defined by the intersection of the multiple data lines and the multiple scan lines. Each pixel area can be considered a sub-pixel. The non-display area NA is used to house circuit structures related to the display function and signal routing.

[0069] Combine Figures 1 to 4 As shown, Figure 2A schematic diagram of pixel arrangement of a display area of ​​a display panel provided in an embodiment of the present application is provided. Figure 3 A schematic diagram of a first pixel region of a display panel provided in an embodiment of the present application, Figure 4 A schematic diagram of the film layer structure of the first pixel area of ​​the display panel provided in an embodiment of the present application, the display panel includes a first conductive layer 1, a second conductive layer 2, a shielding layer 3 and a first electrode layer 4, the first conductive layer 1 includes a shielding signal line 11, the second conductive layer 2 is arranged on the first conductive layer 1, the second conductive layer 2 includes a data line 21, the shielding layer 3 is arranged on the second conductive layer 2, the material of the shielding layer 3 includes a transparent conductive material, the shielding layer 3 includes a shielding portion 31, the shielding portion 31 overlaps with the data line 21 in the thickness direction of the display panel, the first electrode layer 4 is arranged on the shielding layer 3, the first electrode layer 4 includes a pixel electrode 41, and the display panel is provided with a via H, and the shielding portion 31 is electrically connected to the shielding signal line 11 through the via H.

[0070] In an embodiment of the present application, the shielding signal line 11 is connected to the DC signal. A shielding layer 3 is set between the second conductive layer 2 and the first electrode layer 4, and the shielding layer 3 is electrically connected to the shielding signal line 11 through the via H, so that the shielding portion 31 of the shielding layer 3 is used to shield the electric field between the data line 21 and the pixel electrode 41. Since the material of the shielding layer 3 is a transparent conductive material with a higher light transmittance, the aperture ratio of the display panel can be improved, thereby improving the transmittance of the display panel while preventing the liquid crystal near the data line from deflecting and causing light leakage.

[0071] In some embodiments, the DC signal connected to the shielding signal line 11 can be a common voltage signal. The first conductive layer 1 includes a common electrode on the array substrate side, and the common electrode on the array substrate side is connected to the shielding signal line 11. The shielding signal line 11 can be regarded as a part of the common electrode on the array substrate side and has the same potential as the common electrode on the array substrate side.

[0072] In some embodiments, combined Figures 1 to 3 As shown, at least one via H is provided in the display area AA. By providing the via H in the display area AA, the shielding portion 31 is electrically connected to the shielding signal line 11 through the via H in the display area AA. This not only reduces the width of the non-display area NA, thus achieving a narrow bezel effect, but also reduces the difference in potential between the shielding portions 31 in different areas, thereby improving the shielding effect of the shielding portion 31, preventing light leakage caused by deflection of the liquid crystal near the data line, and improving the uniformity of the display brightness of the display panel.

[0073] In some embodiments, the display area AA may be provided with a via hole H, which penetrates the insulating layer between the shielding layer 3 and the first conductive layer 1 . The shielding portion 31 is connected to the shielding signal line 11 through the via hole H to receive the common voltage signal transmitted by the shielding signal line 11 .

[0074] In some embodiments, combined Figure 2 and Figure 3 As shown, the display panel 100 includes a plurality of scan lines 12 and a plurality of data lines 21. The plurality of scan lines 12 extend along a first direction X and are spaced apart along a second direction Y. The plurality of data lines 21 extend along the second direction Y and are spaced apart along the first direction X. The plurality of data lines 21 intersect with the plurality of scan lines 12 to define a plurality of pixel areas PA in the display area AA. Each pixel area PA can be considered a sub-pixel. Vias H are provided in the pixel areas PA. By providing the vias H in the pixel areas PA, the gaps between adjacent pixel areas PA can be reduced, thereby improving the pixel density of the display panel and thereby increasing the resolution of the display panel.

[0075] In some embodiments, combined Figure 2 and Figure 3 As shown, multiple pixel areas PA include a first pixel area PA1 provided with a via H, multiple pixel electrodes 41 include a first pixel electrode 411 located in the first pixel area PA1, the display panel also includes a first transistor T1 located in the first pixel area PA1, the second conductive layer 2 includes a first connecting portion 22 located in the first pixel area PA1, the source of the first transistor T1 is electrically connected to the first pixel electrode 41 through the first connecting portion 22, and the via H is arranged between the first connecting portion 22 and the scan line 12.

[0076] In some embodiments, as Figure 3 As shown, the first connecting portion 22 includes a first connecting sub-portion 221 and a second connecting sub-portion 222. The first connecting sub-portion 221 extends along the extension direction of the scanning line 12, and the first connecting sub-portion 221 is in the shape of a long strip. The second connecting sub-portion 222 is connected to the side of the first connecting sub-portion 221 away from the scanning line 12, and the second connecting sub-portion 222 is in the shape of a block. The second connecting sub-portion 222 overlaps with the first pixel electrode 41 in the thickness direction of the display panel and is electrically connected to the first pixel electrode 41.

[0077] like Figure 3 As shown, by arranging the second connecting sub-portion 222 on the side of the first connecting sub-portion 221 away from the scan line 12, an area for the via H is left between the first connecting portion 22 and the scan line 12, so that the shielding portion 31 can be electrically connected to the shielding signal line 11 through the via H in the first pixel area PA1.

[0078] In some embodiments, combined Figures 2 to 4As shown, the multiple pixel areas PA include multiple first pixel areas PA1, the multiple first pixel areas PA1 include a first-pixel area PA11, the multiple porous H include a first via H1 located in the first-pixel area PA11, and the display panel also includes a first conductive electrode 42. The first conductive electrode 42 is arranged on the shielding layer 3, and the first conductive electrode 42 is connected to the shielding part 31 through the first via H1 to transfer the common voltage signal transmitted by the shielding signal line 11 to the shielding part 31.

[0079] In some embodiments, combined Figure 3 and Figure 4 As shown, the display panel includes an organic insulating layer 5, which is arranged on the shielding layer 3, and a first conductive electrode 42 is arranged on the organic insulating layer 5. The first via H1 penetrates the organic insulating layer 5 in the thickness direction of the display panel to expose part of the shielding portion 31, and the first conductive electrode 42 is overlapped with the shielding portion 31 through the first via H1.

[0080] In some embodiments, combined Figures 2 to 6 As shown, Figure 5 Schematic diagram of the first and second pixel regions of the display panel provided in an embodiment of the present application, Figure 6 A schematic diagram of the membrane layer structure of the first and second pixel areas of the display panel provided in an embodiment of the present application, wherein the multiple first pixel areas PA1 also include the first and second pixel areas PA12, the multiple porous areas H include a second via H2 located in the first and second pixel areas PA12, and the first conductive electrode 42 is connected to the shielding signal line 11 through the second via H2 to transmit the common voltage signal transmitted by the shielding signal line 11 to the shielding portion 31.

[0081] In some embodiments, as Figure 6 As shown, the display panel further includes a gate insulating layer 6 and a passivation layer 7. The gate insulating layer 6 is disposed on the first conductive layer 1, the second conductive layer 2 is disposed on the gate insulating layer 6, the passivation layer 7 is disposed on the second conductive layer 2, the shielding layer 3 is disposed on the passivation layer 7, and the organic insulating layer 5 is disposed on the shielding layer 3. A second via hole H2 penetrates the insulating layer 5, the passivation layer 7, and the gate insulating layer 6 in the thickness direction of the display panel to expose a portion of the shielding signal line 11. The first conductive electrode 42 is connected to the shielding signal line 11 through the second via hole H2.

[0082] In the embodiment of the present application, the shielding portion 31 is connected to the shielding signal line 11 through the first via hole H1, the first conductive electrode 42, and the second via hole H2 in sequence. By disposing the first via hole H1 and the second via hole H2 in different first pixel areas PA1, it is possible to avoid concentrating multiple via holes in the same pixel area, which would result in a low aperture ratio in the pixel area and cause poor display. This ensures the aperture ratio of the first pixel area PA1 while preventing deflection of the liquid crystal near the data line and light leakage.

[0083] Combine Figures 3 to 6 As shown, the first via hole H1 is a shallow hole, and the second via hole H2 is a deep hole. By adopting a deep-shallow transition hole method, the shielding part 31 is electrically connected to the shielding signal line 11 using the first conductive electrode 42. There is no need to etch the passivation layer 7 and the gate insulating layer 6 before forming the shielding part 31 to form a via hole that directly connects the shielding part 31 to the shielding signal line 11. Therefore, a mask can be saved, thereby improving the production efficiency of the display panel and reducing the production cost of the display panel.

[0084] In some embodiments, combined Figure 2 As shown, the shielding layer 3 includes a plurality of shielding portions 31, and the plurality of vias H include a plurality of first vias H1 and a plurality of second vias H2. Each first via H1 is arranged in a corresponding first-one pixel area PA11, and each second via H2 is arranged in a corresponding first-two pixel area PA12. The plurality of shielding portions 31 are electrically connected to the shielding signal line 11 through the corresponding first vias H1, the second vias H2 and the first conductive electrode 42, respectively, to form a grid structure. This can improve the voltage drop of the shielding layer 3 and reduce the signal delay of the shielding layer 3, thereby improving the stability of the common voltage signal of the shielding layer 3, thereby improving the uniformity of the display brightness of the display panel.

[0085] In some embodiments, the multiple pixel areas PA further include a second pixel area PA2, the first pixel area PA11, the first pixel area PA12 and the second pixel area PA2 are arranged along the extension direction of the scan line 12, and at least one second pixel area PA2 is provided between the first pixel area PA11 and the first pixel area PA12.

[0086] It should be noted that since vias H need to be provided within the first pixel area PA1, the vias H will compress the aperture ratio of the first pixel area PA1, resulting in the aperture ratio of the first pixel area PA1 being lower than the aperture ratio of the second pixel area PA2. In the embodiments of the present application, by providing one or more second pixel areas PA2 between the first-pixel area PA11 and the first-second pixel area PA12, the first-pixel area PA11 and the first-second pixel area PA12, which have lower aperture ratios, can be separated, thereby reducing the presence of the first-pixel area PA11 and the first-second pixel area PA12, thereby improving the uniformity of the display brightness. Furthermore, the vias H can be evenly distributed within the display area AA, thereby improving the voltage drop of the shielding layer 3 and reducing the signal delay of the shielding layer 3. Therefore, the stability of the common voltage signal of the shielding layer 3 can be improved, thereby further improving the uniformity of the display brightness of the display panel.

[0087] In some embodiments, as Figure 2As shown, five second pixel areas PA2 are provided between the first-pixel area PA11 and the first-second pixel area PA12 located in the same column and closest to each other. In practical applications, the number of second pixel areas PA2 provided between the first-pixel area PA11 and the first-second pixel area PA12 is not limited to five as in the above embodiment, but may also be one, two, or three or more.

[0088] In some embodiments, as Figure 2 As shown, the plurality of pixel electrodes 41 further include a second pixel electrode 412 located in the second pixel area PA2, and the length of the first pixel electrode 411 in the extending direction of the data line 21 is shorter than the length of the second pixel electrode 412 in the extending direction of the data line 21. By reducing the length of the first pixel electrode 411 in the extending direction of the data line 21, a space for accommodating the via hole H is formed between the first connecting portion 22 and the scan line 12.

[0089] In some embodiments, as Figure 2 As shown, the distance between the first pixel electrode 411 and the scan line 12 in the extending direction of the data line 21 is greater than the distance between the second pixel electrode 412 and the scan line 12 in the extending direction of the data line 21. By increasing the distance between the first pixel electrode 411 and the scan line 12, a space for accommodating the via hole H is formed between the first connecting portion 22 and the scan line 12.

[0090] In some embodiments, as Figure 2 As shown, the display panel further includes a second transistor T2 located in the second pixel area PA2 , the second conductive layer 2 includes a second connecting portion 23 , and the source of the second transistor T2 is electrically connected to the second pixel electrode 412 via the second connecting portion 23 .

[0091] like Figure 2 As shown, the second connection portion 23 includes a third connection sub-portion 231 and a fourth connection sub-portion 232. The third connection sub-portion 231 extends along the extension direction of the scan line 12, and the fourth connection sub-portion 232 is connected to a side of the third connection sub-portion 231 close to the scan line 12. By disposing the fourth connection sub-portion 232 on a side of the third connection sub-portion 231 close to the scan line 12, the length of the second pixel electrode 412 can be increased, and the distance between the second pixel electrode 412 and the scan line 12 can be reduced. In this way, the aperture ratio of the second pixel area PA2 can be increased, thereby improving the transmittance of the entire display panel.

[0092] In some embodiments, combined Figure 2 and Figure 3As shown, the distance between the second connecting sub-portion 222 and the scan line 12 in the extending direction of the data line 21 is greater than the distance between the fourth connecting sub-portion 232 and the scan line 12 in the extending direction of the data line 21. By increasing the distance between the second connecting sub-portion 222 and the scan line 12, a space for accommodating the via H is formed between the second connecting sub-portion 222 and the scan line 12.

[0093] In some embodiments, the first conductive electrode 42 is disposed in the same layer as the first electrode layer 4 and is made of the same material as the first electrode layer 4 .

[0094] like Figure 4 As shown, the first conductive electrode 42 and the first electrode layer 4 are both arranged on the organic insulating layer 5. The materials of the first conductive electrode 42 and the first electrode layer 4 are both transparent conductive materials, and the transparent conductive material can be indium tin oxide. The first conductive electrode 42 and the first electrode layer 4 can be prepared simultaneously using the same film forming process.

[0095] In some embodiments, as Figure 4 As shown, the display panel 100 further includes a first substrate 8, an active layer 9, and a color resist layer 10. The first conductive layer 1 is disposed on the first substrate 8, the active layer 9 is disposed on the gate insulating layer 6, and the color resist layer 10 is disposed on the passivation layer 7. The first substrate 8, the first conductive layer 1, the gate insulating layer 6, the active layer 9, the second conductive layer 2, the passivation layer 7, the color resist layer 10, the shielding layer 3, the organic insulating layer 5, and the first electrode layer 4 constitute an array substrate.

[0096] In some embodiments, as Figure 4 As shown, the display panel 100 further includes a liquid crystal layer 101 and an opposing substrate 102. The opposing substrate 102 is spaced apart from the array substrate, with the liquid crystal layer 101 located between the array substrate and the opposing substrate 102. The opposing substrate 102 includes a second substrate 1021, a black matrix 1022 disposed on the second substrate 1021, and a second electrode layer 1023 disposed on the second substrate 1021 and the black matrix 1022. The second electrode layer 1023 includes a common electrode disposed on the entire surface.

[0097] In some embodiments, at least one via H is disposed in the non-display area NA, and the shielding layer 3 is electrically connected to the shielding signal line 11 via the via H1 located in the non-display area NA. By disposing the via H1 in the non-display area NA, it is possible to prevent the via H1 from reducing the aperture ratio of the display panel. Thus, while ensuring the transmittance of the display panel, the shielding layer 3 can receive the common voltage signal transmitted by the shielding signal line 11, thereby preventing light leakage caused by deflection of the liquid crystal near the data line.

[0098] like Figure 7 As shown, Figure 7The top view of the second display panel provided in the embodiment of the present application has the same structure as Figure 1 The structure of the display panel shown is roughly the same, with the difference that: multiple vias H are only arranged in the non-display area NA, the shielding layer 3 is electrically connected to the shielding signal line 11 through the via H1 located in the non-display area NA, and the display area AA is not provided with vias H for electrically connecting the shielding layer 3 and the shielding signal line 11.

[0099] In some embodiments, combined Figure 7 and Figure 8 As shown, Figure 8 A partial schematic diagram of the non-display area of ​​the second display panel provided in an embodiment of the present application, wherein the multiple vias H include a third via H3 and a fourth via H4 located in the non-display area NA, and the shielding layer 3 includes a shielding connection portion 32 located in the non-display area NA and connected to the shielding portion 31.

[0100] like Figure 7 As shown, the display panel further includes a second conductive electrode 43 located in the non-display area NA, and the shielding connection portion 32 is electrically connected to the shielding signal line 11 through the second conductive electrode 43, the third via hole H3 and the fourth via hole H4.

[0101] In some embodiments, combined Figure 4 and Figure 7 As shown, the third via hole H3 penetrates the organic insulating layer 5 in the thickness direction of the display panel to expose the shielding connection portion 32, and the fourth via hole H4 penetrates the organic insulating layer 5, the passivation layer 7 and the gate insulating layer 6 in the thickness direction of the display panel to expose part of the shielding signal line 11.

[0102] In some embodiments, the plurality of vias H include a plurality of third vias H3 and a plurality of fourth vias H4 , and the shielding connection portion 32 is connected to the shielding signal line 11 through the second conductive electrode 43 , at least two third vias H3 and at least two fourth vias H4 .

[0103] like Figure 7 As shown, the second conductive electrode 43 has a block structure, and the second conductive electrode 43 is connected to the shielding connection part 32 below through three third vias H3 arranged side by side and spaced apart. This not only reduces the contact impedance between the second conductive electrode 43 and the shielding connection part 32, but also improves the stability of the connection between the second conductive electrode 43 and the shielding connection part 32.

[0104] like Figure 7As shown, three fourth via holes H4 are arranged at intervals on the upper and lower sides of the third via hole H3, and the second conductive electrode 43 is connected to the shielding signal line 11 through six fourth via holes. This not only reduces the contact impedance between the second conductive electrode 43 and the shielding signal line 11, but also improves the stability of the connection between the second conductive electrode 43 and the shielding signal line 11.

[0105] In some embodiments, combined Figure 4 and Figure 7 As shown, the second conductive electrode 43 is provided in the same layer as the first electrode layer 4 and is made of the same material as the first electrode layer 4. The second conductive electrode 43 and the first electrode layer 4 are both provided on the organic insulating layer 5. Both the second conductive electrode 43 and the first electrode layer 4 are made of transparent conductive materials, such as indium tin oxide. The second conductive electrode 43 and the first electrode layer 4 can be simultaneously prepared using the same film-forming process.

[0106] In some embodiments, the via hole H is disposed in the non-display area NA on at least one side of the display area AA.

[0107] like Figure 7 As shown, the non-display areas NA surrounding the display area AA are all provided with vias H. In the non-display areas NA on the left and right sides of the display area, the vias H can be provided in the area where the gate driving circuit is located.

[0108] like Figure 9 As shown, Figure 9 The top view of the third display panel provided in the embodiment of the present application has the same structure as Figure 1 The structures of the display panels shown are substantially the same, with the difference being that a plurality of via holes H1 are provided in both the display area AA and the non-display area NA.

[0109] Specifically, in the display area AA, the plurality of vias H include a first via H1 and a second via H2, and the shielding portion 31 is electrically connected to the shielding signal line 11 via the first and second vias H1 and H2, and the first conductive electrode 42. In the non-display area NA, the plurality of vias H include a third and fourth vias H3 and H4, and the shielding connection portion 32 is electrically connected to the shielding signal line via the third and fourth vias H3 and H4, and the second conductive electrode 43. This improves the voltage drop across the shielding layer 3 and reduces signal delay across the shielding layer 3 while ensuring the overall aperture ratio and transmittance of the display panel. This improves the stability of the common voltage signal across the shielding layer 3, thereby further enhancing the uniformity of the display brightness across the display panel.

[0110] According to the display panel provided in the above embodiment of the present application, the embodiment of the present application further provides a display device, see Figure 10 , Figure 10This is a schematic diagram of a display device provided in an embodiment of the present application. The display device 1000 includes a display panel 100 and a housing 200. The display panel 100 is disposed on the housing 200. The display panel 100 can be the display panel provided in any of the above embodiments. The display device provided in an embodiment of the present application can achieve the same technical effects as the display panel provided in any of the above embodiments, and will not be described in detail here.

[0111] Beneficial effects of the embodiments of the present application: The embodiments of the present application provide a display panel and a display device, wherein the display panel includes a first substrate and a first conductive layer, a second conductive layer, a shielding layer and a first electrode layer stacked on the first substrate, the first conductive layer includes a shielding signal line, the second conductive layer includes a data line, the shielding layer includes a shielding portion, and the first electrode layer includes a pixel electrode. A shielding layer is provided between the second conductive layer and the first electrode layer, and the shielding layer is electrically connected to the shielding signal line through a via hole, so that the shielding layer can be used to shield the electric field between the data line and the pixel electrode. Since the material of the shielding layer is a transparent conductive material with higher light transmittance, the aperture ratio of the display panel can be improved, thereby improving the transmittance of the display panel while preventing the liquid crystal near the data line from deflecting and causing light leakage.

[0112] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0113] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0114] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0115] The above are merely preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: include: a first substrate; A first conductive layer, disposed on the first substrate, comprising a shielding signal line; a second conductive layer disposed on the first conductive layer, wherein the second conductive layer includes a data line; a shielding layer disposed on the second conductive layer, wherein the shielding layer comprises a transparent conductive material and includes a shielding portion, and the shielding portion overlaps the data line in a thickness direction of the display panel; as well as A first electrode layer is provided on the shielding layer, wherein the first electrode layer includes a plurality of pixel electrodes; Wherein, the display panel is provided with a via hole, and the shielding portion is electrically connected to the shielding signal line through the via hole.

2. The display panel according to claim 1, wherein The display panel has a display area, and at least one via hole is disposed in the display area.

3. The display panel according to claim 2, wherein: The first conductive layer includes a plurality of scan lines, and the plurality of scan lines are arranged to intersect with the plurality of data lines to define a plurality of pixel areas in the display area, and the via holes are arranged in the pixel areas.

4. The display panel according to claim 3, wherein: The plurality of pixel regions include a first pixel region having the via hole, the plurality of pixel electrodes include a first pixel electrode located in the first pixel region, the display panel further includes a first transistor located in the first pixel region, the second conductive layer includes a first connecting portion located in the first pixel region, and a source of the first transistor is electrically connected to the first pixel electrode via the first connecting portion; Wherein, the via hole is arranged between the first connecting portion and the scan line.

5. The display panel according to claim 4, wherein: The first connecting portion includes: a first connecting sub-portion extending along an extending direction of the scanning line; a second connecting sub-portion, overlapping with the first pixel electrode in a thickness direction of the display panel and connected to the first pixel electrode; The second connecting sub-portion is connected to a side of the first connecting sub-portion away from the scan line.

6. The display panel according to claim 4, wherein: The plurality of pixel areas include a plurality of first pixel areas, the plurality of first pixel areas include a first-first pixel area, and the plurality of via holes include a first via hole located in the first-first pixel area; The display panel further includes a first conductive electrode, which is disposed on the shielding layer and is connected to the shielding portion through the first via hole.

7. The display panel according to claim 6, wherein: The display panel includes an organic insulating layer, which is disposed on the shielding layer. The first conductive electrode is disposed on the organic insulating layer. The first via hole penetrates the organic insulating layer to expose a portion of the shielding portion.

8. The display panel according to claim 6, wherein: The plurality of first pixel regions include first and second pixel regions, and the plurality of via holes include a second via hole provided in the first and second pixel regions; Wherein, the first conductive electrode is connected to the shielding signal line through the second via hole.

9. The display panel according to claim 8, wherein: The display panel includes: a gate insulating layer, disposed on the first conductive layer, and the second conductive layer is disposed on the gate insulating layer; a passivation layer disposed on the second conductive layer, and a shielding layer disposed on the passivation layer; and an organic insulating layer, disposed on the shielding layer; The second via hole penetrates the organic insulating layer, the passivation layer and the gate insulating layer to expose a portion of the shielding signal line.

10. The display panel according to claim 8, wherein The shielding layer includes a plurality of shielding parts, and the plurality of vias include a plurality of first vias and a plurality of second vias. The plurality of shielding parts are electrically connected to the shielding signal lines through the corresponding first vias, the second vias and the first conductive electrodes to form a grid structure.

11. The display panel according to claim 8, wherein The plurality of pixel areas further include a second pixel area, and the first pixel area, the first second pixel area and the second pixel area are arranged along an extending direction of the scan line; At least one second pixel region is disposed between the first-first pixel region and the first-second pixel region.

12. The display panel according to claim 11, wherein: The plurality of pixel electrodes further include a second pixel electrode located in the second pixel area, and a length of the first pixel electrode in the extending direction of the data line is smaller than a length of the second pixel electrode in the extending direction of the data line.

13. The display panel according to claim 12, wherein: The distance between the first pixel electrode and the scan line in the extending direction of the data line is greater than the distance between the second pixel electrode and the scan line in the extending direction of the data line.

14. The display panel according to claim 12, wherein: The display panel further includes a second transistor located in the second pixel area, the second conductive layer includes a second connecting portion, and a source of the second transistor is electrically connected to the second pixel electrode through the second connecting portion; The second connecting portion includes a third connecting sub-portion and a fourth connecting sub-portion, the third connecting sub-portion extends along the extension direction of the scan line, and the fourth connecting sub-portion is connected to a side of the third connecting sub-portion close to the scan line.

15. The display panel according to claim 14, wherein: The first connection portion includes a first connection sub-portion and a second connection sub-portion. The distance between the second connection sub-portion and the scan line in the extending direction of the data line is greater than the distance between the fourth connection sub-portion and the scan line in the extending direction of the data line.

16. The display panel according to claim 6, wherein: The first conductive electrode is provided in the same layer as the first electrode layer and is made of the same material as the first electrode layer.

17. The display panel according to any one of claims 1 to 16, wherein: The display panel includes a display area and a non-display area arranged around the display area, and at least one via hole is arranged in the non-display area.

18. The display panel according to claim 17, wherein: A plurality of via holes are provided in the non-display area, the plurality of via holes include a third via hole and a fourth via hole located in the non-display area, and the shielding layer includes a shielding connection portion located in the non-display area and connected to the shielding portion; The display panel further includes a second conductive electrode located in the non-display area, and the shielding connection portion is electrically connected to the shielding signal line through the second conductive electrode, the third via hole, and the fourth via hole.

19. The display panel according to claim 18, wherein: The display panel includes: a gate insulating layer, disposed on the first conductive layer, wherein the first conductive layer is disposed on the gate insulating layer; a passivation layer disposed on the second conductive layer, and a shielding layer disposed on the passivation layer; and an organic insulating layer, disposed on the shielding layer; The third via hole penetrates the organic insulating layer to expose a portion of the shielding connection portion; the fourth via hole penetrates the organic insulating layer, the passivation layer and the gate insulating layer to expose a portion of the shielding signal line.

20. The display panel according to claim 18, wherein The plurality of vias include a plurality of third vias and a plurality of fourth vias, and the shielding connection portion is connected to the shielding signal line through the second conductive electrode, at least two of the third vias, and at least two of the fourth vias.

21. The display panel according to claim 18, wherein The second conductive electrode is provided in the same layer as the first electrode layer and is made of the same material as the first electrode layer.

22. A display device, characterized in that: Comprising the display panel according to any one of claims 1 to 21.

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