Rotary rectification chip and production method

Abstract

The invention discloses a rotary rectification chip and a production method, relates to the field of chip production, and covers the whole process from substrate layer preparation, PN junction formation, metal electrode manufacturing, passivation protection, wafer thinning and cutting to final chip testing and sorting. In the chip testing and sorting link, an advanced yield management and fault diagnosis mechanism is integrated. According to the method, visual inspection and experience judgment are no longer performed on the wafer graph only by manual work, the test result is intelligently analyzed, especially when the wafer yield is lower than the preset threshold value, the wafer graph image matrix can be automatically constructed, and pattern recognition and attribution of the yield spatial distribution graph are performed based on the wafer graph image matrix. The data-driven analysis mode can efficiently and objectively identify the failure point with the specific spatial pattern, so that the production efficiency and the product yield of the rotary rectification chip are remarkably improved.

Description

Technical Field

[0001] The present application relates to the field of chip production, and more specifically, to a rotating rectifier chip and a production method. Background Art

[0002] Rotating rectifier chips, as essential components in modern electronic devices, are widely used in automotive, industrial control, power management, and other fields. Their performance and reliability directly impact the overall performance of end products. The production of rotating rectifier chips involves a multi-step, high-precision semiconductor manufacturing process, including substrate layer preparation, PN junction formation, metal electrode fabrication, passivation protection, wafer thinning and dicing, and final chip testing and sorting. Even the slightest deviation in any step can lead to chip performance degradation or even failure. Therefore, establishing an efficient and reliable production method to ensure chip yield and quality is a major challenge facing the current semiconductor manufacturing industry.

[0003] However, in the existing production methods for rotary rectifier chips, although the various process links have become mature, the root cause diagnosis of failed chips is often inefficient during the chip testing and sorting stages, especially when the wafer yield is below the expected threshold. Traditional practices usually rely on experienced engineers to perform manual visual inspections and empirical judgments on wafer images to identify the spatial distribution patterns of failed chips. This manual image viewing method is not only time-consuming and labor-intensive, but also highly dependent on the engineer's personal experience, easily affected by subjective factors, and difficult to quickly and accurately locate the root cause of the problem. For those failure points with specific spatial patterns, such as concentrated failures in the edge area of ​​the wafer, they often point to systematic upstream process problems rather than sporadic accidental defects, but manual analysis has difficulty in efficiently extracting this high-value information from massive amounts of data and attributing them.

[0004] In view of this, it is desired to propose an innovative method for producing a rotating rectifier chip. Summary of the Invention

[0005] Taking into account the above limitations in application, according to one aspect of the present application, a method for producing a rotary rectifier chip is provided, which includes: preparing a substrate layer, the substrate layer including an N-type single crystal silicon wafer base layer and an epitaxial layer grown on the N-type single crystal silicon wafer base layer; forming a PN junction on the substrate layer; making metal electrodes for conduction for the P region and N region of the PN junction to obtain a rotary rectifier chip embryo; passivating and protecting the rotary rectifier chip embryo to obtain a rotary rectifier chip panel; wafer thinning and cutting the rotary rectifier chip panel to obtain a plurality of rotary rectifier chips; and performing chip testing and sorting on the plurality of rotary rectifier chips.

[0006] According to another aspect of the present application, a rotating rectifier chip is provided. The rotating rectifier chip is manufactured by the above-mentioned method for producing a rotating rectifier chip.

[0007] Compared to the prior art, the present application provides a rotary rectifier chip and production method that covers the entire process from preparing the substrate layer, forming the PN junction, making the metal electrode, passivation protection, wafer thinning and cutting, to final chip testing and sorting. Advanced yield management and fault diagnosis mechanisms are incorporated into the traditional chip manufacturing process, especially in the chip testing and sorting stages. This eliminates the need for manual visual inspection and empirical judgment of the wafer image. Instead, the system performs intelligent analysis of the test results. In particular, when the wafer yield is below a preset threshold, it can automatically construct a wafer image matrix and perform pattern recognition and attribution of the yield spatial distribution map based on this. This data-driven analysis method can efficiently and objectively identify failure points with specific spatial patterns, thereby accurately pointing to systemic upstream process problems. This significantly overcomes the shortcomings of the prior art, which relied on manual empirical judgment, was inefficient, highly subjective, and had difficulty in quickly locating systemic problems. It achieves automation and intelligence from problem discovery to root cause diagnosis, significantly shortening troubleshooting time and significantly improving the production efficiency and product yield of rotary rectifier chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other purposes, features, and advantages of the present application will become more apparent through a more detailed description of the embodiments of the present application in conjunction with the accompanying drawings. The accompanying drawings are intended to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the drawings, the same reference numerals generally represent the same components or steps.

[0009] Figure 1 Flowchart of a method for producing a rotating rectifier chip according to an embodiment of the present application.

[0010] Figure 2 Flowchart of step S2 in the method for producing a rotating rectifier chip according to an embodiment of the present application.

[0011] Figure 3 Flowchart of step S6 in the method for producing a rotating rectifier chip according to an embodiment of the present application.

[0012] Figure 4 Flowchart of step S61 in the method for producing a rotating rectifier chip according to an embodiment of the present application.

[0013] Figure 5 Flowchart of step S62 in the method for producing a rotating rectifier chip according to an embodiment of the present application. DETAILED DESCRIPTION

[0014] The following describes embodiments of the present disclosure in more detail with reference to the accompanying drawings. While the drawings illustrate certain embodiments of the present disclosure, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of protection of the present disclosure.

[0015] In order to solve the defects in the above technical background, the present application proposes a production method of a rotating rectifier chip. Figure 1 FIG. 1 is a flow chart of a method for producing a rotating rectifier chip according to an embodiment of the present application. Figure 1 As shown, the production method of the rotary rectifier chip according to the embodiment of the present application includes: S1, preparing a substrate layer, the substrate layer including an N-type single crystal silicon wafer base layer and an epitaxial layer grown on the N-type single crystal silicon wafer base layer; S2, forming a PN junction on the substrate layer; S3, making metal electrodes for conduction for the P region and N region of the PN junction to obtain a rotary rectifier chip embryo; S4, passivating and protecting the rotary rectifier chip embryo to obtain a rotary rectifier chip panel; S5, wafer thinning and cutting the rotary rectifier chip panel to obtain a plurality of rotary rectifier chips; S6, chip testing and sorting the plurality of rotary rectifier chips.

[0016] In step S1, a substrate layer is prepared. The substrate layer comprises an N-type single-crystal silicon wafer base layer and an epitaxial layer grown on the N-type single-crystal silicon wafer base layer. It should be understood that in semiconductor device manufacturing, the substrate layer is the foundation of the entire chip structure. Its material selection and structural design are crucial to the device's electrical performance, particularly the withstand voltage, conduction loss, and switching characteristics of the rotary rectifier chip. For rectifier devices that need to withstand high reverse voltages and effectively conduct forward current, the properties of the substrate directly determine the device's reliability and efficiency. To optimize the performance of the rotary rectifier chip, particularly to achieve high withstand voltage while maintaining low on-resistance and effectively control the electric field distribution of the PN junction, the present method utilizes an N-type single-crystal silicon wafer base layer and an epitaxial layer grown thereon when preparing the substrate layer. This composite structure provides a high-resistivity drift region to withstand high reverse voltages. Furthermore, the doping concentration and thickness of the epitaxial layer can be precisely controlled, providing an ideal region for subsequent PN junction formation. This ensures high withstand voltage while reducing forward voltage drop, improving the device's overall efficiency and reliability.

[0017] In one implementation, the specific process of step S1 is as follows: First, a high-purity N-type single-crystalline silicon wafer is selected as the base layer. The base layer has a high resistivity. For example, an N-type silicon wafer with a resistivity in the range of 10 ohm·cm to 100 ohm·cm can be selected to ensure that the device has sufficient voltage resistance when reverse biased. Subsequently, an N-type epitaxial layer is grown on the surface of the base layer of the N-type single-crystalline silicon wafer using epitaxial growth technology. Epitaxial growth is a technology that grows a single crystal thin film with the same crystal orientation on a single crystal substrate. Common methods include chemical vapor deposition. During the epitaxial growth process, it is crucial to precisely control the thickness and doping concentration of the epitaxial layer. For example, for a rotary rectifier chip, the thickness of the epitaxial layer can be set between 5 microns and 50 microns, and the doping concentration can be set between 1x10^15 cm^-3 and 1x10^16 cm^-3. The specific values ​​will be optimized based on the voltage resistance level and conduction loss requirements of the target device.

[0018] In step S2, a PN junction is formed on the substrate layer. Accordingly, in the field of semiconductor devices, the PN junction is the core structure that implements basic electrical functions such as rectification and amplification. For a rotating rectifier chip, its primary function is to convert alternating current into direct current, a conversion process achieved precisely through the unidirectional conductivity of the PN junction. The PN junction allows current to flow freely in one direction (forward bias) while blocking current in the other direction (reverse bias), thereby achieving current rectification. Therefore, the quality of the PN junction, including its junction depth, doping concentration profile, and junction integrity, directly determines key electrical parameters of the rotating rectifier chip, such as the on-state voltage drop, reverse leakage current, and reverse breakdown voltage. To ensure that the rotating rectifier chip can efficiently and reliably complete its rectification task and meet specific withstand voltage and conduction loss requirements, precisely forming the PN junction on the substrate layer in this method is a crucial step.

[0019] In one implementation, Figure 2 FIG. 1 is a flow chart of step S2 in the method for producing a rotating rectifier chip according to an embodiment of the present application. Figure 2 As shown, step S2, forming a PN junction on the substrate layer, includes: S21, growing a layer of silicon dioxide on the surface of the substrate layer by thermal oxidation to obtain a mask layer; S22, coating a photoresist on the mask layer, and performing ultraviolet exposure through a mask with a specific pattern, and then forming a window pattern on the mask layer by development; S23, corroding the silicon dioxide exposed in the window pattern by an etching process to expose the substrate layer located thereunder; S24, doping P-type impurities into the epitaxial layer below the window pattern by a high-temperature diffusion or ion implantation process to obtain the PN junction.

[0020] The specific process of step S2 is as follows: First, step S21 is performed. In this process, the substrate layer is placed in a high-temperature oxidation furnace and heated in an oxygen-rich atmosphere. For example, dry oxygen or wet oxygen oxidation is performed at a temperature range of 900°C to 1100°C for several hours. Specifically, dry oxygen oxidation is usually carried out in a pure oxygen atmosphere, with a slower growth rate but high-quality oxide layer; wet oxygen oxidation is carried out in a mixed atmosphere of water vapor and oxygen, with a faster growth rate. As an excellent insulator and diffusion barrier layer, the thickness of the silicon dioxide (SiO2) layer needs to be precisely controlled. For example, it can be set to 0.5 microns to 1.5 microns to ensure that it can effectively block impurity diffusion and serve as an etching mask in subsequent processes, while avoiding increasing the difficulty of subsequent etching due to excessive thickness.

[0021] Next, step S22 is performed. Photoresist, a polymer material sensitive to ultraviolet light, is first evenly coated onto the surface of the silicon dioxide layer through methods such as spin coating to form a thin film. Subsequently, ultraviolet light is applied through a highly precisely aligned mask (on which the geometric shape of the PN junction area, such as a circle or rectangle, is engraved). The ultraviolet light passes through the transparent areas of the mask, causing a photochemical reaction in the photoresist. For example, positive photoresist becomes soluble in a developer after exposure, while negative photoresist becomes insoluble. Subsequently, the developer selectively dissolves the exposed or unexposed photoresist, accurately replicating the desired window pattern on the silicon dioxide masking layer. These windows will define the final position and size of the PN junction, and their accuracy directly affects the device's integration and performance.

[0022] Subsequently, step S23 is performed. The etching process adopts wet etching (such as using a diluted hydrofluoric acid solution) or dry etching (such as reactive ion etching). Wet etching has the advantages of low cost and simple operation, but there may be isotropic etching that causes pattern distortion; dry etching has anisotropic etching ability and can achieve finer pattern transfer, but the equipment cost is relatively high. The etchant will selectively corrode the silicon dioxide in the window area that is not covered by the photoresist, while retaining the area protected by the photoresist, thereby exposing the surface of the underlying N-type single crystal silicon wafer base layer or epitaxial layer, preparing for subsequent impurity doping. The endpoint control of the etching is crucial to ensure that the silicon dioxide layer is completely removed without damaging the underlying silicon substrate.

[0023] Finally, step S24 is performed. If high-temperature diffusion is used, the substrate layer is placed in an atmosphere containing a P-type impurity source (such as boron) and heated at a high temperature, such as 950°C to 1150°C. This allows the P-type impurity atoms to diffuse through the silicon lattice into the exposed N-type silicon regions, forming a PN junction. The diffusion time and temperature determine the junction depth and doping concentration. For example, the diffusion time can be set to 30 minutes to 2 hours to achieve the desired junction depth and doping profile. If ion implantation is used, P-type impurity ions (such as boron ions) are accelerated and bombarded at the substrate surface with high energy, precisely implanted to a predetermined depth. The energy and dose of ion implantation can be precisely controlled. For example, the implantation energy can be set between 20keV and 100keV, and the dose can be set between 1x10^13 cm^-2 and 1x10^15 cm^-2 to form a PN junction with a specific junction depth and doping profile. Annealing is required after ion implantation to repair lattice damage and activate the implanted impurities. Finally, a P-type region is formed in the N-type substrate, thereby constructing a PN junction with rectification characteristics, whose electrical characteristics will directly affect the performance of the rotating rectifier chip.

[0024] In step S3, metal electrodes for conducting electricity are made for the P region and N region of the PN junction to obtain a rotating rectifier chip embryo. It should be understood that although the successful formation of the PN junction gives the chip basic electrical functions, in order to make it truly a usable electronic component and to be able to make effective electrical connections with external circuits, the problem of introducing and extracting current still needs to be solved. The P region and N region of the PN junction are themselves semiconductor materials, and their direct contact with external wires often forms an unstable Schottky junction or produces a large contact resistance, thereby causing energy loss, signal distortion, and even affecting the normal operation of the device. In order to ensure that the rotating rectifier chip can efficiently collect and transmit current, minimize conduction losses, and ensure the stability and reliability of the device in practical applications, it is an indispensable key step to make metal electrodes for conducting electricity for the P region and N region of the PN junction.

[0025] In one implementation, the specific process of step S3 is as follows: First, after the PN junction is formed, contact holes are precisely opened above the P and N regions through photolithography and etching processes to expose the underlying silicon surface. Specifically, this involves uniformly coating a layer of photoresist on the wafer surface, then performing ultraviolet exposure using a mask with a contact hole pattern, and removing the exposed or unexposed photoresist through development to form a photoresist mask. Subsequently, plasma etching or wet chemical etching techniques are used to selectively remove the dielectric layer, such as a silicon oxide or silicon nitride passivation layer, in the area below the photoresist mask. This allows contact holes to be precisely opened above the P and N regions, with dimensions and positions precisely aligned with the PN junction region, exposing the clean silicon surface. For example, the minimum line width of the contact holes can be set to 0.5 microns to meet the device integration requirements.

[0026] Subsequently, a thin metal film is uniformly deposited across the entire wafer surface using physical vapor deposition techniques such as sputtering or chemical vapor deposition. In physical vapor deposition, sputtering bombards a target with high-energy ions, dislodging atoms from the target and depositing them onto the wafer surface. This results in excellent film uniformity and density. Chemical vapor deposition forms thin films through chemical reactions between gaseous precursors on the wafer surface. Commonly used metal materials include aluminum (Al), widely used due to its low cost, ease of etching, and good conductivity; or multilayer metal systems such as titanium / nickel / silver (Ti / Ni / Ag) or titanium / nickel / gold (Ti / Ni / Au), in which a titanium layer serves as an adhesion layer, a nickel layer as a barrier layer, and a silver or gold layer as a highly conductive layer. These multilayer structures offer superior adhesion, diffusion barrier properties, and ohmic contact characteristics. The total thickness of the metal layer must be precisely controlled, for example, between 0.5 and 2 microns, to ensure sufficient conductivity and mechanical strength while avoiding excessive thickness that can hinder subsequent etching or result in poor step coverage.

[0027] Next, the deposited metal layer is patterned again using photolithography and etching techniques. Specifically, a layer of photoresist is coated again on the deposited metal layer, and ultraviolet exposure and development are performed through a mask with an electrode pattern to form a precise photoresist mask, which will define the final metal electrode pattern. Subsequently, a metal etching process, such as dry etching, such as chlorine-based plasma etching for aluminum, or fluorine-based plasma etching for titanium, nickel, etc., or wet etching using a specific chemical solution, is used to selectively remove the metal area not protected by the photoresist, thereby accurately forming the required metal electrode pattern above the P region and N region. For example, the minimum line width and spacing of the electrode can be controlled within 1 micron to meet the size requirements of the device.

[0028] Finally, an annealing treatment is performed, such as alloying annealing at 400°C to 500°C for several to tens of minutes. This step is intended to promote the reaction between the metal and silicon, forming stable metal silicides such as TiSi2 and NiSi. This significantly reduces the contact resistance between the metal and semiconductor, ensuring that current can efficiently flow from the semiconductor region to the metal electrode and vice versa. This ultimately results in a rotating rectifier chip embryo with a complete electrode structure.

[0029] In step S4, the rotary rectifier chip embryo is passivated to obtain a rotary rectifier chip assembly. Accordingly, after the PN junction and the metal electrode are made, the surface of the chip embryo, especially the edge area of ​​the PN junction and the metal electrode, will be directly exposed to the air. This exposure state makes the chip extremely susceptible to environmental factors, such as moisture, dust, ionic pollutants and mechanical stress in the air. These external factors may cause defect states on the semiconductor surface, increase surface leakage current, reduce the reverse breakdown voltage of the PN junction, and even cause corrosion of the metal electrode, thereby seriously affecting the electrical performance, reliability and long-term stability of the chip. In order to effectively isolate the sensitive structure inside the chip from the external environment, suppress surface effects, improve the device's voltage resistance and moisture and pollution resistance, and provide necessary mechanical protection, the rotary rectifier chip embryo needs to be passivated.

[0030] In one implementation, the specific process of step S4 is as follows: First, after the metal electrode is fabricated, the wafer surface is thoroughly cleaned to remove any residual organic matter, particles, metal ions, or process byproducts. This cleaning utilizes a multi-step wet chemical cleaning process. For example, a standard RCA cleaning process can be employed, including an ammonia-hydrogen peroxide mixture cleaning (SC-1) to remove organic matter and particles, a hydrochloric acid-hydrogen peroxide mixture cleaning (SC-2) to remove metal ions, and a dilute hydrofluoric acid cleaning to remove the surface oxide layer. This ensures good adhesion of the passivation layer and excellent electrical properties, thereby preventing the generation of interface defects.

[0031] Subsequently, a passivation layer is uniformly grown across the entire wafer surface using thin film deposition techniques. Common passivation materials include silicon dioxide, silicon nitride, or polyimide. For example, plasma-enhanced chemical vapor deposition (PECVD) can be used to deposit silicon nitride thin films. PECVD utilizes radio frequency (RF) or microwave energy to generate a plasma at low pressure, activating reactant gases (such as silane and ammonia), causing a chemical reaction on the wafer surface at relatively low temperatures, such as 300°C to 400°C, to form a film. This low-temperature deposition is crucial for protecting the formed metal electrode structure and preventing the adverse effects of high temperatures on the metal layer, such as grain growth, increased stress, or undesirable reactions with silicon. During the deposition process, by precisely controlling the flow ratio of the reactant gases (such as silane and ammonia), RF power, chamber pressure, and substrate temperature, silicon nitride films with specific stress, density, refractive index, and dielectric constant can be obtained, thereby optimizing their passivation effect and mechanical properties. The thickness of the passivation layer needs to be set according to the device's voltage resistance requirements and mechanical protection needs. For example, it can be set between 0.5 microns and 1.5 microns to ensure that it can effectively block impurity diffusion and provide sufficient dielectric strength and mechanical strength, while avoiding being too thick to cause subsequent etching difficulties or excessive stress.

[0032] After the passivation layer is deposited, photolithography and etching processes are required to open windows in the metal pad area that needs to be bonded to the external wires. Specifically, a layer of photoresist is first evenly coated on the passivation layer, and then ultraviolet exposure is performed through a high-precision aligned mask with a pad opening pattern engraved on it, and the exposed or unexposed photoresist is removed by development to form a precise photoresist mask. Subsequently, dry etching such as reactive ion etching is used, using a fluorine-based gas mixture such as SF6 or CF4 or wet etching technology to selectively remove the passivation layer above the pad area, exposing the metal pad underneath for subsequent wire bonding. The etching process needs to be precisely controlled to ensure that the pad is fully exposed without damaging the surrounding passivation layer, while maintaining a good morphology of the etched sidewalls to facilitate subsequent wire bonding. Finally, a rotating rectifier chip panel with a complete passivation protection layer is obtained, and its internal sensitive structure is effectively protected.

[0033] In step S5, the rotating rectifier chip panel is wafer thinned and cut to obtain a plurality of rotating rectifier chips. Accordingly, the wafer usually has a thickness of hundreds of microns, which poses a challenge to subsequent packaging, heat dissipation, and the size and weight of the final product. In particular, for power devices such as rotating rectifier chips, they generate heat when working, and the thickness of the chip directly affects the heat dissipation efficiency. Too thick chips will not only increase the packaging cost and volume, but more importantly, they will hinder the conduction of heat from the inside of the chip to the radiator, causing the chip temperature to rise, thereby affecting the performance, reliability and life of the device. In addition, in order to separate thousands or even tens of thousands of independent chips on the wafer for independent testing, packaging and application, the wafer needs to be cut into single chips to meet the needs of modern electronic products for miniaturization, lightweight, and efficient heat dissipation, and to achieve independent processing and application of single chips.

[0034] In one implementation, the specific process of step S5 is as follows: First, wafer thinning is performed. Before thinning, a protective film, such as a UV-curable protective tape, is applied to the front (device) side of the wafer. This film prevents damage or contamination to the fabricated device structure from abrasive slurries, particles, or mechanical stress during the thinning process. Subsequently, the wafer is placed backside up and thinned using techniques such as mechanical lapping or chemical mechanical polishing. Mechanical lapping uses a high-speed rotating diamond grinding wheel to remove silicon material through the mechanical action of the abrasive particles, rapidly reducing the wafer thickness from an initial few hundred microns, such as 700 microns, to near the target thickness. To achieve a finer surface and remove lapping damage, multi-stage lapping is employed, gradually transitioning from coarse to fine grinding wheels. Chemical mechanical polishing combines mechanical lapping with chemical etching. Chemical components in the lapping slurry react with the silicon surface, while the mechanical action of the lapping pad removes reaction products, resulting in a flatter, damage-free surface and effectively eliminating subsurface damage and stress that may be introduced by mechanical lapping. The target thickness of the thinning depends on the application requirements of the final chip. For example, for a rotary rectifier chip, its thickness will be thinned to between 50 microns and 200 microns. The specific value will be optimized according to the device's heat dissipation requirements, mechanical strength, and subsequent packaging methods. For example, for high-power applications, a thinner chip such as 50 microns may be required to improve thermal conductivity, while for applications with higher mechanical strength requirements, a thicker chip such as 150 microns may be selected. After thinning is completed, the protective film on the front is removed and the wafer is thoroughly cleaned to remove all residual abrasive particles and chemicals.

[0035] Next, the wafer is diced. Before dicing, the wafer is attached to a sheet of dicing tape. This tape has a certain degree of stickiness, securing the diced chips in place and preventing them from scattering or shifting during the dicing process. During the subsequent chip pickup process, UV irradiation and other methods reduce the stickiness, facilitating chip separation. The dicing process utilizes either diamond blade dicing or laser dicing. Diamond blade dicing uses a high-speed rotating ultrathin diamond blade, such as one with a thickness of 20 to 50 microns, to cut the wafer into individual chips along pre-defined dicing lanes (slice streets). The blade width, cutting speed (e.g., 50 to 200 mm per second), and feed depth must be precisely controlled to ensure clean cut edges, minimize chipping and cracking, and maintain chip integrity. Deionized water is sprayed for cooling and rinsing during the dicing process to remove debris and heat generated by dicing. Laser dicing utilizes a high-energy laser beam (e.g., a nanosecond or picosecond laser) to melt or vaporize the silicon material, enabling contactless dicing. This method offers advantages such as high cutting speed, narrow cutting lanes, no mechanical stress, no edge chipping, and no cracks. It is particularly suitable for ultra-thin wafers or chips sensitive to mechanical stress, and can achieve more complex cutting paths. The cutting lanes are device-free areas pre-planned during chip design, with a width of between 50 and 100 microns to ensure that adjacent chips are not damaged during cutting and to provide sufficient space for the blade or laser beam. Ultimately, a complete rotating rectifier chip panel is broken down into multiple independent, dimensionally precise rotating rectifier chips.

[0036] In step S6, the plurality of rotary rectifier chips are subjected to chip testing and sorting. That is to say, in the complex manufacturing process of semiconductor chips, although each step of the process is strictly controlled, due to the microscopic characteristics of the materials, the limitation of equipment precision and the uncontrollability of environmental factors, the electrical performance and reliability of the thousands or even tens of thousands of chips produced on the wafer are often different. After a series of precision processes such as substrate layer preparation, PN junction formation, metal electrode production, passivation protection, wafer thinning and cutting are completed, the internal structure of a single chip may have tiny defects, uneven doping or stress concentration, all of which may cause the chip to fail to achieve the expected electrical parameters or malfunction in actual application. In order to ensure that only rotary rectifier chips that meet design specifications and performance requirements can enter the subsequent packaging link, avoid delivering unqualified products to customers, thereby ensuring product quality, reducing production costs and maintaining corporate reputation, multiple rotary rectifier chips need to be subjected to chip testing and sorting.

[0037] In one implementation, Figure 3 FIG. 1 is a flow chart of step S6 in the method for producing a rotating rectifier chip according to an embodiment of the present application. Figure 3As shown, step S6, chip testing and sorting of the multiple rotating rectifier chips, includes: S61, in response to the wafer yield being lower than a preset threshold, constructing a wafer map image matrix based on the test results of the multiple rotating rectifier chips; S62, performing pattern recognition and attribution of the yield spatial distribution map based on the wafer map image matrix to obtain root cause diagnosis suggestions.

[0038] It is understandable that in the chip testing and sorting process, it is not enough to just know whether the overall yield of the wafer is qualified. When the wafer yield is lower than the preset threshold, it means that there is some abnormality in the production process, but the yield value alone cannot reveal the specific root cause of the problem. For example, a drop in yield may be due to a failure of a component of the equipment that causes the chip to fail in a local area, or it may be due to a drift in process parameters that causes a specific defect to present a specific spatial distribution pattern on the wafer. Traditional troubleshooting methods often rely on engineers' experience and manual analysis, which is inefficient and prone to missing key information. In order to be able to more efficiently and accurately identify the spatial distribution pattern of unqualified chips on the wafer, the root cause of the fault in the production process can be quickly located and diagnosed. Therefore, in order to convert discrete test data into intuitive visual information that can be processed and pattern recognized, the present application constructs a wafer map image matrix.

[0039] In one implementation, Figure 4 FIG. 1 is a flow chart of step S61 in the method for producing a rotating rectifier chip according to an embodiment of the present application. Figure 4 As shown, step S61, in response to the wafer yield being lower than a preset threshold, constructing a wafer map image matrix based on the test results of the multiple rotating rectifier chips, includes: S611, constructing a wafer map image element matrix; S612, traversing the test results of the multiple rotating rectifier chips and performing the following operations: if the test result of the rotating rectifier chip is unqualified, filling zero in the corresponding position of the wafer map image element matrix; if the test result of the rotating rectifier chip is qualified, filling one in the corresponding position of the wafer map image element matrix.

[0040] The specific process of step S61 is as follows: First, perform step S611. During specific implementation, it is necessary to obtain the layout information of the wafer, including the number of rows and columns of chips on the wafer. For example, if the arrangement of chips on a wafer is 100 rows and 100 columns, then a 100x100 two-dimensional matrix will be constructed. Each element of this matrix will correspond to a chip position on the wafer. During the initial construction, all elements in the matrix can be assigned a default empty value or placeholder, indicating that the chip status at that position has not yet been filled. The size of this matrix is ​​predetermined based on the wafer design and chip layout. For example, for an 8-inch diameter wafer, if the size of a single chip is 2 mm x 2 mm, the wafer may contain thousands of chips, thereby determining the precise dimensions of the matrix.

[0041] Then, step S612 is performed. In specific implementation, after completing the electrical performance test of all chips on the wafer, the test equipment will generate a detailed test report, which contains the unique identifier of each chip (its row and column coordinates on the wafer) and its test results (pass or fail). The processing program will read the data of each chip in this test report one by one. For each chip, its physical coordinates on the wafer are first parsed, and then the value of the corresponding position in the wafer image element matrix is ​​updated according to the test results of the chip. If the test result of the chip is judged to be unqualified, the element value of the corresponding position of the chip in the matrix is ​​set to 0; if the test result of the chip is judged to be qualified, the element value of the corresponding position of the chip in the matrix is ​​set to 1. For example, if the test report shows that the chip located at the 5th row and 10th column of the wafer has passed the test, the value of the corresponding position in the matrix is ​​set to 1; if the chip at the 5th row and 11th column has failed the test, the value is set to 0. In this way, the entire wafer image element matrix is ​​filled with a binary image composed of 0 and 1, where 1 represents the pixel point of a qualified chip and 0 represents the pixel point of an unqualified chip, so as to intuitively show the spatial distribution of the yield of the chips on the wafer.

[0042] Accordingly, when the wafer yield is lower than the preset threshold, it means that there is some abnormality in the production process, but the yield value alone cannot reveal the specific root cause of the problem. For example, a drop in yield may be due to a failure of a component of the equipment that causes chip failure in a local area, or it may be due to a drift in process parameters that causes a specific defect to present a specific spatial distribution pattern on the wafer. In order to be able to more efficiently and accurately identify the spatial distribution pattern of unqualified chips on the wafer, and thus quickly locate and diagnose the root cause of the fault in the production process, the method performs pattern recognition and attribution of the yield spatial distribution map based on the wafer image matrix in order to convert discrete test data into intuitive visual information that can be processed and pattern recognized, and further extract meaningful features from it.

[0043] In one implementation, Figure 5 FIG. 1 is a flow chart of step S62 in the method for producing a rotating rectifier chip according to an embodiment of the present application. Figure 5 As shown, step S62, performing pattern recognition and attribution of the yield spatial distribution map based on the wafer map image matrix to obtain root cause diagnosis suggestions, including: S621, extracting the global features of the wafer yield spatial distribution from the wafer map image matrix; S622, extracting the regional spatial distribution features of the wafer yield from the wafer map image matrix; S623, extracting the texture features of the wafer yield distribution from the wafer map image matrix; S624, splicing the global features of the wafer yield spatial distribution, the regional spatial distribution features of the wafer yield and the texture features of the wafer yield distribution into a wafer yield distribution feature vector; S625, generating the root cause diagnosis suggestions based on the wafer yield distribution feature vector.

[0044] The specific process of step S62 is as follows: First, proceed to step S621. The overall wafer yield is calculated by counting the number of elements in the wafer map matrix with a value of 1 (good chips) and dividing this value by the total number of valid chip locations in the matrix. Furthermore, to more accurately capture global distribution trends, the wafer can be divided into multiple concentric regions. For example, for a 200 mm diameter wafer, a series of radius values, such as 50 mm, 90 mm, and 100 mm, can be predefined to divide the wafer into a central circular region (radius 0-50 mm), a middle annular region (radius 50-90 mm), and an edge annular region (radius 90-100 mm). The number of good chips in each region is then counted, and the regional yield is calculated for each region. These regional yields can effectively identify whether there is a center effect (e.g., a significantly lower yield in the center region than at the edges) or an edge effect (e.g., a significantly lower yield in the edge region than at the center). These effects are often related to global process parameters such as temperature, gas flow rate, or etching uniformity during wafer processing. These calculated overall qualified rates and the yield rates of each concentric area together constitute the global characteristics of the spatial distribution of wafer yield.

[0045] Next, step S622 proceeds. This step utilizes a sliding window technique, traversing the wafer map image matrix with a preset window size, such as 5x5 or 10x10 chip units. For each sliding window, the local yield within it is calculated (i.e., the proportion of qualified chips) or the degree of clustering of unqualified chips (i.e., the number of unqualified chips). By analyzing the yield variations in these local areas, clustered distributions of unqualified chips (e.g., localized contamination), linear distributions (e.g., scratches), or point-like distributions (e.g., random defects) can be identified. Furthermore, to more accurately quantify these local anomalies, connected domain analysis (CDA) methods from image processing can be utilized. This method identifies all regions consisting of consecutive zeros (unqualified chips) within the wafer map image matrix and considers each independent, continuous region as a connected domain. For each identified connected domain, its geometric features can be extracted, such as its area (i.e., the number of unqualified chips contained), perimeter, aspect ratio (i.e., the ratio of the longest axis to the shortest axis), compactness (i.e., the ratio of the square of the perimeter to the area), and the orientation of the principal axis. For example, a narrow low-yield area with an aspect ratio significantly greater than 1 may indicate a scratch defect generated during wafer transfer or processing; while a nearly circular low-yield area with a compactness close to 1 may indicate particle contamination or local hot spot effects.

[0046] Next, step S623 is performed. Texture features are calculated using a gray-level co-occurrence matrix (GLCM). For a binary wafer map image matrix (0 represents failure, 1 represents pass), the GLCM is constructed by counting pixel pairs at specific directions and distances within the image, for example, the frequency of a failed die appearing next to a passing die. Various texture features can be derived from the GLCM, such as contrast, which reflects local grayscale variations and texture depth in the image. High contrast may indicate a clear boundary between passing and failing dies. Energy, which reflects image uniformity and texture coarseness. High energy indicates good image uniformity. Homogeneity, which reflects the smoothness of local image variations. High homogeneity indicates a relatively uniform texture. Correlation, which reflects the linear dependence of pixel values ​​in a specific direction. Furthermore, a run-length matrix (GLRLM) can be used to extract the length distribution of consecutive passing or failing dies in different directions. The GLRLM counts the length and number of consecutive pixel runs (runs) with a specific grayscale value (0 or 1) in a given direction. This helps identify periodic defects (such as periodic streaks caused by equipment vibration) or streak-like defects (such as linear low-yield areas caused by uneven cleaning).

[0047] Then, proceed to step S624. All numerical features extracted in the previous three steps are integrated into a unified, high-dimensional numerical vector. For example, if the global feature extracts 5 numerical values, such as the overall yield, the yield of the three concentric regions, and the total number of unqualified chips, the regional feature extracts 10 numerical values, such as the maximum connected domain area, the average connected domain aspect ratio, the local yield standard deviation, etc., and the texture feature extracts 8 numerical values, such as the contrast, energy, homogeneity, and correlation of the GLCM, and the short-run emphasis and long-run emphasis of the GLRLM, then the final spliced ​​wafer yield distribution feature vector will contain 23 numerical values.

[0048] Finally, in step S625. In one implementation, step S625, based on the wafer yield distribution feature vector, generates the root cause diagnosis suggestion, including: S6251, inputting the wafer yield distribution feature vector into a pre-trained SVM model to obtain a prediction pattern category; S6252, searching the fault knowledge base for the prediction pattern category to obtain a list of potential high-risk processes; S6253, extracting a process deviation report from the process history of the wafer object based on the potential high-risk process list; S6254, generating the root cause diagnosis suggestion based on the prediction pattern category and the process deviation report.

[0049] The specific process of step S625 is as follows: First, step S6251 is performed. It is understood that in order to accurately identify wafer defect patterns, a wafer yield distribution feature vector, comprising local-global spatial distribution features and distribution texture features, is input into a support vector machine (SVM) model. Given the diversity of these input features and the complexity of the data distribution, the SVM preferably employs a radial basis function (RBF) as a kernel function to handle nonlinear relationships and fit complex decision boundaries. However, even with the RBF kernel function, differences in the numerical ranges and distribution morphologies of different feature dimensions, as well as potential inconsistencies between local and global features, can still affect the classification performance of the SVM model, resulting in insufficient fitting accuracy for the predicted pattern classification. To further enhance the decision-making consistency of the local-global spatial distribution features and distribution texture features within the SVM's radial basis function framework, and thereby improve the fitting accuracy for the predicted pattern classification, the wafer yield distribution feature vector is further subjected to probability density pre-conditioning before inputting it into the SVM model.

[0050] Step S6251, inputting the wafer yield distribution feature vector into a pre-trained SVM model to obtain a prediction mode category, including: first, performing offset constraint enhancement based on the feature mean on the wafer yield distribution feature vector to obtain an enhanced wafer yield distribution feature vector, namely: ;in, are the eigenvalues ​​in the wafer yield distribution eigenvector, is the characteristic mean of the wafer yield distribution feature vector, It is to strengthen each eigenvalue in the wafer yield distribution eigenvector. It should be understood that for each component in the wafer yield distribution eigenvector, based on the mean of all vector values, that is, the arithmetic mean of all component values ​​of the eigenvector, a nonlinear function is used to strengthen it. This function is similar to a nonlinear transformation with a mean constraint, which can transform the eigenvalue Towards the mean , so as to effectively contain the probability of the eigenvalue deviating from the mean tail and avoid the reinforcement of the extreme discrete distribution. For example, if a certain eigenvalue Much greater than or much less than the mean , after being processed by this function, its enhanced value The values ​​of the yield distribution vectors are adjusted appropriately to be closer to the mean, while retaining their relative magnitude. This ensures that the characteristic distribution of the wafer yield distribution feature vectors achieves balanced mean probability field coverage within the high-dimensional feature space, avoiding local overfitting or central sparsity that deviates from the mean, making the radial basis function more robust in spatial distribution.

[0051] Then, the distance directional modulation of the enhanced wafer yield distribution characteristic vector relative to the wafer yield distribution characteristic vector is used to perform directional modulation to obtain a distance directional modulation coefficient, that is: ;in, is the distance directional modulation coefficient. Accordingly, in order to correct the distance measurement deviation in the feature space, especially the limitation of Euclidean distance in dealing with direction-sensitive problems, so that local features (such as local spatial distribution features and distribution texture features) are consistent with the directional distribution of the mean probability field, the distance directional modulation coefficient is calculated in this application. That is, The quantified change in the overall directionality or offset of the eigenvector after offset constraint reinforcement provides a global modulation factor for the subsequent spatial resonance of the feature distribution, ensuring that when adjusting local features, the overall directionality relative to the original eigenvector can be taken into account.

[0052] Then, based on the distance directional modulation coefficient, the enhanced wafer yield distribution feature vector and the wafer yield distribution feature vector are subjected to feature distribution spatial resonance to obtain an optimized wafer yield distribution feature vector, namely: ;in, is the exponential function value with the natural constant e as the base, are the eigenvalues ​​in the optimized wafer yield distribution feature vector. It should be understood that by introducing a kernel function to resonate the feature distribution space, a probability aggregation effect can be formed in the decision boundary. This exponential function combines the distance directional modulation coefficient and the squared difference of the feature components before and after enhancement. For those feature components that differ significantly from the original value after enhancement, such as Larger, then The resonant processing makes the relationship between the local-global spatial distribution characteristics and the distribution texture characteristics of the feature vector more coordinated and unified before it is input into the SVM model, thereby improving the separability of the data in the feature space.

[0053] Finally, the optimized wafer yield distribution feature vector is input into the pre-trained SVM model to obtain the predicted pattern category. In other words, after the aforementioned pre-modulation of the probability density distribution, the numerical distribution of the various components of the wafer yield distribution feature vector is more balanced, and the directionality between local and global features is corrected, making the distribution of data points in the feature space more conducive to classification by the radial basis function kernel SVM model. When this optimized wafer yield distribution feature vector is input into the pre-trained SVM model, the model can more accurately identify the defect pattern category to which it belongs, thereby improving the fitting accuracy of the predicted pattern category and providing more reliable input for subsequent fault diagnosis. The specific implementation is as follows: The SVM (support vector machine) model is a supervised learning classifier that finds an optimal hyperplane in a high-dimensional feature space to maximize the separation between data points of different categories, thereby achieving effective data classification. Before being put into use, the SVM model was pre-trained using a large amount of historical wafer data. These historical data contain a variety of known wafer yield distribution feature vectors, and each vector has been manually labeled with its corresponding defect mode category, such as the center low yield mode, edge high yield mode, scratch mode, cluster defect mode, etc. When the optimized wafer yield distribution feature vector is input into this pre-trained SVM model, the model calculates the position of the feature vector in the multidimensional space and determines which side of which classification hyperplane it is located. By calculating the distance from the vector to each category hyperplane, the model can determine the defect mode category it most likely belongs to and output the prediction result. For example, if the input feature vector shows that the yield in the center area is significantly lower than that at the edge, the SVM model may predict it as a center low yield mode.

[0054] Subsequently, step S6252 is performed. It should be understood that the fault knowledge base is a structured database or expert system that stores a wealth of historical experience and domain knowledge, associating various known defect pattern categories with the potentially high-risk production processes that cause these patterns. This knowledge base can be designed as a mapping table or relational database, where each defect pattern category is associated with one or more production processes that may cause that pattern. For example, a center low-yield pattern corresponds to processes such as diffusion, ion implantation, and thin film deposition; an edge high-yield pattern corresponds to processes such as etching, cleaning, and photolithography; and a scratch pattern corresponds to processes such as wafer transfer, grinding, and dicing. Once a predicted pattern category, such as a center low-yield pattern, is obtained from the SVM model, the process uses this category as a query key to perform an exact or fuzzy match search within the fault knowledge base. The search operation traverses all entries in the knowledge base, finds the record corresponding to the input pattern category, and extracts the predefined list of potentially high-risk processes within that record. For example, if the predicted pattern category is a center low-yield pattern, the search result may return a list of processes such as diffusion, ion implantation, and thin film deposition.

[0055] Next, proceed to step S6253. Each wafer will have a detailed process history record during the manufacturing process, including the equipment used in each process, the set process parameters, the actual measured parameter values, and any abnormal events or alarm information. Based on the list of potential high-risk processes, the process will accurately extract the detailed data of these specific processes from its complete process history database for the unique identifier of the current wafer. These actual process parameters are then compared with the preset process control limits or standard values. Any parameters that exceed the control limits, have abnormal fluctuations, or deviate significantly from the standard values ​​will be recorded to form a process deviation report. For example, if the diffusion process is classified as high risk, the process will check the temperature curve, gas flow rate, time and other parameters of the wafer in the diffusion furnace, and report specific deviations such as the temperature in the center area of ​​the diffusion furnace exceeding the upper limit by 2°C during a certain period of time or the diffusion gas flow rate experiencing periodic fluctuations.

[0056] Finally, step S6254 is performed. In one implementation, step S6254 generates the root cause diagnosis suggestion based on the predicted pattern category and the process deviation report, including: injecting the predicted pattern category and the process deviation report into a predefined prompt template, and then inputting them into the large language model to obtain the root cause diagnosis suggestion. In specific implementation, one or more predefined prompt templates must first be defined. These templates are structured text strings that contain placeholders for inserting the predicted pattern category and process deviation report. For example, a prompt template can be designed as follows: "The wafer yield exhibits the following pattern: [predicted pattern category]. Simultaneously, the process history report shows the following deviation: [process deviation report]. Based on this information, please provide detailed root cause diagnosis suggestions and preliminary troubleshooting directions." This template is intended to provide clear context and task instructions for the large language model. Subsequently, the predicted pattern category, such as the center low yield pattern, and the process deviation report, such as the temperature in the center area of ​​the diffusion furnace exceeding the upper limit of 2°C during a certain period of time and the diffusion gas flow rate experiencing periodic fluctuations, are injected into the corresponding placeholders in the predefined prompt template. After the injection, the complete prompt string might become: "The wafer yield exhibits the following pattern: a low-yield pattern in the center. Simultaneously, the process history report shows the following deviations: the temperature in the center area of ​​the diffusion furnace exceeded the upper limit by 2°C during a certain period, and the diffusion gas flow rate exhibited periodic fluctuations. Based on this information, please provide detailed root cause diagnosis suggestions and preliminary troubleshooting directions." Finally, this padded prompt string is fed into a pre-trained large language model. This large language model is built on a deep neural network model based on the Transformer architecture, with a core self-attention mechanism. This mechanism enables the model to dynamically evaluate the strength and importance of associations between different words in the input sequence when processing input text, thereby capturing long-range dependencies and complex contextual semantics. For example, when processing the low-yield pattern in the center, the model can simultaneously attend to related words such as the diffusion furnace temperature and understand the potential causal relationship between them. The model internally comprises multiple layers of stacked Transformer encoder or decoder blocks, each consisting of a self-attention layer and a feedforward neural network. Through the complex interaction of these layers, the model is able to perform multi-level abstraction and feature extraction of input information. This model has been pre-trained on massive amounts of text data, acquiring rich linguistic knowledge, world common sense, and a certain level of reasoning ability. Upon receiving a prompt infused with specific information, the large language model leverages its internal weights and bias parameters (learned through large-scale unsupervised learning during the pre-training phase, these parameters encode the statistical regularities and semantic information of the language) to deeply understand and analyze the input text. It identifies the defect patterns and process deviations mentioned in the prompt and, based on the knowledge learned during the pre-training phase, performs logical reasoning and association analysis.Specifically, the model predicts the next most likely word based on the context of the input prompt and iterates this process until a coherent, reasonable, and professional root cause diagnosis suggestion is generated. For example, for the above prompt, the large language model might generate the following suggestion: "Diagnosis: The low yield pattern in the center of the wafer may be caused by abnormal temperature uniformity in the center area of ​​the diffusion furnace during the diffusion process. Recommendation: Immediately check the diffusion furnace temperature control sensor and calibrate the furnace temperature uniformity. At the same time, review the diffusion gas flow control system for fluctuations to ensure its stability." This can integrate discrete, specialized information into easy-to-understand and actionable suggestions, significantly improving the efficiency and accuracy of fault diagnosis.

[0057] In summary, the production method of the rotary rectifier chip based on the embodiment of the present application is explained, which covers the entire process from preparing the substrate layer, forming the PN junction, making the metal electrode, passivation protection, wafer thinning and cutting, to the final chip testing and sorting. In the traditional chip manufacturing process, especially in the chip testing and sorting link, advanced yield management and fault diagnosis mechanisms are incorporated. It is no longer necessary to rely solely on manual visual inspection and experience judgment of the wafer image, but through intelligent analysis of the test results, especially when the wafer yield is lower than the preset threshold, the wafer image matrix can be automatically constructed, and pattern recognition and attribution of the yield spatial distribution map can be performed based on this. This data-driven analysis method can efficiently and objectively identify failure points with specific spatial patterns, thereby accurately pointing to systematic upstream process problems. This significantly overcomes the defects of the prior art that rely on manual experience judgment, low efficiency, strong subjectivity, and difficulty in quickly locating systemic problems, and realizes automation and intelligence from problem discovery to root cause diagnosis, greatly shortening the troubleshooting time, thereby significantly improving the production efficiency and product yield of the rotary rectifier chip.

[0058] Specifically, in a specific example of the present application, a rotating rectifier chip is also included, which is produced by the above-mentioned production method of the rotating rectifier chip.

[0059] While various embodiments of the present disclosure have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for producing a rotating rectifier chip, characterized in that: include: A substrate layer is prepared, the substrate layer comprising an N-type single crystal silicon wafer base layer and an epitaxial layer grown on the N-type single crystal silicon wafer base layer; a PN junction is formed on the substrate layer; metal electrodes for conducting electricity are fabricated for the P region and the N region of the PN junction to obtain a rotating rectifier chip embryo; the rotating rectifier chip embryo is passivated to obtain a rotating rectifier chip panel; the rotating rectifier chip panel is wafer thinned and cut to obtain a plurality of rotating rectifier chips; and the plurality of rotating rectifier chips are chip tested and sorted.

2. The method for producing a rotating rectifier chip according to claim 1, wherein: A PN junction is formed on the substrate layer, comprising: growing a layer of silicon dioxide on the surface of the substrate layer by thermal oxidation to obtain a mask layer; coating the mask layer with photoresist, exposing the mask layer to ultraviolet light through a mask with a specific pattern, and then forming a window pattern on the mask layer by development; etching away the silicon dioxide exposed in the window pattern to expose the substrate layer thereunder by an etching process; and doping P-type impurities into the epitaxial layer below the window pattern by a high-temperature diffusion or ion implantation process to obtain the PN junction.

3. The method for producing a rotating rectifier chip according to claim 2, wherein: Chip testing and sorting are performed on the multiple rotating rectifier chips, including: in response to a wafer yield being lower than a preset threshold, constructing a wafer map image matrix based on the test results of the multiple rotating rectifier chips; and performing pattern recognition and attribution of the yield spatial distribution map based on the wafer map image matrix to obtain root cause diagnosis suggestions.

4. The method for producing a rotating rectifier chip according to claim 3, wherein: In response to the wafer yield being lower than a preset threshold, a wafer map image matrix is ​​constructed based on the test results of the multiple rotating rectifier chips, including: constructing a wafer map image element matrix; traversing the test results of the multiple rotating rectifier chips and performing the following operations: if the test result of the rotating rectifier chip is unqualified, filling zero in the corresponding position of the wafer map image element matrix; if the test result of the rotating rectifier chip is qualified, filling one in the corresponding position of the wafer map image element matrix.

5. The method for producing a rotating rectifier chip according to claim 4, characterized in that: Performing pattern recognition and attribution of the yield spatial distribution map based on the wafer map image matrix to obtain root cause diagnosis suggestions, including: extracting global features of the wafer yield spatial distribution from the wafer map image matrix; extracting regional spatial distribution features of the wafer yield from the wafer map image matrix; extracting texture features of the wafer yield distribution from the wafer map image matrix; splicing the global features of the wafer yield spatial distribution, the regional spatial distribution features of the wafer yield, and the texture features of the wafer yield distribution into a wafer yield distribution feature vector; and generating the root cause diagnosis suggestions based on the wafer yield distribution feature vector.

6. The method for producing a rotating rectifier chip according to claim 5, characterized in that: Based on the wafer yield distribution feature vector, the root cause diagnosis suggestion is generated, including: inputting the wafer yield distribution feature vector into a pre-trained SVM model to obtain a prediction pattern category; searching the prediction pattern category in a fault knowledge base to obtain a list of potential high-risk processes; based on the potential high-risk process list, extracting a process deviation report from the process history of the wafer object; and generating the root cause diagnosis suggestion based on the prediction pattern category and the process deviation report.

7. The method for producing a rotating rectifier chip according to claim 6, wherein: The wafer yield distribution feature vector is input into a pre-trained SVM model to obtain a prediction pattern category, including: performing offset constraint enhancement on the wafer yield distribution feature vector based on the feature mean to obtain an enhanced wafer yield distribution feature vector; performing directional modulation on the enhanced wafer yield distribution feature vector relative to the wafer yield distribution feature vector to obtain a distance directional modulation coefficient; based on the distance directional modulation coefficient, performing feature distribution spatial resonance on the enhanced wafer yield distribution feature vector and the wafer yield distribution feature vector to obtain an optimized wafer yield distribution feature vector; and inputting the optimized wafer yield distribution feature vector into the pre-trained SVM model to obtain the prediction pattern category.

8. The method for producing a rotating rectifier chip according to claim 7, wherein: Generating the root cause diagnosis suggestion based on the prediction mode category and the process deviation report includes: injecting the prediction mode category and the process deviation report into a predefined prompt template, and then inputting them into a large language model to obtain the root cause diagnosis suggestion.

9. A rotating rectifier chip, characterized in that: The rotating rectifier chip is manufactured by the production method of the rotating rectifier chip according to any one of claims 1 to 8.

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