Driving circuit, light-emitting substrate and display device

Abstract

A driving circuit comprises a pulse width modulation driving module (10 / Q), a pulse amplitude modulation driving module (20 / Q) and a light emitting control module (T8 / 30 / Q). The pulse width modulation driving module (10 / Q) comprises a first driving sub-circuit (T3 / 11), a first storage sub-circuit (C1 / 12) and a first reset sub-circuit (T1 / 13). The first reset sub-circuit (T1 / 13) is configured to write a first initialization signal from a first initialization signal end (Vinit1) to a first connection node (N1) under the control of a reset first reset signal from a first reset signal end (Ref1) in an initialization phase. The pulse amplitude modulation driving module (20 / Q) is configured to provide a driving signal to the light emitting control module (T8 / 30 / Q) under the control of the data voltage of the second control node (Nd2). The light emission control module (T8 / 30 / Q) is configured such that a light emission phase varies over time such that the pulse width modulation driving module (10 / Q) controls the voltage of the second control node (Nd2) based on the voltage of the first control node (Ndl) to control the duration of the pulse amplitude modulation driving module (20 / Q) providing the driving signal to the light emission control module (T8 / 30 / Q).

Description

Driving circuit, light-emitting substrate, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a driving circuit, a light-emitting substrate, and a display device. Background Art

[0002] Mini Organic Light-Emitting Diode (Mini LED) / Micro Organic Light-Emitting Diode (Micro LED) display devices have the advantages of high brightness, clear display images and low power consumption, and have good application prospects.

[0003] Summary of the Invention

[0004] In one aspect, a driving circuit is provided. The driving circuit includes a pulse width modulation driving module, a pulse amplitude modulation driving module, and a light-emitting control module. The pulse width modulation driving module includes a first driving sub-circuit, a first storage sub-circuit, and a first reset sub-circuit. The first driving sub-circuit is electrically connected to a first control node, a second control node, and a first power signal terminal, respectively. Under the control of the first control node, the first driving sub-circuit is configured to write a first power signal from the first power signal terminal to the second control node. The first storage sub-circuit is connected in series between the first control node and a first connection node. The first connection node is electrically connected to a first data voltage terminal and a sweep signal terminal, respectively. The first storage sub-circuit is configured to, during a first write phase, store a first data voltage from the first data voltage terminal and couple the first data voltage to the first control node. During a light-emitting phase, the sweep signal from the sweep signal terminal is coupled to the first control node via the first connection node. The first reset sub-circuit is electrically connected to the first connection node, the first reset signal terminal, and the first initialization signal terminal, respectively. The first reset subcircuit is configured to, during an initialization phase, write a first initialization signal from the first initialization signal terminal to the first connection node under control of a reset first reset signal from the first reset signal terminal. The pulse amplitude modulation driver module is electrically connected to the second data voltage terminal and the second control node, respectively. The pulse amplitude modulation driver module is configured to provide a drive signal to the light emission control module under control of the data voltage of the second control node. The light emission control module is electrically connected to the pulse width modulation driver module and the pulse amplitude modulation driver module, respectively. The light emission control module is configured such that the light emission phase varies over time, such that the pulse width modulation driver module controls the voltage of the second control node based on the voltage of the first control node, thereby controlling the duration for which the pulse amplitude modulation driver module provides the drive signal to the light emission control module.

[0005] In some embodiments, the first reset sub-circuit includes a first transistor, a control electrode of the first transistor is electrically connected to a first reset signal terminal, a first electrode of the first transistor is electrically connected to a first initialization signal terminal, and a second electrode of the first transistor is electrically connected to the first connection node.

[0006] In some embodiments, the first initialization signal terminal and the first data voltage terminal respond to the same signal terminal, and / or the first initialization signal terminal and the second data voltage terminal respond to the same signal terminal.

[0007] In some embodiments, the pulse width modulation driving module further includes a second reset sub-circuit, wherein the second reset sub-circuit is electrically connected to a second reset signal terminal, a second initialization signal terminal, and the first control node, respectively. The second reset sub-circuit is configured to, during an initialization phase, write a second initialization signal from the second initialization signal terminal to the first control node under the control of a second reset signal from the second reset signal terminal.

[0008] In some embodiments, the second reset sub-circuit includes a second transistor, a control electrode of the second transistor is electrically connected to the second reset signal terminal, a first electrode of the second transistor is electrically connected to the second initialization signal terminal, and a second electrode of the second transistor is electrically connected to the first control node.

[0009] In some embodiments, the first control node is multiplexed as the first initialization signal terminal.

[0010] In some embodiments, the first driving sub-circuit includes a third transistor, the control electrode of the third transistor is electrically connected to the first control node, the first electrode of the third transistor is electrically connected to the first power signal terminal, and the second electrode of the third transistor is electrically connected to the second connection node.

[0011] In some embodiments, the pulse width modulation driving module further includes a first compensation sub-circuit, which is electrically connected to the first control node, the second connection node and the first scan signal terminal, respectively. The first compensation sub-circuit is configured to write the voltage of the first control node to the second connection node under the control of the first scan signal from the first scan signal terminal during the initialization phase.

[0012] In some embodiments, the first compensation sub-circuit further includes a fourth transistor, the control electrode of the fourth transistor is electrically connected to the first scan signal terminal, the first electrode of the fourth transistor is electrically connected to the first control node, and the second electrode of the fourth transistor is electrically connected to the second connection node.

[0013] In some embodiments, the second connection node is multiplexed as the first initialization signal terminal.

[0014] In some embodiments, the driving circuit also includes a connection control module, which is electrically connected to the second scan signal end, the second connection node and the second control node, respectively. The connection control module is configured to write the voltage of the second connection node into the second control node under the control of the second scan signal from the second scan signal end.

[0015] In some embodiments, the connection control module includes a fifth transistor, the control electrode of the fifth transistor is electrically connected to the second scan signal end, the first electrode of the fifth transistor is electrically connected to the second connection node, and the second electrode of the fifth transistor is electrically connected to the second control node.

[0016] In some embodiments, the second control node is multiplexed as the first initialization signal terminal.

[0017] In some embodiments, the pulse width modulation driving module further includes a first write sub-circuit, which is electrically connected to the first data voltage terminal, the first connection node and the third scan signal terminal, respectively. The first write sub-circuit is configured to write the first voltage data from the first voltage data terminal to the first connection node under the control of the third scan signal from the third scan signal terminal.

[0018] In some embodiments, the first write sub-circuit includes a sixth transistor, the control electrode of the sixth transistor is electrically connected to the third scan signal terminal, the first electrode of the sixth transistor is electrically connected to the first data voltage terminal, and the second electrode of the sixth transistor is electrically connected to the first connection node.

[0019] In some embodiments, the pulse amplitude modulation driving module includes a second write subcircuit and a second storage subcircuit. The second write subcircuit is connected to a fourth scan signal terminal, the second data voltage terminal, and the second control node, respectively. The second write subcircuit is configured to write a second data write voltage from the second data voltage terminal to the second control node under the control of a fourth scan signal from the fourth scan signal terminal. The second storage subcircuit is connected in series between the second control node and the second power signal terminal.

[0020] In some embodiments, the second writing sub-circuit includes a seventh transistor, the control electrode of the seventh transistor is electrically connected to the fourth scan signal terminal, the first electrode of the seventh transistor is electrically connected to the second data voltage terminal, and the second electrode of the seventh transistor is electrically connected to the second control node.

[0021] In another aspect, a light-emitting substrate is provided. The light-emitting substrate includes a substrate, a driving circuit layer, and a light-emitting device layer. The driving circuit layer is located on one side of the substrate and includes a plurality of driving circuits as described above. The light-emitting device layer is located on a side of the driving circuit layer facing away from the substrate.

[0022] In another aspect, a display device is provided. The display device includes a backlight module and a liquid crystal display panel, wherein the liquid crystal display panel is located on the light-emitting side of the backlight module. The backlight module includes the light-emitting substrate described above.

[0023] In another aspect, a display device is provided. The display device includes a display panel and a cover plate. The cover plate is located on the light-emitting side of the display panel, and the display panel includes the light-emitting substrate described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0025] FIG1 is a schematic plan view of a display device according to some embodiments;

[0026] FIG2 is a structural diagram of a display device according to some embodiments;

[0027] FIG3 is a structural diagram of a display device according to some other embodiments;

[0028] FIG4 is a structural diagram of a light-emitting substrate according to some embodiments;

[0029] FIG5 is a cross-sectional view of a light emitting substrate according to some embodiments;

[0030] FIG6 is a schematic diagram of implementing grayscale of a light emitting device by using a pulse amplitude modulation driving method according to some embodiments;

[0031] FIG7 is a schematic diagram of implementing grayscale of a light emitting device by adopting a pulse width modulation driving method according to some embodiments;

[0032] FIG8 is a graph showing current efficiency versus current density for driving current flowing through a blue LED, a green LED, and a red LED according to some embodiments;

[0033] FIG9 is an equivalent circuit diagram of a driving circuit according to some embodiments;

[0034] FIG10 is an equivalent circuit diagram of a driving circuit according to some other embodiments;

[0035] FIG11 is an equivalent circuit diagram of a driving circuit according to yet other embodiments;

[0036] FIG12 is an equivalent circuit diagram of a driving circuit according to yet other embodiments;

[0037] FIG13 is an equivalent circuit diagram of a driving circuit according to yet other embodiments;

[0038] FIG14 is an equivalent circuit diagram of a driving circuit according to yet other embodiments;

[0039] FIG15 is an equivalent circuit diagram of a driving circuit according to yet other embodiments;

[0040] FIG16 is an equivalent circuit diagram of a driving circuit according to yet other embodiments;

[0041] FIG17 is an equivalent circuit diagram of a driving circuit according to yet other embodiments;

[0042] FIG18 is an equivalent circuit diagram of a driving circuit according to yet other embodiments;

[0043] FIG19 is an equivalent circuit diagram of a driving circuit according to yet other embodiments;

[0044] FIG20 is a timing diagram of a driving circuit according to some embodiments;

[0045] FIG. 21 is a timing simulation diagram of a driving circuit according to some embodiments. DETAILED DESCRIPTION

[0046] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0047] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0048] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0049] When describing some embodiments, the word "connected" and its derivatives may be used. The term "connected" should be understood broadly. For example, "connected" can mean fixed, removable, or integrated; it can be directly connected or indirectly connected through an intermediary. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0050] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0051] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0052] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0053] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices being configured to perform additional tasks or steps.

[0054] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0055] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0056] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0057] In the circuit provided in the embodiments of the present disclosure, the first control node, the second control node, the first connection node and the second connection node do not represent actually existing components, but represent the junction points of related electrical connections in the circuit diagram, that is, these nodes are nodes formed by equivalent junction points of related electrical connections in the circuit diagram.

[0058] The transistors included in the circuit structure provided in the embodiments of the present disclosure may all be N-type transistors, or may all be P-type transistors, or may be partly N-type transistors and partly P-type transistors. In the present disclosure, "effective voltage" refers to the voltage that can turn on the transistors. Among them, P-type transistors can be turned on under the control of a low voltage signal, and N-type transistors can be turned on under the control of a high voltage signal.

[0059] In the following, a schematic description is given by taking as an example an example that all transistors included in the circuit structure provided in the embodiment of the present disclosure are P-type transistors.

[0060] In the present disclosure, a P-type transistor may be turned on under the control of a low voltage signal, and an N-type transistor may be turned on under the control of a high voltage signal.

[0061] FIG. 1 is a schematic plan view of a display device according to some embodiments.

[0062] As shown in FIG. 1 , some embodiments of the present disclosure provide a display device 1000 .

[0063] Exemplarily, the display device 1000 can be any display device that displays images, whether in motion (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, it is expected that the display device of the embodiments described can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0064] Exemplarily, the display device 1000 may be a liquid crystal display device (LCD), a Mini LED (Mini Light-Emitting Diode, Mini LED) display device, or a Micro LED (Micro Light-Emitting Diode, Micro LED) display device.

[0065] FIG. 2 is a structural diagram of a display device according to some embodiments.

[0066] As shown in FIG2 , when the display device 1000 is a liquid crystal display device, in some embodiments, the display device 1000 includes a backlight module 300 and a liquid crystal display panel 200. The liquid crystal display panel 200 is located on the light-emitting side of the backlight module 300. The backlight module 300 is used to provide light for the liquid crystal display panel 200, so that the liquid crystal display panel 200 can display images.

[0067] The main structure of the liquid crystal display panel 200 includes an array substrate 210, a cell substrate 220, and a liquid crystal layer 230 disposed between the array substrate 210 and the cell substrate 220. In some examples, the cell substrate 220 may be a color filter substrate (CF).

[0068] As shown in FIG2 , in some embodiments, the backlight module 300 includes a light emitting substrate 100. The light emitting substrate 100 is used to provide light to the liquid crystal display panel so that the liquid crystal display panel can display images.

[0069] As can be understood, light can be emitted through the backlight module 300 and illuminate the liquid crystal layer 230. By adjusting the arrangement of the liquid crystal molecules in the liquid crystal layer 230, the intensity of light passing through the liquid crystal layer 230 can be adjusted, thereby adjusting the intensity of light irradiating the cell substrate 220. Since the cell substrate 220 is a color filter substrate, by adjusting the intensity of light irradiating the different color photoresist units, the display device 1000 can display color images.

[0070] In some examples, the backlight module in the display device 1000 may further include an optical film, which is located on the side of the light-emitting substrate 100 close to the liquid crystal display panel. The optical film may include a reflective sheet, a diffuser, a brightness enhancement film (prism sheet), a diffuser, etc., and may be used to improve the brightness and uniformity of light.

[0071] FIG3 is a structural diagram of a display device according to some other embodiments.

[0072] As shown in FIG3 , when the display device 1000 is a Mini LED display device or a Micro LED display device, in some embodiments, the display device 1000 includes a display panel, and the display panel includes at least one light-emitting substrate 100 , which can realize image display.

[0073] The difference between the display device 1000 shown in FIG3 and the display device 1000 shown in FIG2 is that the display device 1000 shown in FIG3 does not require a backlight module. Instead, the light-emitting substrate 100 within the display panel can directly emit at least one of red, green, and blue light, enabling the display device 1000 to achieve color display. Furthermore, the display device 1000 can implement local dimming (LD) to achieve a high-dynamic range (HDR) effect, significantly improving the contrast of the displayed image and enhancing the display quality of the display device 1000, providing users with a better visual experience.

[0074] In some examples, the display device 1000 may include a plurality of light-emitting substrates 100 , which are spliced ​​together to form the display device 1000 . Alternatively, the display device 1000 may also include a single light-emitting substrate 100 .

[0075] In some examples, the display device 1000 may further include an anti-reflection film layer and a protective cover plate. The anti-reflection film layer is located between the light-emitting substrate 100 and the protective cover plate. The anti-reflection film layer includes a polarizer, which may be a circular polarizer. The polarizer can reduce external light emission and prevent the light-emitting substrate 100 from reflecting ambient light, thereby causing glare.

[0076] FIG4 is a structural diagram of a light emitting substrate according to some embodiments.

[0077] As shown in FIG4 , the light-emitting substrate 100 comprises a display area (active area, AA for short; also referred to as the effective main functional area) AA and a peripheral area SA. The peripheral area SA is located on at least one side (e.g., one side; or, for example, all four sides, i.e., including the upper and lower sides and the left and right sides) of the main functional area AA.

[0078] The light-emitting substrate 100 may include a plurality of sub-pixels P, which are disposed in the display area AA. Each sub-pixel P may include a light-emitting device and a driving circuit for driving the light-emitting device to emit light. The driving circuit may drive the light-emitting device to thereby display grayscale or gradation in sub-pixel units. The plurality of sub-pixels P may be arranged in an array.

[0079] The sub-pixel P is the smallest unit for displaying images on the light-emitting substrate 100. Multiple sub-pixels P may include red sub-pixels, blue sub-pixels, and green sub-pixels. By adjusting the brightness (grayscale) of sub-pixels of different colors, multiple colors can be displayed through color combination and superposition, thereby realizing full-color display of the light-emitting substrate 100.

[0080] In some other examples, the light-emitting substrate 100 may further include white sub-pixels.

[0081] FIG5 is a cross-sectional view of a light emitting substrate according to some embodiments.

[0082] 4 and 5 , the light emitting substrate 100 includes a substrate 101 , a driving circuit layer 102 , and a light emitting device layer 103 , wherein the driving circuit layer 102 is located between the substrate 101 and the light emitting device layer 103 .

[0083] In some examples, substrate 101 may be a flexible substrate. Exemplarily, the material of substrate 101 may be an organic material. For example, the material of substrate 101 may be any one of polyimide (PI), polycarbonate (PC), or polyvinyl chloride (PVC).

[0084] In other examples, the substrate 101 may be a rigid substrate, for example, a glass substrate or a polymethyl methacrylate (PMMA) substrate.

[0085] In some examples, the driving circuit layer 102 includes multiple driving circuits Q, and the light-emitting device layer 103 includes multiple light-emitting devices O. The multiple light-emitting devices O are electrically connected to the multiple driving circuits Q. The driving circuits Q can generate driving signals. Each light-emitting device O can emit light under the driving effect of the driving signal generated by the corresponding driving circuit Q.

[0086] In some examples, the multiple driving circuits Q and the multiple light-emitting devices O may be electrically connected in a one-to-one correspondence. In other examples, one driving circuit Q may be electrically connected to multiple light-emitting devices O, or multiple driving circuits Q may be electrically connected to one light-emitting device O.

[0087] Hereinafter, the present disclosure takes the electrical connection between a driving circuit Q and a light-emitting device O as an example to schematically illustrate the structure of the light-emitting substrate 100 .

[0088] In some examples, the light emitting device O may be at least one of a light emitting diode (LED), a sub-millimeter light emitting diode (Mini Light-Emitting Diode, Mini LED), and a micro light emitting diode (Micro Light-Emitting Diode, Micro LED).

[0089] For example, the plurality of light-emitting devices O may be light-emitting devices O that can emit light of the same color, for example, they may all be blue LEDs, red LEDs, green LEDs, or yellow LEDs. Thus, the display device 1000 may be a monochrome display device, such as an instrument dial, a signal indicator screen, or the like.

[0090] For example, the plurality of light-emitting devices O may include light-emitting devices O of multiple different colors, for example, at least two of a red LED, a green LED, a blue LED, a yellow LED, etc., and the light-emitting diodes of different colors may be independently controlled. In this way, the display device 1000 can perform color display by mixing light.

[0091] Figure 6 is a schematic diagram of achieving grayscale of a light-emitting device using a pulse amplitude modulation driving method according to some embodiments, Figure 7 is a schematic diagram of achieving grayscale of a light-emitting device using a pulse width modulation driving method according to some embodiments, and Figure 8 is a graph showing the current efficiency of the driving current flowing in the blue LED, green LED, and red LED as a function of current density according to some embodiments.

[0092] 6 to 8 , in each sub-pixel P of the light-emitting substrate 100 , the driving circuit Q can drive the light-emitting device O using a pulse amplitude modulation (PAM) driving method. That is, the driving circuit Q can achieve grayscale of the sub-pixel by modulating the pulse amplitude.

[0093] When using the PAM drive method, as the driving current changes, not only the grayscale of the sub-pixel changes, but the wavelength also changes, resulting in a decrease in the color reproducibility of the picture.

[0094] To avoid a decrease in color reproducibility, the overall current of each sub-pixel P should be maintained constant when achieving the brightness of the light-emitting substrate 100. To this end, the driver circuit Q in each sub-pixel P of the light-emitting substrate 100 can also drive the light-emitting device O using a pulse width modulation (PWM) drive method. That is, the driver circuit Q can achieve the grayscale of the sub-pixel by modulating the pulse width. Therefore, a PWM drive method can be used to control the light-emitting device O's emission time, thereby avoiding a decrease in the image's color reproducibility.

[0095] Based on this, in each sub-pixel P within the light-emitting substrate 100 provided by the embodiment of the present disclosure, the driving circuit Q can drive the light-emitting device O using both a PAM driving mode and a PWM driving mode. That is, the driving circuit Q can control both the pulse amplitude and the pulse width of the driving current driving the light-emitting device O, and can provide the light-emitting device O with a driving current having both the pulse amplitude and the pulse width controlled.

[0096] It should be noted that the fact that the driver circuit Q can control both the pulse amplitude and pulse width of the drive current does not necessarily mean that the driver circuit Q must control both simultaneously. In other words, this does not mean that the driver circuit Q controls both the pulse amplitude and pulse width of the drive current simultaneously. Rather, it indicates that the driver circuit Q uses both PAM and PWM drive modes when adjusting the drive current. This allows the driver circuit Q to achieve a consistent pulse amplitude of the drive current using the PAM drive mode. Furthermore, the driver circuit Q can also use the PWM drive mode to adjust the pulse width of the drive current to control the light-emitting duration of the light-emitting element O, thereby presenting a variety of color gradations. This improves the problem of the wavelength of the light-emitting device O varying with the amplitude of the drive current, enabling precise control of the grayscale of the light emitted by the light-emitting device O. The problem of low display quality of the image displayed by the light-emitting substrate 100 is addressed.

[0097] FIG. 9 is an equivalent circuit diagram of a driving circuit according to some embodiments.

[0098] In some embodiments, as shown in FIG. 9 , the driving circuit Q includes a pulse width modulation driving module 10 , a pulse amplitude modulation driving module 20 and a light emitting control module 30 .

[0099] The pulse width modulation driver module 10 is electrically connected to the first control node Nd1, the second control node Nd2, the first power signal terminal VDD1, the first data voltage terminal Data1, and the sweep signal terminal Sweep. The pulse width modulation driver module 10 is configured to control the pulse width of the driving current based on the first data voltage from the first data voltage terminal Data1. Here, the pulse width of the driving current is also referred to as the duty cycle of the driving current or the duration of the driving current.

[0100] For example, the greater the amplitude of the driving current, the higher the brightness of the light that the light emitting device O can emit, and the greater the pulse width (that is, the higher the duty cycle or the longer the duration), the higher the brightness of the light that the light emitting device O can emit.

[0101] By adding a pulse width modulation drive module 10 (PWM drive mode) to provide a certain amount of drive current to the light-emitting device O and controlling the light-emitting time, the brightness performance of the light-emitting device O at low grayscales can be improved. The greater the amplitude of the drive current, the higher the brightness of the light-emitting device O. The longer the pulse width (i.e., the higher the duty cycle or the longer the drive time), the higher the brightness of the light-emitting device O, but the present invention is not limited to this.

[0102] The pulse amplitude modulation driving module 20 is electrically connected to the second data voltage terminal Data2 and the second control node Nd2. The pulse amplitude modulation driving module 20 is configured to provide a driving signal to the light emitting control module 30 under the control of the data voltage at the second control node Nd2. In other words, the pulse amplitude of the driving current is controlled based on the second data voltage from the second data voltage terminal Data2.

[0103] The light-emitting control module 30 is electrically connected to the pulse width modulation driving module 10 and the pulse amplitude modulation driving module 20, respectively. The light-emitting control module 30 is configured to change with time during the light-emitting stage so that the pulse width modulation driving module 10 controls the voltage of the second control node Nd2 based on the voltage of the first control node Nd1, thereby controlling the duration of the drive signal provided by the pulse amplitude modulation driving module 20 to the light-emitting control module 30.

[0104] In summary, in the driving circuit Q provided by the embodiments of the present disclosure, the pulse width modulation driving module 10 (PWM driving mode) can control the pulse width of the driving current provided to the light-emitting device O to be driven based on the first data voltage (pulse width modulation data voltage), and the pulse amplitude modulation driving module 20 (PAM driving mode) can control the amplitude of the driving current provided to the light-emitting device O to be driven based on the second data voltage (pulse amplitude modulation data voltage). In other words, the pulse width of the driving current used by the pulse amplitude modulation driving module 20 to drive the light-emitting device O is ultimately consistent with the pulse width of the first data voltage (pulse width modulation data voltage) received by the modulation driving module 10, and the amplitude of the driving current output by the pulse amplitude modulation driving module 20 to the light-emitting device O is consistent with the amplitude of the second data voltage (pulse amplitude modulation data voltage) received by the pulse amplitude modulation driving module 20. As a result, color gradation can be expressed using driving currents of the same amplitude, thereby alleviating the problem of the wavelength of the light-emitting device O varying with the amplitude of the driving current, thereby achieving precise control of the color gradation of the light emitted by the light-emitting device O.

[0105] FIG10 is an equivalent circuit diagram of a driving circuit according to some other embodiments.

[0106] In some examples, as shown in FIG. 10 , the pulse width modulation driving module 10 may include a first driving sub-circuit 11 and a first storage sub-circuit 12 .

[0107] The first driving sub-circuit 11 is electrically connected to the first control node Nd1, the second control node Nd2, and the first power signal terminal VDD1, respectively. The first driving sub-circuit 11 is configured to write the first power signal of the first power signal terminal VDD1 into the second control node Nd2 under the control of the first control node Nd1.

[0108] In some examples, the first driving sub-circuit 11 includes a third transistor T3, the control electrode g3 of the third transistor T3 is electrically connected to the first control node Nd1, the first electrode s3 of the third transistor T3 is electrically connected to the first power signal terminal VDD1, and the second electrode d3 of the third transistor T3 is electrically connected to the second connection node N2.

[0109] The third transistor T3 can be turned on under the control of the first control node Nd1 to write the first power signal of the first power signal terminal VDD1 into the second control node Nd2.

[0110] The first storage sub-circuit 12 is connected in series between the first control node Nd1 and the first connection node N1. The first connection node N1 is electrically connected to the first data voltage terminal Data1 and the sweep signal terminal Sweep, respectively. The first storage sub-circuit 12 is configured to store the first data voltage from the first data voltage terminal Data1 during a first write phase and couple the first data voltage to the first control node Nd1. During a light-emitting phase, the first storage sub-circuit 12 couples the sweep signal from the sweep signal terminal Sweep to the first control node Nd1 via the first connection node N1.

[0111] As shown in the above structure, during the first write phase, the first storage sub-circuit 12 in the pulse width modulation driving module 10 stores the first data voltage from the first data voltage terminal Data1 and couples the first data voltage (pulse width modulation data voltage) to the first control node Nd1. The first storage sub-circuit 12 can maintain the voltage of the first control node Nd1 based on the stored first data voltage.

[0112] In some examples, the first storage sub-circuit 12 includes a first capacitor C1, wherein a first plate of the first capacitor C1 is electrically connected to the first control node Nd1, and a second plate of the first capacitor C1 is electrically connected to the first connection node N1. Based on capacitive coupling, the first capacitor C1 can couple the voltage of the first connection node N1 to the first control node Nd1.

[0113] In some examples, the pulse width modulation driving module 10 may further include a storage capacitor Cst, where the storage capacitor Cst is connected in series between the first connection node N1 and the sweep signal terminal Sweep.

[0114] During the light emitting period, the sweep signal from the sweep signal terminal Sweep is coupled to the first connection node N1 via the storage capacitor Cst, and the voltage of the first connection node N1 is coupled to the first control node Nd1 using the first capacitor C1.

[0115] Based on this, during the light-emitting phase, the sweep signal terminal Sweep provides a linearly varying sweep signal (sweep voltage), and the first connection node N1 receives the sweep signal from the sweep signal terminal Sweep and couples the sweep signal to the first control node Nd1. As a result, the voltage at the first control node Nd1 begins to decrease linearly until the first driver sub-circuit 11 in the pulse-width modulation driver module 10 is turned on. The first driver sub-circuit 11 writes the first power signal from the first power signal terminal VDD1 to the second control node Nd2. The voltage at the second control node Nd2 gradually increases until a short circuit occurs within the light-emitting control module 30, blocking the drive current and causing the light-emitting device O to cease emitting light. Based on this, the pulse width of the drive current can be controlled based on the first data voltage from the first data voltage terminal Data1.

[0116] However, the inventors discovered through research that due to the indirect electrical connection between the first connection node N1 and the first control node Nd1. Specifically, the first connection node N1 is electrically connected to the first control node Nd1 through the first storage sub-circuit 12 (first capacitor C1). Before the driving circuit Q performs the threshold compensation stage, the first connection node N1 is still maintained at the potential of the previous frame. However, since the potential of the first connection node N1 in the driving circuit Q in the previous frame is not fixed. The voltage of the first connection node N1 will change according to C / (C+Cs)*ΔV1. Among them, C is the capacitance value of the first capacitor C1, ΔV1 is the change value of the voltage of the first control node Na1, and Cs is the capacitance value of the storage capacitor Cst.

[0117] Based on this, the voltage at the first connection node N1 affects the voltage at the first control node Nd1, thereby affecting the potential of the control electrode of the third transistor T3 in the first driver sub-circuit 11, affecting the subsequent threshold compensation of the third transistor T3 in the first driver sub-circuit 11. Therefore, even if the transistors are manufactured under the same conditions, the threshold voltages of the third transistors T3 in different driver circuits Q will be different.

[0118] In this way, if there are differences between the threshold voltages of the third transistors T3 in the respective drive circuits Q, the pulse width modulation drive modules 10 in the respective drive circuits Q cannot provide drive currents with the same pulse width to the corresponding light-emitting devices O. In other words, even if the same data voltage is applied to the control electrodes g3 (first control nodes N1) of the third transistors T3 in the respective drive circuits Q, the pulse width modulation drive modules 10 in the respective drive circuits Q will provide different drive currents corresponding to the differences in threshold voltages to the corresponding light-emitting devices O. This will appear as a mottled appearance in the image, degrading the display quality of the light-emitting substrate 100.

[0119] FIG. 11 is an equivalent circuit diagram of a driving circuit according to yet other embodiments.

[0120] Based on this, in some embodiments, as shown in FIG11 , the pulse width modulation driving module 10 may further include a first reset sub-circuit 13, which is electrically connected to the first connection node N1, the first reset signal terminal Ref1, and the first initialization signal terminal Vinit1. The first reset sub-circuit 13 is configured to, during the initialization phase, write the first initialization signal from the first initialization signal terminal Vinit1 to the first connection node N1 under the control of the reset first reset signal from the first reset signal terminal Ref1.

[0121] Based on this, during the initialization phase, the first reset sub-circuit 13 can be used to write the first initialization signal from the first initialization signal terminal Vinit1 to the first connection node N1, thereby resetting the first connection node N1. This ensures that the first connection node N1 of each driver circuit Q maintains a consistent value before the threshold compensation phase begins. Furthermore, this can alleviate the problem of different voltages at the first connection node N1 leading to different voltages at the corresponding first control node Nd1. This helps improve the stability of the first driver sub-circuit 11 (third transistor T3), allowing the pulse width modulation driver module 10 in each driver circuit Q to provide a driving current with the same pulse width to its corresponding light-emitting device O, thereby enhancing the display effect of the light-emitting substrate 100.

[0122] In some embodiments, as shown in Figure 11, the first reset sub-circuit 13 includes a first transistor T1, the control electrode g1 of the first transistor T1 is electrically connected to the first reset signal terminal Ref1, the first electrode s1 of the first transistor T1 is electrically connected to the first initialization signal terminal Vinit1, and the second electrode d1 of the first transistor T1 is electrically connected to the first connection node N1.

[0123] During the initialization stage, the effective voltage (first reset signal) provided from the first reset signal terminal Ref1 is written to the control electrode g1 of the first transistor T1, and the first transistor T1 is controlled to open, so as to write the first initialization signal from the first initialization signal terminal Vinit1 to the first connection node N1, thereby resetting the first connection node N1.

[0124] Based on this, the problem of different voltages at the first control node Nd1 due to different voltages at the first connection node N1 can be improved. This helps improve the stability of the first driver sub-circuit 11 (third transistor T3), so that the pulse width modulation driver module 10 in each driver circuit Q provides a driving current with the same pulse width to its corresponding light-emitting device O, thereby improving the display effect of the light-emitting substrate 100.

[0125] In some examples, the voltage of the first initialization signal at the first initialization signal terminal Vinit1 may be 0 V. However, the embodiments of the present disclosure are not limited thereto.

[0126] It should be noted that in the present disclosure, “effective voltage” refers to the voltage that can turn on the transistor. Among them, the N-type transistor is turned on when the gate receives a high voltage signal, and the P-type transistor is turned on when the gate receives a low voltage signal. It should be noted that the “high voltage signal” and “low voltage signal” mentioned above are popular terms. Generally speaking, the opening condition of the N-type transistor is that the gate-source voltage difference is greater than its threshold voltage, that is, the gate voltage of the N-type transistor is greater than the sum of its source voltage and its threshold voltage. The threshold voltage of the N-type transistor is a positive value, then the gate voltage signal that turns on the N-type transistor is called a high voltage signal, the opening condition of the P-type transistor is that the absolute value of the gate-source voltage difference is greater than its threshold voltage, the threshold voltage of the P-type transistor is a negative value, that is, the gate voltage of the P-type transistor is less than the sum of its source voltage and its threshold voltage, then the gate voltage signal that turns on the P-type transistor is called a low voltage signal, wherein the voltage of the “high voltage signal” is greater than the voltage of the “low voltage signal”.

[0127] In some examples, the driving circuit Q includes multiple transistors. The multiple transistors may all be P-type transistors. The P-type transistors may be low-temperature polysilicon (LTPS) transistors. FIG. 11 illustrates multiple transistors as P-type transistors for illustrative purposes. However, this is not limiting.

[0128] FIG12 is an equivalent circuit diagram of a driving circuit according to yet another embodiment. The driving circuit Q shown in FIG12 differs from the driving circuit Q shown in FIG11 in that the first initialization signal terminal Vinit1 and the first data voltage terminal Data1 in the driving circuit Q shown in FIG12 respond to the same signal terminal, whereas the first initialization signal terminal Vinit1 and the first data voltage terminal Data1 in the driving circuit Q shown in FIG11 respond to different signal terminals.

[0129] In some embodiments, as shown in FIG12 , the first initialization signal terminal Vinit1 and the first data voltage terminal Data1 respond to the same signal terminal. Alternatively, it can be understood that the first data voltage terminal Data1 can be multiplexed as the first initialization signal terminal Vinit1. In this case, during the initialization phase, the first data voltage signal terminal Data1 can provide an effective voltage to the first transistor T1 of the first reset sub-circuit 13 to control the first transistor T1 to turn on, thereby writing the first initialization signal from the first initialization signal terminal Vinit1 to the first connection node N1, thereby resetting the first connection node N1.

[0130] Based on this, the number of signal terminals in the light-emitting substrate 100 can be reduced, which not only helps to save space in the light-emitting substrate 100 to facilitate the layout of other devices, but also saves resources.

[0131] In some embodiments, as shown in Figure 11, the pulse width modulation driving module 10 further includes a second reset sub-circuit 14, and the second reset sub-circuit 14 is electrically connected to the second reset signal terminal Ref2, the second initialization signal terminal Vinit2 and the first control node Nd1. The second reset sub-circuit 14 is configured to, during the initialization phase, write the second initialization signal from the second initialization signal terminal Vinit2 to the first control node Nd1 under the control of the second reset signal from the second reset signal terminal Ref2.

[0132] Based on this, during the initialization phase, the second reset sub-circuit 14 can be used to write the second initialization signal from the second initialization signal terminal Vinit2 to the first control node Nd1, thereby resetting the first control node Nd1. This is equivalent to resetting the control electrode of the third transistor T3 of the first driver sub-circuit 11. This helps improve the stability of the first driver sub-circuit 11 (the third transistor T3), allowing the pulse width modulation driver modules 10 in each driver circuit Q to provide drive currents with the same pulse width to their corresponding light-emitting devices O, thereby improving the display effect of the light-emitting substrate 100.

[0133] In some examples, as shown in Figure 11, the second reset sub-circuit 14 includes a second transistor T2, the control electrode g2 of the second transistor T2 is electrically connected to the second reset signal terminal Ref2, the first electrode s2 of the second transistor T2 is electrically connected to the second initialization signal terminal Vinit2, and the second electrode d2 of the second transistor T2 is electrically connected to the first control node Nd1.

[0134] During the initialization stage, the effective voltage (second reset signal) provided from the second reset signal terminal Ref2 is written to the control electrode g2 of the second transistor T2 to control the second transistor T2 to open, so as to write the second initialization signal from the second initialization signal terminal Vinit2 to the first control node Nd1, thereby resetting the first control node Nd1.

[0135] Based on this, it is beneficial to improve the stability of the first driving sub-circuit 11 (third transistor T3), so that the pulse width modulation driving module 10 in each driving circuit Q provides a driving current with the same pulse width to its corresponding light-emitting device O, thereby improving the display effect of the light-emitting substrate 100.

[0136] In some examples, the voltage of the second initialization signal at the second initialization signal terminal Vinit2 may be 0 V. However, the embodiments of the present disclosure are not limited thereto.

[0137] In some examples, the second transistor T2 may be an N-type transistor, which can help reduce the risk of leakage of the second transistor T2 and help ensure the stability of the voltage of the first control node Nd1, that is, ensure the stability of the third transistor T3.

[0138] In some examples, the semiconductor material of the N-type transistor may be indium gallium zinc oxide (IGZO), and the oxide transistor has a smaller off-leakage current.

[0139] FIG13 is an equivalent circuit diagram of a driving circuit according to yet another embodiment. The driving circuit Q shown in FIG13 differs from the driving circuit Q shown in FIG11 in that the first control node Nd1 in the driving circuit Q shown in FIG13 is multiplexed as the first initialization signal terminal Vinit1, whereas the first initialization signal terminal Vinit1 and the first data voltage terminal Data1 in the driving circuit Q shown in FIG11 respond to different signal terminals.

[0140] In some embodiments, as shown in Figure 13, the first control node Nd1 is multiplexed as the first initialization signal terminal Vinit1. During the initialization phase, the voltage of the first control node Nd1 is the second initialization signal from the second initialization signal terminal Vinit2, multiplexing the first control node Nd1 as the first initialization signal terminal Vinit1. At this point, the second initialization signal from the second initialization signal terminal Vinit2 can be written to the first connection node N1 via the first control node Nd1, resetting the first connection node N1. This reduces the number of signal terminals in the light-emitting substrate 100, saving space within the light-emitting substrate 100 and facilitating the layout of other components. It also conserves resources.

[0141] In some embodiments, as shown in Figure 11, the pulse width modulation driving module 10 further includes a first compensation sub-circuit 15, which is electrically connected to the first control node Nd1, the second connection node N2 and the first scan signal terminal Res, respectively. The first compensation sub-circuit 15 is configured to, in an initialization phase, write the voltage of the first control node Nd1 to the second connection node N2 under the control of the first scan signal from the first scan signal terminal Res.

[0142] During the initialization phase, the first compensation sub-circuit 15 is turned on under the control of the first scan signal from the first scan signal terminal Res. The second reset sub-circuit 14 and the first compensation sub-circuit 15 cooperate with each other to write the second initialization signal from the second initialization signal terminal Vinit2 to the second connection node N2 via the first control node Nd1, thereby resetting the second connection node N2. This is equivalent to resetting the second electrode d3 of the third transistor T3 of the first driver sub-circuit 11. Therefore, the driver circuit Q can reset the control electrode g3 and the second electrode d3 of the third transistor T3 of the first driver sub-circuit 11 during the initialization phase. This further improves the stability of the first driver sub-circuit 11 (third transistor T3), allowing the pulse width modulation driver module 10 in each driver circuit Q to provide a driving current with the same pulse width to its corresponding light-emitting device O, thereby improving the display effect of the light-emitting substrate 100.

[0143] In some examples, as shown in FIG. 11 , the first compensation sub-circuit 15 is further configured to write the voltage of the second connection node N2 to the first control node Nd1 under the control of the first scan signal from the first scan signal terminal Res.

[0144] During the threshold compensation phase, the first compensation sub-circuit 15 is turned on under the control of the first scan signal from the first scan signal terminal Res. Furthermore, the first control node Nd1 controls the third transistor T3 (first driver sub-circuit 11) to turn on. The first power signal provided by the first power signal terminal VDD1 is written to the first control node Nd1 via the third transistor T3, the second connection node N2, and the first compensation sub-circuit 15 until the voltage at the first control node Nd1 rises to Vd1-Vth1, turning off the third transistor T3 and completing the threshold compensation for the third transistor T3. This improves the hysteresis effect of the driver transistor M3 and enhances the brightness uniformity of the entire display screen. Vd1 is the voltage of the first power signal, and Vth1 is the threshold voltage of the third transistor T3.

[0145] In some examples, as shown in Figure 11, the first compensation sub-circuit 15 also includes a fourth transistor T4, the control electrode g4 of the fourth transistor T4 is electrically connected to the first scan signal terminal Res, the first electrode s4 of the fourth transistor T4 is electrically connected to the first control node Nd1, and the second electrode d4 of the fourth transistor T4 is electrically connected to the second connection node N2.

[0146] During the initialization phase, the first scan signal terminal Res provides an effective voltage (the first scan signal) that is written to the control electrode g4 of the fourth transistor T4, turning on the fourth transistor T4. The second reset sub-circuit 14 then cooperates with the second reset sub-circuit 14 to write the second initialization signal from the second initialization signal terminal Vinit2 to the second connection node N2, resetting the second connection node N2. This helps improve the stability of the first driver sub-circuit 11 (the third transistor T3). Furthermore, during the threshold compensation phase, the first scan signal from the first scan signal terminal Res is written to the control electrode g4 of the fourth transistor T4, turning on the fourth transistor T4. The first power signal provided by the first power signal terminal VDD1 is written to the first control node Nd1 via the third transistor T3, the second connection node N2, and the first compensation sub-circuit 15 until the voltage at the first control node Nd1 rises to Vd1-Vth1, turning off the third transistor T3 and completing the threshold compensation for the third transistor T3. This helps improve the brightness variation across the entire display screen and enhances the uniformity of display quality.

[0147] In some examples, the fourth transistor T4 may be an N-type transistor, which can help reduce the risk of leakage of the fourth transistor T4 and help ensure the stability of the voltage of the first control node Nd1, that is, ensure the stability of the third transistor T3.

[0148] In some examples, the semiconductor material of the N-type transistor may be indium gallium zinc oxide (IGZO), and the oxide transistor has a smaller off-leakage current.

[0149] FIG14 is an equivalent circuit diagram of a driving circuit according to yet another embodiment. The driving circuit Q shown in FIG14 differs from the driving circuit Q shown in FIG11 in that the second connection node N2 in the driving circuit Q shown in FIG14 is multiplexed as the first initialization signal terminal Vinit1, whereas the first initialization signal terminal Vinit1 and the first data voltage terminal Data1 in the driving circuit Q shown in FIG11 respond to different signal terminals.

[0150] In some embodiments, as shown in FIG14 , the second connection node N2 is multiplexed as the first initialization signal terminal Vinit1 .

[0151] During the initialization phase, the voltage at the second connection node N2 is the second initialization signal from the second initialization signal terminal Vinit2, multiplexing the second connection node N2 as the first initialization signal terminal Vinit1. At this point, the second initialization signal from the second initialization signal terminal Vinit2 can be written to the first connection node N1 via the second connection node N2, resetting the first connection node N1. This reduces the number of signal terminals in the light-emitting substrate 100, saving space within the light-emitting substrate 100 and facilitating the layout of other components. It also conserves resources.

[0152] In some embodiments, as shown in Figure 11, the driving circuit Q also includes a connection control module 40, which is electrically connected to the second scan signal terminal Ctrl, the second connection node N2 and the second control node Nd2, respectively. The connection control module 40 is configured to write the voltage of the second connection node N2 into the second control node Nd2 under the control of the second scan signal from the second scan signal terminal Ctrl.

[0153] During the initialization phase, the connection control module 40 is turned on under the control of the second scan signal from the second scan signal terminal Ctrl, and the voltage of the second connection node N2 is written into the second control node Nd2. During the light-emitting phase, the connection control module 40 is turned on under the control of the second scan signal from the second scan signal terminal Ctrl, and the voltage of the second connection node N2 is written into the second control node Nd2.

[0154] The difference between the initialization phase and the light-emitting phase lies in the difference in the voltage at the second connection node N2. During the initialization phase, the voltage at the second connection node N2 is the second initialization signal from the second initialization signal terminal Vinit2. Based on this, the second initialization signal from the second initialization signal terminal Vinit2 is written to the second control node Nd2 via the second connection node N2, resetting the second control node Nd2. This also resets the control electrodes of the transistors within the light-emitting control module 30. This improves the stability of the light-emitting control module 30 and enhances the display quality of the light-emitting substrate 100.

[0155] During the light-emitting phase, the voltage at the second connection node N2 varies over time. That is, the PWM driver module 10 controls the voltage at the second control node Nd2 based on the voltage at the first control node Nd1. This controls the duration of the drive signal provided by the PWM driver module 20 to the light-emitting control module 30.

[0156] In some examples, as shown in Figure 11, the connection control module 40 includes a fifth transistor T5, the control electrode g5 of the fifth transistor T5 is electrically connected to the second scan signal terminal Ctrl, the first electrode s5 of the fifth transistor T5 is electrically connected to the second connection node N2, and the second electrode d5 of the fifth transistor T5 is electrically connected to the second control node Nd2.

[0157] The second scan signal terminal Ctrl provides an effective voltage (a second scan signal) to the control electrode g5 of the fifth transistor T5 to control the fifth transistor T5 to be turned on, and write the voltage of the second connection node N2 into the second control node Nd2.

[0158] During the initialization phase, the voltage of the second control node N2 is the second initialization signal from the second initialization signal terminal Vinit2, thereby resetting the second control node Nd2, thereby improving the stability of the light emitting control module 30 and the display effect of the light emitting substrate 100.

[0159] FIG15 is an equivalent circuit diagram of a driving circuit according to yet another embodiment. The driving circuit Q shown in FIG15 differs from the driving circuit Q shown in FIG11 in that the second control node Nd2 in the driving circuit Q shown in FIG15 is multiplexed as the first initialization signal terminal Vinit1, whereas the first initialization signal terminal Vinit1 and the first data voltage terminal Data1 in the driving circuit Q shown in FIG11 respond to different signal terminals.

[0160] In some embodiments, as shown in FIG14 , the second control node Nd2 is multiplexed as the first initialization signal terminal Vinit1 .

[0161] During the initialization phase, the voltage at the second control node Nd2 is the second initialization signal from the second initialization signal terminal Vinit2, multiplexing the second control node Nd2 as the first initialization signal terminal Vinit1. At this point, the second initialization signal from the second initialization signal terminal Vinit2 can be written to the first connection node N1 via the second control node Nd2, resetting the first connection node N1. This reduces the number of signal terminals in the light-emitting substrate 100, saving space within the light-emitting substrate 100 and facilitating the layout of other components. It also conserves resources.

[0162] In some embodiments, as shown in Figure 11, the pulse width modulation driving module 10 further includes a first writing sub-circuit 16, which is electrically connected to the first data voltage terminal Data1, the first connection node N1 and the third scanning signal terminal, respectively. The first writing sub-circuit 16 is configured to write the first voltage data from the first voltage data terminal Data1 to the first connection node N1 under the control of the third scanning signal from the third scanning signal terminal SPWM(n).

[0163] During the first write phase, the first write sub-circuit 16 is turned on under the control of the third scan signal from the third scan signal terminal SPWM(n), writing the first voltage data from the first voltage data terminal Data1 to the first connection node N1 and coupling the first data voltage to the first control node Nd1. The first storage sub-circuit 12 can maintain the voltage of the first control node Nd1 based on the stored first data voltage. The pulse width modulation driver module 10 controls the voltage of the second control node Nd2 based on the voltage of the first control node Nd1, thereby controlling the duration of the drive signal provided by the pulse amplitude modulation driver module 20 to the light emission control module 30.

[0164] In some examples, as shown in Figure 11, the first write sub-circuit 16 includes a sixth transistor T6, the control electrode g6 of the sixth transistor T6 is electrically connected to the third scan signal terminal SPWM(n), the first electrode s6 of the sixth transistor T6 is electrically connected to the first data voltage terminal Data1, and the second electrode d6 of the sixth transistor T6 is electrically connected to the first connection node N1.

[0165] During the first write phase, the third scan signal terminal SPWM(n) provides an effective voltage (the third scan signal) to the control electrode g6 of the sixth transistor T6, turning on the sixth transistor T6. This writes the first voltage data from the first voltage data terminal Data1 to the first connection node N1 and couples the first data voltage to the first control node Nd1. Subsequently, during the light-emitting phase, the pulse-width modulation driver module 10 controls the voltage of the second control node Nd2 based on the voltage at the first control node Nd1. This controls the duration of the drive signal provided by the pulse-amplitude modulation driver module 20 to the light-emitting control module 30.

[0166] In some embodiments, as shown in Figure 11, the pulse amplitude modulation driving module 20 includes a second write sub-circuit 21, which is respectively connected to the fourth scan signal terminal SPAM(n), the second data voltage terminal Data2 and the second control node Nd2. The second write sub-circuit 21 is configured to write the second data write voltage from the second data voltage terminal Data2 to the second control node Nd2 under the control of the fourth scan signal from the fourth scan signal terminal SPAM(n).

[0167] During the second write phase, the second write sub-circuit 21 is turned on under the control of the fourth scan signal from the fourth scan signal terminal SPAM(n), and writes the second data write voltage from the second data voltage terminal Data2 to the second control node Nd2. Based on this, during the light-emitting phase, a drive signal can be provided to the light-emitting control module 30 under the control of the data voltage on the second control node Nd2. In other words, the pulse amplitude of the drive current is controlled based on the second data voltage from the second data voltage terminal Data2.

[0168] In some examples, the pulse amplitude modulation driving module 20 further includes a second storage sub-circuit 22 , which is connected in series between the second control node Nd2 and the second power signal terminal VDD2 .

[0169] During the second write phase, the second write sub-circuit 21 is turned on by the fourth scan signal from the fourth scan signal terminal SPAM(n). When the second data write voltage from the second data voltage terminal Data2 is written to the second control node Nd2, the second storage sub-circuit 22 is charged. The second storage sub-circuit 22 can maintain the voltage of the second control node Nd2 based on the stored second data voltage. During the light-emitting phase, the pulse amplitude of the drive current can be controlled based on the second data voltage from the second data voltage terminal Data2.

[0170] In some examples, as shown in Figure 11, the second write sub-circuit 21 includes a seventh transistor T7, the control electrode g7 of the seventh transistor T7 is electrically connected to the fourth scan signal terminal SPAM(n), the first electrode s7 of the seventh transistor T7 is electrically connected to the second data voltage terminal Data2, and the second electrode d7 of the seventh transistor T7 is electrically connected to the second control node Nd2.

[0171] In the second writing phase, the fourth scanning signal terminal SPAM(n) provides an effective voltage (fourth scanning signal) to the control electrode g7 of the seventh transistor T7, controlling the seventh transistor T7 to turn on, so as to write the second data writing voltage from the second data voltage terminal Data2 to the second control node Nd2.

[0172] In some examples, the seventh transistor T7 may be an N-type transistor, which can help reduce the risk of leakage of the seventh transistor T7 and help ensure the stability of the voltage of the second control node Nd2, that is, ensure the stability of the light control module 30.

[0173] In some examples, the semiconductor material of the N-type transistor may be indium gallium zinc oxide (IGZO), and the oxide transistor has a smaller off-leakage current.

[0174] FIG16 is an equivalent circuit diagram of a driving circuit according to yet another embodiment. The driving circuit Q shown in FIG16 differs from the driving circuit Q shown in FIG11 in that the first initialization signal terminal Vinit1 and the second data voltage terminal Data2 in the driving circuit Q shown in FIG16 respond to the same signal terminal, whereas the first initialization signal terminal Vinit1 and the second data voltage terminal Data2 in the driving circuit Q shown in FIG11 respond to different signal terminals.

[0175] In some embodiments, as shown in FIG16 , the first initialization signal terminal Vinit1 and the second data voltage terminal Data2 respond to the same signal terminal. Alternatively, it can be understood that the second data voltage terminal Data2 can be multiplexed as the first initialization signal terminal Vinit1. In this case, during the initialization phase, the first data voltage signal terminal Data1 can provide an effective voltage to the first transistor T1 of the first reset sub-circuit 13 to control the first transistor T1 to turn on, thereby writing the first initialization signal from the first initialization signal terminal Vinit1 to the first connection node N1, thereby resetting the first connection node N1.

[0176] Based on this, the number of signal terminals in the light-emitting substrate 100 can be reduced, which not only helps to save space in the light-emitting substrate 100 to facilitate the layout of other devices, but also saves resources.

[0177] FIG17 is an equivalent circuit diagram of a driving circuit according to yet another embodiment. The driving circuit Q shown in FIG17 differs from the driving circuit Q shown in FIG11 in that the first data voltage signal terminal Data1 and the second data voltage terminal Data2 in the driving circuit Q shown in FIG17 respond to the same signal terminal, whereas the first data voltage signal terminal Data1 and the second data voltage terminal Data2 in the driving circuit Q shown in FIG11 respond to different signal terminals.

[0178] In some embodiments, as shown in FIG17 , the first data voltage terminal Data1 and the second data voltage terminal Data2 respond to the same signal terminal. That is, the first data voltage terminal Data1 can be multiplexed as the second data voltage terminal Data2. In this case, the first data voltage terminal Data1 can provide a first data write voltage during the first write phase and a second data write voltage during the second write phase.

[0179] Based on this, the number of signal terminals in the light-emitting substrate 100 can be reduced, which not only helps to save space in the light-emitting substrate 100 to facilitate the layout of other devices, but also saves resources.

[0180] FIG18 is an equivalent circuit diagram of a driving circuit according to yet another embodiment. The driving circuit Q shown in FIG18 differs from the driving circuit Q shown in FIG17 in that the first initialization signal terminal Vinit1, the first data voltage signal terminal Data1, and the second data voltage terminal Data2 in the driving circuit Q shown in FIG18 respond to the same signal terminal, whereas the first data voltage signal terminal Data1, the first data voltage signal terminal Data1, and the second data voltage terminal Data2 in the driving circuit Q shown in FIG17 respond to different signal terminals.

[0181] In some embodiments, as shown in FIG18 , on the basis that the first data voltage terminal Data1 and the second data voltage terminal Data2 respond to the same signal terminal, the first initialization signal terminal Vinit1, the first data voltage signal terminal Data1 and the second data voltage terminal Data2 can be set to respond to the same signal terminal.

[0182] The first data voltage signal terminal Data1 (the second data voltage terminal Data2) can provide an effective voltage to the first transistor T1 of the first reset sub-circuit 13 during the initialization stage to control the first transistor T1 to turn on, so as to write the first initialization signal from the first initialization signal terminal Vinit1 to the first connection node N1, thereby resetting the first connection node N1.

[0183] Based on this, the number of signal terminals in the light-emitting substrate 100 can be reduced, which not only helps to save space in the light-emitting substrate 100 to facilitate the layout of other devices, but also saves resources.

[0184] FIG19 is an equivalent circuit diagram of a driving circuit according to yet other embodiments.

[0185] In some embodiments, as shown in FIG19 , the first initialization signal terminal Vinit1 and the second initialization signal terminal Vinit2 may respond to the same signal terminal, that is, the second initialization signal terminal Vinit2 may be multiplexed as the first initialization signal terminal Vinit1 .

[0186] During the initialization phase, the second initialization signal provided by the second initialization signal terminal Vinit2 can be simultaneously written into the first reset sub-circuit 13 and the second reset sub-circuit 14 to reset the first connection node N1 and the first control node Nd1 .

[0187] Based on this, the number of signal terminals in the light-emitting substrate 100 can be reduced, which not only helps to save space in the light-emitting substrate 100 to facilitate the layout of other devices, but also saves resources.

[0188] In some examples, the first reset signal terminal Ref1 and the second reset signal terminal Ref2 may also respond to the same signal terminal, that is, the second reset signal terminal Ref2 is multiplexed as the first reset signal terminal Ref1.

[0189] During the initialization stage, the second reset signal provided by the second reset signal terminal Ref2 can be written into the first reset sub-circuit 13 and the second reset sub-circuit 14 at the same time, controlling the first reset sub-circuit 13 and the second reset sub-circuit 14 to be turned on, so as to realize that the second initialization signal provided by the second initialization signal terminal Vinit2 is written into the first reset sub-circuit 13 and the second reset sub-circuit 14 at the same time, so as to reset the first connection node N1 and the first control node Nd1.

[0190] In some embodiments, as shown in Figure 19, on the basis that the first data voltage terminal Data1 and the second data voltage terminal Data2 respond to the same signal terminal, the first data voltage terminal Data1, the second data voltage terminal Data2, the first initialization signal terminal Vinit1 and the second initialization signal terminal Vinit2 can be set to respond to the same signal terminal.

[0191] Based on this, the number of signal terminals in the light-emitting substrate 100 can be further reduced, which not only helps to save space in the light-emitting substrate 100 to facilitate the layout of other devices, but also saves resources.

[0192] In summary, at least two of the first data voltage terminal Data1, the second data voltage terminal Data2, the first initialization signal terminal Vinit1, and the second initialization signal terminal Vinit2 can respond to the same signal terminal. This reduces the number of signal terminals in the light-emitting substrate 100, saving space within the light-emitting substrate 100 for facilitating the layout of other components and conserving resources.

[0193] In some embodiments, as shown in Figure 19, the light-emitting control module 30 includes an eighth transistor T8, the control electrode g8 of the eighth transistor T8 is electrically connected to the second control node Nd2, the first electrode s8 of the eighth transistor T8 is electrically connected to the second power supply signal terminal VDD2, and the second electrode d8 of the eighth transistor T8 is electrically connected to the light-emitting device.

[0194] During the light-emitting phase, the sweep signal terminal Sweep provides a linearly varying sweep signal (sweep voltage), and the first connection node N1 receives the sweep signal from the sweep signal terminal Sweep and couples the sweep signal to the first control node Nd1. As a result, the voltage at the first control node Nd1 begins to decrease linearly until the first driver sub-circuit 11 in the pulse-width modulation driver module 10 is turned on. The first driver sub-circuit 11 writes the first power signal at the first power signal terminal VDD1 to the second control node Nd2. The voltage at the second control node Nd2 gradually increases until the eighth transistor T8 is turned off, blocking the drive current and causing the light-emitting device O to stop emitting light. This allows the pulse width of the drive current to be controlled based on the first data voltage from the first data voltage terminal Data1.

[0195] In some examples, as shown in FIG19 , the first power signal terminal VDD1 and the second power signal terminal VDD2 may also respond to the same signal terminal. This reduces the number of signal terminals in the light-emitting substrate 100, saving space in the light-emitting substrate 100 for facilitating the layout of other components and conserving resources.

[0196] In some embodiments, as shown in FIG. 11 , the driving circuit Q further includes a sensing module 50 , and the sensing module 50 is configured to sense the current flowing through the light-emitting device O.

[0197] The sensing module 50 is connected to the light control module 30, the sensing signal terminal RD-out, and the fifth scanning signal terminal Sense. During the sensing phase, the fifth scanning signal provided by the fifth scanning signal terminal Sense controls the sensing module 50 to conduct, transmitting the current flowing through the light-emitting device O to the sensing signal terminal RD-out. The current is then transmitted to an external current detection unit (not shown) for detection via the sensing signal terminal RD-out.

[0198] In some examples, the current detection unit may be a processor or a timing controller (TCON). The current detection unit may correct the first data voltage (provided by the first data voltage terminal Data1) based on the detected current to obtain a corrected first data voltage.

[0199] In some examples, the sensing module 50 includes a ninth transistor T9, a control electrode g9 of the ninth transistor T9 is electrically connected to the fifth scanning signal terminal Sense, a first electrode s9 of the ninth transistor T9 is electrically connected to the sensing signal terminal RD-out, and a second electrode d9 of the ninth transistor T9 is electrically connected to the output terminal of the light emitting control module 30.

[0200] During the sensing phase, the fifth scan signal terminal Sense provides an effective voltage (fifth scan signal) to the control electrode g9 of the ninth transistor T9, turning on the ninth transistor T9 and transmitting the current flowing through the light-emitting device O to the sense signal terminal RD-out. The sense signal terminal RD-out then transmits the current to an external current detection unit (not shown) for detection. This allows the use of a drive current with the same amplitude to represent color gradations, thereby resolving the issue of the wavelength of the light-emitting device varying with the amplitude of the drive current.

[0201] FIG20 is a timing diagram of a driving circuit according to some embodiments, and FIG21 is a timing simulation diagram of a driving circuit according to some embodiments. The first simulation diagram in FIG21 shows a timing diagram of the power supply signal vdd (first power supply signal vdd1 or second power supply signal vdd2) and the third power supply signal vss when the first data voltage data = 8V. The second simulation diagram shows a timing diagram of the sweep signal sweep when the first data voltage data = 8V. The third simulation diagram shows a timing diagram corresponding to different values ​​of the first data voltage data1, where the values ​​of data1 correspond to 2V, 3V, 4V, 5V, 6V, 7V, and 8V from bottom to top. The fourth simulation diagram shows a timing diagram of the voltage of the first control node Nd1 corresponding to different values ​​of the first data voltage data1. The fifth simulation diagram shows a timing diagram of the driving current corresponding to different values ​​of the first data voltage data1. The abscissas of the five simulation diagrams in FIG21 correspond to the corresponding values, and can all refer to the abscissa of the fifth simulation diagram.

[0202] In some embodiments, as shown in FIG19 , the first power signal terminal VDD1 (the second power signal terminal VDD2) is used to provide a first power signal vdd1 (a second power signal vdd2). The third power signal terminal VSS is used to provide a third power signal vss. The first scan signal terminal Res is used to provide a first scan signal res, and the second scan signal terminal Ctrl is used to provide a second scan signal ctrl. The third scan signal terminal SPWM(n) is used to provide a third scan signal spwm(n), and the fourth scan signal terminal SPAM(n) is used to provide a fourth scan signal spam(n). The first reset signal terminal Ref1 (the second reset signal terminal Ref2) is used to provide a first reset signal ref1 (a second reset signal ref2). The sweep signal terminal Sweep is used to provide a sweep signal sweep. The first data voltage terminal Data1 (the second data voltage terminal Data2) is used to provide a first data voltage data1 (a second data voltage data2). At this time, the first data voltage terminal Data1 can be multiplexed as the second data voltage terminal Data2, the first initialization signal terminal Vinit1, and the second initialization signal terminal Vinit2. That is, the first data voltage terminal Data1 is equivalent to providing the initialization signal (the first initialization signal vinit1 / the second initialization signal vinit2 ).

[0203] For the purpose of introduction, it is assumed that all transistors in the driving circuit Q are P-type transistors. As shown in FIG19 to FIG21 , the driving process of the driving circuit Q is as follows: one frame period includes an initialization phase t1, a threshold compensation phase t2, a first writing phase t3, a second writing phase t4, and a light-emitting phase t5.

[0204] Initialization phase t1: The first reset signal ref1 (second reset signal ref2) provided by the first reset signal terminal Ref1 (second reset signal terminal Ref2) is a low-voltage signal. This low-voltage signal is transmitted to the control electrode g1 of the first transistor T1 in the first reset sub-circuit 13 and the control electrode g2 of the second transistor T2 in the second reset sub-circuit 14, thereby turning on the first transistor T1 and the second transistor T2. The first scan signal res provided by the first scan signal terminal Res is a low-voltage signal. This low-voltage signal is transmitted to the control electrode g4 of the fourth transistor T4 in the first compensation sub-circuit 15, thereby turning on the fourth transistor T4. The second scan signal ctrl provided by the second scan signal terminal Ctrl is a low-voltage signal. This low-voltage signal is transmitted to the control electrode g5 of the fifth transistor T5 in the connection control module 40, thereby turning on the fifth transistor T5. The first power signal vdd1 (second power signal vdd2) provided by the first power signal terminal VDD1 (second power signal terminal VDD2) is a low-voltage signal. The third power signal vss provided by the third power signal terminal VSS is also a low-voltage signal. Furthermore, the other signal terminals provide high-voltage signals. For example, the scan signals provided by the third scan signal terminal SPWM(n) and the fourth scan signal terminal SPAM(n) are both high voltage signals.

[0205] As described above, the first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 in the drive circuit Q are in an open state. At this time, the first data voltage data1 (second data voltage data2) provided by the first data voltage terminal Data1 (second data voltage terminal Data2) is a low voltage signal. This low voltage signal can sequentially pass through the second transistor T2, the first control node Nd1, the fourth transistor T4, the second connection node N2, the fifth transistor T5 to the second control node Nd2, and reset the second connection node N2, the first control node Nd1, and the second control node Nd2. In addition, this low voltage signal can also be transmitted to the first connection node N1 through the first transistor T1 to reset the first connection node N1. That is, during the initialization phase, the first connection node N1, the second connection node N2, the first control node Nd1, and the second control node Nd2 in the drive circuit Q are reset.

[0206] Resetting the second connection node N2 and the first control node Nd1 in the driver circuit Q is equivalent to resetting the control electrode g3 and the second electrode d3 of the third transistor T3 in the first driver sub-circuit 11. This helps improve the stability of the first driver sub-circuit 11 (the third transistor T3). Resetting the second control node Nd2 in the driver circuit Q helps improve the stability of the light emitting control module 30 and enhance the display effect of the light emitting substrate 100.

[0207] The first connection node N1 in the driver circuit Q is reset, thereby ensuring that the first connection node N1 of each driver circuit Q maintains a consistent value before the threshold compensation phase begins. This can also alleviate the issue of different voltages at the first connection node N1 leading to different voltages at the corresponding first control node Nd1. This improves the stability of the first driver sub-circuit 11 (third transistor T3), allowing the pulse-width modulation driver module 10 in each driver circuit Q to provide a driving current with the same pulse width to its corresponding light-emitting device O, thereby enhancing the display quality of the light-emitting substrate 100.

[0208] Threshold compensation stage t2: The first scan signal res provided by the first scan signal terminal Res is a low voltage signal. This low voltage signal is transmitted to the control electrode g4 of the fourth transistor T4 in the first compensation sub-circuit 15, turning on the fourth transistor T4. The first power signal vdd1 (second power signal vdd2) provided by the first power signal terminal VDD1 (second power signal terminal VDD2) is a high voltage signal. The third power signal vss provided by the third power signal terminal VSS is also a high voltage signal. All other signal terminals provide high voltage signals.

[0209] Since the voltage of the first control node Nd1 at the initial moment of the threshold compensation phase t2 is the first data voltage data1 (low voltage signal), at this time, the first data voltage data is the initialization voltage vinit. That is, the voltage of the control electrode g3 of the third transistor T3 is the first data voltage data1 (low voltage signal). In addition, the voltage of the first electrode s3 of the third transistor T3 is the first power supply signal vdd1 (high voltage signal) provided by the first power supply signal terminal VDD1. As a result, Vgs1 of the third transistor T3 is less than Vth1, and the third transistor T3 is in the on state. Wherein, Vth1 is the threshold voltage of the third transistor T3, and Vgs1 is the gate-source voltage of the third transistor.

[0210] As described above, the third transistor T3 and the fourth transistor T4 in the drive circuit Q are turned on. At this point, the first power signal vdd1 (a high voltage signal) provided by the first power signal terminal VDD1 can be transmitted sequentially through the third transistor T3, the second connection node N2, and the fourth transistor T4 to the first control node Nd1 until the voltage of the first control node Nd1 rises to Vd1-Vth1. The third transistor T3 is then turned off, completing threshold compensation. This helps improve the brightness differences across the entire display screen and enhances the uniformity of the display quality. Wherein, Vd1 is the voltage of the first power signal vdd1, and Vth1 is the threshold voltage of the third transistor T3.

[0211] First write phase t3: The first power signal vdd1 (second power signal vdd2) provided by the first power signal terminal VDD1 (second power signal terminal VDD2) is a high voltage signal. The third power signal vss provided by the third power signal terminal VSS is also a high voltage signal. Other signal terminals provide high voltage signals. Furthermore, the first data voltage data1 provided by the first data voltage terminal Data1 is a pulse-width modulated data voltage. Furthermore, the third scan signal spwm(n) provided by the third scan signal terminal SPWM(n) is a low voltage signal, which is transmitted to the control electrode g6 of the sixth transistor T6 in the first write sub-circuit 16, controlling the sixth transistor T6 to turn on, thereby transmitting the pulse-width modulated data voltage from the first data voltage terminal Data1 via the sixth transistor T6 and the first connection node N1 to the first capacitor C1 in the first storage sub-circuit 12. The pulse-width modulated data voltage is then coupled to the first control node Nd1 via the first capacitor C1. The voltage at the first connection node N1 is C / (C+Cg)*Δ(data1-vinit). Where C1 is the capacitance of the first capacitor, Cg is the capacitance of the control electrode of the third transistor, data1 is the first data voltage (the pulse width modulation data voltage), and vinit1 is the initialization voltage. Thus, the pulse width modulation driver module 10 controls the voltage of the second control node Nd2 based on the voltage of the first control node Nd1. This controls the duration of the drive signal provided by the pulse amplitude modulation driver module 20 to the light emission control module 30.

[0212] Second writing phase t4: The first power signal vdd1 (second power signal vdd2) provided by the first power signal terminal VDD1 (second power signal terminal VDD2) is a high voltage signal. The third power signal vss provided by the third power signal terminal VSS is also a high voltage signal. Furthermore, other signal terminals provide high voltage signals. Furthermore, the first data voltage data1 provided by the first data voltage terminal Data1 can be the second data voltage data2. That is, the first data voltage terminal Data1 provides a pulse-amplitude modulated data voltage. The fourth scan signal spam(n) provided by the fourth scan signal terminal SPAM(n) is a low voltage signal, which is transmitted to the control electrode g7 of the seventh transistor T7 in the second writing sub-circuit 21. This controls the seventh transistor T7 to turn on, thereby writing the pulse-amplitude modulated data voltage from the first data voltage terminal Data1 to the second control node Nd2 via the seventh transistor T7. The data voltage is then stored in the second capacitor C2 in the second storage sub-circuit 22 to maintain the voltage of the second control node Nd2. At this point, the voltage of the second control node Nd2 is the pulse-amplitude modulated data voltage.

[0213] Light-emitting stage t5: the first power signal vdd1 (second power signal vdd2) provided by the first power signal terminal VDD1 (second power signal terminal VDD2) is a high voltage signal, and the third power signal vss provided by the third power signal terminal VSS is also a low voltage signal.

[0214] In the light emitting control module 30, Vgs2 of the eighth transistor T8 is less than Vth2, and the eighth transistor T8 is in an on state, thereby providing a driving current having a pulse amplitude corresponding to the pulse amplitude modulation data voltage charged to the second capacitor C2 to the light emitting device O, thereby driving the light emitting device O to emit light. Vth2 is the threshold voltage of the eighth transistor T8, and Vgs2 is the gate-source voltage of the eighth transistor T8.

[0215] Furthermore, during light-emitting phase t5, the sweep signal terminal Sweep provides a linearly varying sweep signal (sweep voltage) that gradually decreases. The first connection node N1 receives the sweep signal from the sweep signal terminal Sweep and couples the sweep signal to the first control node Nd1. Consequently, the voltage at the first control node Nd1 begins to decrease linearly until the third transistor T3 is turned on.

[0216] Furthermore, during light-emitting phase t5, the second scan signal ctrl provided by the second scan signal terminal Ctrl is a low-voltage signal. This low-voltage signal is transmitted to the control electrode g5 of the fifth transistor T5 in the connection control module 40, thereby turning on the fifth transistor T5. At this point, the first power signal vdd1 from the first power signal terminal VDD1 can be written to the second control node Nd2. The voltage of the second control node Nd2 gradually increases until it causes a short circuit within the light-emitting control module 30, blocking the drive current and causing the light-emitting device O to cease emitting light. This allows the pulse width of the drive current to be controlled based on the first data voltage from the first data voltage terminal Data1, thereby controlling the duration of the drive signal provided to the light-emitting device O and achieving different brightness levels for the light-emitting device O.

[0217] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A driving circuit, comprising: A pulse width modulation driving module, a pulse amplitude modulation driving module, and a light emitting control module; The pulse width modulation driving module includes: A first driving sub - circuit, electrically connected to a first control node, a second control node, and a first power signal terminal respectively. The first driving sub - circuit is configured to write the first power signal of the first power signal terminal to the second control node under the control of the first control node; A first storage sub - circuit, connected in series between the first control node and a first connection node; the first connection node is electrically connected to a first data voltage terminal and a sweep signal terminal respectively. The first storage sub - circuit is configured to store the first data voltage from the first data voltage terminal in the first writing stage and couple the first data voltage to the first control node, and in the light emitting stage, couple the sweep signal from the sweep signal terminal to the first control node via the first connection node; A first reset sub - circuit, electrically connected to the first connection node, a first reset signal terminal, and a first initialization signal terminal respectively. The first reset sub - circuit is configured to write the first initialization signal from the first initialization signal terminal to the first connection node under the control of the first reset signal from the first reset signal terminal in the initialization stage; The pulse amplitude modulation driving module is electrically connected to a second data voltage terminal and the second control node respectively. The pulse amplitude modulation driving module is configured to provide a driving signal to the light emitting control module under the control of the data voltage of the second control node; The light emitting control module is electrically connected to the pulse width modulation driving module and the pulse amplitude modulation driving module respectively. The light emitting control module is configured to change with time in the light emitting stage, so that the pulse width modulation driving module controls the voltage of the second control node based on the voltage of the first control node, to control the duration of the driving signal provided by the pulse amplitude modulation driving module to the light emitting control module.

2. The drive circuit according to claim 1, wherein, The first reset sub - circuit includes a first transistor. The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first pole of the first transistor is electrically connected to the first initialization signal terminal, and the second pole of the first transistor is electrically connected to the first connection node.

3. The driving circuit according to claim 1 or 2, wherein, The first initialization signal terminal and the first data voltage terminal respond to the same signal terminal; and / or, the first initialization signal terminal and the second data voltage terminal respond to the same signal terminal.

4. The drive circuit according to claim 1 or 2, wherein The pulse width modulation driving module further includes: A second reset sub - circuit, electrically connected to a second reset signal terminal, a second initialization signal terminal, and the first control node respectively. The second reset sub - circuit is configured to write the second initialization signal from the second initialization signal terminal to the first control node under the control of the second reset signal from the second reset signal terminal in the initialization stage.

5. The drive circuit according to claim 4, wherein, The second reset sub-circuit includes a second transistor. The control electrode of the second transistor is electrically connected to the second reset signal terminal. The first electrode of the second transistor is electrically connected to the second initialization signal terminal. The second electrode of the second transistor is electrically connected to the first control node.

6. The drive circuit according to claim 4 or 5, wherein, The first control node is multiplexed as the first initialization signal terminal.

7. The drive circuit according to any one of claims 1 to 6, wherein, The first driving sub-circuit includes a third transistor. The control electrode of the third transistor is electrically connected to the first control node. The first electrode of the third transistor is electrically connected to the first power signal terminal. The second electrode of the third transistor is electrically connected to the second connection node.

8. The drive circuit according to any one of claims 4 to 7, wherein, The pulse width modulation driving module further includes: A first compensation sub-circuit, which is respectively electrically connected to the first control node, the second connection node, and the first scan signal terminal. The first compensation sub-circuit is configured to write the voltage of the first control node to the second connection node under the control of the first scan signal from the first scan signal terminal during the initialization phase.

9. The drive circuit according to claim 8, wherein, The first compensation sub-circuit further includes a fourth transistor. The control electrode of the fourth transistor is electrically connected to the first scan signal terminal. The first electrode of the fourth transistor is electrically connected to the first control node. The second electrode of the fourth transistor is electrically connected to the second connection node.

10. The drive circuit according to claim 8 or 9, wherein The second connection node is multiplexed as the first initialization signal terminal.

11. The driving circuit according to claim 8 or 9 further includes: A connection control module, which is respectively electrically connected to the second scan signal terminal, the second connection node, and the second control node. The connection control module is configured to write the voltage of the second connection node to the second control node under the control of the second scan signal from the second scan signal terminal.

12. The drive circuit according to claim 11, wherein, The connection control module includes a fifth transistor. The control electrode of the fifth transistor is electrically connected to the second scan signal terminal. The first electrode of the fifth transistor is electrically connected to the second connection node. The second electrode of the fifth transistor is electrically connected to the second control node.

13. The drive circuit according to claim 11 or 12, wherein The second control node is multiplexed as the first initialization signal terminal.

14. The drive circuit according to any one of claims 1 to 13, wherein, The pulse width modulation driving module further includes: A first writing sub-circuit, which is respectively electrically connected to the first data voltage terminal, the first connection node, and the third scan signal terminal. The first writing sub-circuit is configured to write the first voltage data from the first voltage data terminal to the first connection node under the control of the third scan signal from the third scan signal terminal.

15. The drive circuit according to claim 14, wherein, The first writing sub-circuit includes a sixth transistor. The control electrode of the sixth transistor is electrically connected to the third scan signal terminal. The first electrode of the sixth transistor is electrically connected to the first data voltage terminal. The second electrode of the sixth transistor is electrically connected to the first connection node.

16. The drive circuit according to any one of claims 1 to 15, wherein, The pulse amplitude modulation driving module includes: A second writing sub - circuit, respectively connected to a fourth scanning signal terminal, the second data voltage terminal, and the second control node. The second writing sub - circuit is configured to write a second data writing voltage from the second data voltage terminal to the second control node under the control of a fourth scanning signal from the fourth scanning signal terminal; A second storage sub - circuit, connected in series between the second control node and a second power signal terminal.

17. The drive circuit according to claim 16, wherein, The second writing sub - circuit includes a seventh transistor. The control electrode of the seventh transistor is electrically connected to the fourth scanning signal terminal. The first electrode of the seventh transistor is electrically connected to the second data voltage terminal. The second electrode of the seventh transistor is electrically connected to the second control node.

18. A light - emitting substrate, comprising: A substrate; A driving circuit layer, located on one side of the substrate. The driving circuit layer includes a plurality of driving circuits as described in any one of claims 1 to 17; A light - emitting device layer, located on the side of the driving circuit layer away from the substrate.

19. A display device, comprising: A backlight module, the backlight module includes the light - emitting substrate described in claim 18; A liquid - crystal display panel, located on the light - emitting side of the backlight module.

20. A display device, comprising: A display panel, the display panel includes at least one light - emitting substrate as described in claim 18; A cover plate, located on the light - emitting side of the display panel.

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