Transistor structures and electrical signal connections for display devices

Abstract

Disclosed herein is an apparatus including a switching transistor (ST) and a driving transistor (DT). The apparatus includes a bottom GI layer disposed over the buffer layer and ST and DT disposed over the substrate. The DT includes a DT bottom gate electrode disposed over the buffer layer, a DT channel structure disposed over the bottom GI layer, a DT top GI layer disposed over the DT channel structure, a DT top gate electrode disposed over the DT top GI layer, a DT drain, and a DT source. A bottom GI layer is disposed over and around the DT bottom gate electrode. The ST includes an ST channel structure disposed over the bottom GI layer, an ST top GI layer disposed over the ST channel structure, an ST top gate electrode disposed over the ST top GI layer, an ST drain, and an ST source.

Description

Technical Field

[0001] The present disclosure generally relates to devices having driving thin film transistors (TFTs) and switching TFTs for gate (scan) driver (GOA) circuits and / or pixel circuits on an array. These devices can be used in display screens (e.g., organic light emitting diode (OLED) display screens). Background Art

[0002] Thin film transistors (TFTs) are made by depositing a thin film of active semiconductor layers, dielectric layers, and metal contacts on a supporting substrate (e.g., glass). More specifically, the TFT can be a metal oxide semiconductor field effect transistor (MOSFET).

[0003] Due to the high resolution, low power consumption and high-speed operation of liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays, TFTs have attracted great interest in display applications. TFTs are embedded in the panel of the display. The data line voltage signal of the source driver IC in the display module and the scan line voltage signal of the gate driver circuit of the peripheral display panel area in the display panel are delivered to the TFTs in the pixel circuit to control the displayed image by turning on and off the TFTs in the active display panel area. Image distortion is reduced by improving the response of TFTs with higher mobility and / or by reducing crosstalk between pixels. Most display products including LCD or OLED televisions (TVs) and monitors include TFTs in the panel. Many modern high-resolution and high-quality electronic visual display devices use active matrix-based OLED displays with a large number of TFTs as components of the pixel circuit. One advantage of TFT technology is that a separate TFT is used for each pixel on the display. By controlling the voltage and current through the data and gate signal lines, each TFT is used as a switch or current source in the pixel circuit or gate driver circuit to increase control over the displayed image. By minimizing the distortion of data and gate signal voltages, the higher on-current of the high-mobility TFT allows for faster updating of the display image and better image quality.

[0004] A key challenge in mass-producing TFTs for OLED displays is achieving high mobility (high on-current) and good electrical stability with a threshold voltage close to 0V. Furthermore, switching transistors require a small subthreshold slope (SS), while drive transistors require a larger SS to achieve better OLED uniformity control. Using conventional techniques, it is difficult to manufacture switching transistors with a small SS and drive transistors with a larger SS on the same substrate.

[0005] Therefore, there is a need to improve the switching and driving TFTs used in pixel circuits. Summary of the Invention

[0006] In one embodiment, a device is disclosed. The device includes a substrate, a buffer layer, a first bottom gate insulation (GI) layer disposed above the buffer layer, a driver transistor disposed above the substrate, and a first switch transistor disposed above the substrate. The driver transistor includes a driver transistor (DT) bottom gate electrode disposed above the buffer layer, a driver transistor (DT) channel structure disposed above the first bottom GI layer, a first driver transistor (DT) top gate insulation (GI) layer disposed above the DT channel structure, a driver transistor (DT) top gate electrode disposed above the DT top GI layer, a driver transistor (DT) drain, and a driver transistor (DT) source. The first bottom GI layer is disposed above and surrounds the DT bottom gate electrode. The first switch transistor includes a first switch transistor (ST) channel structure disposed above the first bottom GI layer, a first switch transistor (ST) top gate insulation (GI) layer disposed above the first ST channel structure, a first switch transistor (ST) top gate electrode disposed above the first ST top GI layer, a first switch transistor (ST) drain, and a first switch transistor (ST) source. The first ST top gate electrode is electrically coupled to a first switch transistor (ST) gate voltage.

[0007] In another embodiment, a device is disclosed. The device includes a substrate, a buffer layer, a first bottom gate insulation (GI) layer disposed above the buffer layer, a driver transistor disposed above the substrate, a first switch transistor disposed above the substrate, and a second switch transistor disposed above the substrate. The driver transistor includes a driver transistor (DT) bottom gate electrode disposed above the buffer layer, a driver transistor (DT) channel structure disposed above the first bottom GI layer, a first driver transistor (DT) top gate insulation (GI) layer disposed above the DT channel structure, a driver transistor (DT) top gate electrode disposed above the DT top GI layer, a driver transistor (DT) drain, and a driver transistor (DT) source. The first bottom GI layer is disposed above and surrounds the DT bottom gate electrode. The first switch transistor includes a first switch transistor (ST) bottom gate electrode disposed above the buffer layer, a first switch transistor (ST) channel structure disposed above the first bottom GI layer, a first switch transistor (ST) top gate insulation (GI) layer disposed above the first ST channel structure, a first switch transistor (ST) drain, and a first switch transistor (ST) source. The top gate electrode of the first switching transistor (ST) is electrically coupled to the first switching transistor (ST) gate voltage. The second switching transistor includes a second switching transistor (ST) channel structure disposed above the bottom GI layer, a second switching transistor (ST) top gate insulating (GI) layer disposed above the second ST channel structure, a second switching transistor (ST) top gate electrode disposed above the second ST top GI layer, a second switching transistor (ST) drain, and a second switching transistor (ST) source. The second ST top gate electrode is electrically coupled to the second switching transistor (ST) gate voltage.

[0008] In another embodiment, a device is disclosed. The device includes a substrate, a buffer layer, a first bottom gate insulating (GI) layer disposed above the buffer layer, a second bottom gate insulating (GI) layer disposed above the first bottom GI layer, a driver transistor disposed above the substrate, a first switching transistor disposed above the substrate, and a second switching transistor disposed above the substrate. The driver transistor includes a driver transistor (DT) bottom gate electrode disposed above the buffer layer, a driver transistor (DT) channel structure disposed above the second bottom GI layer, a first driver transistor (DT) top gate insulating (GI) layer disposed above the DT channel structure, a driver transistor (DT) top gate electrode disposed above the DT top GI layer, a driver transistor (DT) drain, and a driver transistor (DT) source. The first bottom GI layer is disposed above and surrounds the DT bottom gate electrode. The DT top gate electrode is electrically connected to the DT source. The DT top gate electrode and the DT source are electrically coupled to a driver transistor (DT) source voltage. The DT bottom gate electrode is electrically coupled to the driver transistor (DT) gate voltage. The first switching transistor includes a first switching transistor (ST) bottom gate electrode disposed above a first bottom GI layer, a first switching transistor (ST) channel structure disposed above a second bottom GI layer, a first switching transistor (ST) top gate insulating (GI) layer disposed above the first ST channel structure, a first switching transistor (ST) top gate electrode disposed above the first ST top GI layer, a first switching transistor (ST) drain, and a first switching transistor (ST) source. The second bottom GI layer is disposed above and surrounds the first ST bottom gate electrode. The first ST bottom gate electrode is electrically connected to the first ST top gate electrode. The first ST top gate electrode and the first ST bottom gate electrode are electrically coupled to the first switching transistor (ST) gate voltage. The second switching transistor includes a second switching transistor (ST) bottom gate electrode disposed above the first bottom GI layer, a second switching transistor (ST) channel structure disposed above the second bottom GI layer, a second switching transistor (ST) top gate insulating (GI) layer disposed above the second ST channel structure, a second switching transistor (ST) top gate electrode disposed above the second ST top GI layer, a second switching transistor (ST) drain, and a second switching transistor (ST) source. The second bottom GI layer is disposed above and around the top surface and sides of the second ST bottom gate electrode. The second ST top gate electrode is electrically connected to the second ST source electrode. The second ST source electrode and the second ST top gate electrode are electrically coupled to a second switching transistor (ST) source voltage. The second ST bottom gate electrode is electrically coupled to a second ST gate voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order that the above-mentioned features of the present disclosure may be understood in detail, a more particular description of the present disclosure (a brief summary of which is given above) may be obtained by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only exemplary embodiments and are not to be considered limiting of the scope of the invention, as the present disclosure may admit to other equally effective embodiments.

[0010] Figure 1 is a schematic diagram of a simplified organic light emitting diode display (OLED) panel according to some embodiments.

[0011] Figure 2A FIG. 1 is a schematic diagram of a simplified set of pixel circuits and GOA circuits in an OLED display panel according to some embodiments.

[0012] Figure 2B FIG. 1 is a schematic diagram of a simplified set of pixel circuits and GOA circuits in an OLED display panel according to some embodiments.

[0013] Figure 3A is a schematic cross-sectional view of a transistor including a first switching transistor and a driving transistor disposed on the same substrate according to some embodiments.

[0014] Figure 3B is a schematic cross-sectional view of a transistor including a first switching transistor and a driving transistor disposed on the same substrate according to some embodiments.

[0015] Figure 3C is a schematic cross-sectional view of a transistor including a first switching transistor and a driving transistor disposed on the same substrate according to some embodiments.

[0016] Figure 3D is a schematic cross-sectional view of a transistor including a first switching transistor and a driving transistor disposed on the same substrate according to some embodiments.

[0017] Figure 4A is a schematic cross-sectional view of a transistor including a first switching transistor, a driving transistor, and a second switching transistor disposed on the same substrate according to some embodiments.

[0018] Figure 4B is a schematic cross-sectional view of a transistor including a first switching transistor, a driving transistor, and a second switching transistor disposed on the same substrate according to some embodiments.

[0019] Figure 4C is a schematic cross-sectional view of a transistor including a first switching transistor, a driving transistor, and a second switching transistor disposed on the same substrate according to some embodiments.

[0020] Figure 4D is a schematic cross-sectional view of a transistor including a first switching transistor, a driving transistor, and a second switching transistor disposed on the same substrate according to some embodiments.

[0021] Figure 5A is a schematic cross-sectional view of a transistor including a first switching transistor and a driving transistor disposed on the same substrate according to some embodiments.

[0022] Figure 5B is a schematic cross-sectional view of a transistor including a first switching transistor and a driving transistor disposed on the same substrate according to some embodiments.

[0023] Figure 5C is a schematic cross-sectional view of a transistor including a first switching transistor and a driving transistor disposed on the same substrate according to some embodiments.

[0024] Figure 5D is a schematic cross-sectional view of a transistor including a first switching transistor and a driving transistor disposed on the same substrate according to some embodiments.

[0025] Figure 6A is a schematic cross-sectional view of a transistor including a first switching transistor, a driving transistor, and a second switching transistor disposed on the same substrate according to some embodiments.

[0026] Figure 6B is a schematic cross-sectional view of a transistor including a first switching transistor, a driving transistor, and a second switching transistor disposed on the same substrate according to some embodiments.

[0027] To facilitate understanding, identical reference numerals in the various figures designate identical elements whenever possible. It is anticipated that elements disclosed in one embodiment may be advantageously used in other embodiments and are not described in detail herein. Unless otherwise specified, the drawings herein should not be understood as being drawn to scale. Furthermore, for clarity of presentation and illustration, drawings are often simplified and details or components are omitted. The drawings and discussion serve to illustrate the principles discussed below, with identical reference numerals representing identical elements. DETAILED DESCRIPTION

[0028] The following embodiments are merely exemplary in nature and are not intended to limit the present disclosure or the application and use of the present disclosure. In addition, there is no intention to be bound by any express or implied theory presented in the previous prior art, summary of the invention, or the following embodiments.

[0029] Embodiments herein include thin-film transistors (TFTs) for use in circuits of devices (e.g., display devices). Due to the placement of the switching transistor and the driver transistor on the same substrate, and the selection of electrodes for applying bias voltages and the selection of electrodes for connecting each circuit, the TFTs disclosed herein deliver high currents with high stability, good control, and fast response. One or more of the TFTs include a first bottom gate insulating (GI) layer disposed above and surrounding a driver transistor (DT) bottom gate electrode, and a second bottom GI layer disposed above the first bottom GI layer and above and surrounding a switch transistor (ST) bottom gate electrode. One or more of the TFTs include a driver transistor top gate electrode disposed above a first DT top GI layer and a second DT top GI layer. One or more embodiments include an electrical connection between the DT top gate electrode, the DT source electrode, and a DT source voltage. One or more embodiments include an electrical connection between the ST top gate electrode, the ST bottom gate electrode, and a gate bias voltage. One or more embodiments include an electrical connection between the DT bottom gate electrode, the DT source electrode, and the DT source voltage. One or more embodiments include an electrical connection between the ST top gate electrode, the ST source electrode, and the ST source voltage.

[0030] The TFT described herein is particularly useful for dual-gate or triple structures. The channel structure can include one or more layers of different electron mobilities to contribute different benefits to each TFT. More particularly, the high mobility layer of the channel increases the speed of the response of the TFT, while the low mobility layer allows a higher positive threshold voltage (on-state voltage) and lower leakage current compared to the high mobility layer in the same TFT. As described herein, the combination of the low mobility layer and the high mobility layer results in a TFT with improved quality (e.g., improved mobility, lower off leakage current, and positive threshold voltage (on-state voltage)).

[0031] To operate the subpixels of an OLED pixel for a display, at least one switching transistor, a drive transistor, and a capacitor are used. The switching transistor transfers the data voltage to the capacitor (storage). The storage capacitor is connected to the gate of the drive transistor. The gate voltage of the drive TFT connected to the storage capacitor determines how much current from the drive TFT flows to the OLED to control the brightness. The capacitance of the storage capacitor is determined by the frame rate and leakage current of the switching TFT connected to the storage capacitor and the gate of the drive TFT for the display.

[0032] Figure 1This is a simplified schematic diagram of an organic light-emitting diode display (OLED) panel 100. The OLED display panel 100 includes a non-display region 102 for switching TFTs for a gate-on-array (GOA) circuit, a display region 104 for switching and driving TFTs for pixel circuits, and a region 106 for a source (data) driver integrated circuit (IC). In some aspects, the non-display region 102 is disposed in an edge region disposed at one or more sides or surrounding the display region 104.

[0033] Figure 2A FIG. 2 is a schematic diagram of a simplified set of pixel circuits 204 a and GOA circuits 202 a in the OLED display panel 100 according to one or more embodiments. Figure 2B FIG. 1 is a schematic diagram of a simplified set of pixel circuits 204b and GOA circuits 202b in an OLED display panel 100 according to one or more embodiments. Pixel circuits 204a, 204b, GOA circuits 202a, and 202b have multiple thin film transistors (TFTs) and storage capacitors (e.g., more than two transistors and / or more than one capacitor). Figure 2A As shown, pixel circuit 204a includes a first switching transistor ST1, a current regulator or driver transistor DT1, a second switching transistor ST2, a third switching transistor ST3, and a storage capacitor C1. GOA circuit 202a includes switching transistors (e.g., a pull-up buffer switching transistor TUP and a pull-down buffer switching transistor TDOWN). Transistors used in the GOA circuit and pixel circuit can be oxide transistors or low-temperature polysilicon (LTPS) transistors.

[0034] The gate electrode (SG1) of the first switching transistor is connected to the scan line (Vscan), while the source-drain electrode is connected between the Vdata line and the drive transistor gate electrode (DG1) of the drive transistor DT1 through the third switching transistor ST3. The OLED 206 arranged in the OLED area of ​​the sub-pixel in the full-color display is electrically connected to the drive transistor DT1. The circuit for the OLED 206 includes the third switching transistor ST3 between the drive transistor DT1 and the OLED 206. The circuit further continues from the OLED 206 to a low-level supply voltage (VSS) or ground (GND). The third switching transistor gate electrode SG3 of the third switching transistor ST3 is connected to the first emission control signal V EM1The OLED 206 is controlled by current from the driving transistor DT1 in the pixel circuit and has a cathode connected to a common terminal or conductor and an anode connected through the source-drain of the driving transistor DT1. The source-drain of the second switching transistor ST2 is connected to the high level power supply (ELVDD) and the driving transistor DT1. The second switching transistor gate SG2 of the second switching transistor ST2 is connected to the second emission control signal V EM2 The second switching transistor ST2, the third switching transistor ST3, and the driving transistor DT1 are connected to one or more switching transistors or storage capacitors in the circuit region 210. The storage capacitor C1 is connected to the gate of the driving transistor DT1. The storage capacitor C1 maintains the gate voltage of the driving transistor DT1. Additional locations for the storage capacitor are also contemplated (e.g., connected to the anode of the OLED 206, to the source of the second switching transistor ST2, to the source of the third switching transistor ST3, or to a high-level power supply (ELVDD)).

[0035] When a select signal appears on the Vscan line and a data signal appears on the Vdata line, the OLED is addressed or selected. The transistor can be turned on and off by applying the select signal to the gate of the transistor via the selected line. The signal on the Vscan line is applied to the gate (SG1) of the first switching transistor T1 to "turn on" the transistor. The data signal on the Vdata line is applied to the gate (DG1) of the drive transistor DT1 via the circuit area 210 through the source-drain of the first switching transistor ST1, and the drive transistor DT1 is "turned on" according to the amplitude and / or duration of the data signal. The drive transistor DT1 then supplies power to the OLED 206, typically in the form of a drive current. The brightness or intensity of the light generated by the OLED 206 can depend on the amount and / or duration of the current supplied. The emission control signal voltage (VEM1, VEM2) from the GIP circuit is applied to the gate of the second switching transistor ST2 and the gate of the third switching transistor ST3. When the second switching transistor ST2 is turned on, the high-level supply voltage (ELVDD) is electrically connected to the source-drain of the driving transistor ST1. When the third switching transistor ST3 is turned on, the anode of the OLED 206 is electrically connected to the source-drain of the driving transistor ST1. The current of the driving transistor DT1 is delivered to the OLED 206. By changing the gate voltage of the driving transistor DT1, the amount of current from the driving transistor DT1 is changed to control the brightness of the OLED. The gate voltage of the driving transistor DT1 is changed by the voltage from the data signal Vdata. After the switching transistor T1 is turned "off", the storage capacitor C1 stores the voltage on the Vdata line.

[0036] like Figure 2B As shown, pixel circuit 204b includes a first switching transistor ST1, a current regulator or driver transistor DT1, a second switching transistor ST2, and a storage capacitor C1. GOA circuit 202b includes switching transistors (e.g., a pull-up buffer switching transistor TUP and a pull-down buffer switching transistor TDOWN). The transistors used in the GOA circuit and pixel circuit can be oxide transistors or low-temperature polysilicon (LTPS) transistors.

[0037] The first switching transistor gate (SG1) is connected to the scan line (Vscan), while the source-drain is connected between the Vdata line and the drive transistor gate (DG1) of the drive transistor DT1. An OLED 206, arranged in the OLED region of a subpixel in a full-color display, is electrically connected to the drive transistor DT1 via a third switching transistor ST3. The circuitry for the OLED 206 is further connected to a low-level supply voltage (VSS) or ground (GND). The OLED 206 is controlled by current from the drive transistor DT1 in the pixel circuit and has a cathode connected to a shared terminal or conductor and an anode connected via the source-drain of the drive transistor DT1. The source-drain of the second switching transistor ST2 is connected to a high-level power supply (ELVDD) and the drive transistor DT1. The second switching transistor gate SG2 of the second switching transistor ST2 is connected to an emission control signal. The second switching transistor ST2 and the drive transistor DT1 are connected to one or more switching transistors or a storage capacitor in the circuit region 210. The storage capacitor C1 is connected to the gate of the drive transistor DT1. The storage capacitor C1 maintains the gate voltage of the drive transistor DT1. Locations for additional storage capacitors are also contemplated (eg, connected to the anode of the OLED 206, to the source of the second switching transistor ST2, or to the high-level power supply (ELVDD)).

[0038] When a select signal appears on the Vscan line and a data signal appears on the Vdata line, the OLED is addressed or selected. The transistor can be turned on and off by applying the select signal to the gate of the transistor via the selected line. The signal on the Vscan line is applied to the switching transistor gate (SG1) of the switching transistor ST1 to "turn on" the transistor. The data signal on the Vdata line is applied to the driving transistor gate (DG1) of the driving transistor DT1 via the source-drain of the switching transistor T1 via the circuit area 210, and the driving transistor DT1 is "turned on" according to the amplitude and / or duration of the data signal. The driving transistor T2 then supplies power to the OLED 206, typically in the form of a drive current. The brightness or intensity of the light generated by the OLED 206 can depend on the amount and / or duration of the supplied current. The emission control signal voltage from the GIP circuit is applied to the gate of the second switching transistor ST2 and the gate of the third switching transistor ST3. When the second switching transistor ST2 is turned on, the high-level supply voltage (ELVDD) is electrically connected to the source-drain of the driving transistor ST1. The current of the driving transistor DT1 is delivered to the OLED 206. The amount of current from the driving transistor DT1 is varied by changing the gate voltage of the driving transistor DT1 to control the OLED brightness. After the switching transistor T1 is turned "off", the storage capacitor C1 stores the voltage on the Vdata line.

[0039] Figure 3A Depicted is a schematic cross-sectional view of a transistor 300A including a first switch transistor 322 and a driver transistor 324 disposed on the same substrate 302 . Figure 3B Depicted is a schematic cross-sectional view of a transistor 300B including a first switch transistor 322 and a driver transistor 324 disposed on the same substrate 302 . Figure 3C Depicted is a schematic cross-sectional view of a transistor 300C including a first switch transistor 322 and a drive transistor 324 disposed on the same substrate 302 . Figure 3D A schematic cross-sectional view of a transistor 300D is depicted that includes a first switch transistor 322 and a driver transistor 324 disposed on the same substrate 302. In some aspects, each of the driver transistors may be used to Figure 2A The pixel circuit 204a or Figure 2B The driving transistor (T2) in the pixel circuit 204b is shown. In some aspects, each of the switching transistors can be used to Figure 2A The switching transistors (T3, T4) in the pixel circuit 204a shown, or for Figure 2B The switching transistor (T3) in the pixel circuit 204b is shown.

[0040] Transistors 300A-300D are dual-gate TFTs having a first switch transistor (ST) top gate electrode 314A for a first switch transistor 322, a first switch transistor (ST) bottom gate electrode 306A for the first switch transistor 322, a driver transistor (DT) top gate electrode 314B for a driver transistor 324, and a driver transistor (DT) bottom gate electrode 306B for the driver transistor 324. Transistors 300A-300D include a substrate 302 (e.g., a silicon base substrate, an insulating base substrate, a germanium base substrate, or other suitable flexible substrate). Substrate 302 may include one or more common layers found in complementary metal oxide semiconductor (CMOS) device structures. Substrate 302 may include a transparent material (e.g., rigid glass or flexible polyimide (PI)), which may be useful if the TFT is used in an LCD or OLED display application (e.g., a television, tablet computer, laptop computer, mobile phone, or other display). A buffer layer 304 is disposed above substrate 302 (e.g., in direct contact with substrate 302). The buffer layer 304 may include an insulating material (eg, a single silicon dioxide (SiO x ), silicon nitride (SiN x ), multilayer silicon nitride / silicon oxide (SiN x / SiO y ), silicon oxynitride (SiON), other insulating materials, or combinations thereof). The DT bottom gate electrode 306B of the drive transistor 324 is disposed above the buffer layer 304. In some aspects, the DT bottom gate electrode 306B corresponds to DG1 of FIG. 2 . In some embodiments, during use in OLED applications, a gate bias is applied to the DT bottom gate electrode 306B. In some aspects, the DT bottom gate electrode 306B is deposited and patterned using any suitable process known in the art.

[0041] A first bottom gate insulating (GI) layer 308 is disposed over the buffer layer 304. The first bottom GI layer 308 is disposed over and around the top surface and sides of the DT bottom gate electrode 306B. The GI material for the first bottom GI layer 308 and / or for any gate insulator described herein may include an insulating material (e.g., silicon, SiN x , other insulating materials, or combinations thereof (e.g., silicon dioxide (SiO2), polymethylsilsesquioxane (PMSQ), or other suitable materials)).

[0042] A first switch transistor (ST) bottom gate electrode 306A of the first switch transistor 322 is disposed above the first bottom GI layer 308. In some aspects, the first ST bottom gate electrode 306A corresponds to switch transistors SG1, SG2, SG3, or other switch transistors in the circuit area 210 of Figures 2a and 2b. In some embodiments, a gate bias is applied to the first ST bottom gate electrode 306A of the switch transistor SG2 or SG3 for emission control. Current from the drive transistor DT1 is delivered in OLED display applications by connecting the drive transistor DT1 to a high-level voltage (ELVDD) and the anode of the OLED 206 for OLED emission control. In some aspects, the first ST bottom gate electrode 306A is deposited and patterned using any suitable process known in the art. A second bottom gate insulating (GI) layer 309 is disposed above the first bottom GI layer 208. The second bottom GI layer 309 is disposed above and surrounds the top surface and sides of the first ST bottom gate electrode 306A. The first bottom GI layer 308 is a first GI material, and the second bottom GI layer 309 is a second GI material. In one embodiment, the first GI material and the second GI material are the same material. In another embodiment, the first GI material and the second GI material are different materials.

[0043] A first switch transistor (ST) channel structure 310A and a driver transistor (DT) channel structure 310B are disposed above the second bottom GI layer 309. In some embodiments, a single channel structure is deposited above the second bottom GI layer 309 and etched to form the first ST channel structure 310A and the DT channel structure 310B. In other embodiments, the first ST channel structure 310A and the DT channel structure 310B are separately deposited above the second bottom GI layer 309. The first ST channel structure 310A is positioned above the first ST bottom gate electrode 306A in the first switch transistor 322, while the DT channel structure 310B is positioned above the DT bottom gate electrode 306B in the driver transistor 324. The first ST channel structure 310A and the DT channel structure 310B can be single-layer channel structures, a two-layer channel stack (where each layer has a different electron mobility), or three or more layers (where each layer has a different electron mobility than the layer immediately above or below it).

[0044] In some embodiments having a two-layer channel stack, the top layer has a lower mobility than the bottom layer. In some embodiments having three stacked layers, the top layer has a lower mobility than the middle layer, while the middle layer has a higher mobility than the bottom layer. In some embodiments having four stacked layers, the top layer has a lower mobility than the second layer, the second layer has a higher mobility than the third layer, and the third layer has a lower mobility than the bottom layer. Each layer of the multilayer channel structure is about 0.5 nm to about 20 nm. The total thickness of the channel structure is about 5 nm to about 60 nm.

[0045] The first ST channel structure 310A and the DT channel structure 310B are composed of metal oxide materials or low temperature polysilicon (LTPS). Any channel structure described herein may be composed of metal oxide (MO) materials (e.g., single-layer or multi-layer MO channels). Alternatively, any channel structure described herein may be composed of LTPS (e.g., single-layer LTPS channels). Metal oxides may include oxygen (O), indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al), and combinations thereof (e.g., In-Zn-O, In-Ga-O, In-Sn-O, In-Ga-Zn-O, In-Zn-Sn-O, In-Ga-Sn-O, In-Ga-Zn-Sn-O, or any combination thereof). Metal oxide materials or LTPS may be selected based on a predetermined electron mobility selected for one or more layers of the first ST channel structure 310A and the DT channel structure 310B.

[0046] A first switch transistor (ST) top gate insulating (GI) layer 312A is disposed over the first ST channel structure 310A. In some embodiments, the first ST top GI layer 312A is patterned to approximate the width of a first switch transistor (ST) top gate electrode 314A disposed over the first ST top GI layer 312A. A first drive transistor (DT) top gate insulating (GI) layer 312B is disposed over the DT channel structure 310B. In some embodiments, the first DT top GI layer 312B is patterned to approximate the width of a drive transistor (DT) top gate electrode 314B disposed over the first DT top GI layer 312B. Alternatively, as Figure 4C and Figure 4D As shown, a single top GI layer is disposed over and around the top surfaces and sides of the first ST channel structure 310A and the DT channel structure 310B, and over the second bottom GI layer 309. Any other patterning, including a top GI layer having a width greater than that of the top gate electrode, may be used for one or more of the TFTs depicted in any of the other figures.

[0047] The widths of the first ST top gate electrode 314A and the DT top gate electrode 314B are less than or equal to the widths of the first ST bottom gate electrode 306A and the DT bottom gate electrode 306B, respectively. The widths of the first ST bottom gate electrode 306A and the DT bottom gate electrode 306B are adjustable. In some embodiments, the widths of the first ST bottom gate electrode 306A and the DT bottom gate electrode 306B are approximately 2 μm to approximately 40 μm. The widths of the first ST top gate electrode 314A and the DT top gate electrode 314B are approximately 1 μm to approximately 30 μm.

[0048] The thickness of the first ST top GI layer 312A and the first DT top GI layer 312B is less than the combined thickness of the first bottom GI layer 308 and the second bottom GI layer 309. The thickness of the first ST top GI layer 312A and the DT top GI layer 312B is about 50 nm to about 200 nm. The combined thickness of the first bottom GI layer 308 and the second bottom GI layer 309 is about 200 nm to about 600 nm.

[0049] An interlayer dielectric (ILD) layer 316 is disposed over the first ST top gate electrode 314A, the DT top gate electrode 314B, a portion of the first ST channel structure 310A, and a portion of the DT channel structure 310B. Any ILD layer described herein can be composed of materials such as silicon oxide, nitride, oxynitride, and carbide (e.g., a silicon-based dielectric film).

[0050] The first switch transistor 322 includes a first switch transistor (ST) source 318A and a first switch transistor (ST) drain 319A disposed above the ILD layer 316. The driver transistor 324 includes a driver transistor (DT) source 318B and a driver transistor (DT) drain 319B disposed above the ILD layer 316. The first ST source 318A, the DT source 318B, the first ST drain 319A, and the DT drain 319B are coupled to the first ST channel structure 310A and the DT channel structure 310B, respectively, through vias in the ILD layer 316. Each electrode described herein (e.g., the first ST top gate electrode 314A, the first ST bottom gate electrode 306A, the DT top gate electrode 314B, the DT bottom gate electrode 306B, the first ST source 318A, the DT source 318B, the first ST drain 319A, and the DT drain 319B) includes a conductive material (e.g., molybdenum (Mo), chromium (Cr), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), alloy metals (including MoW), combinations of conductive materials (including MoW, TiCu, MoCu, MoCuMo, TiCuTi, MoWCu, MoWCuMoW), any electrically conductive material (e.g., including conductive metal oxides (e.g., indium tin oxide (InSnO) [ITO] and indium zinc oxide (InZnO) [IZO])), or any combination thereof). One or more of the electrodes can be made of the same conductive material, or each electrode can be made of a different material.

[0051] In some embodiments (e.g., in transistor 300C and transistor 300D), the transistor includes a storage capacitor formation 330. In some aspects, storage capacitor formation 330 corresponds to C1 in Figures 2a and 2b. Storage capacitor formation 330 includes a first capacitor bottom gate 332, a second capacitor bottom gate 334, and a capacitor channel structure 336. A first capacitor is formed between first capacitor bottom gate 332 and second capacitor bottom gate 334. A second capacitor is formed between second capacitor bottom gate 334 and capacitor channel 336. In some embodiments, capacitor channel 336 can be removed, leaving only the first capacitor. In other embodiments, first capacitor bottom gate 332 can be removed, leaving only the second capacitor. First capacitor bottom gate 332 is disposed above buffer layer 304 and positioned between first switch transistor 322 and driver transistor 324. First bottom GI layer 308 is disposed above and around the top surface and sides of first capacitor bottom gate 332. A second capacitor bottom gate 334 is disposed above the first bottom GI layer 308 and positioned between the first switch transistor 322 and the driver transistor 324. A second bottom GI layer 309 is disposed above and surrounds the top surface and sides of the second capacitor bottom gate 334. A capacitor channel structure 336 is disposed above the second bottom GI layer 309 and positioned between the first switch transistor 322 and the driver transistor 324. An ILD layer 316 is disposed above and surrounds the top surface and sides of the capacitor channel structure 336. After the switch transistor ST1 is turned "off," the storage capacitor 330 stores the voltage on the Vdata line.

[0052] In each of the figures, each electrode of transistors 300A-300D includes an electrode path, wherein the current path of each electrode is depicted. In transistors 300A and 300C, the first switch transistor 322 includes a first ST drain 319A coupled to a first ST drain voltage V DST The first ST drain electrode path 321A is coupled from the first ST source 318A to the first ST source voltage V SST The first ST source electrode path 320A is connected from the first ST top gate electrode 314A and the first ST bottom gate electrode 306A and is coupled to the first ST gate voltage V GST The drive transistor 324 includes a first ST top gate electrode path 325A and a first ST bottom gate electrode path 326A. ... DDTThe DT drain electrode path 321B is connected from the DT source 318B and the DT top gate electrode 314B and is coupled to the DT source voltage V SDT The DT source electrode path 320B and the DT top gate electrode path 325B and the DT bottom gate electrode 306B are coupled to the DT gate voltage V GDT DT bottom gate electrode path 326B.

[0053] The driver transistor 324 of transistor 300A and transistor 300C includes a physical and electrical connection between the DT source 318B and the DT top gate electrode 314B using a DT source electrode path 320B and a DT top gate electrode path 325B. The first switch transistor 322 of transistor 300A and transistor 300C includes a physical and electrical connection between the first ST bottom gate electrode 306A and the first ST top gate electrode 314A using an ST top gate electrode path 325A and a first ST bottom gate electrode path 326A. In some embodiments, the connection is made via electrical wiring and / or other connection bridges. The connection can be made using contact holes in the active pixel area (e.g., display area 104). A gate bias is applied to the DT bottom gate electrode 306B via the DT bottom gate electrode path 326B.

[0054] The transistors 300A and 300C are structured to be connected and coupled to the DT source voltage V SDT DT top gate electrode 314B and DT source 318B, while DT bottom gate electrode 306B is coupled to DT gate voltage V GDT The architecture further includes a first bottom GI layer 308 and a second bottom GI layer 309. This architecture allows the first switch transistor 322 and the driver transistor 324 to have high mobility and electrical stability. In addition, the architecture allows for smaller subthreshold (SS) values ​​for the first switch transistor 322 and the second switch transistor 323, and a larger SS value for the driver transistor 324 on the same substrate 302. These qualities result in higher speed / higher frequency operation and better display image quality.

[0055] In transistors 300B and 300D, the first switch transistor 322 includes a first ST drain 319A coupled to a first ST drain voltage V DST The first ST drain electrode path 321A is coupled from the first ST source 318A to the first ST source voltage V SST The first ST source electrode path 320A is connected from the first ST top gate electrode 314A and the first ST bottom gate electrode 306A and is coupled to the first ST gate voltage V GSTThe drive transistor 324 includes a first ST top gate electrode path 325A and a first ST bottom gate electrode path 326A. ... DDT DT drain electrode path 321B, coupled from DT source 318B to DT source voltage V SDT DT source electrode path 320B, coupled from DT top gate electrode 314B to DC voltage V DC The DT top gate electrode path 325B and the DT bottom gate electrode 306B are coupled to the DT gate voltage V GDT DT bottom gate electrode path 326B.

[0056] Transistor 300B and first switch transistor 322 of transistor 300B include physical and electrical connections between first ST bottom gate electrode 306A and first ST top gate electrode 314A using ST top gate electrode path 325A and first ST bottom gate electrode path 326A. In some embodiments, the connections are made via electrical wiring and / or other connection bridges. Contact holes in the active pixel area (e.g., display area 104) can be used for the connections. A gate bias is applied to DT bottom gate electrode 306B via DT bottom gate electrode path 326B.

[0057] The transistors 300B and 300D are connected and coupled to a DC voltage V DC DT top gate electrode 314B, while DT bottom gate electrode 306B is coupled to DT gate voltage V GDT The architecture further includes a first bottom GI layer 308 and a second bottom GI layer 309. This architecture allows the first switch transistor 322 and the driver transistor 324 to have high mobility and electrical stability. In addition, the architecture allows for smaller subthreshold (SS) values ​​for the first switch transistor 322 and the second switch transistor 323, and a larger SS value for the driver transistor 324 on the same substrate. These qualities result in higher speed / higher frequency operation and better display image quality.

[0058] Figure 4A Depicted is a schematic cross-sectional view of a transistor 400A including a first switching transistor 422 , a driving transistor 424 , and a second switching transistor 423 disposed on the same substrate 402 . Figure 4B Depicted is a schematic cross-sectional view of a transistor 400B including a first switching transistor 422 , a driving transistor 424 , and a second switching transistor 423 disposed on the same substrate 402 . Figure 4CDepicted is a schematic cross-sectional view of a transistor 400C including a first switching transistor 422 , a driving transistor 424 , and a second switching transistor 423 disposed on the same substrate 402 . Figure 4D A schematic cross-sectional view of a transistor 400D is depicted including a first switch transistor 422, a driver transistor 424, and a second switch transistor 423 disposed on the same substrate 402. In some aspects, the driver transistor may be used to Figure 2A The pixel circuit 204a or Figure 2B The driving transistor (T2) in the pixel circuit 204b is shown. In some aspects, each of the switching transistors can be used to Figure 2A The switching transistors (T3, T4) in the pixel circuit 204a shown, or for Figure 2B The switching transistor (T3) in the pixel circuit 204b is shown.

[0059] Transistors 400A-400D are tri-gate TFTs having a first switch transistor (ST) top gate electrode 414A for a first switch transistor 422, a first switch transistor (ST) bottom gate electrode 406A for the first switch transistor 422, a driver transistor (DT) top gate electrode 414B for a driver transistor 424, a driver transistor (DT) bottom gate electrode 406B for the driver transistor 424, a second switch transistor (ST) top gate electrode 414C for a second switch transistor 423, and a second switch transistor (ST) bottom gate electrode 406C for the second switch transistor 423. Transistors 400A-400D include a substrate 402 (e.g., a silicon substrate, an insulating substrate, a germanium substrate, or other suitable flexible substrate). Substrate 402 may include one or more common layers present in a complementary metal oxide semiconductor (CMOS) device structure. Substrate 402 may include a transparent material (e.g., rigid glass or flexible polyimide (PI)), which may be useful if the TFT is used in an LCD or OLED display application (e.g., a television, tablet computer, laptop computer, mobile phone, or other display). Buffer layer 404 is disposed above substrate 402 (e.g., in direct contact with substrate 402). Buffer layer 404 may include an insulating material (e.g., a single layer of silicon dioxide (SiO x ), silicon nitride (SiN x ), multilayer silicon nitride / silicon oxide (SiN x / SiO y), silicon oxynitride (SiON), other insulating materials, or combinations thereof). The DT bottom gate electrode 406B of the drive transistor 424 is disposed over the buffer layer 404. In some aspects, the DT bottom gate electrode 406B corresponds to DG1 of FIG. 2 . In some embodiments, during use in OLED applications, a gate bias is applied to the DT bottom gate electrode 406B. In some aspects, the DT bottom gate electrode 406B is deposited and patterned using any suitable process known in the art.

[0060] A first bottom gate insulating (GI) layer 408 is disposed over the buffer layer 404. The first bottom GI layer 408 is disposed over and around the top surface and sides of the DT bottom gate electrode 406B. The GI material for the first bottom GI layer 408 and / or for any gate insulator described herein may include an insulating material (e.g., silicon, SiNx, other insulating materials, or combinations thereof (e.g., silicon dioxide (SiO2), polymethylsilsesquioxane (PMSQ), or other suitable materials)).

[0061] A first switch transistor (ST) bottom gate electrode 406A of the first switch transistor 422 and a second ST bottom gate electrode 406C of the second switch transistor 423 are disposed above the first bottom GI layer 408. In some aspects, the first ST bottom gate electrode 406A corresponds to the switch transistor SG1, SG2, SG3, or other switch transistors in the circuit area 210 of Figures 2a and 2b. In some embodiments, a gate bias is applied to the first ST bottom gate electrode 406A of the switch transistor SG2 or SG3 for emission control. The current of the drive transistor DT1 is delivered in OLED display applications by connecting the drive transistor DT1 to a high-level voltage (ELVDD) and the anode of the OLED 206 for OLED emission control. In some aspects, the first ST bottom gate electrode 406A and the second ST bottom gate electrode 406C are deposited and patterned using any suitable process known in the art. A second bottom gate insulating (GI) layer 409 is disposed above the first bottom GI layer 408. The second bottom GI layer 409 is disposed above and around the top surfaces and sides of the first and second ST bottom gate electrodes 406A and 406C. The first bottom GI layer 408 is a first GI material, while the second bottom GI layer 409 is a second GI material. In one embodiment, the first and second GI materials are the same material. In another embodiment, the first and second GI materials are different materials.

[0062] A first switch transistor (ST) channel structure 410A, a driver transistor (DT) channel structure 410B, and a second switch transistor (ST) channel structure 410C are disposed above the second bottom GI layer 409. In some embodiments, a single channel structure is deposited above the second bottom GI layer 409 and etched to form the first ST channel structure 410A, the DT channel structure 410B, and the second ST channel structure 410C. In other embodiments, the first ST channel structure 410A, the DT channel structure 410B, and the second ST channel structure 410C are separately deposited above the second bottom GI layer 409. The first ST channel structure 410A is positioned above the first ST bottom gate electrode 406A in the first switch transistor 422, the DT channel structure 410B is positioned above the DT bottom gate electrode 406B in the driver transistor 424, and the second ST channel structure 410C is positioned above the second ST bottom gate electrode 406C in the second switch transistor 423. The first ST channel structure 410A, the DT channel structure 410B, and the second ST channel structure 410C can be a single-layer channel structure, a double-layer channel stack (in which each layer has a different electron mobility), or three or more layers (each layer has an electron mobility different from the layer directly above or below the layer).

[0063] In some embodiments having a two-layer channel stack, the top layer has a lower mobility than the bottom layer. In some embodiments having three stacked layers, the top layer has a lower mobility than the middle layer, while the middle layer has a higher mobility than the bottom layer. In some embodiments having four stacked layers, the top layer has a lower mobility than the second layer, the second layer has a higher mobility than the third layer, and the third layer has a lower mobility than the bottom layer. Each layer of the multilayer channel structure is about 0.5 nm to about 20 nm. The total thickness of the channel structure is about 5 nm to about 60 nm.

[0064] The first ST channel structure 410A, the DT channel structure 410B, and the second ST channel structure 410C are composed of metal oxide materials or low-temperature polysilicon (LTPS). Any channel structure described herein may be composed of metal oxide (MO) materials (e.g., single-layer or multi-layer MO channels). Alternatively, any channel structure described herein may be composed of LTPS (e.g., single-layer LTPS channels). Metal oxides may include oxygen (O), indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al), and combinations thereof (e.g., In-Zn-O, In-Ga-O, In-Sn-O, In-Ga-Zn-O, In-Zn-Sn-O, In-Ga-Sn-O, In-Ga-Zn-Sn-O, or any combination thereof). Metal oxide materials or LTPS may be selected based on a predetermined electron mobility selected for one or more layers of the first ST channel structure 410A, the DT channel structure 410B, and the second ST channel structure 410C.

[0065] In transistors 400A and 400B, a first switch transistor (ST) top gate insulating (GI) layer 412A is disposed over a first ST channel structure 410A. In some embodiments, the first ST top GI layer 412A is patterned to approximate the width of a first switch transistor (ST) top gate electrode 414A disposed over the first ST top GI layer 412A. A first driver transistor (DT) top gate insulating (GI) layer 412B is disposed over the DT channel structure 410B. In some embodiments, the first DT top GI layer 412B is patterned to approximate the width of a driver transistor (DT) top gate electrode 414B disposed over the first DT top GI layer 412B. A second switch transistor (ST) top gate insulating (GI) layer 412C is disposed over a second ST channel structure 410C. In some embodiments, the second ST top GI layer 412C is patterned to approximate the width of a second switch transistor (ST) top gate electrode 414C disposed over the second ST top GI layer 412C.

[0066] In transistors 400C and 400D, a single top GI layer 412 is disposed over the top surface and sides of the first ST channel structure 410A, over the top surface and sides of the DT channel structure 410B, over the top surface and sides of the second ST channel structure 410C, and surrounds the top surface and sides of the first ST channel structure 410A, the top surface and sides of the DT channel structure 410B, and the top surface and sides of the second ST channel structure 410C, and over the second bottom GI layer 409. Any other patterning, including a top GI layer having a width greater than that of the top gate electrode, may be used for one or more of the TFTs depicted in any other figures.

[0067] The widths of the first ST top gate electrode 414A, the DT top gate electrode 414B, and the second ST top gate electrode 414C are less than or equal to the widths of the first ST bottom gate electrode 406A, the DT bottom gate electrode 406B, and the second ST bottom gate electrode 406C, respectively. The widths of the first ST bottom gate electrode 406A, the DT bottom gate electrode 406B, and the second ST bottom gate electrode 406C are adjustable. In some embodiments, the widths of the first ST bottom gate electrode 406A, the DT bottom gate electrode 406B, and the second ST bottom gate electrode 406C are approximately 2 μm to approximately 40 μm. The widths of the first ST bottom gate electrode 406A, the DT bottom gate electrode 406B, and the second ST bottom gate electrode 406C are approximately 1 μm to approximately 30 μm.

[0068] The thickness of the first ST top GI layer 412A, the first DT top GI layer 412B, and the second ST top GI layer 412C is less than the combined thickness of the first bottom GI layer 408 and the second bottom GI layer 409. The thickness of the first ST top GI layer 412A, the first DT top GI layer 412B, and the second ST top GI layer 412C is about 50 nm to about 200 nm. The combined thickness of the first bottom GI layer 408 and the second bottom GI layer 409 is about 200 nm to about 600 nm.

[0069] An interlayer dielectric (ILD) layer 416 is disposed over the first ST top gate electrode 414A, the DT top gate electrode 314B, the second ST top gate electrode 414C, a portion of the first ST channel structure 410A, a portion of the DT channel structure 310B, and a portion of the second ST channel structure 410C. Any of the ILD layers described herein can be composed of materials such as silicon oxide, nitride, oxynitride, and carbide (e.g., a silicon-based dielectric film).

[0070] The first switch transistor 422 includes a first switch transistor (ST) source 418A and a first switch transistor (ST) drain 419A disposed above the ILD layer 416. The driver transistor 424 includes a driver transistor (DT) source 418B and a driver transistor (DT) drain 419B disposed above the ILD layer 416. The second switch transistor 423 includes a second switch transistor (ST) source 418C and a second switch transistor (ST) drain 419C disposed above the ILD layer 416. The first ST source 418A, the DT source 418B, the second ST source 418C, the first ST drain 419A, the DT drain 419B, and the second ST drain 419C are coupled to the first ST channel structure 410A, the DT channel structure 410B, and the second ST channel structure 410C, respectively, through vias in the ILD layer 416. Each electrode described herein (e.g., the first ST top gate electrode 414A, the first ST bottom gate electrode 406A, the DT top gate electrode 414B, the DT bottom gate electrode 406B, the second ST top gate electrode 414C, the second ST bottom gate electrode 406C, the first ST source 418A, the DT source 418B, the second ST source 418C, the first ST drain 419A, the DT drain 419B, and the second ST drain 419C) includes a conductive material (e.g., molybdenum (Mo), chromium (Cr), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), alloy metals (including MoW), combinations of conductive materials (including MoW, TiCu, MoCu, MoCuMo, TiCuTi, MoWCu, MoWCuMoW), any electrically conductive material (e.g., including conductive metal oxides (e.g., indium tin oxide (InSnO) [ITO] and indium zinc oxide (InZnO) [IZO])), or any combination thereof). One or more of the electrodes may be made of the same conductive material, or each electrode may be made of a different material.

[0071] In some embodiments, as shown in transistors 400A-400D, the transistor includes a storage capacitor formation 430. In some aspects, storage capacitor formation 430 corresponds to C1 in Figures 2a and 2b. Storage capacitor formation 430 includes a first capacitor bottom gate 432, a second capacitor bottom gate 434, and a capacitor channel structure 436. A first capacitor is formed between the first capacitor bottom gate 432 and the second capacitor bottom gate 434. A second capacitor is formed between the second capacitor bottom gate 434 and the capacitor channel 436. In some embodiments, capacitor channel 436 can be removed, leaving only the first capacitor. In other embodiments, the first capacitor bottom gate 432 can be removed, leaving only the second capacitor. The first capacitor bottom gate 432 is disposed above the buffer layer 404 and positioned between the first switch transistor 422 and the driver transistor 424. A first bottom GI layer 408 is disposed above and around the top surface and sides of the first capacitor bottom gate 432. A second capacitor bottom gate 434 is disposed above the first bottom GI layer 408 and positioned between the first switch transistor 422 and the driver transistor 424. A second bottom GI layer 409 is disposed above and surrounds the top surface and sides of the second capacitor bottom gate 434. A capacitor channel structure 436 is disposed above the second bottom GI layer 409 and positioned between the first switch transistor 422 and the driver transistor 424. In transistors 400A and 400B, an ILD layer 416 is disposed above and surrounds the top surface and sides of the capacitor channel structure 436. In transistors 400C and 400D, a top GI layer 412 is disposed above and surrounds the top surface and sides of the capacitor channel structure 436. After the switch transistor ST1 is turned "off," the storage capacitor 430 stores the voltage on the Vdata line. In an alternative embodiment, the storage capacitor formation 430 is positioned between the drive transistor 424 and the second switch transistor 423 .

[0072] In each of the figures, each electrode of transistors 400A-400D includes an electrode path, wherein the current path of each electrode is depicted. In transistors 400A and 400C, the first switch transistor 422 includes a first ST drain 419A coupled to a first ST drain voltage V DST1 The first ST drain electrode path 421A is coupled from the first ST source 418A to the first ST source voltage V SST1 The first ST source electrode path 420A is connected from the first ST top gate electrode 414A and the first ST bottom gate electrode 406A and is coupled to the first ST gate voltage VGST1 The drive transistor 424 includes a first ST top gate electrode path 425A and a first ST bottom gate electrode path 426A. ... DDT The DT drain electrode path 421B is connected from the DT source 418B and the DT top gate electrode 414B and is coupled to the DT source voltage V SDT The DT source electrode path 420B and the DT top gate electrode path 425B and the DT bottom gate electrode 406B are coupled to the DT gate voltage V GDT The second switch transistor 423 includes a second ST drain 419C coupled to the second ST drain voltage V DST2 The second ST drain electrode path 421C is coupled from the second ST source 418C and the second ST top gate electrode 414C to the second ST source voltage V SST2 The second ST source electrode path 420C and the second ST top gate electrode path 425C are coupled from the second ST bottom gate electrode 406C to the second ST gate voltage V GST2 The second ST bottom gate electrode path 426C.

[0073] The driver transistor 424 of transistors 400A and 400C includes a physical and electrical connection between a DT source electrode 418B and a DT top gate electrode 414B via a DT source electrode path 420B and a DT top gate electrode path 425B. The first switch transistor 422 of transistors 400A and 400C includes a physical and electrical connection between a first ST bottom gate electrode 406A and a first ST top gate electrode 414A via a first ST top gate electrode path 425A and a first ST bottom gate electrode path 426A. The second switch transistor 423 of transistors 400A and 400C includes a physical and electrical connection between a second ST source electrode 418C and a second ST top gate electrode 414C via a second ST source electrode path 420C and a second ST top gate electrode path 425C. In some embodiments, the connection is made via electrical wiring and / or other connection bridges. The connection can be made using contact holes in the active pixel region (e.g., display region 104). A gate bias is applied to the DT bottom gate electrode 406B via the DT bottom gate electrode path 426B.

[0074] The transistors 400A and 400C are structured to have a voltage connected to the DT source V SDT DT top gate electrode 414B and DT source 418B, while DT bottom gate electrode 406B is coupled to DT gate voltage V GDTThe architecture further includes a first bottom GI layer 408 and a second bottom GI layer 409. This architecture allows the first switch transistor 422, the driver transistor 424, and the second switch transistor 423 to have high mobility and electrical stability. In addition, the architecture allows for smaller subthreshold (SS) values ​​for the first switch transistor 422 and the second switch transistor 423, and a larger SS value for the driver transistor 424 on the same substrate. These qualities result in higher speed / higher frequency operation and better display image quality.

[0075] In transistors 400B and 400D, the first switch transistor 422 includes a first ST drain 419A coupled to a first ST drain voltage V DST1 The first ST drain electrode path 421A is coupled from the first ST source 418A to the first ST source voltage V SST1 The first ST source electrode path 420A is connected from the first ST top gate electrode 414A and the first ST bottom gate electrode 406A and is coupled to the first ST gate voltage V GST1 The drive transistor 424 includes a first ST top gate electrode path 425A and a first ST bottom gate electrode path 426A. ... DDT DT drain electrode path 421B, coupled from DT source 418B to DT source voltage V SDT DT source electrode path 420B, coupled from DT top gate electrode 414B to DC voltage V DC The DT top gate electrode path 425B and the DT bottom gate electrode 406B are coupled to the DT gate voltage V GDT The second switch transistor 423 includes a second ST drain 419C coupled to the second ST drain voltage V DST2 The second ST drain electrode path 421C is coupled from the second ST source 418C and the second ST top gate electrode 414C to the second ST source voltage V SST2 The second ST source electrode path 420C and the second ST top gate electrode path 425C are coupled from the second ST bottom gate electrode 406C to the second ST gate voltage V GST2 The second ST bottom gate electrode path 426C.

[0076] The second switch transistor 423 of transistor 400B and transistor 400D includes a physical and electrical connection between a second ST source 418C and a second ST top gate electrode 414C using a second ST source electrode path 420C and a second ST top gate electrode path 425C. In some embodiments, the connection is made via electrical wiring and / or other connection bridges. The connection can be made using contact holes in the active pixel area (e.g., display area 104). A gate bias is applied to the DT bottom gate electrode 406B via the DT bottom gate electrode path 426B.

[0077] The transistors 400B and 400D are connected and coupled to a DC voltage V DC DT top gate electrode 414B, while DT bottom gate electrode 406B is coupled to DT gate voltage V GDT The architecture further includes a first bottom GI layer 408 and a second bottom GI layer 409. This architecture allows the first switch transistor 422, the driver transistor 424, and the second switch transistor 423 to have high mobility and electrical stability. In addition, the architecture allows for smaller subthreshold (SS) values ​​for the first switch transistor 422 and the second switch transistor 423, and a larger SS value for the driver transistor 424 on the same substrate. These qualities result in higher speed / higher frequency operation and better display image quality.

[0078] Figure 5A Depicted is a schematic cross-sectional view of a transistor 500A including a first switch transistor 522 and a drive transistor 524 disposed on the same substrate 502 . Figure 5B Depicted is a schematic cross-sectional view of a transistor 500B including a first switch transistor 522 and a drive transistor 524 disposed on the same substrate 502 . Figure 5C Depicted is a schematic cross-sectional view of a transistor 500C including a first switch transistor 522 and a drive transistor 524 disposed on the same substrate 502 . Figure 5D A schematic cross-sectional view of a transistor 500D is depicted that includes a first switch transistor 522 and a driver transistor 524 disposed on the same substrate 502. In some aspects, each of the driver transistors may be used to Figure 2A The pixel circuit 204a or Figure 2B The driving transistor (T2) in the pixel circuit 204b is shown. In some aspects, each of the switching transistors can be used to Figure 2A The switching transistors (T3, T4) in the pixel circuit 204a shown, or for Figure 2B The switching transistor (T3) in the pixel circuit 204b is shown.

[0079] Transistor 500A and transistor 500B are dual-gate TFTs having a first switching transistor (ST) top gate electrode 514A for a first switching transistor 522, a first switching transistor (ST) bottom gate electrode 506A for the first switching transistor 522, a driving transistor (DT) top gate electrode 514B for a driving transistor 524, and a driving transistor (DT) bottom gate electrode 506B for a driving transistor 524.

[0080] Transistor 500C and transistor 500D are dual-gate TFTs having a first switch transistor (ST) top gate electrode 514A for the first switch transistor 522, a drive transistor (DT) top gate electrode 514B for the drive transistor 524, and a drive transistor (DT) bottom gate electrode 506B for the drive transistor 524.

[0081] Transistors 500A-500D include a substrate 502 (e.g., a silicon base substrate, an insulating base substrate, a germanium base substrate, or other suitable flexible substrate). Substrate 502 may include one or more common layers found in complementary metal oxide semiconductor (CMOS) device structures. Substrate 502 may include a transparent material (e.g., rigid glass or flexible polyimide (PI)), which may be useful if the TFT is used in an LCD or OLED display application (e.g., a television, tablet computer, laptop computer, mobile phone, or other display). A buffer layer 504 is disposed above substrate 502 (e.g., in direct contact with substrate 502). Buffer layer 504 may include an insulating material (e.g., a single silicon dioxide (SiO x ), silicon nitride (SiN x ), multilayer silicon nitride / silicon oxide (SiN x / SiO y ), silicon oxynitride (SiON), other insulating materials, or combinations thereof).

[0082] The DT bottom gate electrode 506B of the drive transistor 524 is disposed over the buffer layer 504. In some aspects, the DT bottom gate electrode 506B corresponds to DG1 of FIG. 2 . In some embodiments, during use in an OLED application, a gate bias is applied to the DT bottom gate electrode 506B. In some aspects, the bottom gate electrode 506B is deposited and patterned using any suitable process known in the art.

[0083] In transistors 500A and 500B, a first switch transistor (ST) bottom gate electrode 506A of a first switch transistor 522 is disposed above the buffer layer 504. In some aspects, the first ST bottom gate electrode 506A corresponds to SG2, SG3, or other switch transistors in the circuit region 210 of Figures 2a and 2b. In some embodiments, during use in OLED applications, a gate bias is applied to the first ST bottom gate electrode 506A. In some aspects, the first ST bottom gate electrode 506A is deposited and patterned using any suitable process known in the art.

[0084] In transistors 500A-500D, a first bottom gate insulating (GI) layer 508 is disposed over and around the top surface and sides of the DT bottom gate electrode 506B. The first bottom GI is disposed over the buffer layer 504. In transistors 500A and 500B, the first bottom GI layer 508 is further disposed over and around the top surface and sides of the first ST bottom gate electrode 506A. The GI material for the first bottom GI layer 508 and / or for any gate insulator described herein may include an insulating material (e.g., silicon, SiN x , other insulating materials, or combinations thereof (e.g., silicon dioxide (SiO2), polymethylsilsesquioxane (PMSQ), or other suitable materials)).

[0085] A first switch transistor (ST) channel structure 510A and a driver transistor (DT) channel structure 510B are disposed above the first bottom GI layer 508. In some embodiments, a single channel structure is deposited above the first bottom GI layer 508 and etched to form the first ST channel structure 510A and the DT channel structure 510B. In other embodiments, the first ST channel structure 510A and the DT channel structure 510B are separately deposited above the first bottom GI layer 508. In transistors 500A and 500B, the first ST channel structure 510A is positioned above the first ST bottom gate electrode 506A in the first switch transistor 522. The DT channel structure 510B is positioned above the DT bottom gate electrode 506B in the driver transistor 524. The first ST channel structure 510A and the DT channel structure 510B can be a single-layer channel structure, a two-layer channel stack (where each layer has a different electron mobility), or three or more layers (where each layer has a different electron mobility than the layer immediately above or below it).

[0086] In some embodiments having a two-layer channel stack, the top layer has a lower mobility than the bottom layer. In some embodiments having three stacked layers, the top layer has a lower mobility than the middle layer, while the middle layer has a higher mobility than the bottom layer. In some embodiments having four stacked layers, the top layer has a lower mobility than the second layer, the second layer has a higher mobility than the third layer, and the third layer has a lower mobility than the bottom layer. Each layer of the multilayer channel structure is about 0.5 nm to about 20 nm. The total thickness of the channel structure is about 5 nm to about 60 nm.

[0087] The first ST channel structure 510A and the DT channel structure 510B are composed of metal oxide materials or low temperature polysilicon (LTPS). Any channel structure described herein may be composed of metal oxide (MO) materials (e.g., single-layer or multi-layer MO channels). Alternatively, any channel structure described herein may be composed of LTPS (e.g., single-layer LTPS channels). Metal oxides may include oxygen (O), indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al), and combinations thereof (e.g., In-Zn-O, In-Ga-O, In-Sn-O, In-Ga-Zn-O, In-Zn-Sn-O, In-Ga-Sn-O, In-Ga-Zn-Sn-O, or any combination thereof). Metal oxide materials or LTPS may be selected based on a predetermined electron mobility selected for one or more layers of the first ST channel structure 510A and the DT channel structure 510B.

[0088] A first switch transistor (ST) top gate insulating (GI) layer 512A is disposed over the first ST channel structure 510A. In some embodiments, the first ST top GI layer 512A is patterned to approximate the width of a first switch transistor (ST) top gate electrode 514A disposed over the first ST top GI layer 512A. A first drive transistor (DT) top gate insulating (GI) layer 512B is disposed over the DT channel structure 510B. A second drive transistor (DT) top gate insulating (GI) layer 513 is disposed over the first DT top GI layer 512B. In some embodiments, the first DT top GI layer 512B and the second DT top GI layer 513 are patterned to approximate the width of a drive transistor (DT) top gate electrode 514B disposed over the first DT top GI layer 512B. Alternatively, as Figure 4C and Figure 4DAs shown, the top GI layer is disposed over and around the top surfaces and sides of the first ST channel structure 510A and the DT channel structure 510B, and over the second bottom GI layer 509. Any other patterning, including a top GI layer having a width greater than that of the top gate electrode, may be used for one or more of the TFTs depicted in any other figures.

[0089] In transistors 500A and 500B, the widths of first ST top gate electrode 514A and DT top gate electrode 514B are less than or equal to the widths of first ST bottom gate electrode 506A and DT bottom gate electrode 506B, respectively. In transistors 500C and 500D, the width of DT top gate electrode 514B is less than or equal to the width of DT bottom gate electrode 506B. The widths of first ST bottom gate electrode 506A and DT bottom gate electrode 506B are adjustable. In some embodiments, the widths of first ST bottom gate electrode 506A and DT bottom gate electrode 506B are approximately 2 μm to approximately 40 μm. The widths of first ST top gate electrode 514A and DT top gate electrode 514B are approximately 1 μm to approximately 30 μm.

[0090] The thickness of the first ST top GI layer 512A is less than the thickness of the first bottom GI layer 508. The combined thickness of the first DT top GI layer 512B and the second DT top GI layer 513 is greater than the thickness of the first bottom GI layer 508. The thickness of each of the first ST top GI layer 512A, the first DT top GI layer 512B, and the second DT top GI layer 513 is approximately 50 nm to approximately 200 nm. The combined thickness of the first DT top GI layer 512B and the second DT top GI layer 513 is approximately 200 nm to approximately 600 nm. The thickness of the first bottom GI layer 508 is approximately 50 nm to approximately 200 nm.

[0091] An interlayer dielectric (ILD) layer 516 is disposed over the first ST top gate electrode 514A, the DT top gate electrode 514B, a portion of the first ST channel structure 510A, and a portion of the DT channel structure 510B. Any ILD layer 516 described herein can be composed of materials such as silicon oxide, nitride, oxynitride, and carbide (e.g., a silicon-based dielectric film).

[0092] The first switch transistor 522 includes a first switch transistor (ST) source 518A and a first switch transistor (ST) drain 519A disposed above the ILD layer 516. The driver transistor 524 includes a driver transistor (DT) source 518B and a driver transistor (DT) drain 519B disposed above the ILD layer 516. The first ST source 518A, the DT source 518B, the first ST drain 519A, and the DT drain 519B are coupled to the first ST channel structure 510A and the DT channel structure 510B, respectively, through vias in the ILD layer 516. Each electrode described herein (e.g., the first ST top gate electrode 514A, the first ST bottom gate electrode 506A, the DT top gate electrode 514B, the DT bottom gate electrode 506B, the first ST source 518A, the DT source 518B, the first ST drain 519A, and the DT drain 519B) includes a conductive material (e.g., molybdenum (Mo), chromium (Cr), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), alloy metals (including MoW), combinations of conductive materials (including MoW, TiCu, MoCu, MoCuMo, TiCuTi, MoWCu, MoWCuMoW), any electrically conductive material (e.g., including conductive metal oxides (e.g., indium tin oxide (InSnO) [ITO] and indium zinc oxide (InZnO) [IZO])), or any combination thereof). One or more of the electrodes can be made of the same conductive material, or each electrode can be made of a different material.

[0093] In some embodiments (e.g., in transistor 500C and transistor 500D), the transistor includes a storage capacitor formation 530. In some aspects, storage capacitor formation 530 corresponds to C1 of Figures 2a and 2b. Storage capacitor formation 530 includes a first capacitor top gate insulating (GI) layer 540, a first capacitor top gate 542, a second capacitor top GI layer 544, and a second capacitor top gate 546. The first capacitor top GI layer 540 is disposed above the first bottom GI layer 508 and positioned between the first switch transistor 522 and the drive transistor 524. In some embodiments, the first capacitor top GI layer 540 is patterned to approximate the width of the first capacitor top gate 542 disposed above the first capacitor top GI layer 540. The second capacitor top GI layer 544 is disposed above the first capacitor top gate 542. In some embodiments, the second capacitor top GI layer 544 is patterned to approximate the width of the second capacitor top gate 546 disposed above the second capacitor top GI layer 544. In one embodiment, the width of the first capacitor top gate 542 is approximately the same as the width of the second capacitor top gate 546. The ILD layer 516 is disposed over and around the sides of the first capacitor top gate insulating (GI) layer 540, the sides of the first capacitor top gate 542, the sides of the second capacitor top GI layer 544, and the top surface and sides of the second capacitor top gate 546. After the switching transistor ST1 is turned "off," the storage capacitor 530 stores the voltage on the Vdata line.

[0094] In each of the figures, each electrode of transistors 500A-500D includes an electrode path, wherein the current path of each electrode is depicted. In transistors 500A and 500C, the first switch transistor 522 includes a first ST drain 519A coupled to a first ST drain voltage V DST The first ST drain electrode path 521A is coupled from the first ST source 518A to the first ST source voltage V SST The first ST source electrode path 520A is connected from the first ST top gate electrode 514A and the first ST bottom gate electrode 506A and is coupled to the first ST gate voltage V GST The drive transistor 524 includes a first ST top gate electrode path 525A and a first ST bottom gate electrode path 526A. ... DDTThe DT drain electrode path 521B is connected from the DT source 518B and the DT bottom gate electrode 506B and is coupled to the DT source voltage V SDT The DT source electrode path 520B and the DT bottom gate electrode path 526B are coupled from the DT top gate electrode 514B to the DT gate voltage V GDT DT top gate electrode path 525B.

[0095] The driver transistor 524 of transistor 500A and transistor 500C includes a physical and electrical connection between the DT source 318B and the DT bottom gate electrode 506B using a DT source electrode path 520B and a DT bottom gate electrode path 526B. The first switch transistor 522 of transistor 500A and transistor 500C includes a physical and electrical connection between the first ST bottom gate electrode 506A and the first ST top gate electrode 514A using an ST top gate electrode path 525A and a first ST bottom gate electrode path 526A. In some embodiments, the connection is made via electrical wiring and / or other connection bridges. The connection can be made using contact holes in the active pixel area (e.g., display area 104). A gate bias is applied to the DT top gate electrode 514B via the DT top gate electrode path 525B.

[0096] The transistors 500A and 500C are structured to have a voltage connected to the DT source V SDT The DT bottom gate electrode 506B and the DT source 518B are coupled to the DT gate voltage V GDT This architecture allows the first switch transistor 522, the driver transistor 524, and the second switch transistor 523 to have high mobility and electrical stability. Furthermore, the architecture allows for smaller subthreshold (SS) values ​​for the first and second switch transistors 522 and 523, and a larger SS value for the driver transistor 524 on the same substrate. These qualities result in higher speed / higher frequency operation and better display image quality.

[0097] In transistors 500B and 500D, the first switch transistor 522 includes a first ST drain 519A coupled to a first ST drain voltage V DST The first ST drain electrode path 521A is coupled from the first ST source 518A to the first ST source voltage V SST The first ST source electrode path 520A is connected from the first ST top gate electrode 514A and the first ST bottom gate electrode 506A and is coupled to the first ST gate voltage V GSTThe drive transistor 524 includes a first ST top gate electrode path 525A and a first ST bottom gate electrode path 526A. ... DDT DT drain electrode path 521B, coupled from DT source 518B to DT source voltage V SDT DT source electrode path 520B, coupled from DT top gate electrode 514B to DT gate voltage V GDT The DT top gate electrode path 525B and the DT bottom gate electrode 506B are coupled to the DC voltage V DC DT bottom gate electrode path 526B. Transistor 500B and first switch transistor 522 of transistor 500D include physical and electrical connections between first ST bottom gate electrode 506A and first ST top gate electrode 514A using ST top gate electrode path 525A and first ST bottom gate electrode path 526A. In some embodiments, the connection is made via electrical wiring and / or other connection bridges. Contact holes in the active pixel area (e.g., display area 104) can be used for the connection. A gate bias is applied to DT top gate electrode 514B via DT top gate electrode path 525B.

[0098] The transistors 500B and 500D are structured to be coupled to a DC voltage V DC The DT bottom gate electrode 506B having the first DT top GI layer 512B and the second DT top GI layer 513 is coupled to the DT gate voltage V GDT This architecture further removes the first ST bottom gate electrode 506B. This architecture allows the first switch transistor 522, the driver transistor 524, and the second switch transistor 523 to have high mobility and electrical stability. In addition, this architecture allows for smaller subthreshold (SS) values ​​for the first switch transistor 522 and the second switch transistor 523, as well as a larger SS value for the driver transistor 524 on the same substrate. These qualities result in higher speed / higher frequency operation and better display image quality.

[0099] Figure 6A Depicted is a schematic cross-sectional view of a transistor 600A including a first switching transistor 622 , a driving transistor 624 , and a second switching transistor 623 disposed on the same substrate 602 . Figure 6B A schematic cross-sectional view of a transistor 600B is depicted including a first switch transistor 622, a driver transistor 624, and a second switch transistor 623 disposed on the same substrate 602. In some aspects, the driver transistor may be used to Figure 2A The pixel circuit 204a or Figure 2BThe driving transistor (T2) in the pixel circuit 204b is shown. In some aspects, each of the switching transistors can be used to Figure 2A The switching transistors (T3, T4) in the pixel circuit 204a shown, or for Figure 2B The switching transistor (T3) in the pixel circuit 204b is shown.

[0100] Transistor 600A and transistor 600B are tri-gate TFTs having a first switch transistor (ST) top gate electrode 614A for a first switch transistor 622, a first switch transistor (ST) bottom gate electrode 606A for the first switch transistor 622, a driver transistor (DT) top gate electrode 614B for a driver transistor 624, a driver transistor (DT) bottom gate electrode 606B for the driver transistor 624, and a second switch transistor (ST) top gate electrode 614C for a second switch transistor 623. Transistor 600A and transistor 600B include a substrate 602 (e.g., a silicon base substrate, an insulating base substrate, a germanium base substrate, or other suitable flexible substrate). Substrate 602 may include one or more common layers found in complementary metal oxide semiconductor (CMOS) device structures. Substrate 602 may include a transparent material (e.g., rigid glass or flexible polyimide (PI)), which may be useful if the TFT is used in LCD or OLED display applications (e.g., televisions, tablet computers, laptop computers, mobile phones, or other displays). The buffer layer 604 is disposed above the substrate 602 (eg, in direct contact with the substrate 602). The buffer layer 604 may include an insulating material (eg, a single layer of silicon dioxide (SiO x ), silicon nitride (SiN x ), multilayer silicon nitride / silicon oxide (SiN x / SiO y ), silicon oxynitride (SiON), other insulating materials, or combinations thereof). The DT bottom gate electrode 606B of the drive transistor 624 is disposed above the buffer layer 604. In some aspects, the DT bottom gate electrode 606B corresponds to DG1 of FIG. 2 . In some embodiments, during use in OLED applications, a gate bias is applied to the DT top gate electrode 614B. In some aspects, the bottom gate electrode 606B is deposited and patterned using any suitable process known in the art.

[0101] A first switch transistor (ST) bottom gate electrode 606A of the first switch transistor 622 is disposed above the buffer layer 604. In some aspects, the first ST bottom gate electrode 606A corresponds to SG1, SG2, SG3, or other switch transistors in the circuit region 210 of Figures 2a and 2b. In some embodiments, during use in an OLED application, a gate bias is applied to the first ST bottom gate electrode 606A. In some aspects, the first ST bottom gate electrode 606A is deposited and patterned using any suitable process known in the art.

[0102] A first bottom gate insulating (GI) layer 608 is disposed over and around the top surface and sides of the first ST bottom gate electrode 606A and the top surface and sides of the DT bottom gate electrode 606B. The GI material for the first bottom GI layer 608 and / or for any gate insulator described herein may include an insulating material (e.g., silicon, SiN x , other insulating materials, or combinations thereof (e.g., silicon dioxide (SiO2), polymethylsilsesquioxane (PMSQ), or other suitable materials)).

[0103] A first switch transistor (ST) channel structure 610A, a driver transistor (DT) channel structure 610B, and a second switch transistor (ST) channel structure 610C are disposed above the first bottom GI layer 608. In some embodiments, a single channel structure is deposited above the first bottom GI layer 608 and etched to form the first ST channel structure 610A, the DT channel structure 610B, and the second ST channel structure 610C. In other embodiments, the first ST channel structure 610A, the DT channel structure 610B, and the second ST channel structure 610C are separately deposited above the first bottom GI layer 608. The first ST channel structure 610A is positioned above the first ST bottom gate electrode 606A in the first switch transistor 622, the DT channel structure 610B is positioned above the DT bottom gate electrode 606B in the driver transistor 624, and the second ST channel structure 610C is positioned in the second switch transistor 623. The first ST channel structure 610A, the DT channel structure 610B, and the second ST channel structure 610C can be a single-layer channel structure, a double-layer channel stack (in which each layer has a different electron mobility), or three or more layers (each layer has an electron mobility different from the layer directly above or below the layer).

[0104] In some embodiments having a two-layer channel stack, the top layer has a lower mobility than the bottom layer. In some embodiments having three stacked layers, the top layer has a lower mobility than the middle layer, while the middle layer has a higher mobility than the bottom layer. In some embodiments having four stacked layers, the top layer has a lower mobility than the second layer, the second layer has a higher mobility than the third layer, and the third layer has a lower mobility than the bottom layer. Each layer of the multilayer channel structure is about 0.5 nm to about 20 nm. The total thickness of the channel structure is about 5 nm to about 60 nm.

[0105] The first ST channel structure 610A, the DT channel structure 610B, and the second ST channel structure 610C are composed of metal oxide materials or low temperature polysilicon (LTPS). Any channel structure described herein can be composed of metal oxide (MO) materials (e.g., single-layer or multi-layer MO channels). Alternatively, any channel structure described herein can be composed of LTPS (e.g., single-layer LTPS channels). Metal oxides can include oxygen (O), indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al), and combinations thereof (e.g., In-Zn-O, In-Ga-O, In-Sn-O, In-Ga-Zn-O, In-Zn-Sn-O, In-Ga-Sn-O, In-Ga-Zn-Sn-O, or any combination thereof). Metal oxide materials or LTPS can be selected based on a predetermined electron mobility selected for one or more layers of the first ST channel structure 610A, the DT channel structure 610B, and the second ST channel structure 610C.

[0106] In transistors 600A and 600B, a first switch transistor (ST) top gate insulating (GI) layer 612A is disposed over a first ST channel structure 610A. In some embodiments, the first ST top GI layer 612A is patterned to approximate the width of a first switch transistor (ST) top gate electrode 614A disposed over the first ST top GI layer 612A. A first drive transistor (DT) top gate insulating (GI) layer 612B is disposed over the DT channel structure 610B. A second drive transistor (DT) top gate insulating (GI) layer 613 is disposed over the first DT top GI layer 612B. In some embodiments, the first and second DT top GI layers 612B, 613 are patterned to approximate the width of a drive transistor (DT) top gate electrode 614B disposed over the first DT top GI layer 612B. A second switch transistor (ST) top gate insulating (GI) layer 612C is disposed over the second ST channel structure 610C. In some embodiments, the second ST top GI layer 612C is patterned to approximate the width of the second switch transistor (ST) top gate electrode 614C disposed above the second ST top GI layer 612C. Figure 4C and Figure 4D As shown, the top GI layer is disposed over and around the top surface and sides of the first ST channel structure 610A and the top surface and sides of the DT channel structure 610B, and over the first bottom GI layer 608. Any other patterning, including a top GI layer having a width greater than that of the top gate electrode, may be used for one or more of the TFTs depicted in any of the other figures.

[0107] The widths of the first ST top gate electrode 614A, the DT top gate electrode 614B, and the second ST top gate electrode 614C are less than or equal to the widths of the first ST bottom gate electrode 606A, the DT bottom gate electrode 606B, and the second ST bottom gate electrode 606B, respectively. The widths of the first ST bottom gate electrode 606A, the DT bottom gate electrode 606B, and the second ST bottom gate electrode 606C are adjustable. In some embodiments, the widths of the first ST bottom gate electrode 606A, the DT bottom gate electrode 606B, and the second ST bottom gate electrode 606C are approximately 2 μm to approximately 40 μm. The widths of the first ST bottom gate electrode 606A, the DT bottom gate electrode 606B, and the second ST bottom gate electrode 606C are approximately 1 μm to approximately 30 μm.

[0108] The thickness of the first ST top GI layer 612A and the second ST top GI layer 612C is greater than the thickness of the first bottom GI layer 608. The combined thickness of the first DT top GI layer 612B and the second DT top GI layer 613 is greater than the thickness of the first bottom GI layer 608. The thickness of each of the first ST top GI layer 612A, the first DT top GI layer 512B, the second ST top GI layer 614C, and the DT top GI layer 612B is approximately 200 nm to approximately 600 nm. The thickness of the first bottom GI layer 608 is approximately 50 nm to approximately 200 nm.

[0109] An interlayer dielectric (ILD) layer 616 is disposed over the first ST top gate electrode 614A, the DT top gate electrode 614B, the second ST top gate electrode 614C, a portion of the first ST channel structure 610A, a portion of the DT channel structure 610B, and a portion of the second ST channel structure 610C. Any of the ILD layers described herein can be composed of materials such as silicon oxide, nitride, oxynitride, and carbide (e.g., a silicon-based dielectric film).

[0110] The first switch transistor 622 includes a first switch transistor (ST) source 618A and a first switch transistor (ST) drain 619A disposed above the ILD layer 616. The driver transistor 624 includes a driver transistor (DT) source 618B and a driver transistor (DT) drain 619B disposed above the ILD layer 616. The second switch transistor 623 includes a second switch transistor (ST) source 618C and a second switch transistor (ST) drain 619C disposed above the ILD layer 616. The first ST source 618A, the DT source 68B, the second ST source 618C, the first ST drain 619A, the DT drain 619B, and the second ST drain 619C are coupled to the first ST channel structure 610A, the DT channel structure 610B, and the second ST channel structure 610C, respectively, through vias in the ILD layer 616. Each electrode described herein (e.g., the first ST top gate electrode 614A, the first ST bottom gate electrode 606A, the DT top gate electrode 614B, the DT bottom gate electrode 606B, the second ST top gate electrode 614C, the second ST bottom gate electrode 606C, the first ST source 618A, the DT source 618B, the second ST source 618C, the first ST drain 619A, the DT drain 619B, and the second ST drain 619C) includes a conductive material (e.g., molybdenum (Mo), chromium (Cr), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), alloy metals (including MoW), combinations of conductive materials (including MoW, TiCu, MoCu, MoCuMo, TiCuTi, MoWCu, MoWCuMoW), any electrically conductive material (e.g., including conductive metal oxides (e.g., indium tin oxide (InSnO) [ITO] and indium zinc oxide (InZnO) [IZO])), or any combination thereof). One or more of the electrodes may be made of the same conductive material, or each electrode may be made of a different material.

[0111] In some embodiments, as shown in transistors 600A and 600B, the transistor includes a storage capacitor formation 630. In some aspects, storage capacitor formation 630 corresponds to C1 in Figures 2a and 2b. Storage capacitor formation 630 includes a first capacitor top gate insulating (GI) layer 640, a first capacitor top gate 642, a second capacitor top GI layer 644, and a second capacitor top gate 646. First capacitor top GI layer 640 is disposed above first bottom GI layer 608 and positioned between first switch transistor 622 and drive transistor 624. In some embodiments, first capacitor top GI layer 640 is patterned to approximate the width of first capacitor top gate 642 disposed above first capacitor top GI layer 640. Second capacitor top GI layer 644 is disposed above first capacitor top gate 642. In some embodiments, second capacitor top GI layer 644 is patterned to approximate the width of second capacitor top gate 646 disposed above second capacitor top GI layer 644. In one embodiment, the width of first capacitor top gate 642 is approximately the same as the width of second capacitor top gate 646. The ILD layer 616 is disposed above and around the sides of the first capacitor top gate insulating (GI) layer 640, the sides of the first capacitor top gate 642, the sides of the second capacitor top GI layer 644, and the top surface and sides of the second capacitor top gate 646. After the switching transistor ST1 is turned "off," the storage capacitor 630 stores the voltage on the Vdata line. In an alternative embodiment, the storage capacitor 630 is positioned between the drive transistor 624 and the second switching transistor 623.

[0112] In each of the figures, each electrode of transistor 600A and transistor 600B includes an electrode path, wherein the current path of each electrode is depicted. In transistor 600A, the first switch transistor 622 includes a first ST drain 619A coupled to the first ST drain voltage V DST1 The first ST drain electrode path 621A is coupled from the first ST source 618A to the first ST source voltage V SST1 The first ST source electrode path 620A is connected from the first ST top gate electrode 614A and the first ST bottom gate electrode 606A and is coupled to the first ST gate voltage V GST1 The drive transistor 624 includes a first ST top gate electrode path 625A and a first ST bottom gate electrode path 626A. ... DDTThe DT drain electrode path 621B is connected from the DT source 618B and the DT bottom gate electrode 606B and is coupled to the DT source voltage V SDT The DT source electrode path 620B and the DT bottom gate electrode path 626B are coupled from the DT top gate electrode 614B to the DT gate voltage V GDT The second switch transistor 623 includes a second ST drain 619C coupled to the second ST drain voltage V DST2 The second ST drain electrode path 621C is coupled from the second ST source 618C to the second ST source voltage V SST2 The second ST source electrode path 620C and the second ST top gate electrode 614C are coupled to the second ST gate voltage V GST2 The second ST top gate electrode path 625C.

[0113] The driver transistor 624 of transistor 600B includes a physical and electrical connection between the DT source 618B and the DT bottom gate electrode 606B using a DT source electrode path 620B and a DT bottom gate electrode path 626B. The first switch transistor 622 of transistor 600A includes a physical and electrical connection between the first ST bottom gate electrode 606A and the first ST top gate electrode 614A using a first ST top gate electrode path 625A and a DT bottom gate electrode path 626A. In some embodiments, the connection is made via electrical wiring and / or other connection bridges. The connection can be made using contact holes in the active pixel area (e.g., display area 104). A gate bias is applied to the DT top gate electrode 614B via the DT top gate electrode path 625B.

[0114] The transistor 600A has a structure connected and coupled to the DT source voltage V SDT DT bottom gate electrode 606B and DT source 618B, while DT top gate electrode 614B having first DT top GI layer 612B and second DT top GI layer 613 is coupled to DT gate voltage V GDT This architecture allows the first switch transistor 622, the driver transistor 624, and the second switch transistor 623 to have high mobility and electrical stability. Furthermore, this architecture allows for smaller subthreshold (SS) values ​​for the first switch transistor 622 and the second switch transistor 623, and a larger SS value for the driver transistor 624 on the same substrate. These qualities result in higher speed / higher frequency operation and better display image quality.

[0115] In transistor 600B, the first switch transistor 622 includes a first ST drain 619A coupled to a first ST drain voltage V DST1The first ST drain electrode path 621A is coupled from the first ST source 618A to the first ST source voltage V SST1 The first ST source electrode path 620A is connected from the first ST top gate electrode 614A and the first ST bottom gate electrode 606A and is coupled to the first ST gate voltage V GST1 The drive transistor 624 includes a first ST top gate electrode path 625A and a first ST bottom gate electrode path 626A. ... DDT DT drain electrode path 621B, coupled from DT source 618B to DT source voltage V SDT DT source electrode path 620B, coupled from DT top gate electrode 614B to DT gate voltage V GDT The DT top gate electrode path 625B and the DT bottom gate electrode 606B are coupled to the DC voltage V DC The second switch transistor 623 includes a DT bottom gate electrode path 626B coupled from the second ST drain 619C to the second ST drain voltage V DST2 The second ST drain electrode path 621C is coupled from the second ST source 618C to the second ST source voltage V SST2 The second ST source electrode path 620C and the second ST top gate electrode 614C are coupled to the second ST gate voltage V GST2 The second ST top gate electrode path 625C.

[0116] The driver transistor 624 of transistor 600B includes a physical and electrical connection between the DT source 618B and the DT bottom gate electrode 606B using a DT source electrode path 620B and a DT bottom gate electrode path 626B. The first switch transistor 622 of transistor 600A includes a physical and electrical connection between the first ST bottom gate electrode 606A and the first ST top gate electrode 614A using a first ST top gate electrode path 625A and an ST bottom gate electrode path 626A. In some embodiments, the connection is made via electrical wiring and / or other connection bridges. The connection can be made using contact holes in the active pixel area (e.g., display area 104). A gate bias is applied to the DT top gate electrode 614B via the DT top gate electrode path 625B.

[0117] The transistor 600B is connected to and coupled to a DC voltage V DC DT bottom gate electrode 606B, and DT top gate electrode 614B having first DT top GI layer 612B and second DT top GI layer 613 is coupled to DT gate voltage V GDTThis architecture allows the first switch transistor 622, the driver transistor 624, and the second switch transistor 623 to have high mobility and electrical stability. Furthermore, this architecture allows for smaller subthreshold (SS) values ​​for the first switch transistor 622 and the second switch transistor 623, and a larger SS value for the driver transistor 624 on the same substrate. These qualities result in higher speed / higher frequency operation and better display image quality.

[0118] In summary, the transistors provided herein provide high mobility and electrical stability for both switching transistors and drive transistors. Smaller threshold slope (SS) values ​​for switching transistors and higher SS values ​​for drive transistors on the same substrate allow for higher speed / higher frequency operation and better display image quality.

[0119] These and other advantages can be achieved according to the specific embodiments described and other variations. It should be understood that the above description is intended to be illustrative and not restrictive. After reading the above description, those skilled in the art will understand many other embodiments and modifications within the spirit and scope of the claims. Therefore, the scope of the present disclosure should be determined with reference to the appended claims and the full scope of equivalents to which these claims are assigned. In the following claims, the terms "first," "second," and "third," etc. are used merely as labels and are not intended to impose numerical requirements on their objects.

[0120] As used herein, the term "about" refers to a + / - 10% variation from the nominal value. It is understood that such variations can be included in any value provided herein.

Claims

1. A device, comprising: substrate; buffer layer; a first bottom gate insulating (GI) layer disposed above the buffer layer; A driving transistor is disposed above the substrate, and the driving transistor includes: a drive transistor (DT) bottom gate electrode disposed over the buffer layer, wherein the first bottom GI layer is disposed over and around the DT bottom gate electrode; a driving transistor (DT) channel structure disposed above the first bottom GI layer; a first drive transistor (DT) top gate insulation (GI) layer disposed above the DT channel structure; a driving transistor (DT) top gate electrode disposed above the DT top GI layer; Driver transistor (DT) drain; a driver transistor (DT) source; and A first switch transistor is disposed above the substrate, and the first switch transistor includes: a first switch transistor (ST) channel structure disposed above the first bottom GI layer; a first switch transistor (ST) top gate insulation (GI) layer disposed above the first ST channel structure; a first switch transistor (ST) top gate electrode disposed above the first ST top GI layer and electrically coupled to a first switch transistor (ST) gate voltage; a drain of a first switching transistor (ST); and The source of the first switching transistor (ST).

2. The apparatus of claim 1 , further comprising: a second drive transistor (DT) top gate insulation (GI) layer disposed between the DT top gate electrode and the first DT top GI layer, wherein the DT top gate is electrically coupled to a drive transistor (DT) gate voltage, and the DT bottom gate electrode is electrically connected to the DT source, and the DT bottom gate electrode and the DT source are electrically coupled to a drive transistor (DT) source voltage.

3. The apparatus of claim 1 , further comprising: A second drive transistor (DT) top gate insulating (GI) layer is disposed between the DT top gate electrode and the first DT top GI layer, wherein the DT top gate is electrically coupled to a drive transistor (DT) gate voltage and the DT bottom gate electrode is electrically coupled to a DC voltage.

4. The apparatus of claim 1 , further comprising: a second drive transistor (DT) top gate insulation (GI) layer disposed between the DT top gate electrode and the first DT top GI layer, wherein the DT top gate is electrically coupled to a drive transistor (DT) gate voltage, and the DT bottom gate electrode is electrically connected to the DT source, and the DT bottom gate electrode and the DT source are electrically coupled to a drive transistor (DT) source voltage; as well as A first switch transistor (ST) bottom gate electrode is disposed above the buffer layer, wherein the first ST bottom gate electrode is electrically connected to the first ST top gate electrode and is electrically coupled to the first ST gate voltage.

5. The apparatus of claim 1 , further comprising: a second drive transistor (DT) top gate insulation (GI) layer disposed between the DT top gate electrode and the first DT top GI layer, wherein the DT top gate is electrically coupled to a drive transistor (DT) gate voltage and the DT bottom gate electrode is electrically coupled to a DC voltage; as well as A first switch transistor (ST) bottom gate electrode is disposed above the buffer layer, wherein the first ST bottom gate electrode is electrically connected to the first ST top gate electrode and is electrically coupled to the first ST gate voltage.

6. The apparatus of claim 1 , further comprising: a first switch transistor (ST) bottom gate electrode disposed above the first bottom GI layer, wherein the first ST bottom gate electrode is electrically connected to the first ST top gate electrode and electrically coupled to the first ST gate voltage; as well as a second bottom gate insulating (GI) layer disposed on the first bottom GI layer, disposed above the first ST bottom gate electrode, and surrounding the first ST bottom gate electrode; as well as wherein the DT top gate electrode is electrically connected to the DT source, and the DT top gate electrode and the DT source are electrically coupled to a drive transistor (DT) source voltage, and the DT bottom gate electrode is electrically coupled to a drive transistor (DT) gate voltage.

7. The apparatus of claim 6, further comprising: a storage capacitor, disposed between the first switching transistor and the driving transistor, the storage capacitor comprising: a bottom gate of a first capacitor; a second capacitor bottom gate; and Capacitor channel structure.

8. The apparatus of claim 1 , further comprising: a first switch transistor (ST) bottom gate electrode disposed above the first bottom GI layer, wherein the first ST bottom gate electrode is electrically connected to the first ST top gate electrode and electrically coupled to the first ST gate voltage; as well as a second bottom gate insulating (GI) layer disposed on the first bottom GI layer, disposed above the first ST bottom gate electrode, and surrounding the first ST bottom gate electrode; as well as The DT top gate electrode is electrically coupled to a DC voltage, and the DT bottom gate electrode is electrically coupled to a drive transistor (DT) gate voltage.

9. The apparatus of claim 8, further comprising: A storage capacitor is formed and disposed between the first switching transistor and the driving transistor, wherein the storage capacitor formation includes: a first capacitor located between a bottom gate of the first capacitor and a bottom gate of the second capacitor; and The second capacitor is located between the bottom gate of the second capacitor and the capacitor channel structure.

10. The apparatus of claim 1, wherein: The buffer layer includes single silicon dioxide (SiOx), silicon nitride (SiNx), multi-layer silicon nitride / silicon oxide (SiNx / SiOy), silicon oxynitride (SiON), or a combination thereof; The first bottom GI layer comprises silicon, SiNx, silicon oxide (SiOx), polymethylsilsesquioxane (PMSQ), or a combination thereof; The DT channel structure and the first ST channel structure include oxygen (O), indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al), In-Zn-O, In-Ga-O, In-Sn-O, In-Ga-Zn-O, In-Zn-Sn-O, In-Ga-Sn-O, In-Ga-Zn-Sn-O, or a combination thereof; as well as The first ST top gate electrode, the first ST bottom gate electrode, the DT top gate electrode, the DT bottom gate electrode, the first ST source, the first ST drain, the DT source and the DT drain include molybdenum (Mo), chromium (Cr), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), alloy metals including MoW, MoW, TiCu, MoCu, MoCuMo, TiCuTi, MoWCu, MoWCuMoW, indium tin oxide (InSnO), indium zinc oxide (InZnO), or any combination thereof. 11 . The device of claim 1 , wherein the first bottom GI layer is disposed over and surrounds a top surface and side edges of the DT bottom gate electrode.

12. A device comprising: substrate; buffer layer; a first bottom gate insulating (GI) layer disposed above the buffer layer; A driving transistor is disposed above the substrate, and the driving transistor includes: a drive transistor (DT) bottom gate electrode disposed over the buffer layer, wherein the first bottom GI layer is disposed over and around the DT bottom gate electrode; a driving transistor (DT) channel structure disposed above the first bottom GI layer; a first drive transistor (DT) top gate insulation (GI) layer disposed above the DT channel structure; a driving transistor (DT) top gate electrode disposed above the DT top GI layer; Driver transistor (DT) drain; a driver transistor (DT) source; and A first switch transistor is disposed above the substrate, and the first switch transistor includes: a bottom gate electrode of a first switch transistor (ST), disposed above the buffer layer; a first switch transistor (ST) channel structure disposed above the first bottom GI layer; a first switch transistor (ST) top gate insulation (GI) layer disposed above the first ST channel structure; a first switch transistor (ST) top gate electrode disposed above the first ST top GI layer and electrically coupled to a first switch transistor (ST) gate voltage; a drain of a first switching transistor (ST); and a source of a first switching transistor (ST); A second switch transistor is disposed above the substrate, and the second switch transistor includes: a second switch transistor (ST) channel structure disposed above the bottom GI layer; a second switch transistor (ST) top gate insulation (GI) layer disposed above the second ST channel structure; a second switch transistor (ST) top gate electrode disposed above the second ST top GI layer and electrically coupled to a second switch transistor (ST) gate voltage; a drain of a second switching transistor (ST); and The source of the second switching transistor (ST).

13. The apparatus of claim 12, further comprising: a second drive transistor (DT) top gate insulation (GI) layer disposed between the DT top gate electrode and the first DT top GI layer, wherein the DT top gate is electrically coupled to a drive transistor (DT) gate voltage, and the DT bottom gate electrode is electrically connected to the DT source, and the DT bottom gate electrode and the DT source are electrically coupled to a drive transistor (DT) source voltage.

14. The apparatus of claim 12, further comprising: A second drive transistor (DT) top gate insulating (GI) layer is disposed between the DT top gate electrode and the first DT top GI layer, wherein the DT top gate is electrically coupled to a drive transistor (DT) gate voltage and the DT bottom gate electrode is electrically coupled to a DC voltage.

15. The apparatus of claim 14, further comprising: a storage capacitor, disposed between the first switching transistor and the second switching transistor, the storage capacitor comprising: a gate insulating (GI) layer on top of the first capacitor; a first capacitor top gate; a second capacitor top GI layer; and The second capacitor has a top gate.

16. The apparatus of claim 12, further comprising: a second switch transistor (ST) bottom gate electrode disposed above the first bottom GI layer, wherein the second ST bottom gate electrode is electrically coupled to the second ST gate voltage; as well as a second bottom gate insulating (GI) layer disposed on the first bottom GI layer and over and surrounding the first ST bottom gate electrode and the second ST bottom gate electrode, wherein the first ST bottom gate electrode is electrically connected to the first ST top gate electrode and is electrically coupled to the first ST gate voltage; as well as wherein the DT top gate electrode is electrically connected to the DT source, and the DT top gate electrode and the DT source are electrically coupled to a drive transistor (DT) source voltage, and the DT bottom gate electrode is electrically coupled to a drive transistor (DT) gate voltage.

17. The device of claim 16, wherein the first ST top GI layer, the DT top GI layer, and the second ST top GI layer form a single top GI layer disposed above and surrounding the first ST channel structure, the DT channel structure, and the second ST channel structure.

18. The apparatus of claim 12, further comprising: a second switch transistor (ST) bottom gate electrode disposed above the first bottom GI layer, wherein the second ST bottom gate electrode is electrically coupled to the second ST gate voltage; as well as a second bottom gate insulating (GI) layer disposed on the first bottom GI layer and over and surrounding the first ST bottom gate electrode and the second ST bottom gate electrode, wherein the first ST bottom gate electrode is electrically connected to the first ST top gate electrode and is electrically coupled to the first ST gate voltage; and The DT top gate electrode is electrically coupled to a DC voltage, and the DT bottom gate electrode is electrically coupled to a drive transistor (DT) gate voltage.

19. The device of claim 12, wherein the first ST top GI layer, the DT top GI layer, and the second ST top GI layer form a single top GI layer disposed above and surrounding the first ST channel structure, the DT channel structure, and the second ST channel structure.

20. The apparatus of claim 19, further comprising: a storage capacitor, disposed between the first switching transistor and the driving transistor, the storage capacitor comprising: a bottom gate of a first capacitor; a second capacitor bottom gate; and Capacitor channel structure.

21. The apparatus of claim 12, wherein: The buffer layer includes single silicon dioxide (SiOx), silicon nitride (SiNx), multi-layer silicon nitride / silicon oxide (SiNx / SiOy), silicon oxynitride (SiON), or a combination thereof; The first bottom GI layer comprises silicon, SiNx, silicon oxide (SiOx), polymethylsilsesquioxane (PMSQ), or a combination thereof; The DT channel structure and the first ST channel structure include oxygen (O), indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al), In-Zn-O, In-Ga-O, In-Sn-O, In-Ga-Zn-O, In-Zn-Sn-O, In-Ga-Sn-O, In-Ga-Zn-Sn-O, or a combination thereof; as well as The first ST top gate electrode, the first ST bottom gate electrode, the second ST top gate electrode, the second ST bottom gate electrode, the DT top gate electrode, the DT bottom gate electrode, the first ST source, the first ST drain, the second ST source, the second ST drain, the DT source and the DT drain include molybdenum (Mo), chromium (Cr), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), alloy metals including MoW, MoW, TiCu, MoCu, MoCuMo, TiCuTi, MoWCu, MoWCuMoW, indium tin oxide (InSnO), indium zinc oxide (InZnO), or any combination thereof. 22 . The device of claim 12 , wherein the first bottom GI layer is disposed over and around a top surface and side edges of the DT bottom gate electrode.

23. A device comprising: substrate; buffer layer; a first bottom gate insulating (GI) layer disposed above the buffer layer; a second bottom gate insulating (GI) layer disposed above the first bottom GI layer; A driving transistor is disposed above the substrate, and the driving transistor includes: a drive transistor (DT) bottom gate electrode disposed over the buffer layer, wherein the first bottom GI layer is disposed over and around the DT bottom gate electrode; a driving transistor (DT) channel structure disposed above the second bottom GI layer; a first drive transistor (DT) top gate insulation (GI) layer disposed above the DT channel structure; a driving transistor (DT) top gate electrode disposed above the DT top GI layer; Driver transistor (DT) drain; a driver transistor (DT) source; and wherein the DT top gate electrode is electrically connected to the DT source, and the DT top gate electrode and the DT source are electrically coupled to a drive transistor (DT) source voltage, and the DT bottom gate electrode is electrically coupled to a drive transistor (DT) gate voltage; A first switch transistor is disposed above the substrate, and the first switch transistor includes: a first switch transistor (ST) bottom gate electrode disposed over the first bottom GI layer, wherein the second bottom GI layer is disposed over and around the first ST bottom gate electrode; a first switch transistor (ST) channel structure disposed above the second bottom GI layer; a first switch transistor (ST) top gate insulation (GI) layer disposed above the first ST channel structure; a first switch transistor (ST) top gate electrode disposed above the first ST top GI layer; a drain of a first switching transistor (ST); a source of a first switching transistor (ST); and the first ST bottom gate electrode being electrically connected to the first ST top gate electrode, wherein the first ST top gate electrode and the first ST bottom gate electrode are electrically coupled to a first switching transistor (ST) gate voltage; and A second switch transistor is disposed above the substrate, and the second switch transistor includes: a second switch transistor (ST) bottom gate electrode disposed over the first bottom GI layer, wherein the second bottom GI layer is disposed over and around the second ST bottom gate electrode; a second switch transistor (ST) channel structure disposed above the second bottom GI layer; a second switch transistor (ST) top gate insulation (GI) layer disposed above the second ST channel structure; a second switch transistor (ST) top gate electrode disposed above the second ST top GI layer; a drain of a second switching transistor (ST); a source of a second switching transistor (ST); and The second ST top gate electrode is electrically connected to the second ST source, wherein the second ST source and the second ST top gate electrode are electrically coupled to a second switching transistor (ST) source voltage, and the second ST bottom gate electrode is electrically coupled to a second ST gate voltage.

24. The apparatus of claim 23, further comprising: a storage capacitor, disposed between the first switching transistor and the driving transistor, the storage capacitor comprising: a bottom gate of a first capacitor; a second capacitor bottom gate; and Capacitor channel structure.

25. The apparatus of claim 23, wherein: The buffer layer includes single silicon dioxide (SiOx), silicon nitride (SiNx), multi-layer silicon nitride / silicon oxide (SiNx / SiOy), silicon oxynitride (SiON), or a combination thereof; The first bottom GI layer and the second bottom GI layer include silicon, SiNx, silicon oxide (SiOx), polymethylsilsesquioxane (PMSQ), or a combination thereof; The DT channel structure and the first ST channel structure include oxygen (O), indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al), In-Zn-O, In-Ga-O, In-Sn-O, In-Ga-Zn-O, In-Zn-Sn-O, In-Ga-Sn-O, In-Ga-Zn-Sn-O, or a combination thereof; as well as The first ST top gate electrode, the first ST bottom gate electrode, the second ST top gate electrode, the second ST bottom gate electrode, the DT top gate electrode, the DT bottom gate electrode, the first ST source, the first ST drain, the second ST source, the second ST drain, the DT source and the DT drain include molybdenum (Mo), chromium (Cr), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), alloy metals including MoW, MoW, TiCu, MoCu, MoCuMo, TiCuTi, MoWCu, MoWCuMoW, indium tin oxide (InSnO), indium zinc oxide (InZnO), or any combination thereof.

26. The apparatus of claim 23, wherein: The first bottom GI layer is disposed over and around a top surface and side edges of the DT bottom gate electrode; as well as The second bottom GI layer is disposed over and around a top surface and side edges of the second ST bottom gate electrode.

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