Display device

Abstract

Disclosed in one embodiment of the present invention is a display device including: a first transistor including a first gate electrode and a first semiconductor layer; a second transistor including a second gate electrode and a second semiconductor layer; a node electrode for connecting the first transistor and the second transistor; a first conductive layer disposed on and overlapping the node electrode; and a pixel electrode disposed on the first conductive layer and disposed in the vicinity of the node electrode.

Description

Technical Field

[0001] One or more embodiments relate to a pixel and a display device including the pixel. Background Art

[0002] Recently, the uses of display devices have been diversified. In addition, display devices have become thinner and lighter, and therefore, the use methods of display devices have also increased.

[0003] Since display devices are used for various purposes, there are various methods of designing the shape of the display devices, and functions that can be associated or related to the display devices are also increasing. Summary of the Invention

[0004] Technical issues

[0005] One or more embodiments include a display device with improved display quality. However, this aspect is an example, and the scope of the present disclosure is not limited thereto.

[0006] Technical Solution

[0007] According to one or more embodiments, a display device may include: a first transistor including a first gate electrode and a first semiconductor layer; a second transistor including a second gate electrode and a second semiconductor layer; a node electrode connecting the first transistor to the second transistor; a first conductive layer disposed above the node electrode and overlapping with the node electrode in a plan view; and a pixel electrode disposed above the first conductive layer and near the node electrode.

[0008] The node electrode may connect the first gate electrode of the first transistor to one end of the second semiconductor layer of the second transistor.

[0009] The first conductive layer may be connected to one end of the first semiconductor layer of the first transistor.

[0010] The node electrode may be provided on a layer between the first gate electrode of the first transistor and the first conductive layer.

[0011] The display device may further include: a second conductive layer connected to one end of the first semiconductor layer of the first transistor, wherein the node electrode may be provided on a layer between the first conductive layer and the second conductive layer, and the first conductive layer may overlap with the second conductive layer in a plan view.

[0012] The display device may further include: a first electrode arranged on a substrate, wherein the first electrode may be arranged on a layer between the substrate and a second conductive layer, the second conductive layer may overlap with the first electrode in a plan view, and the first gate electrode of the first transistor may overlap with the second conductive layer in a plan view.

[0013] The second conductive layer may overlap with a channel region of the first semiconductor layer of the first transistor in a plan view.

[0014] The display may further include: a first conductive line connected to the first electrode and extending in the first direction; and a second conductive line connected to the other end of the second semiconductor layer of the second transistor and extending in the second direction.

[0015] The display device may further include a first vertical conductive line connected to the first conductive line and extending in a second direction perpendicular to the first direction; and a second vertical conductive line connected to the second conductive line and extending in the second direction.

[0016] The first vertical conductive line, the second vertical conductive line, and the second conductive layer may be disposed on the same layer.

[0017] The display device may further include a second electrode, wherein the second electrode and the first electrode are provided on the same layer, and the second electrode may be connected to the node electrode.

[0018] According to one or more embodiments, a display device may include: a node electrode connecting a driving transistor to a switching transistor in each of a first circuit region in which a first pixel circuit is provided and a second circuit region in which a second pixel circuit is provided; and a first conductive layer provided above the node electrode and overlapping with the node electrode in a plan view, wherein a pixel electrode connected to the driving transistor in the second circuit region may be provided near the node electrode provided in the first circuit region.

[0019] The node electrode may connect the gate electrode of the driving transistor to one end of the semiconductor layer of the switching transistor.

[0020] The first conductive layer may be connected to one end of the semiconductor layer of the driving transistor.

[0021] The node electrode may be provided on a layer between the gate electrode of the driving transistor and the first conductive layer.

[0022] The display device may further include: a second conductive layer connected to one end of the semiconductor layer of the driving transistor in each of the first circuit region and the second circuit region, wherein the node electrode may be arranged on a layer between the first conductive layer and the second conductive layer, the first conductive layer may overlap with the second conductive layer in a plan view, and the gate electrode of the driving transistor may overlap with the second conductive layer in a plan view.

[0023] The display device may further include: a first electrode and a second electrode, which are arranged to be spaced apart from each other in the first circuit area, wherein the first electrode and the second electrode may be arranged on a layer between the substrate and a second conductive layer arranged in the first circuit area, the second conductive layer arranged in the first circuit area may overlap with the first electrode and the second electrode in a plan view, the first electrode may be connected to a driving voltage line through which a driving voltage is supplied, and the second electrode may be connected to a node electrode arranged in the first circuit area.

[0024] The display device may further include: a third electrode disposed in the second circuit region, wherein the third electrode and the first electrode may be disposed on the same layer, the second conductive layer disposed in the second circuit region may overlap with the third electrode in a plan view, and the third electrode may be connected to a driving voltage line.

[0025] An overlapping area of ​​the first electrode and the second conductive layer in the first circuit region may be different from an overlapping area of ​​the third electrode and the second conductive layer in the second circuit region.

[0026] The display device may further include a vertical conductive line connected to the driving voltage line and extending in a direction perpendicular to an extending direction of the driving voltage line.

[0027] Technical Effects

[0028] According to one or more of the above embodiments of the present disclosure, a display device with improved display quality may be provided. However, the scope of the present disclosure is not limited to the effects as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1a and Figure 1b is a schematic diagram of a display device according to an embodiment.

[0030] Figure 2 is a schematic diagram of a display device according to an embodiment.

[0031] Figure 3 is a schematic diagram of an equivalent circuit of a pixel according to an embodiment.

[0032] Figures 4 to 8 is a schematic diagram of an equivalent circuit of a pixel according to an embodiment.

[0033] Figure 9 and Figure 10 is a schematic diagram of a capacitor according to an embodiment.

[0034] Figure 11 is a schematic plan view showing positions of transistors and capacitors of a pixel according to an embodiment.

[0035] Figures 12 to 22is a schematic plan view showing elements of each layer of a pixel.

[0036] Figure 23 It is along Figure 12 and Figure 21 Schematic cross-sectional view of a pixel taken along line II'.

[0037] Figure 24 It is along Figure 12 and Figure 21 Schematic cross-sectional view of a pixel taken along line II-II'.

[0038] Figure 25 is a schematic diagram of a capacitor for each pixel according to an embodiment.

[0039] Figure 26a It is along Figure 25 Schematic cross-sectional view of the capacitor of the first pixel taken along line IIIa-IIIa'.

[0040] Figure 26b It is along Figure 25 Schematic cross-sectional view of the capacitor of the second pixel taken along line IVa-IVa'.

[0041] Figure 26c It is along Figure 25 Schematic cross-sectional view of the capacitor of the third pixel taken along line Va-Va'.

[0042] Figure 27 is a schematic diagram of a capacitor for each pixel according to an embodiment.

[0043] Figure 28a It is along Figure 27 Schematic cross-sectional view of the capacitor of the first pixel taken along line IIIb-IIIb'.

[0044] Figure 28b It is along Figure 27 FIG. 5 is a cross-sectional view of the capacitor of the second pixel taken along line IVb-IVb′.

[0045] Figure 28c It is along Figure 27 Schematic cross-sectional view of the capacitor of the third pixel taken along line Vb-Vb′.

[0046] Figure 29 is a schematic diagram of a capacitor for each pixel according to an embodiment.

[0047] Figure 30a It is along Figure 29 Schematic cross-sectional view of the capacitor of the first pixel taken along line IIIc-IIIc′.

[0048] Figure 30b It is along Figure 29 Schematic cross-sectional view of the capacitor of the second pixel taken along line IVc-IVc′.

[0049] Figure 30c It is along Figure 29 Schematic cross-sectional view of the capacitor of the third pixel taken along line Vc-Vc′.

[0050] Figures 31 to 33 is a schematic plan view of a vertical conductive line according to an embodiment.

[0051] Figures 34a to 35b is a schematic cross-sectional view illustrating a structure of a display element according to an embodiment.

[0052] Figure 36 is a schematic cross-sectional view illustrating a structure of a pixel of a display device according to an embodiment. DETAILED DESCRIPTION

[0053] According to one or more embodiments, a display device includes a first transistor, a second transistor, a node electrode, a first conductive layer, and a pixel electrode, wherein the first transistor includes a first gate electrode and a first semiconductor layer, the second transistor includes a second gate electrode and a second semiconductor layer, the node electrode connects the first transistor to the second transistor, the first conductive layer is arranged above the node electrode and overlaps with the node electrode in a plan view, and the pixel electrode is arranged above the first conductive layer and near the node electrode.

[0054] Modes for Carrying Out the Invention

[0055] It is to be understood that the present disclosure is susceptible to various changes and may have many embodiments. Specific embodiments are shown in the drawings and described in the detailed description. The effects and features of the present disclosure and methods for achieving them will become apparent with reference to the embodiments described in detail below in conjunction with the drawings. However, the present disclosure is not limited to the embodiments disclosed herein and may be implemented in various forms.

[0056] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, "A and / or B" can be understood to mean any combination of A, B, or A and B. The terms "and" and "or" can be used in a conjunctive or disjunctive sense and can be understood to be equivalent to "and / or".

[0057] For the purpose of this disclosure, the phrase “at least one of A and B” may be interpreted as only A, only B, or any combination of A and B. In addition, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z.

[0058] It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0059] As used herein, the singular expressions "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0060] The terms "comprise," "including," "include," and / or "comprising," "have," "have," and / or "having," and variations thereof, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It will be understood that when a layer, region, or element is referred to as being formed "on" another layer, region, or element, it can be formed directly or indirectly on the other layer, region, or element. For example, intervening layers, regions, or elements may be present.

[0061] It will be understood that the term "connected to" or "coupled to" may include physical connection or physical coupling and / or electrical connection or electrical coupling. It will be understood that in the specification, when an element (or region, layer, portion, etc.) is referred to as being "on," "connected to," or "coupled to" another element, the element (or region, layer, portion, etc.) may be directly disposed on, directly connected to, or directly coupled to the aforementioned another element, or intervening elements may be disposed therebetween.

[0062] The case where X and Y are electrically connected to each other may include, for example, the case where at least one device for electrical connection between X and Y (eg, a switch, a transistor, a capacitance device, an inductor, a resistance device, a diode, etc.) is connected between X and Y.

[0063] In the embodiments described below, the terms "on" and "off" used in relation to device states refer to an activated state of the device and an inactivated state of the device, respectively. The terms "on" and "off" used in relation to signals received by a device may refer to a signal configured to activate the device and a signal configured to deactivate the device, respectively. A device may be activated by a high-level voltage or a low-level voltage. For example, a P-channel transistor (P-type transistor) may be activated by a low-level voltage, and an N-channel transistor (N-type transistor) may be activated by a high-level voltage. Therefore, it should be understood that the "on" voltages for P-type transistors and N-type transistors may have opposite voltage levels (low versus high).

[0064] In the embodiments described below, the x-direction, y-direction, and z-direction may not be limited to the directions of the three axes on the rectangular coordinate system and may be interpreted in a broader sense. For example, the x-direction, y-direction, and z-direction may be perpendicular to each other, or may refer to different directions that are not perpendicular to each other.

[0065] The term "overlap" or "overlapping" means that a first object can be above or below or to one side of a second object, and vice versa. Additionally, the term "overlap" may include layer, stack, facing or facing, extending across, covering or partially covering, or any other suitable term as would be understood and appreciated by one of ordinary skill in the art.

[0066] When elements are described as being “non-overlapping” or “not overlapping” another element, this may include the elements being spaced apart, offset from, or separated from each other, or any other suitable terminology as would be understood and appreciated by one of ordinary skill in the art.

[0067] As used herein, "about" or "approximately" or "substantially" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, in view of the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0068] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0069] The display device according to some embodiments can be a device that displays video or still images. The display device 1 can be used as a display screen for various devices, such as televisions, laptops, monitors, broadcast panels, and Internet of Things (IoT) devices, as well as portable electronic devices such as mobile phones, smartphones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile personal computers (UMPCs). Furthermore, the display device 1 according to embodiments can be used in wearable devices such as smartwatches, watch phones, glasses-type displays, and head-mounted displays (HMDs). Furthermore, the display device 1 according to embodiments can be used as a central information display (CID) on a vehicle's instrument panel, a central instrument panel or instrument panel, a rear-view mirror display in place of a vehicle's side mirrors, or a display on the rear surface of a front seat as a rear-seat entertainment device. Furthermore, the display device can be a flexible device.

[0070] Figure 1a and Figure 1b is a schematic diagram of a display device 1 according to an embodiment. Figure 2 is a schematic diagram of a display device 1 according to an embodiment.

[0071] refer to Figure 1a and Figure 1b The display device 1 may include a display area DA for displaying an image and a peripheral area PA outside the display area DA. The display area DA may be completely surrounded by the peripheral area PA.

[0072] In a plan view, the display area DA may have a rectangular shape. According to another embodiment, the display area DA may have a polygonal shape such as a triangular shape, a pentagonal shape, a hexagonal shape, a circular shape, an elliptical shape, an amorphous shape, etc. The display area DA may have rounded corners. According to an embodiment, as Figure 1a As shown in , the display device 1 may have a display area DA, wherein the length of the display area DA in the x direction is greater than the length of the display area DA in the y direction. Figure 1b As shown in , the display device 1 may have a display area DA, and the length of the display area DA in the y direction is greater than the length of the display area DA in the x direction.

[0073] The display device 1 may include a display panel 10 , and a cover window (not shown) to protect the display panel 10 may be arranged (disposed) above the display panel 10 .

[0074] Various elements included in the display panel 10 may be arranged on a substrate 100. The substrate 100 may include a display area DA and a peripheral area PA surrounding the display area DA.

[0075] The pixels PX may be arranged in the display area DA. The gate lines GL, the data lines DL, and the pixels connected to the gate lines GL and the data lines DL may be arranged in the display area DA. The pixels PX may be arranged in various forms (eg, stripe form, PenTile form, etc.). ® The pixels PX can be arranged in a pattern (e.g., a lattice pattern, a diamond pattern, a mosaic pattern, etc.) to produce an image. Each pixel PX may include an organic light-emitting diode (OLED) as a display element (light-emitting device), and the OLED may be connected to a pixel circuit. The pixel circuit may include a transistor and at least one capacitor. The pixel PX may emit, for example, red, green, blue, or white light through the OLED. Each pixel PX may be connected to a gate line corresponding to the pixel PX among the gate lines GL and a data line corresponding to the pixel PX among the data lines DL.

[0076] Each gate line GL may extend in the x-direction (row direction) and may be connected to pixels PX arranged in the same row. Each gate line GL may be configured to transmit a gate signal to pixels PX arranged in the same row. Each data line DL may extend in the y-direction (column direction) and may be connected to pixels PX arranged in the same column. Each data line DL may be synchronized with the gate signal and may be configured to transmit a data signal to each pixel PX in the same column. Each pixel PX may be connected to a drive voltage line PL and may be supplied with a drive voltage ELVDD. Each drive voltage line PL may extend in the y-direction (column direction) and may be connected to pixels PX arranged in the same column.

[0077] Figure 2 An example is shown in which the pixel PX is connected to one gate line GL. However, the embodiment is not limited thereto. The pixel PX may be connected to one or more gate lines GL.

[0078] Each of the pixel circuits configured to drive the pixel PX may be connected (e.g., electrically connected) to an external circuit disposed in the peripheral area PA. The first gate drive circuit GDRV1, the second gate drive circuit GDRV2, the terminal portion PAD, the drive voltage supply line 11, the common voltage supply line 13, etc. may be disposed in the peripheral area PA.

[0079] Depending on the embodiment, the peripheral area PA may be a non-display area of ​​the type in which no pixels PX are arranged. According to another embodiment, a portion of the peripheral area PA may be implemented as the display area DA. For example, pixels PX may be arranged in at least one corner of the peripheral area PA so as to overlap with external circuitry. This reduces dead zones (e.g., unused space) and expands the display area DA.

[0080] The first gate drive circuit GDRV1 can be connected to the gate line GL and can be configured to apply a gate signal to each of the pixel circuits configured to drive the pixel PX through the gate line GL. The second gate drive circuit GDRV2 can be arranged on the side opposite to the first gate drive circuit DRV1 relative to the display area DA and can be approximately parallel to the first gate drive circuit GDRV1. According to an embodiment, the pixel circuits of the pixels PX of the display area DA can be connected (e.g., electrically connected) to the first gate drive circuit GDRV1 and the second gate drive circuit GDRV2. According to another embodiment, some of the pixel circuits of the pixels PX of the display area DA can be connected (e.g., electrically connected) to the first gate drive circuit GDRV1, and the other pixel circuits can be connected (e.g., electrically connected) to the second gate drive circuit GDRV2. The second gate drive circuit GDRV2 can be omitted.

[0081] The terminal portion PAD may be disposed at one side of the substrate 100. The terminal portion PAD may not be covered by the insulating layer to be exposed, and may be connected to the display circuit board 30. The display driver 32 may be disposed on the display circuit board 30.

[0082] The display driver 32 may include a data driving circuit. The data driving circuit may be connected to the data line DL and may be configured to generate a data signal. The generated data signal may be transmitted to the pixel circuit of the pixel PX via the fan-out line FW and the data line DL connected to the fan-out line FW.

[0083] The display driver 32 may include a power supply circuit, and the power supply circuit may be configured to supply a driving voltage ELVDD to the driving voltage supply line 11 and a common voltage ELVSS to the common voltage supply line 13. The driving voltage ELVDD may be applied to the pixel circuit of the pixel PX through the driving voltage line PL connected to the driving voltage supply line 11, and the common voltage ELVSS may be applied to the opposite electrode of the display element through the common voltage supply line 13.

[0084] The display driver 32 may include a controller, and the controller may be configured to generate control signals that are sent to the first gate driving circuit GDRV1 , the second gate driving circuit GDRV2 , the data driving circuit, and the power supply circuit.

[0085] The driving voltage supply line 11 may be connected to the terminal portion PAD and may extend in the x direction at a lower portion of the display area DA. The common voltage supply line 13 may be connected to the terminal portion PAD and may have a ring shape with an open side to partially surround the display area DA.

[0086] During the process of forming pixel circuits in the display area DA of the substrate 100, the first gate driver circuit GDRV1 and the second gate driver circuit GDRV2 may be partially or completely (e.g., directly) formed in the peripheral area PA of the substrate 100. The display driver 32 may be formed as an integrated circuit chip and may be arranged on the display circuit board 30 connected (e.g., electrically connected) to a terminal portion PAD arranged on one side of the substrate 100. The display circuit board 30 may include a flexible printed circuit board (FPCB). According to another embodiment, the display driver 32 may be arranged directly on the substrate 100 as a chip on glass (COG) or a chip on plastic (COP).

[0087] According to an embodiment, the transistors included in the pixel circuits of the display area DA and the transistors included in the external circuits of the peripheral area PA (e.g., the first gate driver circuit GDRV1 and the second gate driver circuit GDRV2) may be N-type oxide thin film transistors. The transistors included in the external circuits of the peripheral area PA may be formed simultaneously with the transistors included in the pixel circuits of the display area DA during the same process. According to another embodiment, the transistors included in the pixel circuits of the display area DA may be N-type oxide thin film transistors, and the transistors included in the external circuits of the peripheral area PA may be P-type silicon thin film transistors.

[0088] An oxide thin-film transistor may include a semiconductor layer containing an oxide. The oxide semiconductor may include a Zn oxide-based material such as Zn oxide, In-Zn oxide, or Ga-In-Zn oxide. In some embodiments, the oxide semiconductor may include an In-Ga-Zn-O (IGZO) semiconductor, in which metals including In and Ga are contained in ZnO. In some embodiments, the oxide thin-film transistor may include a low-temperature polycrystalline oxide (LTPO) thin-film transistor. A silicon thin-film transistor may include a low-temperature polycrystalline silicon (LTPS) thin-film transistor, in which the semiconductor layer includes amorphous silicon, polycrystalline silicon, or the like.

[0089] Figure 3 is a schematic diagram of an equivalent circuit of a pixel PX according to an embodiment.

[0090] refer to Figure 3 , the pixel PX may include a pixel circuit PC and an organic light emitting diode OLED as a display element connected to the pixel circuit PC.

[0091] Pixel PX can be connected to a first gate line GWL configured to transmit a first gate signal GW, a second gate line GIL configured to transmit a second gate signal GI, a third gate line GRL configured to transmit a third gate signal GR, a fourth gate line EML configured to transmit a fourth gate signal EM, a fifth gate line EMBL configured to transmit a fifth gate signal EMB, and a data line DL configured to transmit a data signal. Emission of pixel PX can be controlled by the fourth gate signal EM and the fifth gate signal EMB. Therefore, the fourth gate signal EM and the fifth gate signal EMB can also be referred to as emission control signals, and the fourth gate line EML and the fifth gate line EMBL can also be referred to as emission control lines. Furthermore, pixel PX can be connected to a driving voltage line PL configured to transmit a driving voltage ELVDD, a reference voltage line VRL configured to transmit a reference voltage Vref, and an initialization voltage line VL configured to transmit an initialization voltage Vint.

[0092] According to an embodiment, the transistor included in the pixel circuit PC may include an N-type oxide thin film transistor. The oxide thin film transistor may include an LTPO thin film transistor, which includes a semiconductor layer containing an oxide. However, the LTPO thin film transistor is merely an example, and the N-type transistor is not limited thereto. For example, the semiconductor layer included in the N-type transistor may include an inorganic semiconductor (e.g., amorphous silicon, polycrystalline silicon, etc.) or an organic semiconductor.

[0093] The pixel circuit PC may include first to sixth transistors T1 to T6 and first and second capacitors C1 and C2. The first transistor T1 may be a driving transistor configured to output a driving current corresponding to a data signal, and the second to sixth transistors T2 to T6 may be switching transistors configured to transmit a signal. The first terminal (first electrode) and the second terminal (second electrode) of each of the first to sixth transistors T1 to T6 may be a source or a drain, depending on the voltages of the first and second terminals. For example, depending on the voltages of the first and second terminals, the first terminal may be a drain and the second terminal may be a source, or the first terminal may be a source and the second terminal may be a drain. Hereinafter, the node to which the first gate of the first transistor T1 is connected may be defined as a first node N1, and the node to which the second terminal of the first transistor T1 is connected may be defined as a second node N2.

[0094] The first transistor T1 can be connected to the driving voltage line PL and the organic light emitting diode OLED. The first transistor T1 can be connected between the fifth transistor T5 and the sixth transistor T6. The first transistor T1 can include a gate, a first terminal, and a second terminal connected to the second node N2. The first transistor T1 can include a first gate connected to the first node N1. The first transistor T1 can also include a second gate connected to the second terminal of the first transistor T1. The first gate and the second gate can be arranged on different layers so as to face each other. For example, the first gate and the second gate of the first transistor T1 can be arranged so as to face each other, with a semiconductor layer between the first gate and the second gate. Hereinafter, the gate (or gate electrode) of the first transistor T1 can refer to the first gate involved in turning the first transistor T1 on and off.

[0095] The first gate of the first transistor T1 can be connected to the second terminal of the second transistor T2, the first terminal of the third transistor T3, and the first capacitor C1. The second gate of the first transistor T1 can be connected to the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The first terminal of the first transistor T1 can be connected to the driving voltage line PL through the fifth transistor T5, and the second terminal of the first transistor T1 can be connected to the pixel electrode of the organic light emitting diode OLED through the sixth transistor T6. The first terminal of the first transistor T1 can be connected to the second terminal of the fifth transistor T5. The second terminal of the first transistor T1 can be connected to the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The first transistor T1 can be configured to receive the data signal DATA according to the switching operation of the second transistor T2, and can be configured to control the amount of current of the driving current flowing to the organic light emitting diode OLED.

[0096] The second transistor T2 (write transistor) can be connected to the data line DL and the first gate of the first transistor T1. The second transistor T2 may include a gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1. The second terminal of the second transistor T2 may be connected to the first gate of the first transistor T1, the first terminal of the third transistor T3, and the first capacitor C1. The second transistor T2 may be turned on by a first gate signal GW transmitted via the first gate line GWL and may be configured to connect (e.g., electrically connect) the data line DL to the first node N1 and transmit the data signal DATA transmitted via the data line DL to the first node N1.

[0097] The third transistor T3 (first initialization transistor) can be connected to the first gate of the first transistor T1 and the reference voltage line VRL. The third transistor T3 may include a gate connected to the third gate line GRL, a first terminal connected to the first node N1, and a second terminal connected to the reference voltage line VRL. The first terminal of the third transistor T3 may be connected to the first gate of the first transistor T1, the second terminal of the second transistor T2, and the first capacitor C1. The third transistor T3 may be turned on by a third gate signal GR transmitted via the third gate line GRL and may be configured to transmit a reference voltage Vref transmitted via the reference voltage line VRL to the first node N1.

[0098] The fourth transistor T4 (second initialization transistor) can be connected to the sixth transistor T6 and the initialization voltage line VL. The fourth transistor T4 can be connected between the organic light emitting diode OLED and the initialization voltage line VL. The fourth transistor T4 can include a gate connected to the second gate line GIL, a first terminal connected to the third node N3, and a second terminal connected to the initialization voltage line VL. The first terminal of the fourth transistor T4 can be connected to the second terminal of the sixth transistor T6 and the pixel electrode of the organic light emitting diode OLED. The fourth transistor T4 can be turned on by the second gate signal GI transmitted via the second gate line GIL and can be configured to transmit the initialization voltage Vint transmitted via the initialization voltage line VL to the third node N3.

[0099] A fifth transistor T5 (a first emission control transistor) may be connected to the driving voltage line PL and the first transistor T1. The fifth transistor T5 may include a gate connected to the fourth gate line EML, a first terminal connected to the driving voltage line PL, and a second terminal connected to the first terminal of the first transistor T1. The fifth transistor T5 may be turned on or off based on a fourth gate signal EM transmitted via the fourth gate line EML.

[0100] The sixth transistor T6 (second emission control transistor) can be connected to the first transistor T1 and the organic light emitting diode OLED. The sixth transistor T6 can be connected between the second node N2 and the third node N3. The sixth transistor T6 can include a gate connected to the fifth gate line EMBL, a first terminal connected to the second node N2, and a second terminal connected to the third node N3. The first terminal of the sixth transistor T6 can be connected to the second terminal of the first transistor T1, the first capacitor C1, and the second capacitor C2. The second terminal of the sixth transistor T6 can be connected to the first terminal of the fourth transistor T4 and the pixel electrode of the organic light emitting diode OLED. The sixth transistor T6 can be turned on or off based on a fifth gate signal EMB transmitted via the fifth gate line EMBL.

[0101] The first capacitor C1 may be connected between the first gate of the first transistor T1 and the second terminal of the first transistor T1. The first electrode of the first capacitor C1 may be connected to the first node N1, and the second electrode of the first capacitor C1 may be connected to the second node N2. The first electrode of the first capacitor C1 may be connected to the first gate of the first transistor T1, the second terminal of the second transistor T2, and the first terminal of the third transistor T3. The second electrode of the first capacitor C1 may be connected to the second terminal and the second gate of the first transistor T1, the second electrode of the second capacitor C2, and the first terminal of the sixth transistor T6. The first capacitor C1 may be a storage capacitor and may be configured to store a threshold voltage of the first transistor T1 and a voltage corresponding to the data signal DATA.

[0102] When the third transistor T3 and the fifth transistor T5 are turned on together, the first transistor T1 can be turned on. When the voltage of the second terminal of the first transistor T1 reaches the difference Vref-Vth between the reference voltage Vref and the threshold voltage Vth of the first transistor T1, the first transistor T1 can be turned off, and a voltage corresponding to the threshold voltage Vth of the first transistor T1 can be stored in the first capacitor C1, so that the threshold voltage Vth of the first transistor T1 can be compensated.

[0103] The second capacitor C2 may be connected between the driving voltage line PL and the second node N2. A first electrode of the second capacitor C2 may be connected to the driving voltage line PL. A second electrode of the second capacitor C2 may be connected to the second terminal and the second gate of the first transistor T1, the second electrode of the first capacitor C1, and the first terminal of the sixth transistor T6.

[0104] The capacitance of each of the first capacitor C1 and the second capacitor C2 may vary according to the color of light emitted by the pixel PX.

[0105] The organic light-emitting diode OLED can be connected to the first transistor T1 via the sixth transistor T6. The organic light-emitting diode OLED may include a pixel electrode (anode) connected to the third node N3 and an opposing electrode (cathode) facing the pixel electrode. The opposing electrode may receive a common voltage EVLSS. The opposing electrode may be a common electrode shared by multiple pixels PX. When the fifth transistor T5 and the sixth transistor T6 are turned on, the first transistor T1 may output a driving current that can flow through the organic light-emitting diode OLED, and the organic light-emitting diode OLED may emit light with a brightness corresponding to the magnitude of the driving current.

[0106] The pixel circuit of the pixel according to the embodiment is not limited to Figure 3According to another embodiment, various pixel circuits may be implemented, the pixel circuit including a first capacitor C1 and a second capacitor C2 connected to the second terminal (source) of the first transistor T1.

[0107] Figures 4 to 8 is a schematic diagram of an equivalent circuit of a pixel PX according to an embodiment.

[0108] Figure 4 The pixel circuit PC of the pixel PX shown in FIG. Figure 3 The pixel circuit PC shown in FIG. 1 may differ at least in that Figure 4 In the pixel circuit PC of the pixel PX shown in FIG, the fourth transistor T4 can be connected to the second node N2 and the initialization voltage line VL. The fourth transistor T4 can be turned on by the second gate signal GI sent through the second gate line GIL and can be configured to send the initialization voltage Vint sent through the initialization voltage line VL to the second node N2.

[0109] Figure 5 The pixel circuit PC of the pixel PX shown in FIG. Figure 4 The pixel circuit PC shown in FIG. 1 may differ at least in that Figure 5 In the pixel circuit PC of the pixel PX shown in FIG, a seventh transistor T7 connected to the third node N3 and the second initialization voltage line VL2 may be further included. The second initialization voltage line VL2 may be provided separately from the initialization voltage line VL and may be configured to transmit a second initialization voltage Vaint to the third node N3. According to an embodiment, the second initialization voltage Vaint may have a higher voltage level than the initialization voltage Vint.

[0110] The seventh transistor T7 can be turned on by the second gate signal GI sent through the second gate line GIL and can be configured to send the second initialization voltage Vaint sent through the second initialization voltage line VL2 to the third node N3. The second node N2 and the third node N3 can be initialized to different voltages from each other through the fourth transistor T4 and the seventh transistor T7.

[0111] Figure 6 The pixel circuit PC of the pixel PX shown in FIG. Figure 5 The pixel circuit PC shown in FIG. 1 may differ in at least one of the following aspects: Figure 6 In the pixel circuit PC of the pixel PX shown in FIG, the gate of the seventh transistor T7 can be connected to the sixth gate line GBL and configured to receive the sixth gate signal GB. The fourth transistor T4 and the seventh transistor T7 can be connected to different gate lines and controlled by different gate signals, and therefore, the initialization timing of the second node N2 and the third node N3 can be controlled separately.

[0112] Figure 7 The pixel circuit PC of the pixel PX shown in FIG. Figure 6 The pixel circuit PC shown in FIG. 1 may differ in at least one of the following aspects: Figure 7 In the pixel circuit PC of the pixel PX shown in FIG, the seventh transistor T7 can be connected to the second node N2 and the second initialization voltage line VL2. The fourth transistor T4 and the seventh transistor T7 can be connected to different gate lines and controlled by different gate signals, and therefore, the initialization of the second node N2 can be accurately controlled.

[0113] Figure 8 The pixel circuit PC of the pixel PX shown in FIG. Figure 7 The pixel circuit PC shown in FIG. 1 may differ in at least one of the following aspects: Figure 8 In the pixel circuit PC of the pixel PX shown in , the sixth transistor T6 can be omitted.

[0114] Figure 9 and Figure 10 is a schematic diagram of a capacitor according to an embodiment.

[0115] Figure 9 and Figure 10 It can be shown Figures 3 to 8 The first capacitor C1 and the second capacitor C2 are shown in FIG. The capacitance of the first capacitor C1 and the capacitance of the second capacitor C2 can be controlled by the overlapping area between the conductive lines.

[0116] refer to Figure 9 The first electrode E11 and the second electrode E12 may be arranged spaced apart from each other on the substrate 100. The third electrode E13, overlapping the first and second electrodes E11 and E12, may be arranged on the first and second electrodes E11 and E12. The fourth electrode E14, overlapping the third electrode E13, may be arranged on the third electrode E13. The fifth and sixth electrodes E15 and E16 may be arranged spaced apart from each other on the fourth electrode E14. The fifth and sixth electrodes E15 and E16 may overlap the fourth electrode E14. The fifth electrode E15 may be connected (e.g., electrically connected) to the third electrode E13. The sixth electrode E16 may be connected (e.g., electrically connected) to the fourth electrode E14 and the first electrode E11. The seventh electrode E17, overlapping the sixth electrode E16, may be arranged on the sixth electrode E16. The seventh electrode E17 may be connected (e.g., electrically connected) to the third electrode E13.

[0117] The second electrode E12 may be configured to receive a driving voltage ELVDD. The third electrode E13, the fifth electrode E15, and the seventh electrode E17 may be connected (e.g., electrically connected) to the source of the first transistor T1. The first electrode E11, the fourth electrode E14, and the sixth electrode E16 may be connected (e.g., electrically connected) to the gate (first gate) of the first transistor T1.

[0118] At least one insulating layer IL may be disposed between the first electrode E11, the second electrode E12, and the third electrode E13. At least one insulating layer IL may be disposed between the third electrode E13 and the fourth electrode E14. At least one insulating layer IL may be disposed between the fourth electrode E14, the fifth electrode E15, and the sixth electrode E16. At least one insulating layer IL may be disposed between the sixth electrode E16 and the seventh electrode E17. The insulating layer IL may include one or more inorganic insulating layers and / or organic insulating layers.

[0119] The first capacitor C1 may have a structure in which a first sub-capacitor and a second sub-capacitor are connected in parallel. The first sub-capacitor may be formed by a first electrode E11, a third electrode E13 overlapping with the first electrode E11, a fourth electrode E14 overlapping with the third electrode E13, and a fifth electrode E15 overlapping with the fourth electrode E14. In addition, the second sub-capacitor may be formed by a sixth electrode E16 and a seventh electrode E17. The capacitance of the first capacitor C1 may be the sum of the capacitance formed by the first electrode E11 and the third electrode E13, the capacitance formed by the third electrode E13 and the fourth electrode E14, the capacitance formed by the fourth electrode E14 and the fifth electrode E15, and the capacitance formed by the sixth electrode E16 and the seventh electrode E17.

[0120] The second capacitor C2 may include a second electrode E12 and a third electrode E13 overlapping the second electrode E12. The capacitance of the second capacitor C2 may be a capacitance formed by the second electrode E12 and the third electrode E13.

[0121] According to another embodiment, Figure 10 As shown in , the first electrode E11 may be omitted. The first capacitor C1 may have a structure in which a first sub-capacitor and a second sub-capacitor are connected in parallel to each other. The first sub-capacitor may be formed by the third electrode E13, the fourth electrode E14, and the fifth electrode E15. In addition, the second sub-capacitor may be formed by the sixth electrode E16 and the seventh electrode E17. The capacitance of the first capacitor C1 may be the sum of the capacitance formed by the third electrode E13 and the fourth electrode E14, the capacitance formed by the fourth electrode E14 and the fifth electrode E15, and the capacitance formed by the sixth electrode E16 and the seventh electrode E17.

[0122] Figure 11is a schematic plan view showing positions of transistors and capacitors of a pixel according to an embodiment. Figures 12 to 22 is a schematic plan view showing elements of each layer of a pixel. Figure 23 It is along Figure 12 and Figure 21 Schematic cross-sectional view of an element of a pixel taken along line II'. Figure 24 It is along Figure 12 and Figure 21 Schematic cross-sectional view of an element of a pixel taken along line II-II'.

[0123] Figure 11 Shown Figure 3 An example of a pixel circuit PC of a pixel PX shown in FIG. However, Figure 11 The embodiment shown in can be similarly applied to Figures 4 to 8 The pixel circuit of the pixel shown in FIG, and Figures 4 to 8 The corresponding transistors and capacitors can have substantially the same Figure 11 Same location as shown in .

[0124] The pixels PX arranged in the display area DA may include a first pixel PX1 that emits a first color, a second pixel PX2 that emits a second color, and a third pixel PX3 that emits a third color. For example, the first pixel PX1 may be a red pixel, the second pixel PX2 may be a green pixel, and the third pixel PX3 may be a blue pixel. The first, second, and third pixels PX1, PX2, and PX3 may be arranged repeatedly in a predetermined or selected pattern in the x- and y-directions. Each of the first, second, and third pixels PX1, PX2, and PX3 may include a pixel circuit and an organic light emitting diode (OLED) as a display element connected (e.g., electrically connected) to the pixel circuit.

[0125] The display area DA defined on the substrate 100 may include rows and columns intersecting each other, and may include circuit areas in which pixel circuits are arranged. Depending on the embodiment, a unit circuit area PCAu may be defined, including two or more circuit areas adjacent to each other in the x-direction. For example, the unit circuit area PCAu may include three circuit areas (e.g., a first circuit area PCA1, a second circuit area PCA2, and a third circuit area PCA3 adjacent to each other in the x-direction). The first circuit area PCA1 may be an area in which the pixel circuit of the first pixel PX1 is arranged. The second circuit area PCA2 may be an area in which the pixel circuit of the second pixel PX2 is arranged. The third circuit area PCA3 may be an area in which the pixel circuit of the third pixel PX3 is arranged.

[0126] Each of the pixel circuits PC arranged in the first to third circuit areas PCA1 to PCA3 may be connected to Figure 3 . The pixel circuits PC arranged in the first through third circuit areas PCA1 through PCA3 can be connected (e.g., electrically connected) to display elements that emit light of different colors. Each of the pixel circuits PC arranged in the first through third circuit areas PCA1 through PCA3 can be configured to drive the display element to which it is connected (e.g., electrically connected). For example, a display element connected (e.g., electrically connected) to a pixel circuit arranged in the first circuit area PCA1 can emit red light. A display element connected (e.g., electrically connected) to a pixel circuit arranged in the second circuit area PCA2 can emit green light. A display element connected (e.g., electrically connected) to a pixel circuit arranged in the third circuit area PCA3 can emit blue light.

[0127] According to an embodiment, considering the emission characteristics of the first to third pixels PX1 to PX3, the initialization voltages Vint supplied to the first to third pixels PX1 to PX3 may be different from each other. For example, the pixel circuit PC of the first pixel PX1 may be connected to the 1-1 initialization voltage line VL11, and the pixel circuits PC of the second and third pixels PX2 and PX3 may be connected to the 1-2 initialization voltage line VL12. The initialization voltage supplied to the 1-1 initialization voltage line VL11 and the initialization voltage supplied to the 1-2 initialization voltage line VL12 may be different from each other.

[0128] The same components can be arranged on each layer of the first to third circuit areas PCA1 to PCA3. Hereinafter, for the convenience of illustration and explanation, reference numerals are assigned to components of the pixel circuit PC arranged in the first circuit area PCA1, and description is given based on the first circuit area PCA1. However, the description can also be applied to the same components of the second and third circuit areas PCA2 and PCA3. Figures 12 to 24 Hereinafter, a connection electrode may be an electrode configured to connect (eg, electrically connect) conductive lines or conductive patterns arranged on different layers from each other and transmit a signal.

[0129] The first conductive layer may be disposed on the substrate 100. Figure 12 As shown in , the first conductive layer may include a first electrode layer 210, a driving voltage line PL, and a repair line RL.

[0130] The substrate 100 may include a glass material, a ceramic material, a metal material, a flexible and / or bendable material. The substrate 100 may have a single-layer structure including an organic layer or a multi-layer structure including an organic layer and an inorganic layer. For example, the substrate 100 may have a stacked structure of a first base layer / a barrier layer / a second base layer. Each of the first base layer and the second base layer may be an organic layer including a polymer resin. The first base layer and the second base layer may include a transparent polymer resin. The barrier layer may be configured to prevent penetration of external impurities and may include a layer including a SiN x or SiO x According to another embodiment, a barrier layer may be further disposed between the substrate 100 and the first conductive layer.

[0131] The first electrode layer 210 may be provided as an island (eg, isolated) type. The first electrode layer 210 may be arranged adjacent to the driving voltage line PL in the first and second circuit areas PCA1 and PCA2, and may not be arranged in the third circuit area PCA3.

[0132] The driving voltage line PL may extend in the x-direction and may be arranged across the first circuit area PCA1, the second circuit area PCA2, and the third circuit area PCA3. The driving voltage line PL may include a main line PLa extending in the x-direction in each circuit area and a protruding portion PLb protruding from the main line PLa in the -y-direction. The area of ​​the driving voltage line PL and the area of ​​the main line PLa may differ for each circuit area. According to an embodiment, the area of ​​the main line PLa of the driving voltage line PL in the third circuit area PCA3 may be larger than the area of ​​the main line PLa of the driving voltage line PL in the first circuit area PCA1 and the second circuit area PCA2. The area of ​​the main line PLa of the driving voltage line PL in the second circuit area PCA2 may be larger than the area of ​​the main line PLa of the driving voltage line PL in the first circuit area PCA1.

[0133] The repair line RL may extend in the x-direction and may be arranged across the first circuit area PCA1 , the second circuit area PCA2 , and the third circuit area PCA3 .

[0134] A first insulating layer 111 may be disposed on the substrate 100 to cover the first conductive layer, and a second conductive layer may be disposed on the first insulating layer 111. Figure 13 As shown in , the second conductive layer may include a second electrode layer 220, a lower first gate line GWLb, a reference voltage line VRL, and a 1-2 th initialization voltage line VL12.

[0135] The second electrode layer 220 may be configured as an island. The second electrode layer 220 may overlap the first electrode layer 210 and the main line PLa of the driving voltage line PL. The second electrode layer 220 may include the second gate electrode G12 of the first transistor T1. An opening SOP overlapping the first electrode layer 210 may be defined in the second electrode layer 220 in the first circuit area PCA1 and the second circuit area PCA2.

[0136] The lower first gate line GWLb, the reference voltage line VRL, and the 1-2 nd initialization voltage line VL12 may extend in the x-direction and may be arranged across the first to third circuit areas PCA1 to PCA3 .

[0137] The second insulating layer 112 may be disposed on the first insulating layer 111 to cover the second conductive layer, and a semiconductor layer ACT including an oxide semiconductor may be disposed on the second insulating layer 112, as shown in FIG. Figure 14 As shown in . The semiconductor layer ACT may include a first semiconductor layer ACT1, a second semiconductor layer ACT2, and a third semiconductor layer ACT3. The semiconductor layer ACT may include a channel region of each of the first transistor T1 to the sixth transistor T6, a source region and a drain region on both sides of the channel region. Depending on the situation, the source region or the drain region may also be interpreted as the source electrode or the drain electrode of the transistor.

[0138] Figure 16 The transistors of the first circuit area PCA1 are shown. Figure 16 The first semiconductor layer ACT1 may include the source region S1 and drain region D1 of the first transistor T1, and the source region S5 and drain region D5 of the fifth transistor T5. The second semiconductor layer ACT2 may include the source region S2 and drain region D2 of the second transistor T2, and the source region S3 and drain region D3 of the third transistor T3. The third semiconductor layer ACT3 may include the source region S4 and drain region D4 of the fourth transistor T4, and the source region S6 and drain region D6 of the sixth transistor T6.

[0139] A third insulating layer 113 may be disposed on the second insulating layer 112 to cover the semiconductor layer ACT, and a third conductive layer may be disposed on the third insulating layer 113. Figure 15 As shown in , the third conductive layer may include a third electrode layer 230, a fourth electrode layer 240, a connecting electrode 250, an upper first gate line GWLt, a second gate line GIL, a third gate line GRL, a fourth gate line EML, a fifth gate line EMBL and a 1-1th initialization voltage line VL11.

[0140] The third electrode layer 230, the fourth electrode layer 240, and the connection electrode 250 may be provided in an island type. The third electrode layer 230, the fourth electrode layer 240, and the connection electrode 250 may be arranged in each of the first to third circuit areas PCA1 to PCA3.

[0141] In the first circuit area PCA1 and the second circuit area PCA2, the third electrode layer 230 may be connected (e.g., electrically connected) to the first electrode layer 210 through a contact hole 31 passing through the first insulating layer 111 to the third insulating layer 113. The contact hole 31 may be insulated from the opening SOP of the second electrode layer 220 and may be disposed in the opening SOP.

[0142] In the first to third circuit areas PCA1 to PCA3 , the connection electrode 250 may be connected (eg, electrically connected) to the protrusion portion PLb of the driving voltage line PL through the contact hole 33 passing through the first to third insulating layers 111 to 113 .

[0143] The upper first, second, third, GRL, fourth, and fifth gate lines GWLt, GIL, GRL, EML, EMBL, and 1-1th initialization voltage line VL11 may extend in the x-direction and may be arranged across the first to third circuit areas PCA1 to PCA3.

[0144] The upper first gate line GWLt may be connected (eg, electrically connected) to the lower first gate line GWLb through a contact hole 32 passing through the second insulating layer 112 and the third insulating layer 113 .

[0145] like Figure 16 As shown in FIG, the third conductive layer may include gate electrodes G1 to G6 of the first to sixth transistors T1 to T6. The gate electrodes G1 to G6 may overlap with the channel region of the semiconductor layer ACT.

[0146] refer to Figure 16 The third electrode layer 230 may include a first gate electrode G11 of the first transistor T1. The first gate electrode G11 may overlap the first semiconductor layer ACT1. The fourth electrode layer 240 may correspond to the gate electrode G2 of the second transistor T2. The fourth electrode layer 240 may overlap the second semiconductor layer ACT2. The gate electrode G3 of the third transistor T3 may be a portion of the third gate line GRL that overlaps the second semiconductor layer ACT2. The gate electrode G4 of the fourth transistor T4 may be a portion of the second gate line GIL that overlaps the third semiconductor layer ACT3. The gate electrode G5 of the fifth transistor T5 may be a portion of the fourth gate line EML that overlaps the first semiconductor layer ACT1. The gate electrode G6 of the sixth transistor T6 may be a portion of the fifth gate line EMBL that overlaps the third semiconductor layer ACT3.

[0147] The fourth insulating layer 114 may be disposed on the third insulating layer 113 to cover the third conductive layer, and the fourth conductive layer may be disposed on the fourth insulating layer 114. Figure 17 As shown in , the fourth conductive layer may include data lines DL and connection electrodes 270 , 271 , 272 , 273 , 274 , 275 , 276 , and 277 .

[0148] The data line DL may be arranged to extend in the y direction for each circuit region and may be connected (eg, electrically connected) to the drain region D2 of the second transistor T2 through a contact hole 43 passing through the third and fourth insulating layers 113 and 114 .

[0149] The connection electrode 270 may include a first region 270a overlapping the first to third electrode layers 210 to 230 and a second region 270b protruding from the first region 270a in the -y direction. The connection electrode 270 may connect (e.g., electrically connect) the source region S1 of the first transistor T1 to the second gate electrode of the first transistor T1 and the sixth transistor T6.

[0150] The first region 270a of the connection electrode 270 can be connected (e.g., electrically connected) to the source region S1 of the first transistor T1 via a contact hole 42 extending through the third insulating layer 113 and the fourth insulating layer 114. The first region 270a of the connection electrode 270 can be connected (e.g., electrically connected) to the second electrode layer 220 via a contact hole 41 extending through the second insulating layer 112 and the fourth insulating layer 114. Therefore, the connection electrode 270 can correspond to a source electrode connected (e.g., electrically connected) to the source region S1 of the first transistor T1. The second electrode layer 220 can correspond to the second gate electrode G12 of the first transistor T1, which faces the first gate electrode G11 of the first transistor T1 and overlaps with the channel region of the first transistor T1. When the connection electrode 270 is connected to the second electrode layer 220, the second gate electrode G12 of the first transistor T1 can be connected (e.g., electrically connected) to the source region S1 of the first transistor T1.

[0151] The second region 270 b of the connection electrode 270 may be connected (eg, electrically connected) to the drain region D6 of the sixth transistor T6 through a contact hole 50 passing through the third insulating layer 113 and the fourth insulating layer 114 .

[0152] The connection electrode 271 may be connected (eg, electrically connected) to the gate electrode G2 of the second transistor T2 through a contact hole 45 passing through the fourth insulating layer 114. The connection electrode 271 may be connected (eg, electrically connected) to the upper first gate line GWLt through a contact hole 44 passing through the fourth insulating layer 114.

[0153] The connection electrode 272 can be connected (e.g., electrically connected) to the source region S3 of the third transistor T3 through a contact hole 46 passing through the third insulating layer 113 and the fourth insulating layer 114, and can be connected (e.g., electrically connected) to the reference voltage line VRL through a contact hole 47 passing through the second insulating layer 112 to the fourth insulating layer 114.

[0154] The connection electrode 273 may be connected (e.g., electrically connected) to the source region S2 of the second transistor T2 and the drain region D3 of the third transistor T3 through the contact hole 48 passing through the third insulating layer 113 and the fourth insulating layer 114. The connection electrode 273 may be connected (e.g., electrically connected) to the third electrode layer 230 through the contact hole 49 passing through the fourth insulating layer 114, and may be connected (e.g., electrically connected) to the first gate electrode G11 of the first transistor T1. The connection electrode 273 may be connected to the corresponding Figure 3 The connection electrode 273 may correspond to a node electrode of the first node N1 of the transistor. The connection electrode 273 may correspond to a bridge electrode that connects (e.g., electrically connects) at least two transistors. For example, the connection electrode 273 may correspond to a bridge electrode that connects the first gate electrode G11 of the first transistor T1, the source region S2 of the second transistor T2, and the drain region D3 of the third transistor T3.

[0155] The connection electrode 274 may be connected (e.g., electrically connected) to the protruding portion PLb of the driving voltage line PL through a contact hole 51 passing through the first insulating layer 111 to the fourth insulating layer 114. The connection electrode 274 may be connected (e.g., electrically connected) to the drain region D5 of the fifth transistor T5 through a contact hole 52 passing through the third insulating layer 113 and the fourth insulating layer 114. Thus, the drain region D5 of the fifth transistor T5 may be connected (e.g., electrically connected) to the driving voltage line PL.

[0156] The connection electrode 275 may be connected (e.g., electrically connected) to the source region S6 of the sixth transistor T6 and the drain region D4 of the fourth transistor T4 via a contact hole 53 passing through the third insulating layer 113 and the fourth insulating layer 114. The connection electrode 275 may overlap with a portion of the repair line RL. The connection electrode 275 may be insulated from the repair line RL and, if a defect occurs in a pixel circuit disposed in a circuit region corresponding to the connection electrode 275, the connection electrode 275 may be connected (e.g., electrically connected) to the repair line RL.

[0157] In the first circuit area PCA1, the connection electrode 276 may be connected (e.g., electrically connected) to the source region S4 of the fourth transistor T4 via a contact hole 54 passing through the third insulating layer 113 and the fourth insulating layer 114. The connection electrode 276 may be connected to the 1-1 initialization voltage line VL11 via a contact hole 55 passing through the fourth insulating layer 114.

[0158] In the second circuit area PCA2 and the third circuit area PCA3, the connection electrode 276 may be connected (e.g., electrically connected) to the source region S4 of the fourth transistor T4 through a contact hole 54 passing through the third insulating layer 113 and the fourth insulating layer 114. The connection electrode 276 may be connected (e.g., electrically connected) to the 1-2 initialization voltage line VL12 through a contact hole 56 passing through the second insulating layer 112 to the fourth insulating layer 114.

[0159] In the first circuit area PCA1, the connection electrode 277 may be connected (e.g., electrically connected) to the 1-2 initialization voltage line VL12 through the contact hole 57 that passes through the second insulating layer 112 to the fourth insulating layer 114. The connection electrode 277 may be arranged in some of the first circuit areas PCA1. For example, the connection electrode 277 may be arranged only in the area where the second vertical initialization voltage line VL12v (see FIG. 1 ) from among the vertical conductive lines described below is arranged. Figure 19 ) in the first circuit area PCA1.

[0160] A fifth insulating layer 115 may be disposed over the fourth insulating layer 114 to cover the fourth conductive layer, and a fifth conductive layer may be disposed over the fifth insulating layer 115. Figures 18 to 20 As shown in FIG, the fifth conductive layer may include vertical conductive lines and connecting electrodes 281 and 283. For ease of illustration and explanation, Figures 18 to 20 Only some of the lower conductive lines connected to the fifth conductive layer are shown.

[0161] The connection electrode 281 may be connected (eg, electrically connected) to the connection electrode 275 through the contact hole 61 passing through the fifth insulating layer 115 , and may be connected (eg, electrically connected) to the source region S6 of the sixth transistor T6 .

[0162] The connection electrode 283 may be connected (eg, electrically connected) to the connection electrode 270 through the contact hole 62 passing through the fifth insulating layer 115. The connection electrode 283 may be arranged to cover and overlap the connection electrode 273 as a node electrode.

[0163] The vertical conductive lines may include a first vertical driving voltage line PLv, a first vertical initialization voltage line VL11v, a second vertical initialization voltage line VL12v, a second vertical driving voltage line ELv, and a vertical reference voltage line VRLv. Each of the vertical conductive lines may extend in the y-direction and may be arranged to be spaced apart from each other in the x-direction in the first to third circuit areas PCA1 to PCA3.

[0164] Four vertical conductive lines can be arranged spaced apart from one another in the x-direction within the first to third circuit areas PCA1 to PCA3. For example, four vertical conductive lines from among the first vertical initialization voltage line VL11v, the second vertical initialization voltage line VL12v, the first vertical drive voltage line PLv, the second vertical drive voltage line ELv, and the vertical reference voltage line VRLv can be arranged spaced apart from one another in the x-direction. The vertical conductive lines can be connected (e.g., electrically connected) to horizontal conductive lines extending in the x-direction. The horizontal conductive lines can include the drive voltage line PL, the 1-1 initialization voltage line VL11, the 1-2 initialization voltage line VL12, and the reference voltage line VRL.

[0165] Figure 18 An example is shown in which a first vertical initialization voltage line VL11v, a first vertical driving voltage line PLv, a second vertical driving voltage line ELv, and a vertical reference voltage line VRLv are sequentially arranged in the x direction in the first to third circuit areas PCA1 to PCA3.

[0166] Figure 19 An example is shown in which the second vertical initialization voltage line VL12v, the first vertical driving voltage line PLv, the second vertical driving voltage line ELv, and the vertical reference voltage line VRLv are sequentially arranged in the x direction in the first to third circuit areas PCA1 to PCA3.

[0167] Figure 20 An example is shown in which the second vertical initialization voltage line VL12v, the first vertical drive voltage line PLv, the first vertical drive voltage line PLv, and the vertical reference voltage line VRLv are sequentially arranged in the x direction in the first circuit area PCA1 to the third circuit area PCA3. A pair of first vertical drive voltage lines PLv adjacent to each other can be connected by a connecting portion BR. The pair of first vertical drive voltage lines PLv can be formed integrally. According to an embodiment, the connecting portion BR can be arranged in every other row. For example, as shown in FIG. Figure 20 As shown in , the pair of first vertical driving voltage lines PLv may be connected to each other through the connection portion BR in the odd or even rows and may be spaced apart from each other without the connection portion BR in the even or odd rows.

[0168] The first vertical initialization voltage line VL11v may overlap with the data line DL arranged in the first circuit area PCA1. The first vertical initialization voltage line VL11v may be connected (e.g., electrically connected) to the connection electrode 276 arranged in the first circuit area PCA1 through the contact hole 63 passing through the fifth insulating layer 115. Because the connection electrode 276 may be connected (e.g., electrically connected) to the 1-1 initialization voltage line VL11, the 1-1 initialization voltage line VL11 may have a mesh structure in the display area DA.

[0169] The second vertical initialization voltage line VL12v may overlap with the data line DL arranged in the first circuit area PCA1. The second vertical initialization voltage line VL12v may be connected (e.g., electrically connected) to a connection electrode 277 arranged in the first circuit area PCA1 through a contact hole 66 passing through the fifth insulating layer 115. Because the connection electrode 277 may be connected (e.g., electrically connected) to the first-second initialization voltage line VL12, the first-second initialization voltage line VL12 may have a mesh structure in the display area DA.

[0170] The first vertical driving voltage line PLv may overlap with the data line DL arranged in the second circuit area PCA2. The first vertical driving voltage line PLv may be connected (e.g., electrically connected) to the connection electrode 274 arranged in the second circuit area PCA2 through the contact hole 64 passing through the fifth insulating layer 115. Because the connection electrode 274 may be connected (e.g., electrically connected) to the driving voltage line PL, the driving voltage line PL may have a mesh structure in the display area DA.

[0171] The second vertical driving voltage line ELv may overlap with the data line DL arranged in the third circuit area PCA3. The second vertical driving voltage line ELv may be connected (eg, electrically connected) to the common voltage supply line 13 (see FIG. 1 ) arranged in the peripheral area PA. Figure 2 ).

[0172] A vertical reference voltage line VRLv may be disposed in the third circuit area PCA3. The vertical reference voltage line VRLv may be connected (e.g., electrically connected) to a connection electrode 272 disposed in the third circuit area PCA3 via a contact hole 65 passing through the fifth insulating layer 115. Because the connection electrode 272 may be connected (e.g., electrically connected) to the reference voltage line VRL, the reference voltage line VRL may have a mesh structure in the display area DA.

[0173] like Figure 18As shown in , each of the vertical conductive lines may include a region having a first width Wv1 in the x-direction and a region having a second width Wv2 greater than the first width Wv1. By increasing the width of the conductive line, the resistance of the conductive line can be reduced, and thus, the voltage drop of the signal transmitted through the conductive line can be reduced.

[0174] Although not shown, voltage supply lines connected (e.g., electrically connected) to the horizontal conductive lines and / or vertical conductive lines may also be arranged in the peripheral area PA. The voltage supply lines may be arranged on at least one of the upper side, lower side, left side, and right side of the display area DA.

[0175] The connection electrodes having the same function and corresponding to the first to third circuit areas PCA1 to PCA3 may have shapes and positions different from each other according to positions of lines arranged in the first to third circuit areas PCA1 to PCA3.

[0176] A sixth insulating layer 116 may be disposed over the fifth insulating layer 115 to cover the fifth conductive layer, and organic light emitting diodes (OLEDs: OLED1, OLED2, OLED3) as display elements may be disposed over the sixth insulating layer 116. The organic light emitting diode OLED may include a pixel electrode 311, an opposing electrode 315, and an intermediate layer between the pixel electrode 311 and the opposing electrode 315.

[0177] The pixel electrode 311 may be connected (eg, electrically connected) to the connection electrode 281 as the lower conductive pattern through the contact hole 71 of the sixth insulating layer 116 and may be connected (eg, electrically connected) to the first transistor T1. Figure 21 As shown in FIG, the pixel electrode 311 of the pixel circuit connected to the first pixel PX1 can be connected (e.g., electrically connected) to the connection electrode 281 arranged in the first circuit area PCA1, and thus can be connected (e.g., electrically connected) to the first transistor T1. The pixel electrode 311 of the pixel circuit connected to the second pixel PX2 can be connected (e.g., electrically connected) to the connection electrode 281 arranged in the second circuit area PCA2, and thus can be connected (e.g., electrically connected) to the first transistor T1. The pixel electrode 311 of the pixel circuit connected to the third pixel PX3 can be connected (e.g., electrically connected) to the connection electrode 281 arranged in the third circuit area PCA3, and thus can be connected (e.g., electrically connected) to the first transistor T1.

[0178] like Figure 22As shown in , the auxiliary electrode layer AE may also be arranged on the same layer as the pixel electrode 311. The auxiliary electrode layer AE may be arranged between the pixel electrodes 311 of the third pixel PX3. The auxiliary electrode layer AE may be in contact with the counter electrode 315 in the display area DA. According to an embodiment, the auxiliary electrode layer AE may be connected (e.g., electrically connected) to the second vertical driving voltage line ELv in the display area DA.

[0179] like Figure 23 As shown in FIG, a seventh insulating layer 117, which is a pixel defining layer covering an edge of the pixel electrode 311, may be disposed over the pixel electrode 311. An opening 117OP exposing a portion of the pixel electrode 311 and defining an emission region may be defined in the seventh insulating layer 117. The seventh insulating layer 117 may be a single organic insulating layer or a plurality of organic insulating layers and / or a single inorganic insulating layer or a plurality of inorganic insulating layers.

[0180] The intermediate layer may include an emission layer 313 and a first functional layer below the emission layer 313 and / or a second functional layer above the emission layer 313. The first functional layer may be a hole transport layer HTL. Alternatively, the first functional layer may include a hole injection layer HIL and a hole transport layer HTL. The second functional layer may include an electron transport layer ETL and / or an electron injection layer EIL. The first functional layer and the second functional layer may be formed integrally to correspond to the organic light emitting diode OLED included in the display area DA. The first functional layer or the second functional layer may be omitted. Figure 21 Shown are an emission layer 313 a connected (e.g., electrically connected) to the organic light emitting diode OLED1 of the pixel circuit arranged in the first circuit area PCA1, an emission layer 313 b connected (e.g., electrically connected) to the organic light emitting diode OLED2 of the pixel circuit arranged in the second circuit area PCA2, and an emission layer 313 c connected (e.g., electrically connected) to the organic light emitting diode OLED3 of the pixel circuit arranged in the third circuit area PCA3.

[0181] Figure 22 The emission area EA and the pixel electrode 311 of each of the first to third pixels PX1 to PX3 are shown. The emission area EA may be a region in which the emission layer 313 of the organic light emitting diode OLED is disposed. The emission area EA may be defined by the opening 117OP of the seventh insulating layer 117. Since the emission layer 313 is disposed on the pixel electrode 311, Figure 22 The arrangement of the emission areas EA shown in FIG. 3 may indicate the arrangement of the pixel electrodes 311 or the arrangement of the pixels PX.

[0182] The emission area EA may have a polygonal shape such as a quadrangular shape or an octagonal shape, a circular shape, an elliptical shape, etc., wherein the polygonal shape may include a shape having rounded corners (vertices).

[0183] The emission area EA of the first pixel PX1 and the emission area EA of the second pixel PX2 may be arranged adjacent to each other in the y direction, and the emission area EA of the third pixel PX3 may be arranged adjacent to the emission area EA of the first pixel PX1 and the emission area EA of the second pixel PX2 in the x direction. Therefore, the emission area EA of the first pixel PX1 and the emission area EA of the second pixel PX2 may be alternately arranged in the y direction along the imaginary straight line ISL1, and the emission area EA of the third pixel PX3 may be repeatedly arranged in the y direction along the imaginary straight line ISL2.

[0184] The length of each of the emission areas EA of the first to third pixels PX1 to PX3 in the x-direction and the length in the y-direction may be the same as or different from each other. For example, the emission area EA of the first pixel PX1 may have a square shape, and the emission areas EA of the second pixel PX2 and the emission areas EA of the third pixel PX3 may have a rectangular shape with a long side in the y-direction. The length of the emission area EA of the third pixel PX3 in the y-direction may be equal to or greater than the sum of the lengths of the emission areas EA of the first pixel PX1 and the second pixel PX2 in the y-direction.

[0185] The emission area EA of the first pixel PX1, the emission area EA of the second pixel PX2, and the emission area EA of the third pixel PX3 may have different areas (sizes) from each other. According to an embodiment, the emission area EA of the third pixel PX3 may have a larger area than the emission area EA of the first pixel PX1. The emission area EA of the third pixel PX3 may have a larger area than the emission area EA of the second pixel PX2. The emission area EA of the second pixel PX2 may have a larger area than the emission area EA of the first pixel PX1.

[0186] The opposite electrode 315 may be integrally formed to correspond to the organic light emitting diode OLED disposed in the display area DA.

[0187] refer to Figure 23 , the source region S1 of the first transistor T1 may be connected (e.g., electrically connected) to the second electrode layer 220 and the connection electrode 270. The third electrode layer 230 and the connection electrode 270 may correspond to the middle first electrode C11m and the middle second electrode C12m of the first capacitor C1, respectively. The driving voltage line PL and the second electrode layer 220 may correspond to the first electrode C21 and the second electrode C22 of the second capacitor C2, respectively.

[0188] refer to Figure 24 , the second electrode layer 220 may be arranged below the connection electrode 273 serving as a node electrode, and the connection electrode 283 may be arranged above the connection electrode 273. The connection electrode 283 may almost completely cover the connection electrode 273, and the second electrode layer 220 may almost completely cover the connection electrode 273. The connection electrode 283 may serve as an upper shielding layer for the connection electrode 273, and the second electrode layer 220 may serve as a lower shielding layer for the connection electrode 273.

[0189] In the case where parasitic capacitance is formed due to the coupling between the connection electrode 273 and the pixel electrode 311 adjacent to the connection electrode 273, the gate-source voltage (Vgs) of the first transistor T1 connected to the connection electrode 273 may change. According to an embodiment, by arranging the connection electrode 283 on a layer between the connection electrode 273 and the pixel electrode 311, the coupling between the pixel electrode 311 and the connection electrode 273 adjacent to each other can be prevented. For example, Figure 24 As shown in FIG, coupling between the connection electrode 273 connected to the first node N1 of the pixel circuit of the second pixel PX2 arranged in the second circuit area PCA2 and the pixel electrode 311 of the third pixel PX3 may be prevented by the connection electrode 283 .

[0190] The second electrode layer 220 and the connection electrode 283 may be connected (e.g., electrically connected) to the source region S1 of the first transistor T1 through the connection electrode 270. The connection electrode 273 may be connected (e.g., electrically connected) to the third electrode layer 230 serving as the first gate electrode G11 of the first transistor T1. The first gate electrode G11 may be connected (e.g., electrically connected) to the first electrode layer 210. Therefore, according to an embodiment, in addition to Figure 23 In addition to the first capacitor C1 shown in FIG, further first capacitors C1 may be formed between the first electrode layer 210 and the second electrode layer 220, between the second electrode layer 220 and the third electrode layer 230, and between the connecting electrode 273 and the connecting electrode 283. The first electrode layer 210 and the second electrode layer 220 may correspond to the lower first electrode C11b and the lower second electrode C12b of the first capacitor C1, respectively. The connecting electrode 273 and the connecting electrode 283 may correspond to the upper first electrode C11t and the upper second electrode C12t of the first capacitor C1, respectively.

[0191] According to an embodiment, by arranging connection electrode 283 and second electrode layer 220 above and below connection electrode 273, respectively, coupling between connection electrode 273 and adjacent conductive layers can be prevented, thereby reducing parasitic capacitance and increasing the capacitance of the storage capacitor. Consequently, the compensation function of the first transistor can be improved, and the brightness difference between adjacent pixels can be minimized.

[0192] Figure 25 is a schematic diagram of a capacitor for each pixel according to an embodiment. Figure 26a It is along Figure 25 Schematic cross-sectional view of the capacitor of the first pixel PX1 taken along line IIIa-IIIa′. Figure 26b It is along Figure 25 Schematic cross-sectional view of the capacitor of the second pixel PX2 taken along line IVa-IVa′. Figure 26c It is along Figure 25 FIG. 1 is a schematic cross-sectional view of the capacitor of the third pixel PX3 taken along line Va-Va′.

[0193] refer to Figure 26a and Figure 26b , the first electrode layer 210 and the driving voltage line PL may be arranged to be spaced apart from each other in each of the first circuit area PCA1 and the second circuit area PCA2 on the substrate 100. The second electrode layer 220 may be arranged on the first insulating layer 111 and may overlap with the first electrode layer 210 and the driving voltage line PL. The third electrode layer 230 may be arranged on the third insulating layer 113 and may overlap with the second electrode layer 220. The connecting electrode 270 and the connecting electrode 273 may be arranged on the fourth insulating layer 114 and may overlap with the third electrode layer 230. The connecting electrode 283 may be arranged on the fifth insulating layer 115 and may overlap with the connecting electrode 273.

[0194] The first capacitor C1 of the first pixel PX1 and the first capacitor C1 of the second pixel PX2 may include a first electrode C11 and a second electrode C12. The first electrode C11 may include a lower first electrode C11b formed by the first electrode layer 210, a middle first electrode C11m formed by the third electrode layer 230, and an upper first electrode C11t formed by the connection electrode 273. Figure 25 As shown in , the lower first electrode C11b and the middle first electrode C11m may be connected to each other (e.g., electrically connected) through the contact hole 31, and the middle first electrode C11m and the upper first electrode C11t may be connected to each other (e.g., electrically connected) through the contact hole 49. The second electrode C12 may include a lower second electrode C12b formed by the second electrode layer 220, an middle second electrode C12m formed by the connection electrode 270, and an upper second electrode C12t formed by the connection electrode 283. Figure 25 As shown in FIG, the lower second electrode C12b and the middle second electrode C12m may be connected to each other (eg, electrically connected) through the contact hole 41, and the middle second electrode C12m and the upper second electrode C12t may be connected to each other (eg, electrically connected) through the contact hole 62.

[0195] The capacitance of the first capacitor C1 may be the sum of the capacitance formed by the lower first electrode C11b and the lower second electrode C12b, the capacitance formed by the lower second electrode C12b and the middle first electrode C11m, the capacitance formed by the middle first electrode C11m and the middle second electrode C12m, and the capacitance formed by the upper first electrode C11t and the upper second electrode C12t. The first capacitor C1 may have a structure in which sub-capacitors formed by conductive lines overlapping each other in the z-direction are connected in parallel to each other, and thus may have (obtain) increased capacitance without increasing the area in the x-direction and y-direction.

[0196] The second capacitor C2 of the first pixel PX1 and the second capacitor C2 of the second pixel PX2 may include a first electrode C21 formed by the driving voltage line PL and a second electrode C22 formed by the second electrode layer 220 .

[0197] The minimum width W1 of the first electrode C21 of the second capacitor C2 of the first pixel PX1 in the y direction and the width W2 of the lower first electrode C11b of the first capacitor C1 in the y direction may be the same as each other. Along line IVa-IVa', the minimum width W1 of the first electrode C21 of the second capacitor C2 of the second pixel PX2 in the y direction may be greater than the width W2 of the lower first electrode C11b of the first capacitor C1 of the second pixel PX2 in the y direction. The minimum width W1 of the first electrode C21 of the second capacitor C2 of the second pixel PX2 in the y direction may be greater than the minimum width W1 of the first electrode C21 of the second capacitor C2 of the first pixel PX1 in the y direction.

[0198] Figure 26a and Figure 26b The first capacitor C1 and the second capacitor C2 shown in FIG. Figure 9 The first capacitor C1 and the second capacitor C2 shown in FIG.

[0199] refer to Figure 26c , the driving voltage line PL may be arranged in the third circuit area PCA3 on the substrate 100. The second electrode layer 220 may be arranged on the first insulating layer 111 and may overlap with the driving voltage line PL. The third electrode layer 230 may be arranged on the third insulating layer 113 and may overlap with the second electrode layer 220. The connecting electrode 270 and the connecting electrode 273 may be arranged on the fourth insulating layer 114 and may overlap with the third electrode layer 230. The connecting electrode 283 may be arranged on the fifth insulating layer 115 and may overlap with the connecting electrode 273.

[0200] The first capacitor C1 of the third pixel PX3 may include a first electrode C11 and a second electrode C12. The first electrode C11 may include a middle first electrode C11m formed by the third electrode layer 230 and an upper first electrode C11t formed by the connection electrode 273. Figure 25 As shown in , the middle first electrode C11m and the upper first electrode C11t may be connected (eg, electrically connected) to each other through the contact hole 49. The second electrode C12 may include a lower second electrode C12b formed by the second electrode layer 220, an middle second electrode C12m formed by the connection electrode 270, and an upper second electrode C12t formed by the connection electrode 283. Figure 25 As shown in FIG, the lower second electrode C12b and the middle second electrode C12m may be connected to each other (eg, electrically connected) through the contact hole 41, and the middle second electrode C12m and the upper second electrode C12t may be connected to each other (eg, electrically connected) through the contact hole 62.

[0201] The capacitance of the first capacitor C1 may be the sum of the capacitance formed by the lower second electrode C12b and the middle first electrode C11m, the capacitance formed by the middle first electrode C11m and the middle second electrode C12m, and the capacitance formed by the upper first electrode C11t and the upper second electrode C12t. The first capacitor C1 may have a structure in which sub-capacitors formed by conductive lines overlapping each other in the z-direction are connected in parallel to each other, and thus may have (obtain) increased capacitance without increasing the area in the x-direction and y-direction.

[0202] The second capacitor C2 of the third pixel PX3 may include a first electrode C21 formed by the driving voltage line PL and a second electrode C22 formed by the second electrode layer 220 .

[0203] A minimum width W1 of the first electrode C21 of the second capacitor C2 of the third pixel PX3 in the y direction may be greater than a minimum width W1 of the first electrode C21 of the second capacitor C2 of the first pixel PX1 and the second pixel PX2 in the y direction.

[0204] Figure 26c The first capacitor C1 and the second capacitor C2 shown in FIG can be Figure 10 The first capacitor C1 and the second capacitor C2 shown in FIG.

[0205] Figure 27 is a schematic diagram of a capacitor for each pixel according to an embodiment. Figure 28a It is along Figure 27 Schematic cross-sectional view of the capacitor of the first pixel PX1 taken along line IIIb-IIIb′. Figure 28b It is along Figure 27Schematic cross-sectional view of the capacitor of the second pixel PX2 taken along line IVb-IVb′. Figure 28c It is along Figure 27 FIG. 1 is a schematic cross-sectional view of the capacitor of the third pixel PX3 taken along line Vb-Vb′.

[0206] refer to Figure 27 , the connection electrode 283 as a shielding layer may be disposed only above the connection electrode 273 , and the second electrode layer 220 may be below the connection electrode 273 without overlapping with the connection electrode 273 .

[0207] refer to Figures 28a to 28c Since the area of ​​the second electrode layer 220 is reduced, the capacitance of the first capacitor C1 of each of the first to third pixels PX1 to PX3 may be smaller than Figures 26a to 26c The capacitance of the first capacitor C1 of each of the first to third pixels PX1 to PX3 is shown in FIG.

[0208] Figure 29 is a schematic diagram of a capacitor for each pixel according to an embodiment. Figure 30a It is along Figure 29 Schematic cross-sectional view of the capacitor of the first pixel PX1 taken along line IIIc-IIIc′. Figure 30b It is along Figure 29 Schematic cross-sectional view of the capacitor of the second pixel PX2 taken along line IVc-IVc′. Figure 30c It is along Figure 29 FIG. 1 is a schematic cross-sectional view of the capacitor of the third pixel PX3 taken along line Vc-Vc′.

[0209] refer to Figure 29 , the connection electrode 283 above the connection electrode 273 may be omitted, and the second electrode layer 220 may overlap the connection electrode 273 below the connection electrode 273 as a shielding layer.

[0210] refer to Figures 28a to 28c Since the connection electrode 283 is omitted, the capacitance of the first capacitor C1 of each of the first to third pixels PX1 to PX3 may be less than Figures 26a to 26c The capacitance of the first capacitor C1 of each of the first to third pixels PX1 to PX3 is shown in FIG.

[0211] Figures 31 to 33 is a schematic plan view of a vertical conductive line according to an embodiment.

[0212] like Figures 31 to 33 As shown in , the arrangement of the four vertical conductive lines can be changed for each unit circuit area PCAu.

[0213] According to the implementation method, Figure 31 As shown in FIG, the first vertical conductive line in the unit circuit area PCAu may be a first vertical initialization voltage line VL11v or a second vertical initialization voltage line VL12v. The fourth vertical conductive line in the unit circuit area PCAu may be a vertical reference voltage line VRLv. The second and third vertical conductive lines in the unit circuit area PCAu may be a pair of first vertical driving voltage lines PLv or a pair of first vertical driving voltage line PLv and second vertical driving voltage line ELv.

[0214] According to the implementation method, Figure 32 As shown in FIG, the first vertical conductive line in the unit circuit area PCAu may be a first vertical initialization voltage line VL11v, a second vertical initialization voltage line VL12v, or a first vertical driving voltage line PLv. The fourth vertical conductive line in the unit circuit area PCAu may be a vertical reference voltage line VRLv. The second vertical conductive line and the third vertical conductive line in the unit circuit area PCAu may be a pair of first vertical driving voltage lines PLv, a pair of second vertical driving voltage lines ELv, or a pair of first vertical driving voltage line PLv and second vertical driving voltage line ELv.

[0215] According to the implementation method, Figure 33 As shown in FIG, the first vertical conductive line in the unit circuit area PCAu may be a first vertical initialization voltage line VL11v or a second vertical initialization voltage line VL12v. The fourth vertical conductive line in the unit circuit area PCAu may be a vertical reference voltage line VRLv. The second vertical conductive line and the third vertical conductive line in the unit circuit area PCAu may be a pair of first vertical driving voltage lines PLv, a pair of first vertical driving voltage line PLv and vertical reference voltage line VRLv, or a pair of second vertical driving voltage line ELv and vertical reference voltage line VRLv.

[0216] According to an embodiment, conductive lines that must have reduced resistance (eg, conductive lines to which signals must be sent with reduced voltage drop) may be arranged additionally. Figures 31 to 33 As shown in , instead of arranging four different vertical conductive lines in the unit circuit area PCAu, one of the first vertical drive voltage line PLv, the second vertical drive voltage line ELv, and the vertical reference voltage line VRLv can be additionally arranged in the second position or the third position in the unit circuit area PCAu. In the case where the same vertical conductive lines are arranged adjacent to each other based on the additional arrangement of the conductive lines, the vertical conductive lines can be connected to each other. For example, a pair of first vertical drive voltage lines PLv adjacent to each other, a pair of second vertical drive voltage lines ELv adjacent to each other, or a pair of vertical reference voltage lines VRLv adjacent to each other can be formed integrally with each other and can be connected by, for example, Figure 20The connecting portions BR shown in are connected to each other.

[0217] The first vertical initialization voltage line VL11v can be connected (e.g., electrically connected) to the 1-1 initialization voltage line VL11 via a connection electrode 276 disposed in the circuit region where the first vertical initialization voltage line VL11v is disposed. The second vertical initialization voltage line VL12v can be connected (e.g., electrically connected) to the 1-2 initialization voltage line VL12 via a connection electrode 276 disposed in the circuit region where the second vertical initialization voltage line VL12v is disposed. The first vertical drive voltage line PLv can be connected (e.g., electrically connected) to the drive voltage line PL via a connection electrode 274 disposed in the circuit region where the first vertical drive voltage line PLv is disposed. The second vertical drive voltage line ELv can be connected (e.g., electrically connected) to the counter electrode 315 via the auxiliary electrode layer AE disposed in the display area DA. The vertical reference voltage line VRLv can be connected (e.g., electrically connected) to the reference voltage line VRL via a connection electrode 272 disposed in the circuit region where the vertical reference voltage line VRLv is disposed.

[0218] Figures 34a to 35b is a schematic cross-sectional view illustrating a structure of a display element according to an embodiment.

[0219] The organic light emitting diode OLED as a display element according to the embodiment may include a pixel electrode 311 , an opposite electrode 315 , and an intermediate layer 313 m between the pixel electrode 311 (first electrode, anode) and the opposite electrode 315 (second electrode, cathode).

[0220] The pixel electrode 311 may include a transmissive conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and / or aluminum zinc oxide (AZO). The pixel electrode 311 may include a reflective layer containing Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or compounds thereof. For example, the pixel electrode 311 may have a three-layer structure of ITO / Ag / ITO.

[0221] The counter electrode 315 may be disposed on the intermediate layer 313m. The counter electrode 315 may include a metal, alloy, conductive compound, or any combination thereof having a low work function. For example, the counter electrode 315 may include Li, Ag, Mg, Al, Al-Li, Ca, Mg-In, Mg-Ag, Yb, Ag-Yb, ITO, IZO, or any combination thereof. The counter electrode 315 may include a transmissive electrode, a semi-transmissive semi-reflective electrode, or a reflective electrode.

[0222] The intermediate layer 313m may include a high molecular weight organic material or a low molecular weight organic material that emits light of a certain color. In addition to various organic materials, the intermediate layer 313m may also include a metal-containing compound such as an organic metal compound and an inorganic material such as a quantum dot.

[0223] According to an embodiment, the intermediate layer 313m may include an emission layer and a first functional layer and a second functional layer below and above the emission layer, respectively. The first functional layer may include, for example, a hole transport layer HTL, or a hole transport layer HTL and a hole injection layer HIL. The second functional layer may include an electron transport layer ETL and / or an electron injection layer EIL. The first functional layer or the second functional layer may be omitted. The first functional layer and the second functional layer may be formed integrally to correspond to the organic light emitting diode OLED included in the display area DA.

[0224] According to embodiments, the intermediate layer 313m may include at least two emission units and a charge generation layer CGL, wherein the at least two emission units may be stacked between the pixel electrode 311 and the opposing electrode 315, and the charge generation layer CGL may be disposed between the at least two emission units. When the intermediate layer 313m includes the emission units and the charge generation layer CGL, the organic light emitting diode OLED may be a tandem light emitting device. When the organic light emitting diode OLED has a stacked structure of emission units, the organic light emitting diode OLED may have improved color purity and emission efficiency.

[0225] An emissive unit may include an emissive layer and a first functional layer and a second functional layer disposed below and above the emissive layer, respectively. The charge generation layer (CGL) may include a negative charge generation layer and a positive charge generation layer. The negative charge generation layer and the positive charge generation layer further enhance the luminous efficiency of an organic light-emitting diode (OLED), a tandem light-emitting device comprising an emissive layer.

[0226] The negative charge generation layer may be an n-type charge generation layer. The negative charge generation layer may provide electrons. The negative charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material. The positive charge generation layer may be a p-type charge generation layer. The positive charge generation layer may provide holes. The positive charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material.

[0227] According to the implementation method, Figure 34aAs shown in , the organic light emitting diode OLED may include a first emission unit EU1 including a first emission layer EML1 and a second emission unit EU2 including a second emission layer EML2, and the first emission unit EU1 and the second emission unit EU2 are stacked. The charge generation layer CGL may be provided between the first emission unit EU1 and the second emission unit EU2. For example, the organic light emitting diode OLED may include a pixel electrode 311, a first emission layer EML1, a charge generation layer CGL, a second emission layer EML2, and an opposing electrode 315 stacked on each other. The first functional layer and the second functional layer may be included below and above the first emission layer EML1, respectively. The first functional layer and the second functional layer may be included below and above the second emission layer EML2, respectively. The first emission layer EML1 may be a blue emission layer, and the second emission layer EML2 may be a yellow emission layer.

[0228] According to the implementation method, Figure 34b As shown in , the organic light emitting diode OLED may include a first emission unit EU1 and a third emission unit EU3 including a first emission layer EML1, and a second emission unit EU2 including a second emission layer EML2. The first charge generation layer CGL1 may be disposed between the first emission unit EU1 and the second emission unit EU2, and the second charge generation layer CGL2 may be disposed between the second emission unit EU2 and the third emission unit EU3. For example, the organic light emitting diode OLED may include a pixel electrode 311, a first emission layer EML1, a first charge generation layer CGL1, a second emission layer EML2, a second charge generation layer CGL2, a first emission layer EML1, and an opposing electrode 315 stacked on each other. The first functional layer and the second functional layer may be included below and above the first emission layer EML1, respectively. The first functional layer and the second functional layer may be included below and above the second emission layer EML2, respectively. The first emission layer EML1 may be a blue emission layer, and the second emission layer EML2 may be a yellow emission layer.

[0229] According to an embodiment, the organic light emitting diode OLED may include a second emission unit EU2, and the second emission unit EU2 may further include a third emission layer EML3 and / or a fourth emission layer EML4 directly contacting the second emission layer EML2 below and / or above the second emission layer EML2. Here, direct contact may mean that no layer is arranged between the second emission layer EML2 and the third emission layer EML3 and / or no layer is arranged between the second emission layer EML2 and the fourth emission layer EML4. The third emission layer EML3 may be a red emission layer, and the fourth emission layer EML4 may be a green emission layer.

[0230] For example, Figure 34cAs shown in , the organic light emitting diode OLED may include a pixel electrode 311, a first emission layer EML1, a first charge generation layer CGL1, a third emission layer EML3, a second emission layer EML2, a second charge generation layer CGL2, a first emission layer EML1, and an opposite electrode 315 stacked on each other. Figure 34d As shown in the figure, the organic light emitting diode OLED may include a pixel electrode 311, a first emission layer EML1, a first charge generation layer CGL1, a third emission layer EML3, a second emission layer EML2, a fourth emission layer EML4, a second charge generation layer CGL2, a first emission layer EML1 and a relative electrode 315 stacked on each other.

[0231] Figure 35a It shows Figure 34c A cross-sectional view of an example of an organic light emitting diode OLED, and Figure 35b It shows Figure 34d A cross-sectional view of an example of an organic light emitting diode OLED.

[0232] refer to Figure 35a The organic light emitting diode OLED may include a stacked first emission unit EU1, a second emission unit EU2, and a third emission unit EU3. A first charge generation layer CGL1 may be disposed between the first emission unit EU1 and the second emission unit EU2, and a second charge generation layer CGL2 may be disposed between the second emission unit EU2 and the third emission unit EU3. Each of the first charge generation layer CGL1 and the second charge generation layer CGL2 may include a negative charge generation layer nCGL and a positive charge generation layer pCGL.

[0233] The first emission unit EU1 may include a blue emission layer BEML. The first emission unit EU1 may further include a hole injection layer HIL and a hole transport layer HTL between the pixel electrode 311 and the blue emission layer BEML. According to an embodiment, a p-type doped layer may further be included between the hole injection layer HIL and the hole transport layer HTL. The p-type doped layer may be formed by doping the hole injection layer HIL with a p-type dopant material. According to an embodiment, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may further be included between the blue emission layer BEML and the hole transport layer HTL. The blue light auxiliary layer may improve the emission efficiency of the blue emission layer BEML. The blue light auxiliary layer may improve the emission efficiency of the blue emission layer BEML by adjusting the hole charge balance. The electron blocking layer may prevent electrons from being injected into the hole transport layer HTL. The buffer layer may compensate for the resonance distance according to the wavelength of light emitted from the emission layer.

[0234] The second emission unit EU2 may include a yellow emission layer YEML and a red emission layer REML directly contacting the yellow emission layer YEML below the yellow emission layer YEML. The second emission unit EU2 may further include a hole transport layer HTL between the red emission layer REML and the positive charge generation layer pCGL of the first charge generation layer CGL1, and may further include an electron transport layer ETL between the yellow emission layer YEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0235] The third emission unit EU3 may include a blue emission layer BEML. The third emission unit EU3 may also include a hole transport layer HTL between the blue emission layer BEML and the positive charge generation layer pCGL of the second charge generation layer CGL2. The third emission unit EU3 may also include an electron transport layer ETL and an electron injection layer EIL between the blue emission layer BEML and the opposite electrode 315. The electron transport layer ETL may include a single layer or multiple layers. According to an embodiment, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may also be included between the blue emission layer BEML and the hole transport layer HTL. At least one of a hole blocking layer and a buffer layer may also be included between the blue emission layer BEML and the electron transport layer ETL. The hole blocking layer may prevent holes from being injected into the electron transport layer ETL.

[0236] Figure 35b The organic light emitting diode OLED shown in FIG can have Figure 35a The organic light emitting diode OLED shown in FIG has a stacked structure of a second emission unit EU2 that is different from the stacked structure of the second emission unit EU2, and in addition to the stacked structure of the second emission unit EU2, it may have the same Figure 35a The same structure of the organic light emitting diode OLED shown in the reference Figure 35b The second emission unit EU2 may include a yellow emission layer YEML, a red emission layer REML directly contacting the yellow emission layer YEML below the yellow emission layer YEML, and a green emission layer GEML directly contacting the yellow emission layer YEML above the yellow emission layer YEML. The second emission unit EU2 may also include a hole transport layer HTL between the red emission layer REML and the positive charge generation layer pCGL of the first charge generation layer CGL1, and may also include an electron transport layer ETL between the green emission layer GEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0237] Figure 36 is a schematic cross-sectional view illustrating a structure of a pixel of a display device according to an embodiment.

[0238] refer to Figure 36The display device may include pixels. The pixels may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. Each of the first pixel PX1 to the third pixel PX3 may include a pixel electrode 311, an opposing electrode 315, and an intermediate layer 313m. According to an embodiment, the first pixel PX1 may include a red pixel, the second pixel PX2 may include a green pixel, and the third pixel PX3 may include a blue pixel. Here, the pixel may include an organic light emitting diode (OLED) as a display element, and the organic light emitting diode OLED of each pixel may be connected (e.g., electrically connected) to the pixel circuit.

[0239] The pixel electrode 311 may be provided in each of the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 , respectively.

[0240] The middle layer 313m of the organic light emitting diode OLED of each of the first to third pixels PX1 to PX3 may include a stacked first and second emission units EU1 to EU2, and a charge generation layer CGL between the first and second emission units EU1 and EU2. The charge generation layer CGL may include a negative charge generation layer nCGL and a positive charge generation layer pCGL. The charge generation layer CGL may be a common layer continuously formed throughout the first to third pixels PX1 to PX3.

[0241] The first emission unit EU1 of the first pixel PX1 may include a hole injection layer HIL, a hole transport layer HTL, a red emission layer REML, and an electron transport layer ETL stacked on each other on the pixel electrode 311. The first emission unit EU1 of the second pixel PX2 may include a hole injection layer HIL, a hole transport layer HTL, a green emission layer GEML, and an electron transport layer ETL stacked on each other on the pixel electrode 311. The first emission unit EU1 of the third pixel PX3 may include a hole injection layer HIL, a hole transport layer HTL, a blue emission layer BEML, and an electron transport layer ETL stacked on each other on the pixel electrode 311. Each of the hole injection layer HIL, the hole transport layer HTL, and the electron transport layer ETL of each of the first emission units EU1 may be a common layer continuously formed throughout the first to third pixels PX1 to PX3.

[0242] The second emission unit EU2 of the first pixel PX1 may include a hole transport layer HTL, an auxiliary layer AXL, a red emission layer REML, and an electron transport layer ETL stacked on each other on the charge generation layer CGL. The second emission unit EU2 of the second pixel PX2 may include a hole transport layer HTL, a green emission layer GEML, and an electron transport layer ETL stacked on each other on the charge generation layer CGL. The second emission unit EU2 of the third pixel PX3 may include a hole transport layer HTL, a blue emission layer BEML, and an electron transport layer ETL stacked on each other on the charge generation layer CGL. Each of the hole transport layer HTL and the electron transport layer ETL of each of the second emission units EU2 may be a common layer continuously formed throughout the first to third pixels PX1 to PX3. According to an embodiment, in the second emission units EU2 of the first to third pixels PX1 to PX3, at least one of a hole blocking layer and a buffer layer may further be included between the emission layer and the electron transport layer ETL.

[0243] The thickness H1 of the red emission layer REML, the thickness H2 of the green emission layer GEML, and the thickness H3 of the blue emission layer BEML can be determined based on the resonance distance. The auxiliary layer AXL can be a region added to adjust the resonance distance and can include a resonance-assisting material. For example, the auxiliary layer AXL can include the same material as the hole transport layer HTL.

[0244] Figure 36 The auxiliary layer AXL is shown to be included only in the first pixel PX1. However, the embodiment is not limited thereto. For example, the auxiliary layer AXL may be provided in at least one of the first to third pixels PX1 to PX3 to adjust the resonance distance of at least one of the first to third pixels PX1 to PX3.

[0245] The display device may further include a capping layer 317 disposed outside the opposing electrode 315. The capping layer 317 may improve emission efficiency based on the principle of constructive interference. Therefore, since the light extraction efficiency of the organic light emitting diode OLED is improved, the emission efficiency of the organic light emitting diode OLED may also be improved.

[0246] Although the embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and details may be made in the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, the true technical protection scope of the present invention should be determined by the technical concepts of the appended patent claims.

Claims

1. A display device comprising: A first transistor comprising: a first gate electrode; and a first semiconductor layer; A second transistor comprising: a second gate electrode; and a second semiconductor layer; a node electrode connecting the first transistor to the second transistor; a first conductive layer disposed above the node electrode and overlapping the node electrode in a plan view; and The pixel electrode is disposed above the first conductive layer and near the node electrode.

2. The display device according to claim 1, wherein The node electrode connects the first gate electrode of the first transistor to one end of the second semiconductor layer of the second transistor.

3. The display device according to claim 2, wherein: The first conductive layer is connected to one end of the first semiconductor layer of the first transistor.

4. The display device according to claim 3, wherein The node electrode is provided on a layer between the first gate electrode of the first transistor and the first conductive layer.

5. The display device according to claim 3, further comprising: a second conductive layer connected to one end of the first semiconductor layer of the first transistor, wherein The node electrode is provided on a layer between the first conductive layer and the second conductive layer, and The first conductive layer overlaps the second conductive layer in a plan view.

6. The display device according to claim 5, further comprising: A first electrode is provided on the substrate, wherein The first electrode is provided on a layer between the substrate and the second conductive layer, The second conductive layer overlaps with the first electrode in a plan view, and The first gate electrode of the first transistor overlaps with the second conductive layer in a plan view.

7. The display device according to claim 6, wherein: The second conductive layer overlaps with a channel region of the first semiconductor layer of the first transistor in a plan view.

8. The display device according to claim 6, further comprising: a first conductive line connected to the first electrode and extending in a first direction; as well as A second conductive line is connected to the other end of the second semiconductor layer of the second transistor and extends in a second direction.

9. The display device according to claim 8, further comprising: a first vertical conductive line connected to the first conductive line and extending in the second direction perpendicular to the first direction; as well as A second vertical conductive line is connected to the second conductive line and extends in the second direction.

10. The display device according to claim 9, wherein The first vertical conductive line, the second vertical conductive line, and the second conductive layer are disposed on the same layer.

11. The display device according to claim 6, further comprising: The second electrode, wherein The second electrode and the first electrode are provided on the same layer, and The second electrode is connected to the node electrode.

12. A display device comprising: a node electrode connecting the driving transistor to the switching transistor in each of a first circuit region in which the first pixel circuit is provided and a second circuit region in which the second pixel circuit is provided; as well as a first conductive layer disposed above the node electrode and overlapping the node electrode in a plan view; The pixel electrode connected to the driving transistor in the second circuit region is arranged near the node electrode in the first circuit region.

13. The display device according to claim 12, wherein: The node electrode connects the gate electrode of the driving transistor to one end of the semiconductor layer of the switching transistor.

14. The display device according to claim 13, wherein: The first conductive layer is connected to one end of the semiconductor layer of the driving transistor.

15. The display device according to claim 14, wherein The node electrode is provided on a layer between the gate electrode of the driving transistor and the first conductive layer.

16. The display device according to claim 14, further comprising: a second conductive layer connected to the one end of the semiconductor layer of the driving transistor in each of the first circuit region and the second circuit region, wherein The node electrode is provided on a layer between the first conductive layer and the second conductive layer, The first conductive layer overlaps with the second conductive layer in a plan view, and The gate electrode of the driving transistor overlaps with the second conductive layer in a plan view.

17. The display device according to claim 16, further comprising: A first electrode and a second electrode are arranged to be spaced apart from each other in the first circuit region, wherein The first electrode and the second electrode are provided on a layer between the substrate and the second conductive layer provided in the first circuit region, The second conductive layer provided in the first circuit region overlaps the first electrode and the second electrode in a plan view, The first electrode is connected to a driving voltage line through which a driving voltage is supplied, and The second electrode is connected to the node electrode provided in the first circuit region.

18. The display device according to claim 17, further comprising: A third electrode is provided in the second circuit region, wherein The third electrode and the first electrode are provided on the same layer, The second conductive layer provided in the second circuit region overlaps with the third electrode in a plan view, and The third electrode is connected to the driving voltage line.

19. The display device according to claim 18, wherein An overlapping area of ​​the first electrode and the second conductive layer in the first circuit region is different from an overlapping area of ​​the third electrode and the second conductive layer in the second circuit region.

20. The display device according to claim 18, further comprising: A vertical conductive line is connected to the driving voltage line and extends in a direction perpendicular to an extending direction of the driving voltage line.

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