Display device

Abstract

The display device includes: a substrate; a polycrystalline semiconductor layer including a channel of the driving transistor and a channel of the seventh transistor; a gate electrode of the driving transistor overlapping with its channel; a gate electrode of the seventh transistor overlapping with its channel; an oxide semiconductor layer including a channel of the fourth transistor; a gate electrode of the fourth transistor overlapping with its channel; a first initialization voltage line connected to a first electrode of the fourth transistor, the first initialization voltage line and a gate electrode of the fourth transistor being on the same layer; and a second initialization voltage line connected to a second electrode of the seventh transistor, the second initialization voltage line and the first initialization voltage line being on different layers from each other.

Description

[0001] This application is a divisional application of the patent application with application number 202110208318.9 and title “Display Device” filed on February 24, 2021.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0027043, filed on March 4, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0004] The present disclosure relates to a display device, and more particularly, to a display device including a transistor including a polysilicon semiconductor and a transistor including an oxide semiconductor. Background Art

[0005] An organic light-emitting device includes two electrodes and an organic emission layer disposed between the two electrodes, and electrons injected from one electrode combine with holes injected from the other electrode in the organic emission layer to form excitons. The excitons transition from an excited state to a ground state to output energy and emit light.

[0006] The organic light emitting device includes a plurality of pixels including organic light emitting diodes (OLEDs) that are self-luminous devices, and a plurality of transistors and at least one capacitor for driving the organic light emitting diodes are formed on the corresponding pixels. The plurality of transistors include switching transistors and driving transistors.

[0007] As the number of pixels increases to improve the resolution of organic light-emitting devices and high-speed driving is performed to achieve stable video, the aperture ratio may decrease, the current density may increase, and the driving voltage may increase. Accordingly, stains may occur and the reliability of components such as transistors may deteriorate.

[0008] The above information disclosed in this Background section is only for enhancement of understanding of the background of the technology and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art. Summary of the Invention

[0009] The described technology aims to drive a display device in a stable manner, improve reliability, and reduce power consumption.

[0010] According to an exemplary embodiment of the present invention, a display device includes: a substrate; a polycrystalline semiconductor layer located on the substrate, the polycrystalline semiconductor layer including a channel, a first electrode, and a second electrode of a driving transistor and a channel, a first electrode, and a second electrode of a seventh transistor; a gate electrode of the driving transistor, overlapping with the channel of the driving transistor; a gate electrode of the seventh transistor, overlapping with the channel of the seventh transistor; an oxide semiconductor layer located on the substrate, the oxide semiconductor layer including a channel, a first electrode, and a second electrode of a fourth transistor; a gate electrode of the fourth transistor, overlapping with the channel of the fourth transistor; a first initialization voltage line connected to the first electrode of the fourth transistor, the first initialization voltage line and the gate electrode of the fourth transistor being located on the same layer; and a second initialization voltage line connected to the second electrode of the seventh transistor, the second initialization voltage line and the first initialization voltage line being located on different layers from each other.

[0011] The first initialization voltage line overlaps with the second initialization voltage line.

[0012] The display device further includes: a scan line overlapping the first initialization voltage line and the second initialization voltage line; a data line overlapping the first initialization voltage line and the second initialization voltage line; and a second transistor connected to the scan line and the data line.

[0013] The display device further includes a connection electrode for connecting the first initialization voltage line and the first electrode of the fourth transistor.

[0014] The display device further includes an insulating layer located between the first initialization voltage line and the connecting electrode and between the first electrode of the fourth transistor and the connecting electrode, the insulating layer including a first opening exposing the first initialization voltage line and a second opening exposing the first electrode of the fourth transistor, the connecting electrode is connected to the first initialization voltage line through the first opening, and the connecting electrode is connected to the first electrode of the fourth transistor through the second opening.

[0015] The connection electrode and the data line are disposed on the same layer, and the connection electrode overlaps the first initialization voltage line and the first electrode of the fourth transistor.

[0016] The display device further includes a connection electrode for connecting the second initialization voltage line and the second electrode of the seventh transistor.

[0017] The display device further includes an insulating layer located between the second initialization voltage line and the connecting electrode and between the second electrode of the seventh transistor and the connecting electrode, the insulating layer including a first opening exposing the second initialization voltage line and a second opening exposing the second electrode of the seventh transistor, the connecting electrode is connected to the second initialization voltage line through the first opening, and the connecting electrode is connected to the second electrode of the seventh transistor through the second opening.

[0018] The connection electrode and the data line are disposed on the same layer, and the connection electrode overlaps the second initialization voltage line and the second electrode of the seventh transistor.

[0019] A first initialization voltage is applied to the first electrode of the fourth transistor via a first initialization voltage line, a second initialization voltage is applied to the second electrode of the seventh transistor via a second initialization voltage line, and the first initialization voltage may be different from the second initialization voltage.

[0020] The display device further includes a first storage electrode overlapping with the gate electrode of the driving transistor, the second initialization voltage line and the first storage electrode are located on the same layer, the oxide semiconductor layer further includes a channel of the third transistor, the first electrode and the second electrode, and the channel of the third transistor and the channel of the fourth transistor are located on the same layer.

[0021] The display device further includes a light blocking layer of the fourth transistor overlapping with a channel of the fourth transistor, the light blocking layer of the fourth transistor and the first storage electrode being located on the same layer.

[0022] The display device further includes a gate electrode of the third transistor overlapping with the channel of the third transistor, a light blocking layer of the third transistor overlapping with the channel of the third transistor, the light blocking layer of the third transistor and the first storage electrode are located on the same layer, and the connecting electrode connects the second electrode of the driving transistor and the first electrode of the third transistor.

[0023] The display device includes a plurality of pixels, each of the plurality of pixels includes a driving transistor, a fourth transistor, and a seventh transistor, and the plurality of pixels have the same shape as one another.

[0024] According to an exemplary embodiment of the present invention, a display device includes: a light-emitting diode connected between a driving voltage line for applying a driving voltage to an anode of the light-emitting diode and a common voltage line for applying a common voltage to a cathode of the light-emitting diode; a driving transistor connected between the driving voltage line and the anode of the light-emitting diode and configured to supply a driving current to the light-emitting diode; a second transistor connected between a first electrode of the driving transistor connected to the driving voltage line and a data line to which a data voltage is applied; a third transistor connected between a second electrode of the driving transistor connected to the light-emitting diode and a gate electrode of the driving transistor; a fourth transistor connected between the gate electrode of the driving transistor and a first initialization voltage line to which a first initialization voltage is applied; a seventh transistor connected between the anode of the light-emitting diode and a second initialization voltage line to which a second initialization voltage is applied; and a storage capacitor connected between the driving voltage line and the gate electrode of the driving transistor. The driving transistor and the second transistor include a polycrystalline semiconductor layer, and the third transistor and the fourth transistor may include an oxide semiconductor layer.

[0025] The first initialization voltage line overlaps the second initialization voltage line.

[0026] The display device further includes a scan line connected to the second transistor and receiving a scan signal. The scan line overlaps the first initialization voltage line and the second initialization voltage line.

[0027] The display device further includes a first connection electrode connecting the first initialization voltage line and the fourth transistor, and a second connection electrode connecting the second initialization voltage line and the seventh transistor.

[0028] The driving transistor, the second transistor, and the seventh transistor are p-type transistors, and the third transistor and the fourth transistor are n-type transistors.

[0029] The display device further includes a fifth transistor connected between the driving voltage line and the first electrode of the driving transistor, and a sixth transistor connected between the second electrode of the driving transistor and the light emitting diode.

[0030] According to exemplary embodiments, a display device can be stably driven, reliability can be improved, and power consumption can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 A circuit diagram of a display device according to an exemplary embodiment is shown.

[0032] Figure 2 A top view of a display device according to an exemplary embodiment is shown.

[0033] Figure 3 A cross-sectional view taken along line III-III of Figure 2 is shown.

[0034] Figure 4 A cross-sectional view taken along line IV-IV of Figure 2 is shown.

[0035] Figure 5 A cross-sectional view taken along line V-V of Figure 2 is shown.

[0036] Figures 6 to 10 Top views according to a sequence for manufacturing a display device according to an exemplary embodiment are shown in sequence. DETAILED DESCRIPTION

[0037] The present application will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the application are shown. As those skilled in the art will appreciate, the described embodiments can be modified in various different ways without departing from the spirit or scope of the application.

[0038] The drawings and description are to be regarded as illustrative in nature and not restrictive, and like reference numerals refer to like elements throughout the specification.

[0039] For better understanding and ease of description, the size and thickness of each configuration shown in the drawings are arbitrarily shown, and the present invention is not limited thereto. In the drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. For better understanding and ease of description, the thickness of some layers and regions are exaggerated.

[0040] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, the element may be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly on” another element, no intervening elements are present. Further, in this specification, the words “on” or “above” mean being above or below an object part, and do not necessarily mean being on the upper side of the object part based on the direction of gravity.

[0041] Unless described to the contrary, the word “comprise” and variations such as “comprises” or “comprising”, will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0042] The phrase “in a plan view” means observing an object portion from the top, and the phrase “in a cross-sectional view” means observing a cross section in which the object portion is vertically cut from the side.

[0043] Now refer to Figure 1 A pixel of a display device according to an exemplary embodiment is described.

[0044] Figure 1 1 is a circuit diagram of a display device according to an exemplary embodiment. One pixel PX of the display device according to the exemplary embodiment includes a storage capacitor Cst, a boost capacitor Cboost, a light emitting diode LED, and a plurality of transistors T1, T2, T3, T4, T5, T6, and T7 connected to various signal lines 127, 128, 151, 152, 153, 154, 155, 171, 172, and 741.

[0045] The display device includes a display area for displaying an image, and pixels PX are arranged in the display area in various forms.

[0046] A plurality of signal lines 127, 128, 151, 152, 153, 154, 155, 171, 172, and 741 are connected to one pixel PX. The plurality of signal lines include a first initialization voltage line 127, a second initialization voltage line 128, a scan line 151, an inverted scan line 152, an initialization control line 153, a bypass control line 154, an emission control line 155, a data line 171, a driving voltage line 172, and a common voltage line 741.

[0047] The scan line 151 is connected to a gate driver (not shown) and transmits a scan signal GW to the second transistor T2. The inverted scan line 152 can receive a voltage having a polarity opposite to that of the voltage applied to the scan line 151 at the same timing as the signal of the scan line 151. For example, when a high voltage is applied to the scan line 151, a low voltage can be applied to the inverted scan line 152. The inverted scan line 152 transmits the inverted scan signal GC to the third transistor T3.

[0048] The initialization control line 153 transmits the initialization control signal GI to the fourth transistor T4 (i.e., the first initialization transistor). The bypass control line 154 transmits the bypass signal GB to the seventh transistor T7 (i.e., the second initialization transistor). The bypass control line 154 can be formed by the scan line 151 at the back end. The emission control line 155 transmits the emission control signal EM to the fifth transistor T5 and the sixth transistor T6.

[0049] The data line 171 is a wiring for transmitting a data voltage DATA generated by a data driver (not shown), and the brightness of light emitted by the light emitting diode LED changes according to the data voltage DATA applied to the pixel PX.

[0050] The driving voltage line 172 applies a driving voltage ELVDD. For example, the driving voltage ELVDD is supplied to the pixel PX via the driving voltage line 172. The first initialization voltage line 127 transmits a first initialization voltage VINT, and the second initialization voltage line 128 transmits a second initialization voltage AINT. The common voltage line 741 applies a common voltage ELVSS to the cathode of the light-emitting diode LED. In this exemplary embodiment, the voltage applied to the driving voltage line 172, the first and second initialization voltage lines 127 and 128, and the common voltage line 741 may be a constant voltage.

[0051] The configuration and connection relationship of the plurality of transistors will now be described in detail.

[0052] The driving transistor T1 (i.e., the first transistor) may be a p-type transistor and may include a polycrystalline semiconductor (i.e., a polycrystalline semiconductor layer). The driving transistor T1 controls the magnitude of the current output to the anode of the light-emitting diode LED based on the data voltage DATA applied to the gate electrode of the driving transistor T1. The brightness of the light-emitting diode LED is controlled by the magnitude of the driving current output to the anode of the light-emitting diode LED, and thus the brightness of the light-emitting diode LED can be controlled based on the data voltage DATA applied to the pixel PX. To this end, the first electrode of the driving transistor T1 receives the driving voltage ELVDD and is connected to the driving voltage line 172 via the fifth transistor T5. The first electrode of the driving transistor T1 is connected to the second electrode of the second transistor T2 to receive the data voltage DATA. The second electrode of the driving transistor T1 outputs current to the light-emitting diode LED and is connected to the anode of the light-emitting diode LED via the sixth transistor T6. The second electrode of the driving transistor T1 transmits the data voltage DATA applied to the first electrode to the third transistor T3. The gate electrode of the driving transistor T1 is connected to one electrode (hereinafter referred to as the second storage electrode) of the storage capacitor Cst. The voltage at the gate electrode of the driving transistor T1 changes according to the voltage stored in the storage capacitor Cst, and the driving current output by the driving transistor T1 changes accordingly. The storage capacitor Cst also maintains the voltage at the gate electrode of the driving transistor T1 for one frame.

[0053] The second transistor T2 may be a p-type transistor and may include a polycrystalline semiconductor. The second transistor T2 receives a data voltage DATA to be supplied to the pixel PX. The gate electrode of the second transistor T2 is connected to the scan line 151 and the first electrode of the boost capacitor Cboost. The first electrode of the second transistor T2 is connected to the data line 171. The second electrode of the second transistor T2 is connected to the first electrode of the drive transistor T1. When the second transistor T2 is turned on by a low voltage in the scan signal GW transmitted via the scan line 151, the data voltage DATA transmitted via the data line 171 is transmitted to the first electrode of the drive transistor T1.

[0054] The third transistor T3 (i.e., an oxide semiconductor transistor) can be an n-type transistor and can include an oxide semiconductor (i.e., an oxide semiconductor layer). The third transistor T3 electrically connects the second electrode of the driving transistor T1 and the gate electrode of the driving transistor T1. As a result, the third transistor T3 transmits the compensation voltage that is changed when the data voltage DATA passes through the driving transistor T1 to the second storage electrode of the storage capacitor Cst. The gate electrode of the third transistor T3 is connected to the inverting scan line 152, and the first electrode of the third transistor T3 is connected to the second electrode of the driving transistor T1. The second electrode of the third transistor T3 is connected to the second storage electrode of the storage capacitor Cst, the gate electrode of the driving transistor T1, and the second electrode of the boost capacitor Cboost. The third transistor T3 is turned on by the high voltage in the inverting scan signal GC transmitted through the inverting scan line 152 to connect the gate electrode of the driving transistor T1 and the second electrode of the driving transistor T1, and transmits the voltage applied to the gate electrode of the driving transistor T1 to the second storage electrode of the storage capacitor Cst, and stores it in the storage capacitor Cst.

[0055] The fourth transistor T4 may be an n-type transistor and may include an oxide semiconductor (i.e., an oxide semiconductor layer). The fourth transistor T4 initializes the gate electrode of the drive transistor T1 and the second storage electrode of the storage capacitor Cst. The gate electrode of the fourth transistor T4 is connected to the initialization control line 153, and the first electrode of the fourth transistor T4 is connected to the first initialization voltage line 127. The second electrode of the fourth transistor T4 is connected to the second electrode of the third transistor T3, the second storage electrode of the storage capacitor Cst, the gate electrode of the drive transistor T1, and the second electrode of the boost capacitor Cboost. The fourth transistor T4 is turned on by the high voltage in the initialization control signal GI received through the initialization control line 153, and in response to the high voltage of the initialization control signal GI, the fourth transistor T4 transmits the first initialization voltage VINT to the gate electrode of the drive transistor T1 and the second storage electrode of the storage capacitor Cst. Accordingly, the voltage at the gate electrode of the drive transistor T1 and the storage capacitor Cst are initialized.

[0056] The fifth transistor T5 may be a p-type transistor and may include a polycrystalline semiconductor. The fifth transistor T5 transmits the driving voltage ELVDD to the driving transistor T1. The gate electrode of the fifth transistor T5 is connected to the emission control line 155, the first electrode of the fifth transistor T5 is connected to the driving voltage line 172, and the second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T1.

[0057] The sixth transistor T6 may be a p-type transistor and may include a polycrystalline semiconductor. The sixth transistor T6 transmits the driving current output by the driving transistor T1 to the light-emitting diode LED. The gate electrode of the sixth transistor T6 is connected to the emission control line 155, the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T1, and the second electrode of the sixth transistor T6 is connected to the anode of the light-emitting diode LED.

[0058] The seventh transistor T7 (i.e., the second initialization transistor) can be a p-type transistor and can include a polycrystalline semiconductor. The seventh transistor T7 initializes the anode of the light-emitting diode LED. The gate electrode of the seventh transistor T7 is connected to the bypass control line 154, the first electrode of the seventh transistor T7 is connected to the anode of the light-emitting diode LED, and the second electrode of the seventh transistor T7 is connected to the second initialization voltage line 128. When the seventh transistor T7 is turned on by the low voltage in the bypass signal GB, the second initialization voltage AINT is applied to the anode of the light-emitting diode LED to be initialized.

[0059] It has been described that one pixel includes seven transistors T1 to T7 , one storage capacitor Cst, and one boosting capacitor Cboost, but the present exemplary embodiment is not limited thereto, and the number of transistors, the number of capacitors, and their connection relationship may be modified in various ways.

[0060] In this exemplary embodiment, the driving transistor T1 may include a polycrystalline semiconductor. The third transistor T3 and the fourth transistor T4 may include an oxide semiconductor. The second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include a polycrystalline semiconductor. However, they are not limited thereto, and at least any one of the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include an oxide semiconductor. In this exemplary embodiment, the third transistor T3 and the fourth transistor T4 include a semiconductor material different from that of the driving transistor T1, so that their driving strength can be more stable and their reliability can be improved.

[0061] As described above, when a high voltage is applied to scan line 151, a low voltage is applied to inverted scan line 152, and when a low voltage is applied to scan line 151, a high voltage is applied to inverted scan line 152. For example, the inverted scan signal GC applied to inverted scan line 152 includes the scan signal GW applied to scan line 151 and an inverted signal, thereby reducing the gate voltage of drive transistor T1 after data is programmed. Conversely, scan signal GW boosts the gate voltage of drive transistor T1 via boost capacitor Cboost. Therefore, when the black voltage is programmed, the black voltage can be reduced. In this exemplary embodiment, by positioning boost capacitor Cboost between scan line 151, to which scan signal GW is applied, and the gate electrode of drive transistor T1, the gate voltage of drive transistor T1 can be increased, allowing drive transistor T1 to stably output a black voltage. As the capacitance of boost capacitor Cboost increases, the gate voltage of drive transistor T1 can further increase. The gate voltage of drive transistor T1 can be controlled by controlling the capacitance of boost capacitor Cboost.

[0062] Now refer to Figures 2 to 10 Planar and cross-sectional configurations of the driving transistor T1 , the third transistor T3 , the fourth transistor T4 , and the seventh transistor T7 are described in more detail.

[0063] Figure 2 shows a top view of a display device according to an exemplary embodiment, Figure 3 Shown relative to Figure 2 A cross-sectional view along line III-III, Figure 4 Shown relative to Figure 2 A cross-sectional view along line IV-IV of Figure 5 Shown relative to Figure 2 A cross-sectional view along line VV of . Figures 6 to 10 Top views in the order of manufacturing a display device according to an exemplary embodiment are sequentially shown. Figures 2 to 10 Two adjacent pixels are shown which may have substantially the same shape as each other.A display device may include a plurality of pixels which may be repeatedly arranged to form a display area.

[0064] like Figures 2 to 10 As shown in FIG, a polycrystalline semiconductor (ie, a polycrystalline semiconductor layer) may be located on a substrate 110. The polycrystalline semiconductor may include a channel 1132, a first electrode 1131, and a second electrode 1133 of the driving transistor T1 and a channel 7132, a first electrode 7131, and a second electrode 7133 of the seventh transistor T7. Figure 6 The polycrystalline semiconductor may further include channels, first electrodes, and second electrodes of the second transistor T2 , the fifth transistor T5 , and the sixth transistor T6 .

[0065] The channel 1132 of the driving transistor T1 may be curved in a plan view. The shape of the channel 1132 of the driving transistor T1 is not limited thereto and may be modified in various ways. For example, the channel 1132 of the driving transistor T1 may be curved in another shape and may have a bar shape. The first electrode 1131 and the second electrode 1133 of the driving transistor T1 may be located on opposite sides of the channel 1132 of the driving transistor T1. In a plan view, the first electrode 1131 of the driving transistor T1 may extend toward the top and bottom sides, and the upwardly extending portion of the first electrode 1131 may be connected to the second electrode of the second transistor T2, while the downwardly extending portion of the first electrode 1131 may be connected to the second electrode of the fifth transistor T5. In a plan view, the second electrode 1133 of the driving transistor T1 may extend downward and may be connected to the first electrode of the sixth transistor T6.

[0066] In a plan view, the channel 7132 of the seventh transistor T7 may have a bar shape. The shape of the channel 7132 of the seventh transistor T7 is not limited thereto and may be modified in various ways. The first electrode 7131 and the second electrode 7133 of the seventh transistor T7 may be formed on opposite sides of the channel 7132 of the seventh transistor T7. In a plan view, the first electrode 7131 of the seventh transistor T7 may be formed on the upper side of the channel 7132. In a plan view, the first electrode 7131 of the seventh transistor T7 may extend on the upper side and may reach the second electrode of the sixth transistor T6. In a plan view, the second electrode 7133 of the seventh transistor T7 may be formed on the lower side of the channel 7132.

[0067] A buffer layer 111 may be formed between the substrate 110 and the polycrystalline semiconductor including the channel 1132, the first electrode 1131, and the second electrode 1133 of the driving transistor T1 and the channel 7132, the first electrode 7131, and the second electrode 7133 of the seventh transistor T7. The buffer layer 111 may have a single-layer or multi-layer structure. The buffer layer 111 may include an organic insulating material or an inorganic insulating material.

[0068] A first gate insulating layer 141 may be formed on the polycrystalline semiconductor including the channel 1132, first and second electrodes 1131 and 1133 of the driving transistor T1 and the channel 7132, first and second electrodes 7131 and 7133 of the seventh transistor T7. The first gate insulating layer 141 may include silicon nitride or silicon oxide.

[0069] A first gate conductor including a gate electrode 1151 of the driving transistor T1 and a gate electrode 7151 of the seventh transistor T7 may be formed on the first gate insulating layer 141 . Figure 7 A polycrystalline semiconductor and a first gate conductor are shown.

[0070] The gate electrode 1151 of the driving transistor T1 may overlap with the channel 1132 of the driving transistor T1. The channel 1132 of the driving transistor T1 is covered by the gate electrode 1151 of the driving transistor T1. The gate electrode 7151 of the seventh transistor T7 may overlap with the channel 7132 of the seventh transistor T7. The channel 7132 of the seventh transistor T7 is covered by the gate electrode 7151 of the seventh transistor T7.

[0071] The first gate conductor may further include a scan line 151, an emission control line 155, and a bypass control line 154. The scan line 151, the emission control line 155, and the bypass control line 154 may extend substantially in a horizontal direction. In a plan view, the scan line 151 may extend downward to reach the gate electrode of the second transistor T2 and the first electrode of the boost capacitor Cboost. The gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6 may be connected to the emission control line 155. The gate electrode 7151 of the seventh transistor T7 may be connected to the bypass control line 154. The bypass control line 154 may be a scan line for the next pixel.

[0072] A first gate conductor including a gate electrode 1151 of the driving transistor T1 and a gate electrode 7151 of the seventh transistor T7 may be formed, and then a doping process may be performed. The polycrystalline semiconductor covered by the first gate conductor may not be doped, and the portion of the polycrystalline semiconductor not covered by the first gate conductor may be doped to be conductive. For example, the doping process may be performed using a p-type dopant, and the driving transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 including the polycrystalline semiconductor may be p-type transistors.

[0073] A second gate insulating layer 142 may be formed on the first gate conductor including the gate electrode 1151 of the driving transistor T1 and the gate electrode 7151 of the seventh transistor T7 and the first gate insulating layer 141. The second gate insulating layer 142 may include silicon nitride or silicon oxide.

[0074] A second gate conductor including the first storage electrode 1153 of the storage capacitor Cst, the light blocking layer 3155 of the third transistor T3 , and the light blocking layer 4155 of the fourth transistor T4 may be formed on the second gate insulating layer 142 . Figure 8 A polycrystalline semiconductor, a first gate conductor, and a second gate conductor are shown.

[0075] The first storage electrode 1153 overlaps with the gate electrode 1151 of the driving transistor T1 to form a storage capacitor Cst. An opening 1152 is formed in the first storage electrode 1153 of the storage capacitor Cst. The opening 1152 of the first storage electrode 1153 of the storage capacitor Cst may overlap with the gate electrode 1151 of the driving transistor T1. The light-blocking layer 3155 of the third transistor T3 may overlap with the channel 3137 and the gate electrode 3151 of the third transistor T3. The light-blocking layer 4155 of the fourth transistor T4 may overlap with the channel 4137 and the gate electrode 4151 of the fourth transistor T4.

[0076] The second gate conductor may further include a second initialization voltage line 128 and an inverting scan line 152. The second initialization voltage line 128 and the inverting scan line 152 may extend substantially in a horizontal direction. The second initialization voltage line 128 may overlap with the channel 7132 and the first electrode 7131 of the seventh transistor T7. The second initialization voltage line 128 may overlap with the gate electrode 7151 of the seventh transistor T7. The inverting scan line 152 may be connected to the light blocking layer 3155 of the third transistor T3.

[0077] A first interlayer insulating layer 161 may be formed on the second gate conductor including the first storage electrode 1153 of the storage capacitor Cst, the light blocking layer 3155 of the third transistor T3 , and the light blocking layer 4155 of the fourth transistor T4 .

[0078] The first interlayer insulating layer 161 may include silicon nitride or silicon oxide.

[0079] An oxide semiconductor (ie, an oxide semiconductor layer) including the channel 3137 , first and second electrodes 3136 and 3138 of the third transistor T3 and the channel 4137 , first and second electrodes 4136 and 4138 of the fourth transistor T4 may be formed on the first interlayer insulating layer 161 . Figure 9 A polycrystalline semiconductor, first and second gate conductors, and an oxide semiconductor are shown.

[0080] The oxide semiconductor may include at least one of the following: a monometallic oxide such as indium oxide (In), tin oxide (Sn) or zinc oxide (Zn); a binary metal oxide such as an In-Zn oxide, a Sn-Zn oxide, an Al-Zn oxide, a Zn-Mg oxide, a Sn-Mg oxide, an In-Mg oxide or an In-Ga oxide; a monometallic oxide such as an In-Ga-Zn oxide, an In-Al-Zn oxide, an In-Sn-Zn oxide, a Sn-Ga-Zn oxide, an Al-Ga-Zn oxide, a Sn-Al-Zn oxide, an In-Hf-Zn oxide, an In-La-Zn oxide, an In-Ce-Zn oxide, an In-Pr-Zn oxide The oxide semiconductor may include a ternary metal oxide such as an In-Nd-Zn oxide, an In-Sm-Zn oxide, an In-Eu-Zn oxide, an In-Gd-Zn oxide, an In-Tb-Zn oxide, an In-Dy-Zn oxide, an In-Ho-Zn oxide, an In-Er-Zn oxide, an In-Tm-Zn oxide, an In-Yb-Zn oxide, or an In-Lu-Zn ​​oxide; and a tetravalent metal oxide such as an In-Sn-Ga-Zn oxide, an In-Hf-Ga-Zn oxide, an In-Al-Ga-Zn oxide, an In-Sn-Al-Zn oxide, an In-Sn-Hf-Zn oxide, or an In-Hf-Al-Zn oxide. For example, the oxide semiconductor may include indium-gallium-zinc oxide (IGZO) among In-Ga-Zn oxides.

[0081] The channel 3137, first electrode 3136, and second electrode 3138 of the third transistor T3 and the channel 4137, first electrode 4136, and second electrode 4138 of the fourth transistor T4 may be connected to each other and may be formed integrally. The first electrode 3136 and second electrode 3138 of the third transistor T3 may be formed on opposite sides of the channel 3137 of the third transistor T3. The first electrode 4136 and second electrode 4138 of the fourth transistor T4 may be formed on opposite sides of the channel 4137 of the fourth transistor T4. The second electrode 3138 of the third transistor T3 may be connected to the second electrode 4138 of the fourth transistor T4. The channel 3137 of the third transistor T3 may overlap with the light-blocking layer 3155. The channel 4137 of the fourth transistor T4 may overlap with the light-blocking layer 4155.

[0082] The oxide semiconductor may further include a second electrode of a boost capacitor Cboost. The second electrode of the boost capacitor Cboost may be connected to the second electrode 3138 of the third transistor T3. The second electrode of the boost capacitor Cboost may be connected to the second electrode 4138 of the fourth transistor T4. The second electrode of the boost capacitor Cboost may overlap with the first electrode of the boost capacitor Cboost. The capacitance of the boost capacitor Cboost may be determined by the overlapping area of ​​the first and second electrodes of the boost capacitor Cboost and the thickness of the second gate insulating layer 142 and the first interlayer insulating layer 161 between the first and second electrodes of the boost capacitor Cboost.

[0083] A third gate insulating layer 143 may be formed on the oxide semiconductor including the channel 3137, first and second electrodes 3136 and 3138 of the third transistor T3, and the channel 4137, first and second electrodes 4136 and 4138 of the fourth transistor T4. The third gate insulating layer 143 may be formed on the entire surface of the oxide semiconductor and the first interlayer insulating layer 161. Therefore, the third gate insulating layer 143 may cover the upper surface and side surfaces of the channel 3137, first and second electrodes 3136 and 3138 of the third transistor T3, and the channel 4137, first and second electrodes 4136 and 4138 of the fourth transistor T4. However, the exemplary embodiment is not limited thereto, and the third gate insulating layer 143 may not be formed on the entire surface of the oxide semiconductor and the first interlayer insulating layer 161. For example, the third gate insulating layer 143 may overlap the channel 3137 of the third transistor T3 without overlapping the first and second electrodes 3136 and 3138. The third gate insulating layer 143 may overlap with the channel 4137 of the fourth transistor T4 without overlapping with the first electrode 4136 and the second electrode 4138 .

[0084] A third gate conductor including a gate electrode 3151 of the third transistor T3 and a gate electrode 4151 of the fourth transistor T4 may be formed on the third gate insulating layer 143 . Figure 10 A polycrystalline semiconductor, a first gate conductor, a second gate conductor, an oxide semiconductor, and a third gate conductor are shown.

[0085] The gate electrode 3151 of the third transistor T3 may overlap with the channel 3137 of the third transistor T3. The gate electrode 3151 of the third transistor T3 may overlap with at least one of the inverting scan line 152 and the light-blocking layer 3155 of the third transistor T3. The first interlayer insulating layer 161 and the third gate insulating layer 143 may be formed between the gate electrode 3151 of the third transistor T3 and the inverting scan line 152, and between the gate electrode 3151 of the third transistor T3 and the light-blocking layer 3155. A first opening 3145 may be formed in the third gate insulating layer 143 and the first interlayer insulating layer 161. The first opening 3145 may overlap with at least a portion of at least one of the inverting scan line 152 and the light-blocking layer 3155 of the third transistor T3 (i.e., expose at least a portion of at least one of the inverting scan line 152 and the light-blocking layer 3155 of the third transistor T3). The gate electrode 3151 of the third transistor T3 can be connected to at least one of the inversion scan line 152 and the light blocking layer 3155 of the third transistor T3 through the first opening 3145. The gate electrode 3151 and the light blocking layer 3155 of the third transistor T3 can receive the inversion scan signal GC through the inversion scan line 152.

[0086] The gate electrode 4151 of the fourth transistor T4 may overlap with the channel 4137 of the fourth transistor T4. The third gate conductor may further include an initialization control line 153. The initialization control line 153 may extend substantially in a horizontal direction. The gate electrode 4151 of the fourth transistor T4 may be connected to the initialization control line 153. At least one of the gate electrode 4151 of the fourth transistor T4 and the initialization control line 153 may overlap with the light-blocking layer 4155 of the fourth transistor T4. The first interlayer insulating layer 161 and the third gate insulating layer 143 may be formed between the gate electrode 4151 of the fourth transistor T4 and the light-blocking layer 4155, and between the initialization control line 153 and the light-blocking layer 4155 of the fourth transistor T4. A second opening 4145 may be formed in the third gate insulating layer 143 and the first interlayer insulating layer 161. The second opening 4145 may overlap with at least a portion of the light-blocking layer 4155 of the fourth transistor T4 (i.e., expose at least a portion of the light-blocking layer 4155 of the fourth transistor T4). At least one of the gate electrode 4151 of the fourth transistor T4 and the initialization control line 153 may be connected to the light blocking layer 4155 of the fourth transistor T4 through the second opening 4145. The gate electrode 4151 and the light blocking layer 4155 of the fourth transistor T4 may receive the initialization control signal GI through the initialization control line 153.

[0087] The third gate conductor may further include a first initialization voltage line 127. The first initialization voltage line 127 may extend substantially in a horizontal direction. The first initialization voltage line 127 may extend parallel to the initialization control line 153. The first initialization voltage line 127 may extend parallel to the second initialization voltage line 128 and the scan line 151. The first initialization voltage line 127 may overlap with the second initialization voltage line 128 and the scan line 151. The scan line 151 may be insulated from the second initialization voltage line 128, with the second gate insulation layer 142 located therebetween. The second initialization voltage line 128 may be insulated from the first initialization voltage line 127, with the first interlayer insulation layer 161 and the third gate insulation layer 143 located therebetween. In an exemplary embodiment, the second initialization voltage line 128 and the first initialization voltage line 127 are located on different layers from each other. For example, the second initialization voltage line 128 may be disposed on (or may contact) the second gate insulation layer 142 , and the first initialization voltage line 127 may be disposed on (or may contact) a third gate insulation layer 143 different from the second gate insulation layer 142 .

[0088] A third gate conductor including a gate electrode 3151 of the third transistor T3 and a gate electrode 4151 of the fourth transistor T4 may be formed, and a doping process may be performed. The portion of the oxide semiconductor covered by the third gate conductor may not be doped, and the portion of the oxide semiconductor not covered by the third gate conductor may be doped to have the same characteristics as a conductor. The channel 3137 of the third transistor T3 may be located below the gate electrode 3151 so as to overlap with the gate electrode 3151. The first electrode 3136 and the second electrode 3138 of the third transistor T3 may not overlap with the gate electrode 3151. The channel 4137 of the fourth transistor T4 may be located below the gate electrode 4151 so as to overlap with the gate electrode 4151. The first electrode 4136 and the second electrode 4138 of the fourth transistor T4 may not overlap with the gate electrode 4151. The doping process of the oxide semiconductor may be performed using an n-type dopant, and the third transistor T3 and the fourth transistor T4 including the oxide semiconductor may have n-type transistor characteristics.

[0089] A second interlayer insulating layer 162 may be formed on the third gate conductor including the gate electrode 3151 of the third transistor T3 and the gate electrode 4151 of the fourth transistor T4. A third opening 1165, a fourth opening 3165, a fifth opening 3166, a sixth opening 4165, a seventh opening 4166, an eighth opening 7165, and a ninth opening 7166 may be formed in the second interlayer insulating layer 162.

[0090] The third opening 1165 may expose at least a portion of the gate electrode 1151 of the drive transistor T1. The third opening 1165 may be further formed in the third gate insulating layer 143, the first interlayer insulating layer 161, and the second gate insulating layer 142. The third opening 1165 may overlap with the opening 1152 of the first storage electrode 1153. For example, in a top view, the third opening 1165 may be disposed in the opening 1152. In an exemplary embodiment, the third opening 1165 may penetrate the portion of the second gate insulating layer 142 exposed by the opening 1152 and expose a portion of the gate electrode 1151 of the drive transistor T1. The third opening 1165 may be formed in the opening 1152 of the first storage electrode 1153. The fourth opening 3165 may overlap with at least a portion of the second electrode 1133 of the drive transistor T1.

[0091] A fourth opening 3165 may be further formed in the third gate insulating layer 143, the first interlayer insulating layer 161, the second gate insulating layer 142, and the first gate insulating layer 141. A fifth opening 3166 may expose at least a portion of the first electrode 3136 of the third transistor T3. The fifth opening 3166 may be further formed in the third gate insulating layer 143.

[0092] The sixth opening 4165 may expose at least a portion of the first initialization voltage line 127. The seventh opening 4166 may expose at least a portion of the first electrode 4136 of the fourth transistor T4. The seventh opening 4166 may be further formed in the third gate insulating layer 143.

[0093] The eighth opening 7165 may expose at least a portion of the second initialization voltage line 128. The eighth opening 7165 may be further formed in the third gate insulating layer 143 and the first interlayer insulating layer 161. The ninth opening 7166 may expose at least a portion of the second electrode 7133 of the seventh transistor T7. The ninth opening 7166 may be further formed in the third gate insulating layer 143, the first interlayer insulating layer 161, the second gate insulating layer 142, and the first gate insulating layer 141.

[0094] The first connection electrode 1175 , the second connection electrode 3175 , the third connection electrode 4175 , the fourth connection electrode 7175 , the data line 171 , and the driving voltage line 172 may be formed on the second interlayer insulating layer 162 .

[0095] The first connection electrode 1175 can overlap the gate electrode 1151 of the driving transistor T1. The first connection electrode 1175 can be connected to the gate electrode 1151 of the driving transistor T1 through the third opening 1165 and the opening 1152 of the first storage electrode 1153. The first connection electrode 1175 can overlap the boost capacitor Cboost. The first connection electrode 1175 can be connected to the second electrode of the boost capacitor Cboost. Accordingly, the gate electrode 1151 of the driving transistor T1 can be connected to the second electrode of the boost capacitor Cboost through the first connection electrode 1175.

[0096] The second connection electrode 3175 can overlap the second electrode 1133 of the driving transistor T1. The second connection electrode 3175 can be connected to the second electrode 1133 of the driving transistor T1 through the fourth opening 3165. The second connection electrode 3175 can overlap the first electrode 3136 of the third transistor T3. The second connection electrode 3175 can be connected to the first electrode 3136 of the third transistor T3 through the fifth opening 3166. Accordingly, the second electrode 1133 of the driving transistor T1 can be connected to the first electrode 3136 of the third transistor T3 through the second connection electrode 3175.

[0097] The third connection electrode 4175 can overlap the first initialization voltage line 127. The third connection electrode 4175 can be connected to the first initialization voltage line 127 through the sixth opening 4165. The third connection electrode 4175 can overlap the first electrode 4136 of the fourth transistor T4. The third connection electrode 4175 can be connected to the first electrode 4136 of the fourth transistor T4 through the seventh opening 4166. Accordingly, the first initialization voltage line 127 can be connected to the first electrode 4136 of the fourth transistor T4 through the third connection electrode 4175.

[0098] The fourth connection electrode 7175 can overlap the second initialization voltage line 128. The fourth connection electrode 7175 can be connected to the second initialization voltage line 128 through the eighth opening 7165. The fourth connection electrode 7175 can overlap the second electrode 7133 of the seventh transistor T7. The fourth connection electrode 7175 can be connected to the second electrode 7133 of the seventh transistor T7 through the ninth opening 7166. Accordingly, the second initialization voltage line 128 can be connected to the second electrode 7133 of the seventh transistor T7 through the fourth connection electrode 7175.

[0099] The data line 171 and the driving voltage line 172 may extend substantially in a vertical direction. The data line 171 may be connected to the second transistor T2. The data line 171 may be connected to the first electrode of the second transistor T2. The driving voltage line 172 may be connected to the fifth transistor T5. The driving voltage line 172 may be connected to the first electrode of the fifth transistor T5. The driving voltage line 172 may be connected to the storage capacitor Cst. The driving voltage line 172 may be connected to the first storage electrode 1153 of the storage capacitor Cst. The first storage electrodes 1153 of the storage capacitors Cst of adjacent pixels are connected to each other, and they may extend substantially in a horizontal direction.

[0100] A third interlayer insulating layer 180 may be formed on the first connection electrode 1175 , the second connection electrode 3175 , the third connection electrode 4175 , the fourth connection electrode 7175 , the data line 171 , and the driving voltage line 172 .

[0101] Although not shown, the anode of the light-emitting diode LED may be formed on the third interlayer insulating layer 180. The anode may be connected to the sixth transistor T6 and may receive the output current of the driving transistor T1. A partition wall may be formed on the anode. An opening may be formed in the partition wall, and the opening in the partition wall may overlap with the anode. A light-emitting device layer may be formed in the opening of the partition wall. A cathode may be formed on the light-emitting device layer and the partition wall. The anode, the light-emitting device layer, and the cathode may constitute the light-emitting diode LED.

[0102] Regarding the display device according to the exemplary embodiment, the driving transistor T1 may include a polycrystalline semiconductor, and the third and fourth transistors T3 and T4 may include an oxide semiconductor. The third and fourth transistors T3 and T4 include a semiconductor material different from that of the driving transistor T1, so their driving strength can be more stable and their reliability can be improved.

[0103] Further, the third transistor T3 including an oxide semiconductor may include a light-blocking layer 3155, and the fourth transistor T4 may include a light-blocking layer 4155. The light-blocking layer 3155 of the third transistor T3 and the light-blocking layer 4155 of the fourth transistor T4 may be formed on the same layer (e.g., the second gate insulating layer 142) as the first storage electrode 1153 of the storage capacitor Cst, they may be made of the same material, and may be formed using the same process. In an exemplary embodiment, the light-blocking layer 3155 of the third transistor T3, the light-blocking layer 4155 of the fourth transistor T4, and the first storage electrode 1153 may be formed on the same layer (e.g., the second gate insulating layer 142) as the second initialization voltage line 128, they may be made of the same material, and may be formed using the same process. In an exemplary embodiment, the light-blocking layer 3155 of the third transistor T3, the light-blocking layer 4155 of the fourth transistor T4, and the second initialization voltage line 128 can be formed on the same second gate insulating layer 142. The light-blocking layer 3155 of the third transistor T3 can receive the same signal as the gate electrode 3151, and the third transistor T3 can have a dual-gate structure. The light-blocking layer 4155 of the fourth transistor T4 can receive the same signal as the gate electrode 4151, and the fourth transistor T4 can have a dual-gate structure. As described above, the third transistor T3 and the fourth transistor T4 have configurations including the light-blocking layers 3155 and 4155, respectively, without the need for additional processes, thereby preventing leakage current from occurring in the third transistor T3 and the fourth transistor T4. Therefore, device characteristics and reliability can be improved.

[0104] The fourth transistor T4 and the seventh transistor T7 are not connected to the same initialization voltage line, but are connected to different initialization voltage lines. The fourth transistor T4 can be connected to the first initialization voltage line 127 and can receive the first initialization voltage VINT. The seventh transistor T7 can be connected to the second initialization voltage line 128 and can receive the second initialization voltage AINT. When the fourth transistor T4 and the seventh transistor T7 are connected to the same initialization voltage line, the same initialization voltage is applied to the fourth transistor T4 and the seventh transistor T7. The organic light-emitting device may be driven at a changed frequency. For example, a frequency of 120 Hz can be changed to 60 Hz, 30 Hz, or 1 Hz. When the organic light-emitting device is driven at a changed frequency, the variable refresh rate (VRR) characteristic may deviate. For example, a greater deviation may be generated in an area indicating low grayscale. In this exemplary embodiment, different initialization voltages can be applied to the fourth transistor T4 and the seventh transistor T7. Therefore, by allowing the first initialization voltage VINT applied to the fourth transistor T4 to be different from the second initialization voltage AINT applied to the seventh transistor T7, the deviation of the VRR characteristic can be reduced in low grayscale.

[0105] In the present exemplary embodiment, the first initialization voltage line 127 may overlap the second initialization voltage line 128. The fourth transistor T4 may be connected to the first initialization voltage line 127 via the third connection electrode 4175 and may receive the first initialization voltage VINT. The seventh transistor T7 may be connected to the second initialization voltage line 128 via the fourth connection electrode 7175 and may receive the second initialization voltage AINT.

[0106] While the disclosure has been described in connection with what are presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but on the contrary is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A display device comprising: light-emitting diodes; a first transistor configured to supply a driving current to the light emitting diode; a data line configured to transmit a data voltage; a second transistor connected between the data line and the first electrode of the first transistor; an initialization voltage line configured to transmit an initialization voltage; a seventh transistor connected between the initialization voltage line and the anode of the light emitting diode; as well as A scan line is configured to transmit a scan signal, the scan line is connected to the gate electrode of the second transistor and overlaps with at least a portion of the initialization voltage line.

2. The display device according to claim 1, wherein The data line extends in a first direction, and The scan line and the initialization voltage line extend in a second direction crossing the first direction.

3. The display device according to claim 1, further comprising: substrate; a first insulating layer, disposed between the substrate and the scanning line; as well as The second insulating layer is disposed between the scan line and the initialization voltage line.

4. The display device according to claim 1, further comprising: a third transistor connected between the gate electrode of the first transistor and the second electrode of the first transistor; another initialization voltage line configured to transmit an initialization voltage different from the initialization voltage transmitted by the initialization voltage line; as well as A fourth transistor is connected between the another initialization voltage line and the gate electrode of the first transistor.

5. The display device according to claim 4, wherein The scan line overlaps with at least a portion of the another initialization voltage line. The display device according to claim 5 , wherein: The data line extends in a first direction, and The scan line and the another initialization voltage line extend in a second direction crossing the first direction.

7. The display device according to claim 4, wherein The initialization voltage line and the another initialization voltage line are disposed in different layers from each other.

8. The display device according to claim 7, wherein: The another initialization voltage line overlaps at least a portion of the initialization voltage line.

9. The display device according to claim 4, further comprising: a driving voltage line configured to transmit a driving voltage; a fifth transistor connected between the driving voltage line and the first electrode of the first transistor; a sixth transistor connected between the second electrode of the first transistor and the anode of the light emitting diode; as well as A storage capacitor is connected between the driving voltage line and the gate electrode of the first transistor.

10. The display device according to claim 4, further comprising: an initialization control line configured to transmit an initialization control signal and connected to the gate electrode of the fourth transistor, Wherein, the another initialization voltage line and the initialization control line are arranged in the same layer.

11. The display device according to claim 4, wherein Each of the first transistor, the second transistor, and the seventh transistor includes a polycrystalline semiconductor layer, and Each of the third transistor and the fourth transistor includes an oxide semiconductor layer.

12. The display device according to claim 9, wherein Each of the fifth transistor and the sixth transistor includes a polycrystalline semiconductor layer.

13. The display device according to claim 4, further comprising: substrate; a first insulating layer, disposed between the substrate and the scanning line; a second insulating layer, disposed between the scan line and the initialization voltage line; a third insulating layer, disposed between the initialization voltage line and the another initialization voltage line; as well as The fourth insulating layer is disposed between the third insulating layer and the another initialization voltage line.

14. The display device according to claim 13, wherein: Each of the first transistor, the second transistor, and the seventh transistor includes a semiconductor layer provided between the substrate and the first insulating layer, and Each of the third transistor and the fourth transistor includes a semiconductor layer disposed between the third insulating layer and the fourth insulating layer.

15. The display device according to claim 13, wherein The gate electrode of the first transistor, the gate electrode of the second transistor, and the gate electrode of the seventh transistor are provided between the first insulating layer and the second insulating layer, and A gate electrode of the third transistor and a gate electrode of the fourth transistor are provided on the fourth insulating layer.

16. The display device according to claim 15, wherein The another initialization voltage line and the gate electrode of the fourth transistor are provided in the same layer.

17. The display device according to claim 14, further comprising: a fifth insulating layer, provided on the another initialization voltage line; as well as A connecting electrode is provided on the fifth insulating layer and electrically connects the other initialization voltage line and the semiconductor layer of the fourth transistor.

18. The display device according to claim 17, further comprising: Another connecting electrode is disposed on the fifth insulating layer and electrically connects the initialization voltage line and the semiconductor layer of the seventh transistor.

19. The display device according to claim 17, further comprising: Another connection electrode is provided on the fifth insulating layer and electrically connects the semiconductor layer of the first transistor and the semiconductor layer of the third transistor.

20. The display device according to claim 14, further comprising: a light blocking layer overlapping the semiconductor layer of the third transistor, Wherein, the light blocking layer and the initialization voltage line are arranged in the same layer.

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