Rapid wiring method for adaptive standard frame adjustment and through hole optimization

Abstract

The invention discloses a rapid wiring method for adaptive standard frame adjustment and through hole optimization, and the method comprises the steps: carrying out the initialization division of a chip region, and obtaining an initialization region; performing congestion evaluation operation on the initialized area; judging whether the congestion evaluation result reaches the condition of re-division or not, if the congestion evaluation result reaches the condition of secondary division, carrying out region classification on the divided region, and then carrying out dynamic adjustment division on the standard frame of the region again; and performing wiring operation, and guiding the wiring operation to preferentially select a wiring path for reducing the through holes by adopting a weighted through hole influence evaluation model in the wiring process. According to the invention, a mechanism of dynamically adjusting the size of a standard frame based on real-time congestion data reduces DRC violation and significantly improves wiring efficiency; by weighting the through hole influence evaluation model and increasing the weight used by the through holes, the influence of the through holes on the wiring quality is more accurately measured, and a wiring algorithm is guided to preferentially select and reduce the wiring path of the through holes, so that DRC violation and the number of the through holes are optimized.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of circuit wiring, in particular to a fast wiring method with adaptive standard frame adjustment and via optimization. BACKGROUND

[0002] In the field of integrated circuit detailed routing, routing frame design and pin order selection still lack sufficient attention, and currently a fixed frame scheme is mostly used. According to the result of track allocation, multiple detailed routing iterations are performed. In each iteration, the design is divided into 7x7 non-overlapping, grid cell-aligned tile areas, and a detailed routing worker is created for each tile area. Each detailed routing worker first initializes its own data structure (worker database) from the global database, then performs routing and design rule checking (Design Rule Check), during which the global database is not modified. Finally, each worker submits changes by writing back to the global database. In alternating iterations, the partitioning of 7x7 tile areas is adjusted by offsets of 0 and -4 to optimize the routing at the tile boundary. Section V will describe the routing process within the detailed routing worker in detail.

[0003] When constructing a detailed routing worker, each tile area has three boundary frames: a standard boundary frame, a Design Rule Check (DRC) boundary frame, and an extended boundary frame. In the database of the detailed routing worker, all objects within the extended boundary frame are constructed locally. However, only objects located within or in the standard boundary frame can be modified, while other objects are fixed. Fixed objects are used for cost calculation and design rule checking.

[0004] Existing routing frameworks are mostly based on a single, fixed-size standard frame to allocate routing space. The fixed frame scheme in traditional algorithms is suitable for uniform density routing environments. However, the limitations of fixed frameworks in modern designs have gradually emerged, especially in high-density and significantly locally congested chip regions, where it is difficult to meet the needs of fine routing.

[0005] In fixed frame routing, since the frame size significantly affects the search space of the A* algorithm, a large frame can provide a larger search space, which is beneficial for complex path optimization, but at the same time increases the computational overhead and search time of the algorithm. In low congestion areas, a smaller frame can effectively reduce the search space and computational complexity, speeding up the routing speed. However, the current fixed frame design cannot adapt to the different needs of local areas: in high-density areas, a large frame increases the search space, leading to excessive consumption of computational resources; while in low-density areas, a too small frame may result in a lack of flexibility in path selection, making it difficult to balance efficiency and quality.

[0006] In addition, the pin selection strategy is still dominated by the traditional shortest path algorithm, which is usually optimized based on Manhattan distance. However, this single consideration fails to fully focus on the impact of via quantity on overall routing quality. In multi-layer routing design, the number of vias directly affects the delay of signal transmission and the complexity of the process, especially when the design node tends to smaller process level, via management becomes an important factor affecting the performance of routing. Although there have been studies trying to introduce a via penalty term in path selection, the overall method is still biased towards post-processing, which fails to fully consider in advance, increasing the waste of routing resources. SUMMARY

[0007] To solve the above problems, the present application provides a fast routing method of adaptive standard frame adjustment and via optimization, which dynamically adjusts the size of the standard frame based on real-time congestion data, dynamically adjusts the size of the standard frame according to the pin density, wire density and metal shape density in the region, reduces DRC violations, and significantly improves routing efficiency; through the weighted via influence evaluation model, the weight of via use is increased, the influence of via on routing quality is more accurately measured, and the routing algorithm is guided to preferentially select the routing path that reduces the via, thereby optimizing DRC violations and the number of vias.

[0008] To achieve the above purpose, the technical scheme adopted by the present application is: a fast routing method of adaptive standard frame adjustment and via optimization, comprising the steps of:

[0009] S10, initializing and dividing the chip region to obtain an initialized region;

[0010] S20, congestion evaluation operation on the initialized region;

[0011] S30, judging whether the result after congestion evaluation meets the condition for re-division, if the condition for secondary division is met, classifying the division region, and then dynamically adjusting and dividing the standard frame of the region again;

[0012] The judgment condition for whether to perform secondary division is set, and the number of times of re-routing of the region is judged, if the number of times of re-routing reaches a preset value, the secondary division is not allowed to be performed;

[0013] S30, performing routing operation, and in the routing process, a weighted via influence evaluation model is used to guide the routing operation to preferentially select the routing path that reduces the via.

[0014] Further, the initialization division divides the chip region into standardized 8x8 grid units, so that each unit contains an appropriate number of pins and wires.

[0015] Further, the congestion evaluation operation includes:

[0016] After the initialization of the 8x8 grid cells, congestion evaluation is performed on each cell; the congestion value of each cell is calculated to determine whether further subdivision is needed.

[0017] Further, the congestion value calculation formula is:

[0018] Congestion=α×wlen+β×irs+γ×pins+δ×pins_area+∈×blks+ζ×blks_area+η×nets;

[0019] Where: wlen represents the global routing line length of the region; irs represents the number of iroute of the region; pins represents the number of pins of the region; pins_area represents the total area of the pins of the region; blks represents the number of blockers of the region; blks_area represents the total area of the blockers of the region; nets represents the number of different net segments of the region; α, β, γ, δ, ε, ζ and η are weight parameters for adjusting the influence degree of each factor.

[0020] Further, after congestion evaluation, each region is divided into high congestion, moderate congestion and low congestion regions, and a standard frame size is matched for each type of region.

[0021] Further, the high congestion region remains 8x8, providing sufficient computing resources for optimization of routing;

[0022] The moderate congestion region is reduced to 4x4 to balance routing quality and efficiency;

[0023] The low congestion region is further reduced to 2x2 to improve routing speed and reduce calculation time.

[0024] Further, after region classification, for the region marked as low congestion, secondary division is performed to further refine the allocation of routing resources.

[0025] Further, in the secondary division stage, the low congestion region is subdivided into small grids, and the number of times of rerouting is determined; if the number of times of rerouting of the region exceeds the preset upper limit, the region is not allowed to be divided again.

[0026] Further, when performing routing operations, the connectable pins are traversed, and the next connection point is dynamically selected based on a weighted via impact evaluation model.

[0027] Further, the weighted via impact evaluation model uses a weighted cost model to minimize Manhattan distance while penalizing excessive via usage; by controlling the weights of various factors, connection and resource allocation are adaptively optimized according to design requirements;

[0028] To evaluate each candidate pin, the cost of potential paths is calculated, and the cost function is:

[0029] Costpin = Δx + Δy + Δz + α * via_count;

[0030] Where Δx, Δy and Δz represent the horizontal distance, vertical distance and vertical distance between the current pin and the candidate pin, respectively, via_count is the estimated number of vias in the global routing, and α is an adjustable parameter that assigns a weight to the via and prefers to reduce the number of vias.

[0031] The beneficial effects of using the technical solution are:

[0032] The present application can show significant advantages in wiring speed and via number indicators. Compared with traditional methods such as TritonRoute-WXL, the wiring efficiency is significantly improved and the number of vias is reduced under the premise of ensuring the original quality solution.

[0033] In the present application, an adaptive routing frame size adjustment based on layout connection relationship and congestion prediction is used to dynamically adjust the size of the routing frame, combine the prediction of region division and congestion, ensure that high congestion areas are allocated sufficient routing resources, while avoiding resource waste in low congestion areas, thereby optimizing the overall routing efficiency and resource utilization.

[0034] In the present application, the pin sequence optimization is introduced to reduce the complexity of routing and path length by analyzing the connection relationship between pins, and to improve the efficiency of routing.

[0035] In the present application, an adaptive pin ordering strategy is used to order pins according to their positions and connection requirements, minimizing routing intersection and path overlap. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 A flowchart of a fast routing method of adaptive standard frame adjustment and via optimization according to the present application;

[0037] Figure 2 A path diagram of different pin connection sequences in an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application will be further described below with reference to the accompanying drawings.

[0039] In this embodiment, referring to Figure 1 The present application proposes a fast routing method of adaptive standard frame adjustment and via optimization, which includes the following steps:

[0040] S10, the chip region is initialized and divided to obtain an initialized region;

[0041] S20, performing an initialization region congestion evaluation operation;

[0042] S30, judging whether the result of the congestion evaluation meets a condition for re-division, and if the condition for re-division is met, performing region classification on the divided region, and then performing a dynamic adjustment and division operation on the standard frame of the region;

[0043] The judgment condition for the re-division is set, and the number of times of re-wiring of the region is judged. If the number of times of re-wiring reaches a preset value, the re-division operation is not allowed. In this way, some design rule violations that cannot be solved due to the small size of the wiring region can be avoided. In this way, the efficiency of detailed wiring is improved while ensuring the number of final DCVs.

[0044] S30, performing a wiring operation, and in the wiring process, a weighted via influence evaluation model is used to guide the wiring operation to preferentially select a wiring path that reduces the number of vias;

[0045] Finally, a wiring result, for example, a DEF file, is output.

[0046] As an optimization scheme of the above embodiment, the chip region is divided into standardized 8x8 grid cells, so that each cell contains an appropriate number of pins and wires. This division method can provide local information within the region at an early stage, which is convenient for subsequent congestion evaluation and dynamic adjustment. Through this standardized initial segmentation, we can quickly determine the configuration of the preliminary wiring resources, while ensuring the balance between calculation efficiency and fine-grained analysis.

[0047] As an optimization scheme of the above embodiment, the congestion evaluation operation includes:

[0048] After the initialization division into 8x8 grid cells, the congestion of each cell is evaluated. The congestion value of each cell is calculated to determine whether further subdivision is needed.

[0049] Preferably, the formula for calculating the congestion value is:

[0050] Congestion=α×wlen+β×irs+γ×pins+δ×pins_area+∈×blks+ζ×blks_area+η×nets;

[0051] Wherein: wlen represents the global routing length of the region; irs represents the number of iroute of the region; pins represents the number of pins of the region; pins_area represents the total area of the pins of the region; blks represents the number of blockers of the region; blks_area represents the total area of the blockers of the region; nets represents the number of different nets of the region; and a, b, g, d, e, z and h are weight parameters for adjusting the influence degree of each factor.

[0052] As an optimization scheme of the above embodiment, after congestion evaluation, each region is divided into high congestion, moderate congestion and low congestion regions, and a standard box size is matched for each type of region.

[0053] The high congestion region remains 8x8, providing sufficient computing resources to optimize routing;

[0054] The moderate congestion region is reduced to 4x4 to balance routing quality and efficiency;

[0055] The low congestion region is further reduced to 2x2 to improve routing speed and reduce computing time. Through this classification adjustment, the algorithm significantly improves the overall computing efficiency while ensuring the accuracy of the routing.

[0056] As an optimization scheme of the above embodiment, after region classification, for the region marked as low congestion, secondary division is performed to further refine the allocation of routing resources;

[0057] In the secondary division stage, the low congestion region is subdivided into small grids to more accurately control the routing path and reduce the impact of local congestion. The secondary division condition is not only based on the congestion value, but also refers to the number of times of re-routing, and if the number of times of re-routing of the region exceeds the preset upper limit, it is not allowed to be divided again to avoid the problem of irreparable design rule check violation caused by excessive subdivision. In this way, the secondary division effectively improves the overall computing efficiency of the algorithm while ensuring the quality of the routing.

[0058] As an optimization scheme of the above embodiment, in order to reduce the impact of standard box reduction on the routing result, we take a step to reduce vias, that is, before the routing operation performs path search, a new method is adopted for the selection of the next connection pin.

[0059] During the routing operation, the connectable pins are traversed, and the next connection point is dynamically selected based on the weighted via influence evaluation model.

[0060] The weighted via impact evaluation model adopts a weighted cost model, minimizes Manhattan distance, and penalizes excessive via usage because vias can significantly increase signal delay and increase routing complexity in multi-layer designs; by controlling the weights of various factors, connection and resource allocation are adaptively optimized according to design requirements;

[0061] To evaluate each candidate pin, the cost of the potential path is calculated, and the cost function is:

[0062] Costpin = Δx + Δy + Δz + α * via_count;

[0063] Where Δx, Δy and Δz represent the horizontal distance, vertical distance and vertical distance between the current pin and the candidate pin, respectively, via_count is the estimated number of vias in the global routing, and α is an adjustable parameter that assigns a weight to via usage to preferentially reduce the number of vias.

[0064] As shown in Figure 2 Due to the addition of the via weight, the connection order of the pins is adjusted from 1-2-3-4 to 1-4-2-3, and the routing result also changes accordingly, with a significant reduction in the number of vias.

[0065] The above shows and describes the basic principles and main features of the present application and the advantages of the present application. Those skilled in the art should understand that the present application is not limited to the above embodiments, and the above embodiments and descriptions in the specification are only to illustrate the principles of the present application. Without departing from the spirit and scope of the present application, various changes and improvements can be made to the present application, and these changes and improvements all fall within the scope of the present application. The scope of protection of the present application is defined by the appended claims and their equivalents.

Claims

1. A fast routing method with adaptive standard frame adjustment and through-hole optimization, characterized in that: Including steps: S10, performing initialization division on the chip area to obtain an initialization area; S20, performing congestion assessment operation on the initialization area; S30, determining whether the result of the congestion assessment meets the conditions for re-division. If the conditions for re-division are met, the divided area is classified, and then the standard frame of the area is dynamically adjusted and divided again; Set the judgment condition for whether to perform secondary division, and judge the number of rewiring times of the area. If the number of rewiring times reaches the preset value, secondary division is not allowed; S30, performing a routing operation, using a weighted through-hole impact assessment model during the routing process to guide the routing operation to preferentially select a routing path that reduces through-holes.

2. A fast routing method with adaptive standard frame adjustment and through-hole optimization according to claim 1, characterized in that: Initialize the partitioning and divide the chip area into standardized 8×8 grid cells so that each cell contains an appropriate number of pins and wires.

3. A fast routing method with adaptive standard frame adjustment and through-hole optimization according to claim 2, characterized in that: The congestion assessment operation includes: After initialization into 8×8 grid cells, congestion assessment is performed on each cell; the congestion value of each cell is calculated to determine whether further subdivision is required.

4. A fast routing method with adaptive standard frame adjustment and through-hole optimization according to claim 3, characterized in that: The calculation formula of the congestion value is: Congestion=α×wlen+β×irs+γ×pins+δ×pins_area+∈×blks+ζ×blks_are a+η×nets; Among them: wlen represents the global wiring length of the area; irs ​​represents the number of iroutes in the area; pins represents the number of pins in the area; pins_area represents the total area of ​​the pins in the area; blks represents the number of blockers in the area; blks_area represents the total area of ​​the blockers in the area; nets represents the number of different network segments in the area; α, β, γ, δ, ε, ζ and η are weight parameters that adjust the degree of influence of each factor.

5. The fast routing method with adaptive standard frame adjustment and through-hole optimization according to claim 1, characterized in that: After congestion evaluation, each region is divided into high congestion, medium congestion, and low congestion regions, and a standard box size is matched for each type of region.

6. A fast routing method with adaptive standard frame adjustment and through-hole optimization according to claim 5, characterized in that: The high congestion area is kept at 8×8, providing sufficient computing resources to optimize routing; The moderately congested area is reduced to 4×4 to balance wiring quality and efficiency; The low congestion area is further reduced to 2×2, which improves routing speed and reduces calculation time.

7. A fast routing method with adaptive standard frame adjustment and through-hole optimization according to claim 6, characterized in that: After the area classification, the areas marked as low congestion are divided twice to further refine the wiring resource allocation.

8. The fast routing method with adaptive standard frame adjustment and through-hole optimization according to claim 6, characterized in that: In the secondary division stage, the low congestion area is subdivided into small grids and the number of rewiring times is determined. If the number of rewiring times of the area exceeds the preset upper limit, no further division is allowed.

9. The fast routing method with adaptive standard frame adjustment and through-hole optimization according to claim 1, characterized in that: During routing operations, connectable pins are traversed and the next connection point is dynamically selected based on a weighted via impact assessment model.

10. The fast routing method with adaptive standard frame adjustment and through-hole optimization according to claim 9, characterized in that: The weighted via impact assessment model adopts a weighted cost model to minimize the Manhattan distance while penalizing excessive via usage; by controlling the weights of various factors, it adaptively optimizes connectivity and resource allocation according to design requirements; To evaluate each candidate pin, the cost of the potential path is calculated, the cost function: Costpin=Δx+Δy+Δz+α*via_count; Where Δx, Δy, and Δz represent the horizontal, vertical, and vertical distances between the current pin and the candidate pin, respectively. via_count is the estimated number of vias in the global routing. α is an adjustable parameter that assigns weights to the use of vias, giving priority to reducing the number of vias.

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