Interrupt system integrated automation tool

Abstract

The invention discloses an interrupt system integrated automation tool, which relates to the field of interrupt signal processing, and comprises an input layer: a standardized table management unit for establishing a standardized input system of interrupt signals and ensuring that the formats of multi-module data are unified; the processing layer comprises an automatic logic processing unit which is used for analyzing table data, constructing an interrupt signal logic model and completing preprocessing; the output layer comprises a code and report generation unit used for outputting hardware description codes and matched documents; and the supporting framework comprises a system interface and an error processing unit and is used for realizing module interaction and exception processing. Through layered decoupling design, a complex interrupt system integration process is disassembled into four modules including input standardization, logic processing, code generation and whole process support, all the units cooperate closely through structured data transmission and interface interaction, and finally efficient automation from demand collection to design verification is achieved. The labor cost is obviously reduced; and the design accuracy is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of interrupt signal processing, in particular to an interrupt system integration automation tool. BACKGROUND

[0002] In chip design, interrupt signals are one of the core elements, with various types and complex priority alignment logic. Traditional interrupt signal integration relies on designers to manually collect interrupt information from each module and implement integration by writing code line by line. This process has significant defects: low efficiency, requiring cross-module coordination and communication, manual statistics and coding being time-consuming and laborious, especially in a multi-module collaboration scenario, the single designer coordination mode leads to a long process; insufficient accuracy, manual operation is prone to integration errors due to signal omission, priority errors or code logic loopholes, which need to be checked and solved by code inspection, which is inefficient and prone to missed judgment; poor maintainability, interrupt logic is directly embedded in the code, and the signal relationship is hidden, which requires deep code details modification when the demand changes or debugging, which is costly and prone to introduce new problems.

[0003] However, in the prior art, there is a lack of a tool that can standardize interrupt signal input and automate the integration process, leading to a prolonged chip design cycle, increased labor costs, and difficulty in meeting the requirements of complex SoC chips for interrupt system efficiency and reliability. Therefore, an automation tool is urgently needed to solve the problems of low efficiency and low accuracy of traditional manual integration. SUMMARY

[0004] The present application relates to the technical field of interrupt signal processing, in particular to an interrupt system integration automation tool.

[0005] To achieve the above-mentioned purpose, the present application provides the following technical solution: an interrupt system integration automation tool, comprising:

[0006] Input layer: standardized table management unit, for establishing a standardized input system of interrupt signals to ensure uniform data format of multiple modules;

[0007] Processing layer: automatic logic processing unit, for parsing table data, constructing interrupt signal logic model and completing preprocessing;

[0008] Output layer: code and report generation unit, for outputting hardware description code and supporting documents;

[0009] Support architecture: system interface and error handling unit, for realizing module interaction and exception handling.

[0010] Preferably, the standardized table management unit comprises:

[0011] A table template generator generates an interrupt signal collection template containing fixed fields, including: interrupt number: a unique digital code for identifying priority or physical connection; module source: a chip module to which the signal belongs; interrupt name: adopting a three-part naming rule of "source name_to_destination name_interrupt function name"; and a logic column for identifying logical or merging relationship under the same interrupt number.

[0012] A data verifier verifies the legality of input data in real time, and the verification rules include format verification and logic verification.

[0013] Preferably, the code and report generation unit includes:

[0014] A code generator outputs Verilog code conforming to EDA tool specifications, including module declaration, priority logic and logic merging operation;

[0015] An integrated report generator generates a readable report containing a signal list, a priority mapping diagram and a logic merging diagram.

[0016] Preferably, the system interface and error handling unit includes:

[0017] A system interface unit supports Excel / CSV file reading for the input interface, generates Verilog files and PDF / HTML reports for the output interface, and supports import of EDA tools;

[0018] An error handling unit captures file format errors, data logic errors and other exceptions, locates error line numbers and generates an editable mark table.

[0019] Preferably, the input layer outputs legal structured data through the table template generator and the data verifier, and transmits the data to the data parser of the processing layer;

[0020] The data parser converts table data into JSON / instance for further processing by the priority arranger and the logic merger.

[0021] Preferably, the priority arranger generates a priority list, and the logic merger generates a signal merging expression, both of which are combined with the code template engine to dynamically fill in the Verilog template.

[0022] The code generator outputs compilable code based on the filled-in template, and the integrated report generator generates a visual report based on the processed data.

[0023] Preferably, the system interface unit provides a file reading interface for the input layer and a file generation interface for the output layer, and supports automatic code import.

[0024] Preferably, the error processing unit: captures format / logic errors when checking data in the input layer, captures missing parameters when parsing templates in the processing layer, captures rendering exceptions when generating code in the output layer, and feeds back error information and locates the problem line.

[0025] Compared with the prior art, the present application has the beneficial effects that:

[0026] In the present application, the tool is divided into four layers by hierarchical decoupling design, i.e., an input layer responsible for standardized input, a processing layer responsible for logic processing, an output layer responsible for code and report generation, and a support architecture responsible for system interaction and exception handling, the complex interrupt system integration process is disassembled into four modules of 'input standardization->logic processing->code generation->full-process support', each unit closely cooperates through structured data transmission and interface interaction, and finally realizes efficient automation from requirement collection to design verification, significantly reduces manual cost and improves design accuracy. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 is a component block diagram of the interrupt system integration automation tool in the present application;

[0028] Figure 2 is a processing flow block diagram of the interrupt system integration automation tool in the present application;

[0029] Figure 3 is an interrupt signal diagram of the interrupt system integration automation tool in the present application. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0031] Embodiment one: refer to Figures 1-3 As shown: the interrupt system integration automation tool includes a standardized table management unit as an input layer, an automated logic processing unit as a processing layer, a code and report generation unit as an output layer, and a system interface and error processing unit as a support architecture.

[0032] I. Input layer: standardized table management unit, the core function of which is to establish a standardized input system of interrupt signals, ensure uniform data format and clear semantics of multiple modules, and reduce collaboration cost.

[0033] 1. Table template generator, which is used to generate an interrupt signal collection template containing fixed fields, and forces the format and semantics of the input content to be standardized. The technology implemented is field definition and template format:

[0034] (1) Field definition (based on document).

[0035] Interrupt number (mandatory): a unique numerical code (e.g. "180" "960") used to identify the interrupt priority or physical connection;

[0036] Module source (mandatory): mark the chip module to which the signal belongs (e.g. "CPU" "DMA" or "1000C" "101" etc. in the document);

[0037] Interrupt name (mandatory): use a three-part naming rule "source name_to_destination name_interrupt function name" (e.g. "uart_to_cpu_rx_overflow"), to ensure traceability of signal flow and function;

[0038] Logic column (optional): when multiple signals share the same interrupt number, add "OR" keyword before the corresponding interrupt name (e.g. "OR adc_to_cpu_conv_done"), to identify the logical or merge relationship.

[0039] (2) Template format: support Excel (.xlsx) or CSV format, with pre-set field order and data type verification (e.g. interrupt number is an integer, interrupt name does not contain special symbols).

[0040] 2. Data verifier, which is used to verify the legality of input data in real time and prevent illegal data from entering the processing flow, including verification rules and feedback mechanisms.

[0041] (1) Verification rules:

[0042] Format verification: interrupt number must be a positive integer and within the chip interrupt number address space range (e.g. 0-1023); interrupt name must comply with the "source name_to_destination name_function name" rule, and spaces and special symbols (except underscore) are prohibited; Logic column is only allowed to fill in "OR" or leave blank, and is only valid when there are multiple data lines for the same interrupt number.

[0043] Logical verification: interrupt number is unique within the same table, and duplication is prohibited; when "OR" is present in the Logic column, it must correspond to multiple signals of the same interrupt number (e.g. document example); module source must match the legal module list defined by the chip architecture (e.g. pre-defined module library).

[0044] (2) Feedback mechanism: Highlight illegal data in red and generate error reports (e.g., "Interrupt number 960 is defined multiple times" or "Interrupt name lacks destination identifier").

[0045] II. Processing layer: An automated logic processing unit that primarily functions to parse table data, construct interrupt signal logic models, and perform preprocessing such as priority arrangement and signal merging to provide structured data for code generation. It includes data parsers, priority arrangers, logic mergers, and code template engines.

[0046] 1. Data parser: Its function is to convert table data into machine-readable structured data (such as JSON objects or class instances).

[0047] Technical implementation: Use Python libraries (such as pandas, openpyxl) to read tables, parse interrupt numbers, module sources, interrupt names, and Logic columns by row, and convert them into structured data such as JSON objects or class instances.

[0048] 2. Priority arranger: Its function is to determine the response priority of interrupt signals, supporting static priority (such as interrupt number) or dynamic configuration.

[0049] (1) Arrangement rules have the following two types:

[0050] Default rule (based on implicit logic in the document): The larger the interrupt number, the higher the priority (e.g., interrupt number 960 > 180);

[0051] Extended support: Allow adding a "priority" column (0-255, the larger the value, the higher the priority) in the table to override the default rule.

[0052] (2) Output results: Generate a priority list, such as: [("960", "high"), ("180", "medium")].

[0053] 3. Logic merger: Its function is to merge multiple signals under the same interrupt number and generate logic or expressions. The implementation logic is to group by interrupt number, filter out signal groups containing the "OR" keyword; for each signal group, remove the "OR" prefix to generate a logic or expression.

[0054] 4. The code template engine dynamically populates Verilog code templates based on preprocessed structured data to generate compilable RTL files. The template structure of the code template engine is based on Verilog code and includes a modular declaration framework. It reserves dynamically populated interfaces through placeholders (such as {{num_intr}}{{input_ports}}{{priority_logic}}{{merge_logic}}, corresponding to key content such as the number of interrupt signals, input port declarations, priority encoding logic, and signal merging logic. Ultimately, data matching generates a complete, compilable RTL code file.

[0055] Its dynamic filling rules are:

[0056] Input port: Generate a unique port name based on the module source and interrupt number, such as input wire intr_{{module}}_{{id}};

[0057] Priority logic: Generates conditional statements based on the priority list (e.g., when interrupt number 960 has a higher priority than 180, it is assigned first);

[0058] Logic merging: Insert the expression in merged_signals into the logic block corresponding to the interrupt number.

[0059] Output layer: Code and report generation unit. Its core function is to output standardized hardware description code and supporting documentation to ensure design traceability and easy verification. It includes a code generator and an integrated report generator.

[0060] 1. Code generator, whose function is to generate Verilog code that complies with EDA tool specifications and implement the integrated logic of interrupt signals.

[0061] The output content is module declaration: including input and output ports; priority logic: assigning bus priority according to the size of the interrupt number; logical merge: implementing the physical OR operation of the "OR" signal.

[0062] 2. The integrated report generator generates human-readable integrated result reports to assist designers in quick verification.

[0063] The report contains the following contents:

[0064] (1) Signal list:

[0065] Interrupt number Module source Interrupt name Priority Merge status 180 1000C cpu_to_axi_interrupt_req High Merge with tx_err 960 101 uart_to_cpu_tx_err High Merge with rx_err 960 101 ​ ​ ​

[0066] (2) Priority Map: Visually displays the correspondence between interrupt numbers and bus widths;

[0067] (3) Logic merge schematic diagram: use flowchart to represent the merging path of "OR" signals.

[0068] Four, support architecture: system interface and error handling unit, including system interface unit and error handling unit.

[0069] 1. System interface unit, its function is to realize the interaction between module and external tool, including file reading and writing, data transmission. Its technical implementation is input interface: support Excel / CSV file reading, compatible with mainstream office software; output interface: generate Verilog file (.v) and report file (PDF / HTML), support automatic import EDA tool (such as Vivado's IPIntegrator).

[0070] 2. Error handling unit, its function is to capture and handle the exception in the running of module, provide friendly error prompt.

[0071] Exception types include: file format error: such as missing required columns (interrupt number, module source) in table; data logic error: such as the same interrupt number corresponding to different module sources; code generation error: such as missing parameters when rendering template.

[0072] Its processing mechanism is to throw specific error information (such as "interrupt number 960 is repeated in Sheet1, please check"); locate error line number and field, generate directly editable mark table (such as mark problem line with red)

[0073] In summary, the tool has the following advantages:

[0074] 1. Full-process automation, improve efficiency. Cover the whole chain of requirement collection→code generation: through the pipeline design of input layer standardized table, processing layer logic automation, output layer code and report generation, replace traditional manual configuration and coding process, reduce manual operation steps, shorten design cycle. Data parser (Python library), code template engine (dynamic filling Verilog) and other components realize the non-intervention of data processing and code generation, reduce labor cost.

[0075] 2. Standardized input system, reduce collaboration cost. Mandatory format specification: input layer through fixed field template (interrupt number, module source, three-part interrupt name) and data verifier (format / logic verification), ensure that multi-module data format is uniform and semantic is clear, avoid communication errors and repeated modifications caused by data confusion.

[0076] 3. Logic processing automation, reducing human error. Priority and merging logic standardization: The processing layer uses a priority scheduler (default rules + dynamic configuration) and a logic merger (automatically generates OR expressions) to avoid logical omissions when manually arranging priorities or merging signals, improving design consistency. Data structure conversion: Table data is automatically converted to JSON / instance, avoiding field omission or errors caused by manual parsing of tables, ensuring the accuracy of subsequent processing.

[0077] 4. Code generation standardization and compilability. Compliance with EDA tool specifications: The output layer code generator dynamically fills in Verilog templates, generating RTL code that includes modular declarations, priority logic, and logic merging operations, which can be directly imported into EDA tools (such as Vivado) for compilation, reducing code debugging time. Dynamic filling rules are clear: port names, priority logic, and merging expressions are generated according to preset rules (such as intr_{{module}}_{{id}}), avoiding format errors or compliance issues caused by manual coding.

[0078] 5. Visualized reports and traceability. Integrated reporting aids verification: The output layer generates readable reports containing signal lists, priority mapping diagrams, and logic merging diagrams, allowing designers to quickly compare requirements and implementation results, improving verification efficiency. Data link traceability: Each link from input tables to code generation (such as interrupt number mapping and signal merging paths) is visualized in the report, facilitating problem localization and version iteration tracking.

[0079] 6. Full-process exception handling and stability. Real-time error capture: The error handling unit throws exceptions in real-time during input verification (such as duplicate interrupt numbers), data parsing (such as missing fields), and code generation (such as template parameter errors), locates error lines, and generates editable marker tables, reducing the risk of "dirty data" flowing into subsequent processes. Friendly feedback mechanism: Through red highlighting and specific error information (such as "interrupt name missing destination identifier"), the debugging threshold is reduced, and problem repair efficiency is improved.

[0080] 7. Cross-tool compatibility and extensibility. Flexible input and output interfaces: The system interface unit supports Excel / CSV input (compatible with mainstream office software) and Verilog / PDF / HTML output (supports automatic import into EDA tools), facilitating integration with existing design toolchains.

[0081] There is a layered decoupling architecture: each layer (input / processing / output / support) function is independent, the bottom technology can be replaced (such as replacing the code template language, extending the verification rule), and the expansion of different chip architectures or design requirements is adapted. Through the fine design of the above units, the module realizes the full-process automation from requirement collection to logic processing to code generation to result verification, ensuring the efficiency, accuracy and traceability of the integrated interrupt system.

[0082] Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art can modify the technical solutions recorded in the foregoing embodiments or make equivalent replacements for part of the technical features, and any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. Interrupt system integration automation tool, characterized by, include: Input layer: Standardized table management unit, used to establish a standardized input system for interrupt signals to ensure the uniformity of multi-module data formats; Processing layer: Automated logic processing unit, used to parse table data, build interrupt signal logic model and complete preprocessing; Output layer: code and report generation unit, used to output hardware description code and supporting documents; Support architecture: system interface and error handling unit, used to implement module interaction and exception handling.

2. The interrupt system integration automation tool according to claim 1, characterized in that: Standardized form management units include: The table template generator generates interrupt signal collection templates containing fixed fields, including: Interrupt Number: a unique numeric code used to identify priority or physical connection; Module Source: identifies the chip module to which the signal belongs; Interrupt Name: uses a three-part naming convention of "Source Terminal Name_To_Destination Terminal Name_Interrupt Function Name"; and the Logic column, used to identify logical or merge relationships under the same interrupt number. Data validator verifies the legitimacy of input data in real time. Verification rules include format verification and logic verification.

3. The interrupt system integration automation tool according to claim 2, characterized in that: The code and report generation unit includes: Code generator, which outputs Verilog code that complies with EDA tool specifications, including module declarations, priority logic, and logic merging operations; An integrated report generator generates readable reports containing signal lists, priority maps, and logic merging diagrams.

4. The interrupt system integration automation tool according to claim 3, characterized in that: The system interface and error handling unit includes: System interface unit, the input interface supports Excel / CSV file reading, the output interface generates Verilog files and PDF / HTML reports, and supports importing into EDA tools; The error handling unit captures exceptions such as file format errors and data logic errors, locates the error line number and generates an editable markup table.

5. The interrupt system integration automation tool according to claim 4, characterized in that: The input layer outputs legal structured data through the table template generator and data validator, and passes it to the data parser of the processing layer; The data parser converts tabular data into JSON / class instances for further processing by the priority orchestrator and logic merger.

6. The interrupt system integration automation tool according to claim 5, characterized in that: The priority arranger generates a priority list, and the logic combiner generates a signal merging expression. Both are combined with the code template engine to dynamically fill in the Verilog template; The code generator outputs compilable code based on the filled-in templates, and the integrated report generator produces visual reports based on the processed data.

7. The interrupt system integration automation tool according to claim 6, characterized in that: System interface unit: provides a file reading interface for the input layer, a file generation interface for the output layer, and supports automatic code import.

8. The interrupt system integration automation tool according to claim 7, characterized in that: Error handling unit: Captures format / logic errors when validating data at the input layer, captures missing parameters when parsing templates at the processing layer, and captures rendering exceptions when generating code at the output layer. It provides unified feedback on error information and locates the problem line.

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