Pickup circuit and electronic device

Abstract

The invention discloses a pickup circuit and electronic equipment. The pickup circuit comprises at least one audio acquisition module (YM); the audio acquisition module (YM) comprises an analog-to-digital conversion unit (ADU) and at least one audio detection unit (MA); the audio detection unit (MA) is electrically connected with the analog-to-digital conversion unit (ADU) and is used for generating an analog audio signal and transmitting the analog audio signal to the analog-to-digital conversion unit (ADU); the analog-to-digital conversion unit (ADU) is configured to generate a digital audio signal from an analog audio signal provided by the audio detection unit (MA). The pickup circuit can improve the stability of audio signal transmission.

Description

Pickup circuits and electronics Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a sound pickup circuit and an electronic device. Background Art

[0002] Electronic devices are placing increasingly stringent demands on audio pickup circuits to meet these evolving needs. For example, as televisions move toward larger sizes and narrower bezels, ensuring stable audio signal transmission becomes increasingly crucial. Furthermore, with the increasing integration of electronic devices, the variety of integrated electronic systems is increasing, and the interference these systems cause on audio signal transmission is becoming increasingly severe.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Summary of the Invention

[0005] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and provide a sound pickup circuit and electronic equipment to improve the stability of audio signal transmission.

[0006] According to a first aspect of the present disclosure, there is provided a sound pickup circuit, comprising at least one audio acquisition module; the audio acquisition module comprises an analog-to-digital conversion unit and at least one audio detection unit;

[0007] The audio detection unit is electrically connected to the analog-to-digital conversion unit, and is used to generate an analog audio signal and transmit it to the analog-to-digital conversion unit;

[0008] The analog-to-digital conversion unit is configured to generate a digital audio signal according to the analog audio signal provided by the audio detection unit.

[0009] According to an embodiment of the present disclosure, the audio acquisition module includes two audio detection units, and the two audio detection units are respectively located on both sides of the analog-to-digital conversion unit.

[0010] According to an embodiment of the present disclosure, there are multiple audio acquisition modules and the sound pickup circuit further includes a data bus;

[0011] The analog-to-digital conversion units of the audio acquisition modules are all interactively connected to the data bus;

[0012] The analog-to-digital conversion unit is configured to output the digital audio signal to the data bus.

[0013] According to an embodiment of the present disclosure, the sound pickup circuit further includes a circuit board, and the plurality of audio acquisition modules are arranged sequentially along a first direction on the circuit board.

[0014] According to one embodiment of the present disclosure, an infrared receiver is provided on the circuit board, and the infrared receiver is electrically connected to the data bus.

[0015] According to one embodiment of the present disclosure, the size of the circuit board in the first direction is 20 to 30 times the size of the circuit board in the second direction; the second direction is parallel to the plane where the circuit board is located and perpendicular to the first direction.

[0016] According to an embodiment of the present disclosure, the audio detection unit includes an audio acquisition chip.

[0017] According to an embodiment of the present disclosure, the audio acquisition chip has a positive output pin and a negative output pin;

[0018] The audio detection unit further includes a first filtering subcircuit and a second filtering subcircuit;

[0019] The first filtering sub-circuit is used to filter out differential mode interference between the positive output pin and the negative output pin;

[0020] The second filtering sub-circuit is used to filter out common-mode interference of the positive output pin and the negative output pin.

[0021] According to one embodiment of the present disclosure, the analog-to-digital conversion unit includes an analog-to-digital conversion chip and a third filtering sub-circuit, the analog-to-digital conversion chip having an input port corresponding one-to-one to at least one of the audio detection units; the audio detection unit is electrically connected to the corresponding input port through the third filtering sub-circuit.

[0022] According to an embodiment of the present disclosure, the pickup circuit further includes a data bus, and the data bus includes an IIC signal bus;

[0023] The analog-to-digital conversion unit includes an analog-to-digital conversion chip, and the analog-to-digital conversion chip has an IIC signal terminal; the IIC signal terminal is interactively connected to the IIC signal bus.

[0024] According to an embodiment of the present disclosure, the pickup circuit further includes a data bus, and the data bus includes a TDM signal bus;

[0025] The analog-to-digital conversion unit includes an analog-to-digital conversion chip, and the analog-to-digital conversion chip has a TDM signal terminal; the TDM signal terminal is interactively connected to the TDM signal bus.

[0026] According to an embodiment of the present disclosure, the pickup circuit further includes a data bus, and the data bus includes an IIS signal bus;

[0027] The analog-to-digital conversion unit includes an analog-to-digital conversion chip, and the analog-to-digital conversion chip has an IIS signal terminal; the IIS signal terminal is interactively connected to the IIS signal bus.

[0028] According to an embodiment of the present disclosure, the pickup circuit further includes a data bus, and the data bus includes an IIC signal bus, a TDM signal bus, and an IIS signal bus;

[0029] The analog-to-digital conversion unit includes an analog-to-digital conversion chip, which has an IIC signal terminal, a TDM signal terminal, and an IIS signal terminal; the IIC signal terminal is interactively connected to the IIC signal bus; the TDM signal terminal is interactively connected to the TDM signal bus; and the IIS signal terminal is interactively connected to the IIS signal bus.

[0030] The analog-to-digital conversion unit is configured to be configured as one of a first operating mode and a second operating mode under the control of the IIC signal terminal;

[0031] In the first working mode, the analog-to-digital conversion chip sends the digital audio signal to the TDM signal bus through the TDM signal terminal;

[0032] In the second working mode, the analog-to-digital conversion chip sends the digital audio signal to the IIS signal bus through the IIS signal terminal.

[0033] According to an embodiment of the present disclosure, the analog-to-digital conversion unit includes a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, and an address configuration circuit;

[0034] The analog-to-digital conversion chip further comprises a first power pin, a second power pin, a third power pin, a first reference pin, a second reference pin, a ground pin, and an address configuration port;

[0035] The first end of the fifth capacitor and the first end of the sixth capacitor are both electrically connected to the first power pin, and the second end of the fifth capacitor and the second end of the sixth capacitor are both used to load a ground voltage;

[0036] The first end of the seventh capacitor is electrically connected to the second reference pin, and the first end of the eighth capacitor is electrically connected to the first reference pin; the second end of the seventh capacitor and the second end of the eighth capacitor are both used to load the ground voltage;

[0037] The second power pin is electrically connected to the first end of the ninth capacitor and is used to apply a power supply voltage; the third power pin is electrically connected to the first end of the tenth capacitor and is used to apply the power supply voltage; the second end of the ninth capacitor and the second end of the tenth capacitor are both used to apply the ground voltage;

[0038] The ground pin is used to load the ground voltage;

[0039] The address configuration circuit is electrically connected to the address configuration port to configure the address of the analog-to-digital conversion chip.

[0040] According to an embodiment of the present disclosure, the pickup circuit is further provided with a data bus and a motherboard interface; each of the analog-to-digital conversion units is interactively connected to the data bus, and the motherboard interface is connected to the data bus;

[0041] The distance between the audio detection unit and the analog-to-digital conversion unit is smaller than the distance between the mainboard interface and the analog-to-digital conversion unit.

[0042] According to a second aspect of the present disclosure, an electronic device is provided, wherein the electronic device is provided with the pickup circuit.

[0043] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0045] FIG1 is a schematic structural diagram of an electronic device in one embodiment of the present disclosure.

[0046] FIG2 is a schematic diagram showing the principle of a sound pickup circuit in one embodiment of the present disclosure.

[0047] FIG3 is a schematic structural diagram of a sound pickup circuit in one embodiment of the present disclosure.

[0048] FIG4 is a schematic diagram showing the principle of an audio detection unit in one embodiment of the present disclosure.

[0049] FIG5 is a schematic diagram showing the principle of an analog-to-digital conversion unit in one embodiment of the present disclosure.

[0050] FIG6 is a schematic diagram of a partial structure of a sound pickup circuit in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0052] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0053] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0054] Referring to FIG1 , an embodiment of the present disclosure provides an electronic device, particularly a household appliance capable of intelligent voice control, such as a smart refrigerator, smart TV, smartphone, smart speaker, smart lamp, smart electronic screen, etc. The electronic device may include a sound pickup circuit to detect voice in the environment.

[0055] Optionally, referring to FIG1 , the electronic device may include a sound pickup circuit, a control module CTR, and a device body (e.g., a display module of a television); the sound pickup circuit may detect voice in the environment and send an audio signal to the control module CTR, and the control module CTR may generate instructions based on the audio signal and thereby control the action of the device body.

[0056] For example, an electronic device such as a television includes a sound pickup circuit, a control module (CTR), and a display module, which serves as the main device. The sound pickup circuit detects ambient sound waves and generates an audio signal, which is then sent to the control module (CTR). The control module (CTR) processes the audio signal and determines whether to generate an action command, or what action command to generate. When the control module (CTR) generates an action command, it can cause the display module to operate. In one example, action commands include, but are not limited to, playing the previous channel, playing the next channel, turning up the volume, turning down the volume, increasing the brightness, decreasing the brightness, pausing, playing, and searching.

[0057] In one example, the television has a lower frame, and the pickup circuit can be arranged at the lower frame of the television, that is, at the lower side of the television.

[0058] Electronic devices are currently placing increasingly stringent demands on their audio pickup circuits to meet these evolving needs. For example, as televisions move toward larger sizes and narrower bezels, ensuring stable audio signal transmission becomes increasingly crucial. Furthermore, with the increasing integration of electronic devices, the variety of integrated electronic systems is increasing, and the interference these systems cause on audio signal transmission is becoming increasingly severe.

[0059] In an embodiment of the present disclosure, referring to FIG. 2 , the sound pickup circuit includes at least one audio acquisition module YM; the audio acquisition module YM includes an analog-to-digital conversion unit ADU and at least one audio detection unit MA.

[0060] The audio detection unit MA is electrically connected to the analog-to-digital conversion unit ADU, and is used to generate an analog audio signal and load it into the analog-to-digital conversion unit ADU; the analog-to-digital conversion unit ADU is configured to generate a digital audio signal based on the analog audio signal provided by the audio detection unit MA.

[0061] In an embodiment of the present disclosure, the audio acquisition module YM includes an audio detection unit MA capable of outputting an analog audio signal. The audio detection unit MA does not need to output a digital audio signal, so the audio detection unit MA does not need a digital clock signal from the control module CTR, thereby avoiding interference with the digital clock signal during long-distance transmission (from the control module CTR to the audio detection unit MA) and causing signal errors. In the related art, the audio detection unit MA often directly outputs a digital audio signal, and the audio detection unit MA needs to obtain a clock signal from the control module CTR; however, the signal path from the control module CTR to the audio detection unit MA is not only long, but the electromagnetic environment along the path is also relatively complex, which makes it easy for the clock signal to error when it reaches the audio detection unit MA. Therefore, compared with the related art, the embodiment of the present disclosure avoids the distortion caused by clock signal errors by adopting an audio detection unit MA capable of outputting an analog audio signal, thereby improving the accuracy and reliability of audio transmission. In an embodiment of the present disclosure, the audio acquisition module YM is also provided with an analog-to-digital conversion unit ADU, which can convert the analog audio signal into a digital audio signal and transmit the digital audio signal to the control module CTR. In this way, the analog-to-digital conversion unit ADU can use digital signals to transmit digital audio signals, avoiding signal attenuation when using analog signals for long-distance transmission and signal distortion caused by the introduction of other interference sources.

[0062] Therefore, the pickup circuit of the embodiment of the present disclosure can transmit voice signals more stably and accurately in the increasingly complex electromagnetic environment in which electronic devices are located, which is conducive to improving the accuracy of voice recognition and enhancing the user's voice interaction experience.

[0063] In one embodiment of the present disclosure, the audio acquisition module YM includes two audio detection units MA, and the two audio detection units MA are respectively located on both sides of the analog-to-digital conversion unit ADU. For example, the audio acquisition module YM includes a first audio detection unit MAL and a second audio detection unit MAR, and the first audio detection unit MAL and the second audio detection unit MAR are both capable of transmitting analog audio signals to the analog-to-digital conversion unit ADU in the same audio acquisition module YM. The analog-to-digital conversion unit ADU can convert the analog audio signals generated by the first audio detection unit MAL and the second audio detection unit MAR into digital audio signals. In this example, each audio acquisition module YM includes two audio detection units MA, which can realize multi-point audio input and improve the reliability of sound pickup. At the same time, the two audio detection units MA in the same audio acquisition module YM are respectively located on both sides of the analog-to-digital conversion unit ADU, which can maintain an appropriate distance between the two audio detection units MA, which is conducive to the arraying of the various audio detection units MA of the sound pickup circuit.

[0064] Of course, it is understandable that in other embodiments of the present disclosure, three or more audio detection units MA may also be provided in one audio acquisition module YM.

[0065] In one embodiment of the present disclosure, referring to FIG2 , the pickup circuit further includes a data bus BUS, and the number of audio acquisition modules YM is multiple; the analog-to-digital conversion units ADU of the multiple audio acquisition modules YM are all interactively connected to the data bus BUS. On the one hand, by providing multiple audio acquisition modules YM, an array arrangement of the audio detection unit MA can be realized, which is beneficial for sampling and filtering the spatial characteristics of the sound field. On the other hand, by providing the data bus BUS, the various audio acquisition modules YM can be flexibly configured and the wiring space can be reduced, which is beneficial for controlling or even reducing the size of the pickup circuit while increasing the number of audio acquisition modules YM.

[0066] In this example, the MA array can suppress noise and enhance human voices through beamforming technology. Furthermore, the MA array only recognizes sounds from a certain angle (generally adjustable), while sounds from other angles are suppressed, thereby achieving the purpose of suppressing noise.

[0067] In one example, as shown in Figure 3 , the sound pickup circuit also includes a PCB. By providing a data bus (BUS), the complexity of routing on the PCB can be reduced, as can the size of the PCB, thereby enabling the PCB's dimensions to be tailored to the environment in which it is used. For example, the PCB can be made slender, thus meeting the PCB size requirements of large, narrow-framed, and thin-body televisions.

[0068] Optionally, multiple audio acquisition modules YM are arranged sequentially along a first direction on the circuit board PCB. In this manner, the sound pickup circuit can include a linear array of audio acquisition modules YM, facilitating sampling of the spatial characteristics of the sound field using a limited number of audio acquisition modules YM to facilitate spatial filtering. Furthermore, the linear arrangement of multiple audio acquisition modules YM along the first direction facilitates the slenderness of the circuit board PCB, thereby facilitating the placement of the sound pickup circuit on the electronic device.

[0069] Optionally, the size of the PCB in the first direction is 20 to 30 times the size of the PCB in the second direction; the second direction is parallel to the plane of the PCB and perpendicular to the first direction. For example, the size of the PCB in the first direction is between 150 and 250 mm, such as 150 mm, 156 mm, 162 mm, 168 mm, 174 mm, 180 mm, 186 mm, 192 mm, 198 mm, 204 mm, 210 mm, 216 mm, 222 mm, 228 mm, 234 mm, 240 mm, 245 mm, or 250 mm. For another example, the dimension of the circuit board PCB in the second direction is between 5 and 12.5 mm, such as 5.0 mm, 5.5 mm, 6.0 mm, 6.5 mm, 7.0 mm, 7.5 mm, 8.0 mm, 8.5 mm, 9.0 mm, 9.5 mm, 10.0 mm, 10.5 mm, 11.0 mm, 11.5 mm, 12.0 mm, and 12.5 mm.

[0070] In one example, the audio detection units MA in the pickup circuit are arranged in sequence with equal spacing along the first direction. This helps the control module CTR extract the spatial features of the sound field based on the audio information collected by the audio detection units MA, reducing the amount of calculation.

[0071] In one example, an infrared receiver is provided on the circuit board PCB, and the infrared receiver is electrically connected to the data bus BUS. In this way, the infrared receiver can be electrically connected to the control module CTR via the data bus BUS, for example, interacting with the control module CTR. Accordingly, the electronic device can interact with a remote controller (such as a TV remote control) via infrared. For example, the infrared receiver can receive an infrared control signal emitted by the remote controller and convert it into a control signal, such as an analog control signal or a digital control signal. The control signal can be transmitted to the control module CTR via the data bus BUS; the control module CTR can generate corresponding control instructions based on the control signal to control the device body, such as controlling the TV to switch channels, increase the volume, reduce the brightness, etc.

[0072] In this example, the electronic device can respond to infrared signals and voice signals, for example, it can be remotely awakened by voice commands; this means that the user's control over the electronic device is no longer limited to direct contact control and remote control, and can be directly voice controlled without the aid of a remote controller, which can greatly improve the user experience.

[0073] In one embodiment of the present disclosure, referring to FIG3 , the sound pickup circuit further comprises a data bus BUS and a motherboard interface CNT; each of the analog-to-digital conversion units ADU is interconnected with the data bus BUS, and the motherboard interface CNT is connected to the data bus BUS. The distance between the audio detection unit MA and the analog-to-digital conversion unit ADU is less than the distance between the motherboard interface CNT and the analog-to-digital conversion unit ADU.

[0074] In this way, the distance between the audio detection unit MA and the analog-to-digital conversion unit ADU is relatively short, and the transmission of the analog audio signal is not easily interfered with.

[0075] In one embodiment of the present disclosure, the circuit board PCB is provided with an on-board power supply to supply power to the audio acquisition module YM.

[0076] In one embodiment of the present disclosure, a circuit board (PCB) includes multiple metal layers, at least one of which is a reference ground layer for applying a ground voltage (GND). No signal traces are provided on this reference ground layer. However, structures above and below the ground layer can be electrically connected and signal transmitted using vias passing through the reference ground layer. This improves signal stability.

[0077] In one embodiment of the present disclosure, an isolation structure (such as an isolation line) is provided on the circuit board PCB, and at least some signal lines on the same layer are isolated from each other by an isolation ground line between signals, thereby reducing crosstalk between the two signal lines.

[0078] In one example, a circuit board (PCB) comprises four stacked metal layers. The first metal layer is a power layer, providing power voltage to various components. The second metal layer is a routing layer, which may be provided with routing lines for signal transmission, such as the signal lines of a data bus (BUS). The third layer is a reference ground layer, and the fourth layer is a device layer, used to bind or connect various required electronic components, such as an audio acquisition chip (UA), an analog-to-digital conversion chip (UB), capacitors, resistors, etc.

[0079] In one example, ground signal lines are provided in at least some areas of both the first and second metal layers, and the ground signal lines of the two layers are designed to cross and run parallel to each other. This can better enhance the electromagnetic shielding effect between the two layers and improve the stability and reliability of signal transmission.

[0080] In one embodiment of the present disclosure, referring to FIG4 , the audio detection unit MA includes an audio acquisition chip UA that can acquire sound wave signals and output analog audio signals.

[0081] In one example, the audio acquisition chip UA is a MEMS (micro-electromechanical system) microphone, which is a microphone manufactured based on MEMS technology. For example, a MEMS microphone includes a capacitor integrated on a micro silicon wafer, can be manufactured using a surface mount process, can withstand high reflow soldering temperatures, is easily integrated with CMOS processes and other audio circuits, and has improved noise cancellation performance, good radio frequency noise suppression performance, and electromagnetic interference suppression performance.

[0082] In one example, the audio acquisition chip UA can not only record ordinary ambient sounds, but also has functions such as stereo, active noise reduction, directionality (beaming), and voice recognition.

[0083] In one example, the audio capture chip UA includes a digital-to-analog converter (DAC) that can convert the digital audio signal generated by the MEMS into an analog audio signal for output. Furthermore, the DAC can provide audio amplification functionality; for example, the DAC can generate a DC voltage gain via microcontroller commands. In one example, the DAC can be integrated into the audio decoder of the audio capture chip UA, which can also perform signal processing.

[0084] In one embodiment of the present disclosure, referring to Figure 4 , the audio acquisition chip UA has a positive output pin OUT+ and a negative output pin OUT-. The audio acquisition chip UA can use differential signaling to transmit analog audio signals, thereby improving the stability and reliability of analog audio signal transmission.

[0085] In one example, the audio detection unit MA further includes a first filtering subcircuit configured to filter out differential-mode interference between the positive output pin OUT+ and the negative output pin OUT-. For example, referring to FIG4 , the first filtering subcircuit includes a first filter capacitor CX1, one end of the first filter capacitor CX1 being electrically connected to the positive output pin OUT+ and the other end being electrically connected to the negative output pin OUT-.

[0086] In an example, the withstand voltage of the first filter capacitor CX1 is between 40V and 60V. For example, the withstand voltage of the first filter capacitor CX1 is 50V.

[0087] In an example, the capacitance of the first filter capacitor CX1 is between 20 pF and 40 pF. For example, the capacitance of the first filter capacitor CX1 is 33 pF.

[0088] In one example, the audio detection unit MA further includes a second filtering subcircuit; the second filtering subcircuit is configured to filter out common-mode interference from the positive output pin OUT+ and the negative output pin OUT-. For example, the second filtering subcircuit includes a second filter capacitor CX2 and a third filter capacitor CX3; wherein a first end of the second filter capacitor CX2 is electrically connected to the positive output pin OUT+, and a second end of the second filter capacitor CX2 is configured to apply a ground voltage GND. A first end of the third filter capacitor CX3 is electrically connected to the negative output pin OUT-, and a second end of the third filter capacitor CX3 is configured to apply a ground voltage GND.

[0089] In an example, the withstand voltage of the second filter capacitor CX2 is between 40V and 60V, for example, the withstand voltage of the second filter capacitor CX2 is 50V.

[0090] In an example, the capacitance of the second filter capacitor CX2 is between 80 pF and 120 pF. For example, the capacitance of the second filter capacitor CX2 is 100 pF.

[0091] In an example, the withstand voltage of the third filter capacitor CX3 is between 40V and 60V. For example, the withstand voltage of the third filter capacitor CX3 is 50V.

[0092] In an example, the capacitance of the third filter capacitor CX3 is between 80 pF and 120 pF. For example, the capacitance of the third filter capacitor CX3 is 100 pF.

[0093] In one example, the audio acquisition chip UA has a chip power terminal and a ground terminal, wherein the chip power terminal is used to apply a chip power voltage, and the ground terminal is used to apply a ground voltage GND.

[0094] In one example, the audio detection unit MA further includes a protection subcircuit for filtering and current limiting the chip power supply terminal to ensure reliable input of the chip power supply voltage in an abnormal state. For example, referring to FIG4 , the protection subcircuit includes a fourth filter capacitor CX4 and a first protection resistor RX1; a first end of the fourth filter capacitor CX4 is electrically connected to the chip power supply terminal, and a second end of the fourth filter capacitor CX4 is used to apply a ground voltage GND; a first end of the first protection resistor RX1 is electrically connected to the chip power supply terminal, and a second end of the first protection resistor RX1 is used to apply the chip power supply voltage.

[0095] In an example, the withstand voltage of the fourth filter capacitor CX4 is between 10V and 20V. For example, the withstand voltage of the third filter capacitor CX3 is 16V.

[0096] In an example, the capacitance of the fourth filter capacitor CX4 is between 0.08 μF and 0.12 μF. For example, the capacitance of the third filter capacitor CX3 is 0.1 μF.

[0097] In an example, the resistance of the first protection resistor RX1 is between 20Ω and 30Ω. For example, the resistance of the first protection resistor RX1 is 22Ω.

[0098] In one example, the chip power supply voltage is between 2V and 5V, for example, the chip power supply voltage is 3.3V.

[0099] In one example, referring to FIG6 , the first filter capacitor CX1, the fourth filter capacitor CX4, and the first protection resistor RX1 are placed close to the audio acquisition chip UA. This makes the distance between the first filter capacitor CX1 and the audio acquisition chip UA smaller than the distance between the second filter capacitor CX2, the third filter capacitor CX3, and the audio acquisition chip UA. This can further enhance the anti-interference capability of the audio detection unit MA.

[0100] In an embodiment of the present disclosure, referring to FIG5 , the analog-to-digital conversion unit ADU includes an analog-to-digital conversion chip UB, which is electrically connected to the audio detection unit MA to receive analog audio signals from the audio detection unit MA. Referring to FIG5 , the analog-to-digital conversion chip UB has an input port corresponding one-to-one with at least one of the audio detection units MA, and the input port is electrically connected to an output port of the audio detection unit MA.

[0101] In one embodiment of the present disclosure, referring to FIG5 , the analog-to-digital conversion unit ADU further includes a third filtering subcircuit, through which the audio detection unit MA is electrically connected to the corresponding input port. Furthermore, the third filtering subcircuit is a capacitor disposed between the output port of the audio detection unit MA and the input port of the analog-to-digital conversion chip UB.

[0102] In the example of FIG4 , the output ports of the audio detection unit MA are a positive output pin OUT+ and a negative output pin OUT-, which together output a differential signal. Accordingly, in the analog-to-digital conversion chip UB, the input ports include a positive input pin (e.g., the first positive input pin AINLP and the second positive input pin AINRP in FIG5 ) and a negative input pin (e.g., the first negative input pin AINLN and the second negative input pin AINRN in FIG5 ). The positive input pin is electrically coupled to the positive output pin OUT+ via a capacitor, and the negative input pin is electrically coupled to the negative output pin OUT- via a capacitor.

[0103] In the examples of Figures 2 and 5 , each audio acquisition module YM includes two audio detection units MA, both of which are electrically connected to the analog-to-digital conversion unit ADU. Therefore, in the example of Figure 5 , the analog-to-digital conversion chip UB is provided with two input ports corresponding to the two audio detection units MA, respectively. The input port corresponding to the second audio detection unit MAR includes a second positive input pin AINRP and a second negative input pin AINRN. The third filtering subcircuit corresponding to the second audio detection unit MAR includes a first capacitor CY1 and a second capacitor CY2. The first capacitor CY1 has one end electrically connected to the positive output pin OUT+ of the second audio detection unit MAR and the other end electrically connected to the second positive input pin AINRP of the analog-to-digital conversion chip UB. The second capacitor CY2 has one end electrically connected to the negative output pin OUT- of the second audio detection unit MAR and the other end electrically connected to the second negative input pin AINRN of the analog-to-digital conversion chip UB. The input port corresponding to the first audio detection unit MAL includes a first positive input pin AINLP and a first negative input pin AINLN. The third filtering subcircuit corresponding to the first audio detection unit MAL includes a third capacitor CY3 and a fourth capacitor CY4. Among them, one end of the third capacitor CY3 is electrically connected to the positive output pin OUT+ of the first audio detection unit MAL, and the other end is electrically connected to the first positive input pin AINLP of the analog-to-digital conversion chip UB; one end of the fourth capacitor CY4 is electrically connected to the negative output pin OUT- of the first audio detection unit MAL, and the other end is electrically connected to the first negative input pin AINLN of the analog-to-digital conversion chip UB.

[0104] In an example, the withstand voltage of the first capacitor CY1 is between 8V and 12V, for example, the withstand voltage of the first capacitor CY1 is 10V.

[0105] In an example, the capacitance of the first capacitor CY1 is between 4.0 μF and 6.0 μF. For example, the capacitance of the first capacitor CY1 is 4.7 μF.

[0106] In an example, the specifications of the first capacitor CY1 , the second capacitor CY2 , the third capacitor CY3 , and the fourth capacitor CY4 may be the same.

[0107] In one embodiment of the present disclosure, referring to FIG. 5 , the analog-to-digital conversion unit ADU has a first power pin VDDA, and the first power pin VDDA is used to load a power voltage VCC to power the analog-to-digital conversion chip UB.

[0108] In an example, the power supply voltage VCC is between 2.5V and 4V, for example, 3.3V.

[0109] In an example, the analog-to-digital conversion unit ADU has a power supply filter sub-circuit, and the power supply filter sub-circuit is electrically connected to the first power supply pin VDDA.

[0110] For example, referring to FIG5 , the power supply filter subcircuit includes a fifth capacitor CY5 and a sixth capacitor CY6 . A first end of the fifth capacitor CY5 and a first end of the sixth capacitor CY6 are both electrically connected to the first power pin VDDA, and a second end of the fifth capacitor CY5 and a second end of the sixth capacitor CY6 are both used to apply a ground voltage GND.

[0111] In an example, the withstand voltage of the fifth capacitor CY5 is between 8V and 12V. For example, the withstand voltage of the fifth capacitor CY5 is 10V.

[0112] In an example, the capacitance of the fifth capacitor CY5 is between 4.0 μF and 6.0 μF. For example, the capacitance of the fifth capacitor CY5 is 4.7 μF.

[0113] In an example, the specifications of the fifth capacitor CY5 and the sixth capacitor CY6 may be the same.

[0114] In one embodiment of the present disclosure, referring to FIG. 5 , the analog-to-digital conversion chip UB has a second reference pin REFQ and a first reference pin REFP; the analog-to-digital conversion unit ADU further includes a signal level reference subcircuit, which is used to load a ground voltage GND to the second reference pin REFQ and the first reference pin REFP.

[0115] For example, in the example of FIG. 5 , the signal level reference subcircuit includes a seventh capacitor CY7 and an eighth capacitor CY8 . A first end of the seventh capacitor CY7 is electrically connected to the second reference pin REFQ, and a first end of the eighth capacitor CY8 is electrically connected to the first reference pin REFP. The second ends of the seventh capacitor CY7 and the eighth capacitor CY8 are both used to apply the ground voltage GND.

[0116] In one embodiment of the present disclosure, referring to FIG5 , the analog-to-digital conversion chip UB has a second power pin VDDD and a third power pin VDDP, and the analog-to-digital conversion unit ADU further includes a ninth capacitor CY9 and a tenth capacitor CY10. The second power pin VDDD is electrically connected to the first end of the ninth capacitor CY9 and is used to apply the power supply voltage VCC; the third power pin VDDP is electrically connected to the first end of the tenth capacitor CY10 and is used to apply the power supply voltage VCC. The second ends of the ninth capacitor CY9 and the second ends of the tenth capacitor CY10 are both used to apply the ground voltage GND. In this way, the second power pin VDDD and the third power pin VDDP can apply the power supply voltage VCC to serve as or generate a positive bias voltage for the differential signal. The ninth capacitor CY9 and the tenth capacitor CY10 can be used to filter the second power pin VDDD and the third power pin VDDP, respectively.

[0117] In an example, the withstand voltage of the ninth capacitor CY9 is between 12V and 20V. For example, the withstand voltage of the ninth capacitor CY9 is 16V.

[0118] In an example, the capacitance of the ninth capacitor CY9 is between 0.08 μF and 0.12 μF. For example, the capacitance of the ninth capacitor CY9 is 0.1 μF.

[0119] In an example, the ninth capacitor CY9 and the tenth capacitor CY10 may have the same specifications.

[0120] Optionally, the analog-to-digital conversion chip UB has a power pin, and the ground pin is used to load a ground voltage GND.

[0121] In an example, the analog-to-digital conversion chip UB further has a first ground pin GNDDD, and the first ground pin GNDDD is used to load a ground voltage GND to provide a reference voltage for the negative electrode of the differential signal.

[0122] In an example, the analog-to-digital conversion chip UB further has a second ground pin GNDA and a third ground pin PAD, and both the second ground pin GNDA and the third ground pin PAD are used to load a ground voltage GND.

[0123] For example, in the example of FIG. 5 , the ground pins include a first ground pin GNDDD, a second ground pin GNDA, and a third ground pin PAD.

[0124] In one embodiment of the present disclosure, referring to FIG5 , the analog-to-digital conversion chip UB has an address configuration port, and the analog-to-digital conversion unit ADU has an address configuration circuit electrically connected to the address configuration port to configure the address of the analog-to-digital conversion chip UB. The address configuration port includes one or more address configuration pins, and the address configuration circuit includes address configuration resistors corresponding to each address configuration pin. The address configuration pins are supplied with a power supply voltage VCC or a ground voltage GND via the address configuration resistors.

[0125] For example, in the example of FIG5 , the address configuration port of the analog-to-digital conversion chip UB includes two address configuration pins: a first address pin AD0 and a second address pin AD1. The address configuration circuit includes two address configuration resistors: a second address configuration resistor RY1 and a first address configuration resistor RY0. The first end of the first address configuration resistor RY0 is electrically connected to the first address pin AD0, and the second end of the first address configuration resistor RY0 is loaded with the ground voltage GND. The first end of the second address configuration resistor RY1 is electrically connected to the second address pin AD1, and the second end of the second address configuration resistor RY1 is loaded with the power supply voltage VCC. It will be understood that when the address of the analog-to-digital conversion chip UB changes, the voltages loaded on the second end of the second address configuration resistor RY1 and the second end of the first address configuration resistor RY0 can be adaptively adjusted.

[0126] In an example, the resistance of the second address configuration resistor RY1 is between 5 kΩ and 15 kΩ, for example, 10 kΩ.

[0127] In one example, the specification of the second address configuration resistor RY1 is the same as the specification of the first address configuration resistor RY0 .

[0128] In one embodiment of the present disclosure, the data bus BUS includes an IIC (Inter-integerted Circuit) signal bus; the analog-to-digital conversion chip UB has an IIC signal terminal; the IIC signal terminal and the IIC signal bus are interconnectable.

[0129] For example, in the example of FIG5 , the IIC signal terminal includes a first data pin CDATA and a first clock pin CCLK; the IIC signal bus includes a first signal line and a second signal line. The first data pin CDATA is electrically connected to the first signal line via a third connection resistor RY3 , and the first clock pin CCLK is electrically connected to the second signal line via a fourth capacitor CY4 .

[0130] In one example, the analog-to-digital conversion chip UB is configured to be initialized under the control of a signal on an IIC signal terminal. For example, when the analog-to-digital conversion chip UB is powered on, the IIC signal terminal may receive configuration data from the IIC signal bus and configure at least one of an address, an operating mode, etc. of the analog-to-digital conversion chip UB based on the configuration data.

[0131] In one example, the resistance of the third connection resistor RY3 is very small, substantially zero; for example, the third connection resistor RY3 is a zero-resistance connection resistor, which serves as an electrical connection.

[0132] In one example, the specifications of the third connection resistor RY3 and the fourth connection resistor RY4 are the same.

[0133] Of course, in other embodiments of the present disclosure, the third connection resistor RY3 and the fourth connection resistor RY4 may not be provided.

[0134] In one embodiment of the present disclosure, the data bus BUS comprises an IIS (Inter IC Sound) signal bus; the analog-to-digital conversion chip UB comprises an IIS signal terminal; and the IIS signal terminal is interconnected with the IIS signal bus. Thus, the analog-to-digital conversion chip UB can communicate with the control module CTR and other analog-to-digital conversion units ADU using the IIS protocol.

[0135] For example, in the example of FIG5 , the IIS signal terminal includes pins such as the second data pin SDOUT, the bit clock pin SCLK, the frame clock pin LRCK, and the master clock pin MCLK. The IIS signal bus includes a third signal line, a fourth signal line, and a fifth signal line. The second data pin SDOUT is electrically connected to the fifth signal line via an eighth connecting resistor RY8 , the bit clock pin SCLK is electrically connected to the fourth signal line via a seventh connecting resistor RY7 , the frame clock pin LRCK is electrically connected to the third signal line via a sixth connecting resistor RY6 , and the master clock pin MCLK is electrically connected to the third signal line via a fifth connecting resistor RY5 .

[0136] In one example, the resistance of the fifth connection resistor RY5 to the eighth connection resistor RY8 is very small, substantially zero; for example, the fifth connection resistor RY5 to the eighth connection resistor RY8 are zero-resistance connection resistors, which serve as electrical connections.

[0137] In one embodiment of the present disclosure, the data bus BUS includes a TDM (Time-Division Multiplexing) signal bus; the analog-to-digital conversion chip UB has a TDM signal terminal; the TDM signal terminal and the TDM signal bus are interconnectable.

[0138] For example, in the example of FIG5 , the TDM signal terminal includes a third data pin TDMIN, and the third data pin TDMIN is electrically connected to the TDM signal bus.

[0139] In one embodiment of the present disclosure, referring to FIG5 , the analog-to-digital conversion chip UB can be configured with an IIC signal terminal, a TDM signal terminal, and an IIS signal terminal. Accordingly, the data bus BUS can be configured with an IIC signal bus, a TDM signal bus, and an IIS signal bus.

[0140] The IIC signal terminal and the IIC signal bus can be interconnected; the TDM signal terminal and the TDM signal bus can be interconnected; the IIS signal terminal and the IIS signal bus can be interconnected.

[0141] The analog-to-digital conversion unit ADU is configured to be configured as one of a first operating mode and a second operating mode under the control of the IIC signal terminal;

[0142] In the first working mode, the analog-to-digital conversion chip UB sends the digital audio signal to the data bus BUS through the TDM signal terminal;

[0143] In the second working mode, the analog-to-digital conversion chip UB sends the digital audio signal to the data bus BUS through the IIS signal terminal.

[0144] In this embodiment, multiple analog-to-digital conversion chips UB can be used in a clustered manner. The data output format of a single analog-to-digital conversion chip UB can be selected in either IIS or TDM mode. When IIS signaling is selected, each analog-to-digital conversion chip UB shares a common clock reference signal and independently outputs an IIS data signal. This allows for differentiated data processing based on the real-time data signals of different analog-to-digital conversion chips UB. When TDM signaling is selected, data output is achieved through chip series connection (the preceding chip serves as the data input for the subsequent chip, and the final chip completes the overall data output). This has the advantage of reducing signal lines.

[0145] In one example, the analog-to-digital conversion chip UB has a 102dB signal-to-noise ratio, -85dB THD+N (total harmonic distortion plus noise), 24-bit, 8-200kHz sampling frequency, I2S / PCM master or slave serial data port, support for TDM, 256 / 384Fs, USB 12 / 24MHz and other non-standard audio system clocks, and a low-power standby mode.

[0146] In one embodiment of the present disclosure, the analog-to-digital conversion chip UB can simultaneously be configured with an IIC signal terminal, a TDM signal terminal, and an IIS signal terminal. The third data pin TDMIN can be loaded with a ground voltage GND via a ninth connection resistor RY9. In this embodiment, the analog-to-digital conversion unit ADU is configured to operate in a second operating mode under the control of the IIC signal terminal. In this mode, the third data pin TDMIN is shielded, thereby reducing interference with the IIS signal.

[0147] In one embodiment of the present disclosure, the analog-to-digital conversion chip UB can be configured with an IIC signal terminal, a TDM signal terminal, and an IIS signal terminal at the same time. The third data pin TDMIN is electrically connected to the TDM signal bus, and the third data pin TDMIN is not loaded with the ground voltage GND; in other words, the analog-to-digital conversion unit ADU is not configured with the ninth connection resistor RY9. The analog-to-digital conversion unit ADU is also not configured with the fifth connection resistor RY5 to the eighth connection resistor RY8, which causes a disconnection between the IIS signal terminal and the IIS signal trace. In this embodiment, the analog-to-digital conversion unit ADU is configured to be configured in a first operating mode under the control of the IIC signal terminal. In this mode, the IIS signal terminal is shielded, which can reduce interference with the TDM signal.

[0148] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A sound pickup circuit, comprising at least one audio acquisition module; the audio acquisition module includes an analog-to-digital conversion unit and at least one audio detection unit; The audio detection unit is electrically connected to the analog-to-digital conversion unit, and is configured to generate an analog audio signal and transmit it to the analog-to-digital conversion unit; The analog-to-digital conversion unit is configured to generate a digital audio signal according to the analog audio signal provided by the audio detection unit.

2. The sound pickup circuit according to claim 1, wherein The audio acquisition module includes two such audio detection units, and the two audio detection units are respectively located on both sides of the analog-to-digital conversion unit.

3. The sound pickup circuit according to claim 1, wherein, The number of the audio acquisition modules is multiple and the sound pickup circuit further includes a data bus; The analog-to-digital conversion units of each of the audio acquisition modules are interactively connected to the data bus; The analog-to-digital conversion unit is configured to output the digital audio signal to the data bus.

4. The sound pickup circuit according to claim 3, wherein, The sound pickup circuit further includes a circuit board, and multiple audio acquisition modules are arranged in sequence along a first direction on the circuit board; An infrared receiver is provided on the circuit board, and the infrared receiver is electrically connected to the data bus.

5. The sound pickup circuit according to claim 4, wherein, The size of the circuit board in the first direction is 20 to 30 times the size of the circuit board in a second direction; the second direction is parallel to the plane of the circuit board and perpendicular to the first direction.

6. The sound pickup circuit according to claim 1, wherein, The audio detection unit includes an audio acquisition chip.

7. The sound pickup circuit according to claim 6, wherein, The audio acquisition chip has a positive output pin and a negative output pin; The audio detection unit further includes a first filtering sub-circuit and a second filtering sub-circuit; The first filtering sub-circuit is used to filter out differential mode interference between the positive output pin and the negative output pin; The second filtering sub-circuit is used to filter out common mode interference of the positive output pin and the negative output pin.

8. The sound pickup circuit according to any one of claims 1 to 7, wherein, The analog-to-digital conversion unit includes an analog-to-digital conversion chip and a third filtering sub-circuit, and the analog-to-digital conversion chip has input ports corresponding to at least one of the audio detection units one by one; the audio detection unit is electrically connected to the corresponding input port through the third filtering sub-circuit.

9. The sound pickup circuit according to any one of claims 1 to 7, wherein The sound pickup circuit further includes a data bus, and the data bus includes an IIC signal bus; The analog-to-digital conversion unit includes an analog-to-digital conversion chip, and the analog-to-digital conversion chip has an IIC signal terminal; the IIC signal terminal is interactively connected to the IIC signal bus.

10. The sound pickup circuit according to any one of claims 1 to 7, wherein, The sound pickup circuit further includes a data bus, and the data bus includes a TDM signal bus; The analog-to-digital conversion unit includes an analog-to-digital conversion chip, and the analog-to-digital conversion chip has a TDM signal terminal; the TDM signal terminal is interactively connected to the TDM signal bus.

11. The sound pickup circuit according to any one of claims 1 to 7, wherein, The sound pickup circuit further includes a data bus, and the data bus includes an IIS signal bus; The analog-to-digital conversion unit includes an analog-to-digital conversion chip, and the analog-to-digital conversion chip has an IIS signal terminal; the IIS signal terminal is interactively connected to the IIS signal bus.

12. The sound pickup circuit according to any one of claims 1 to 7, wherein, The sound pickup circuit further includes a data bus, and the data bus includes an IIC signal bus, a TDM signal bus and an IIS signal bus; The analog-to-digital conversion unit includes an analog-to-digital conversion chip, and the analog-to-digital conversion chip has an IIC signal terminal, a TDM signal terminal, and an IIS signal terminal; the IIC signal terminal can be interactively connected to the IIC signal bus; the TDM signal terminal can be interactively connected to the TDM signal bus; the IIS signal terminal can be interactively connected to the IIS signal bus; The analog-to-digital conversion unit is configured to be able to be configured as one of a first working mode and a second working mode under the control of the IIC signal terminal; In the first working mode, the analog-to-digital conversion chip sends the digital audio signal to the TDM signal bus through the TDM signal terminal; In the second working mode, the analog-to-digital conversion chip sends the digital audio signal to the IIS signal bus through the IIS signal terminal.

13. The sound pickup circuit according to claim 12, wherein, The analog-to-digital conversion unit includes a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, and an address configuration circuit; The analog-to-digital conversion chip also has a first power supply pin, a second power supply pin, a third power supply pin, a first reference pin, a second reference pin, a ground pin, and an address configuration port; Wherein, the first ends of the fifth capacitor and the sixth capacitor are both electrically connected to the first power supply pin, and the second ends of the fifth capacitor and the sixth capacitor are both used to load the ground wire voltage; The first end of the seventh capacitor is electrically connected to the second reference pin, and the first end of the eighth capacitor is electrically connected to the first reference pin; the second ends of the seventh capacitor and the eighth capacitor are both used to load the ground wire voltage; The second power supply pin is electrically connected to the first end of the ninth capacitor and is used to load the power supply voltage; the third power supply pin is electrically connected to the first end of the tenth capacitor and is used to load the power supply voltage; the second ends of the ninth capacitor and the tenth capacitor are both used to load the ground wire voltage; The ground pin is used to load the ground wire voltage; The address configuration circuit is electrically connected to the address configuration port to configure the address of the analog-to-digital conversion chip.

14. The sound pickup circuit according to any one of claims 1 to 7, wherein, The sound pickup circuit is further provided with a data bus and a main board interface; each of the analog-to-digital conversion units is interactively connected to the data bus, and the main board interface is connected to the data bus; The distance between the audio detection unit and the analog-to-digital conversion unit is less than the distance between the main board interface and the analog-to-digital conversion unit.

15. An electronic device, wherein, The electronic device is provided with the sound pickup circuit according to any one of claims 1 to 14.

Images