Auxiliary driving circuit and method, chip, display device

Abstract

The application discloses an auxiliary driving circuit and method, a chip and a display device. The auxiliary driving circuit is used for assisting a driving transistor to provide a driving current to a load. The auxiliary driving circuit comprises: a biasing unit, which is used for providing a biasing current, the biasing current being changed synchronously with a threshold voltage of the driving transistor; a mirror unit, which is used for copying the biasing current to provide a pull-up current or a pull-down current; and a control terminal charging and discharging unit, which is used for charging a control terminal of the driving transistor according to the pull-up current and discharging the control terminal of the driving transistor according to the pull-down current. By providing the pull-up current or the pull-down current which is changed synchronously with the threshold voltage of the driving transistor, the speed and the required time for different driving transistors to provide stable driving currents are consistent, and the uniformity of display is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to an auxiliary driving circuit and method, a chip, and a display device. Background Technology

[0002] LED display devices use LED chips as the light-emitting element. LED display devices offer advantages such as high brightness, wide viewing angles, rich colors, and customizable screen shapes. Therefore, LED display devices are widely used in various fields including industry, transportation, commercial advertising, information dissemination, and sporting events.

[0003] An LED display device includes a display panel and a chip. The display panel has multiple LED beads, each driven by a driving transistor in its corresponding chip. Specifically, the driving transistor is typically activated by controlling the control terminal voltage of the driving transistor through a feedback loop, thereby enabling the driving transistor to provide a stable driving current.

[0004] However, manufacturing process variations can lead to mismatches between driver transistors, causing differences in the control terminal voltages of different driver transistors when providing constant current output. Consequently, the adjustment time required to regulate the control terminal voltage of the driver transistors via the feedback loop will vary, resulting in different times when different driver transistors reach a stable drive current. Especially in low-gray conditions, where the LED's light-emitting cycle is short, some driver transistors can quickly establish and stabilize the drive current, allowing the LED to emit light at the set brightness for most of the light-emitting cycle. Conversely, some driver transistors require a longer time to stabilize, resulting in the LED emitting light at the set brightness for only a small portion of the light-emitting cycle, or even failing to reach the set brightness at all. This leads to brightness discrepancies between different LEDs, significantly impacting the user experience. Summary of the Invention

[0005] In view of the above problems, the purpose of this application is to provide an auxiliary driving circuit and method, chip, and display device that can assist driving transistors in providing driving current to the load, so that the speed and time required for different driving transistors to provide stable driving current tend to be consistent.

[0006] According to one aspect of this application, an auxiliary driving circuit is provided, wherein the auxiliary driving circuit is used to assist a driving transistor in providing a driving current to a load, the auxiliary driving circuit comprising: a biasing unit for providing a bias current, the bias current changing synchronously with the threshold voltage of the driving transistor; a mirroring unit for replicating the bias current to provide a pull-up current or a pull-down current; and a control terminal charging and discharging unit for charging the control terminal of the driving transistor according to the pull-up current, and for discharging the control terminal of the driving transistor according to the pull-down current.

[0007] Optionally, the bias unit includes: a resistor string comprising a plurality of resistors, the output node of the resistor string including a common node of at least some adjacent resistors; a multiplexer, each input terminal connected to a corresponding output node; a first transistor, the control terminal connected to the output terminal of the multiplexer, the first terminal connected to a first power supply terminal, and the second terminal connected to a first signal; and a second transistor, the control terminal connected to the second terminal of the first transistor, the first terminal connected to the control terminal of the first transistor, and the second terminal providing the bias current, wherein the multiplexer connects the control terminal of the first transistor and the corresponding output node according to a target selection signal, such that the actual resistance of the resistor string between the first power supply terminal and the control terminal of the first transistor is a set value.

[0008] Optionally, the bias unit further includes: a third transistor, with a first end connected to the first power supply terminal and a second end connected to the control terminal of the first transistor, the control terminal being connected to an enable signal; wherein, during the active level of the enable signal, the first end of the resistor string is connected to the first power supply terminal, the second end is floating, the third transistor is turned off, and the bias unit provides the bias current; during the inactive level of the enable signal, the first end of the resistor string is connected to the first power supply terminal, the second end is grounded, the third transistor is turned on, and the current of the resistor string represents the difference between the actual resistance value and the set value under the initial selection signal.

[0009] Optionally, the auxiliary drive circuit further includes a processing unit for adjusting the initial selection signal according to the difference to obtain the target selection signal.

[0010] Optionally, the bias unit further includes a logic gate, whose input receives the target selection signal and the enable signal, and whose output is connected to the multiplexer.

[0011] Optionally, the mirror unit includes: a first mirror branch connected to the bias current; a second mirror branch connected to the first mirror branch for providing a mirror current of the bias current; a third mirror branch connected to the second mirror branch for replicating the mirror current to provide the pull-up current; and a fourth mirror branch connected to the first mirror branch for replicating the bias current to provide the pull-down current.

[0012] Optionally, the first mirror branch includes: a fourth transistor, with a first end connected to a control terminal and receiving the bias current, and a second end connected to a second power supply terminal; the second mirror branch includes: a fifth transistor, with a control terminal connected to the control terminal of the fourth transistor, and a second end connected to the second power supply terminal; and a sixth transistor, with a first end connected to the first power supply terminal, and a second end connected to the first end of the fifth transistor.

[0013] Optionally, the third mirror branch includes at least one seventh transistor, the control terminal of each seventh transistor is connected to the control terminal of the sixth transistor, the first terminal is connected to the first power supply terminal, and the second terminal provides the pull-up current; the fourth mirror branch includes at least one eighth transistor, the control terminal of each eighth transistor is connected to the control terminal of the fourth transistor, the second terminal is connected to the second power supply terminal, and the first terminal provides the pull-down current.

[0014] Optionally, the control terminal charging and discharging unit includes: a ninth transistor, with a first terminal connected to the pull-up current and a second terminal connected to the control terminal of the driving transistor, the control terminal being connected to a pulse width modulation signal, the ninth transistor being turned on according to a first level of the pulse width modulation signal, thereby charging the control terminal of the driving transistor according to the pull-up current; and a tenth transistor, with a first terminal connected to the control terminal of the driving transistor, a second terminal connected to the pull-down current, the control terminal being connected to a pull-down signal, the tenth transistor being turned on according to a valid pull-down signal, thereby discharging the control terminal of the driving transistor according to the pull-down current.

[0015] Optionally, the control terminal charging and discharging unit further includes: at least one eleventh transistor, with its control terminal connected to a first switch signal and its second terminal connected to the control terminal of the driving transistor, the first terminal of the ninth transistor and the first terminal of each of the eleventh transistors connected to the second terminal of their respective seventh transistors; and at least one twelfth transistor, with its control terminal connected to a second switch signal, its first terminal connected to the second terminal of the tenth transistor, the second terminal of the tenth transistor and the second terminal of each of the twelfth transistors connected to the first terminal of their respective eighth transistors, wherein the eleventh transistor is used to turn on when the first switch signal is valid, and the twelfth transistor is used to turn on when the second switch signal is valid.

[0016] Optionally, the first switch signal and the second switch signal include multiple binary numbers, and each of the eleventh transistors is turned on when the corresponding bit in the first switch signal is a valid code value, and each of the twelfth transistors is turned on when the corresponding bit in the second switch signal is a valid code value.

[0017] Optionally, the auxiliary driving circuit further includes: a pull-down signal generation unit for providing the pull-down signal, wherein the pull-down signal generation unit provides the effective pull-down signal when the pulse width modulation signal is at the second level and the control terminal voltage of the driving transistor is greater than the reference voltage.

[0018] Optionally, the pull-down signal generation unit includes: a comparator, with its non-inverting input connected to the control terminal of the driving transistor and its inverting input receiving the reference voltage; and a first AND gate, with its input connected to the pulse width modulation signal and the output of the comparator, and its output providing the pull-down signal.

[0019] According to a second aspect of this application, a chip is provided, comprising: a driving transistor for providing a driving current to a load; and an auxiliary driving circuit as described in any of the preceding claims, the auxiliary driving circuit being connected to a control terminal of the driving transistor.

[0020] According to a third aspect of this application, a display device is provided, comprising: a display panel including a plurality of light-emitting elements; and a chip as described above for providing driving current to the light-emitting elements.

[0021] According to a fourth aspect of this application, an auxiliary driving method is provided, wherein the auxiliary driving method is used to assist a driving transistor in providing a driving current to a load, the auxiliary driving method comprising: providing a bias current, the bias current changing synchronously with a threshold voltage of the driving transistor; replicating the bias current to provide a pull-up current or a pull-down current; and charging a control terminal of the driving transistor according to the pull-up current, or discharging a control terminal of the driving transistor according to the pull-down current.

[0022] According to the auxiliary driving circuit, method, chip, and display device provided in this application, the driving transistor is assisted in rapid conduction by providing pull-up and pull-down currents to the control terminal of the driving transistor. Furthermore, the magnitudes of the pull-up and pull-down currents are synchronously varied with the threshold voltage of the driving transistor, that is, adapted to the control terminal voltage of the driving transistor when a stable driving current is provided. This allows different driving transistors to provide stable driving current at similar speeds and in similar times, thus eliminating brightness deviations in the light-emitting element caused by driving transistor mismatch. In particular, it can significantly improve display consistency under low grayscale conditions, thereby enhancing the user experience. Attached Figure Description

[0023] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0024] Figure 1 This paper shows a schematic structural diagram of the display device according to an embodiment of the present application;

[0025] Figure 2 Show Figure 1 A schematic circuit diagram of the driving circuit.

[0026] Figure 3 A schematic circuit diagram of the auxiliary drive circuit according to an embodiment of this application is shown;

[0027] Figure 4 A schematic circuit diagram of the bias unit is shown;

[0028] Figure 5 A schematic circuit diagram of the pull-down signal generation unit is shown;

[0029] Figure 6 A schematic flowchart of the auxiliary driving method according to an embodiment of this application is shown. Detailed Implementation

[0030] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0031] Furthermore, certain terms are used in this specification and claims to refer to specific components. Those skilled in the art will understand that manufacturers may use different names to refer to the same component. This specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0032] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0033] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0034] It should also be noted that in the various methods and processes of this application, the order of the steps does not imply the order of execution, nor does it constitute any limitation on the implementation process of the embodiments of this application.

[0035] Figure 1 A schematic structural diagram of a display device according to an embodiment of this application is shown. (See reference...) Figure 1 The display device includes a display panel and a circuit board 1. The display panel includes multiple light-emitting modules D1~Dn, and... Figure 1 In this example, the light-emitting modules D1~Dn are exemplified by LED beads. Circuit board 1 includes a driving circuit 100 adapted to each light-emitting module for providing driving current to each module. As an example, in... Figure 1 Only the drive circuit 100 that provides the drive current Iout to the light-emitting module D1 is shown.

[0036] Furthermore, Figure 2 Show Figure 1 A schematic circuit diagram of the drive circuit 100. (Reference) Figure 2 The driving circuit 100 includes a driving transistor T1, a first operational amplifier OP1, a second operational amplifier OP2, a bias current generating circuit 120, and a current mirror 130.

[0037] The current mirror 130 includes a reference transistor P1 and at least one mirror transistor. Figure 2The example includes mirror transistors P2, P3, and P4, with P1 through P4 being PMOS transistors. The first terminal of the reference transistor P1 and each mirror transistor is connected to the first power supply terminal AVDD. The control terminal of the reference transistor P1 is connected to the control terminal of each mirror transistor. The second terminal of the reference transistor P1 is connected to the bias current generation circuit 120 to receive a reference current. The second terminals of each mirror transistor are connected to and connected to the first terminal of the drive transistor T1. The current mirror 130 can replicate the reference current generated by the bias current generation circuit 120 to the branch containing the drive transistor T1.

[0038] Furthermore, in some embodiments, the non-inverting input of the second operational amplifier OP2 is connected to the second terminal of the reference transistor P1, the inverting input receives the clamping signal V1, and the output is connected to the control terminal of the reference transistor P1. By clamping the voltage at the second terminal of the reference transistor P1, the accurate replication of the reference current is achieved.

[0039] The driving transistor T1 provides a driving current Iout to the load. The load is, for example, the display module D1 described above, and again, using LED beads as an example of the display module D1. Specifically, the first terminal of the driving transistor T1 is connected to the current mirror 130, the second terminal is connected to the anode of the LED bead, and the cathode of the LED bead is connected to the second power supply terminal AVSS. Figure 2 In this example, the driving transistor T1 is also a PMOS transistor.

[0040] The non-inverting input of the first operational amplifier OP1 is connected to the first terminal of the driving transistor T1, the inverting input receives the reference voltage Vref, and the output is connected to the control terminal of the driving transistor T1. The first operational amplifier OP1 adjusts the voltage at the control terminal of the driving transistor T1, i.e., the voltage at point A, based on the comparison between the voltage at the non-inverting input and the reference voltage Vref. When the voltage at the non-inverting input approaches the reference voltage Vref, the output of the first operational amplifier OP1 tends to stabilize, causing the driving transistor T1 to conduct stably. At this time, the driving current Iout is in a stable phase.

[0041] However, circuit board 1 typically includes multiple driving circuits 100. Since different driving circuits 100 are manufactured as independent chips, process variations during manufacturing can lead to different threshold voltages for the driving transistors T1 in different driving circuits 100, resulting in different voltages at point A when the different driving transistors T1 reach a stable state. Consequently, the time required for different driving transistors T1 to provide a stable driving current Iout will also differ, leading to brightness variations between different light-emitting elements.

[0042] To solve this problem, such as Figure 2As shown, the driving circuit 100 in this embodiment of the application also includes an auxiliary driving circuit 110 connected to the control terminal of the driving transistor T1, which is used to assist the driving transistor T1 in providing driving current Iout to the load.

[0043] Figure 3 A schematic circuit diagram of the auxiliary drive circuit according to an embodiment of this application is shown. (See reference...) Figure 3 The auxiliary drive circuit 110 includes a bias unit 111, a mirror unit, a control terminal charging and discharging unit 113, and a pull-down signal generation unit 114.

[0044] The bias unit 111 provides a bias current Ivgs, which changes synchronously with the threshold voltage of the driving transistor T1. The mirror unit replicates the bias current Ivgs to provide a pull-up or pull-down current. The control terminal charging / discharging unit 113 charges the control terminal of the driving transistor T1 according to the pull-up current and discharges the control terminal of the driving transistor T1 according to the pull-down current.

[0045] The bias current Ivgs changes synchronously with the threshold voltage of the driving transistor T1. Therefore, the pull-up and pull-down currents obtained based on the bias current Ivgs can compensate for process variations between different driving circuits 100, making the speed and time required for different driving transistors T1 to provide a stable driving current Iout more consistent, thereby improving the uniformity of the display.

[0046] Further, refer to Figure 3 The mirror unit includes a first mirror branch 112a, a second mirror branch 112b, a third mirror branch 112c, and a fourth mirror branch 112d. The first mirror branch 112a serves as the source branch in the mirror unit and is connected to the bias current Ivgs. The second mirror branch 112b is connected to the first mirror branch 112a and provides a mirror current for the bias current Ivgs. The third mirror branch 112c is connected to the second mirror branch 112b and replicates the mirror current provided by the second mirror branch 112b to provide a pull-up current. The fourth mirror branch 112d is connected to the first mirror branch 112a and replicates the bias current Ivgs to provide a pull-down current.

[0047] Specifically, the first mirror branch 112a includes a fourth transistor MN1. The first terminal of the fourth transistor MN1 is connected to the control terminal and to the bias unit 111 to receive the bias current Ivgs. The second terminal of the fourth transistor MN1 is connected to the second power supply terminal AVSS.

[0048] The second mirror branch 112b includes a fifth transistor MN2 and a sixth transistor MP4. The control terminal of the fifth transistor MN2 is connected to the control terminal of the fourth transistor MN1, and its second terminal is connected to the second power supply terminal AVSS. The first terminal of the sixth transistor MP4 is connected to the first power supply terminal AVDD, and its second terminal is connected to the first terminal of the fifth transistor MN2.

[0049] The third mirror branch 112c includes at least one seventh transistor. Figure 3 In the example, the third mirror branch 112c includes three seventh transistors MSP1, MSP2, and MSP3. The control terminal of each seventh transistor is connected to the control terminal of the sixth transistor MP4, the first terminal is connected to the first power supply terminal AVDD, and the second terminal provides pull-up current.

[0050] The fourth mirror branch 112d includes at least one eighth transistor. Figure 3 In the example, the fourth mirror branch 112d includes three eighth transistors MSN1, MSN2, and MSN3. The control terminal of each eighth transistor is connected to the control terminal of the fourth transistor MN1, the second terminal is connected to the second power supply terminal AVSS, and the first terminal provides pull-down current.

[0051] It should be noted that different seventh transistors can have different sizes to achieve a proportional replication of the mirrored current, i.e., the bias current Ivgs. For example, the ratio of pull-up current to bias current Ivgs provided by seventh transistors MSP1, MSP2, and MSP3 can be 1:2:4. Similarly, different eighth transistors can also have different sizes; for example, the ratio of pull-down current to bias current Ivgs provided by eighth transistors MSN1, MSN2, and MSN3 can also be 1:2:4.

[0052] The control terminal charging / discharging unit 113 includes a ninth transistor MCP and a tenth transistor MCN. The first terminal of the ninth transistor MCP is connected to a pull-up current, and the second terminal is connected to the control terminal (point A) of the driving transistor T1. The control terminal is connected to a pulse width modulation (PWM) signal. The ninth transistor MCP is turned on according to the first level of the PWM signal, thereby charging the control terminal of the driving transistor T1 according to the pull-up current. The first terminal of the tenth transistor MCN is connected to the control terminal (point A) of the driving transistor T1, and the second terminal is connected to a pull-down current. The control terminal is connected to a pull-down signal VD. The tenth transistor MCN is turned on according to a valid pull-down signal VD, thereby discharging the control terminal of the driving transistor T1 according to the pull-down current.

[0053] In a preferred embodiment, the control terminal charging / discharging unit 113 further includes at least one eleventh transistor and at least one twelfth transistor. Figure 3The diagram illustrates two eleventh transistors, MRP1 and MPR2, and two twelfth transistors, MRN1 and MRN2. The control terminal of each eleventh transistor is connected to the first switch signal PULL, and its second terminal is connected to the control terminal of the drive transistor T1. The first terminal of the ninth transistor MCP and the first terminal of each eleventh transistor are connected to the second terminal of their respective seventh transistors. That is, the total number of ninth transistors MCP and eleventh transistors is equal to the total number of seventh transistors. The control terminal of each twelfth transistor is connected to the second switch signal DOWN, and its first terminal is connected to the second terminal of the tenth transistor MCN. The second terminal of the tenth transistor MCN and the second terminal of each twelfth transistor are connected to the first terminal of their respective eighth transistors. That is, the total number of tenth transistors MCN and twelfth transistors is equal to the total number of eighth transistors.

[0054] The first switching signal PULL and the second switching signal DOWN can be multi-bit binary numbers. Each eleventh transistor is turned on when the corresponding bit in the first switching signal PULL is a valid value or turned off when the corresponding bit is an invalid value. Similarly, each twelfth transistor is turned on when the corresponding bit in the second switching signal DOWN is a valid value or turned off when the corresponding bit is an invalid value. The pull-up and pull-down currents can be adjusted as needed using the first switching signal PULL and the second switching signal DOWN to avoid wasting power.

[0055] It should be noted that, in Figure 3 In this transistor configuration, the eleventh transistor, the ninth transistor MCP, the seventh transistor, and the sixth transistor MP4 are all PMOS transistors; the twelfth transistor, the tenth transistor MCN, the eighth transistor, the fourth transistor MN1, and the fifth transistor MN2 are all NMOS transistors. When the transistors are turned on, current flows from the first terminal to the second terminal. The first terminal of a PMOS transistor is the source, and the second terminal is the drain; the first terminal of an NMOS transistor is the drain, and the second terminal is the source.

[0056] Figure 4 A schematic circuit diagram of the bias unit is shown. (Reference) Figure 4 The bias unit 111 includes a first transistor MP1, a second transistor MP2, a multiplexer 111a, and a resistor string 111b. Specifically, the bias unit 111 provides a bias current Ivgs that changes synchronously with the threshold voltage of the driving transistor T1 by adjusting the actual resistance between the control terminal of the first transistor MP1 and the first power supply terminal AVDD to a set value.

[0057] Specifically, the resistor string 111b includes multiple resistors, and the output node of the resistor string 111b includes at least some of the common nodes of adjacent resistors. Figure 4In the example, resistor string 111b includes resistors R1 to Rm+1, and the common node of any two adjacent resistors is an output node of resistor string 111b. In a preferred embodiment, all resistors in resistor string 111b are identical.

[0058] Each input terminal of the multiplexer 111a is connected to a corresponding output node of the resistor string 111b. In some embodiments, the multiplexer 111a may include a plurality of switching elements, the first terminal of each switching element being connected to a corresponding output node of the resistor string 111b, and the second terminals of each switching element being connected together as the output terminal of the multiplexer 111a. For example, refer to... Figure 4 The multiplexer 111a includes switching elements MNCS1, MNCS2...MNCSm, and each switching element is an NMOS transistor.

[0059] The first terminal of the first transistor MP1 is connected to the first power supply terminal AVDD, the second terminal is connected to the first signal ICN, and the control terminal is connected to the output terminal of the multiplexer 111a. The first transistor MP1 and the driving transistor T1 are of the same type, for example, refer to [reference missing]. Figure 2 and Figure 4 The example uses PMOS transistors as an example, where both the first transistor MP1 and the driving transistor T1 are PMOS transistors.

[0060] The first terminal of the second transistor MP2 is connected to the control terminal of the first transistor MP1, and the control terminal is connected to the second terminal of the first transistor MP1. The second terminal provides a bias current Ivgs.

[0061] The auxiliary drive circuit 110 provided in this application is integrated on the same chip as the corresponding drive transistor T1. Therefore, the first transistor MP1 and the drive transistor T1 are affected by the same process deviation, causing their threshold voltages to change in the same direction. For example, when the threshold voltage of the drive transistor T1 is low, the threshold voltage of the first transistor MP1 is also low. When the first signal ICN is constant, the voltage difference between the first power supply terminal AVDD and the control terminal (node ​​B) of the first transistor MP1 will change along with the threshold voltage of the first transistor MP1. At this time, the multiplexer 111a connects the control terminal of the first transistor MP1 with the corresponding output node on the resistor string 111b according to the target selection signal CS, so that the actual resistance between the first power supply terminal AVDD and the control terminal of the first transistor MP1 is a set value. According to the current calculation formula I=U / R, since the voltage U changes due to the process deviation, and the change of voltage U is synchronized with the change of the threshold voltage of the drive transistor, when the actual resistance value of the resistor R remains unchanged, a bias current Ivgs containing the above-mentioned process deviation can be provided, that is, a bias current Ivgs that changes synchronously with the threshold voltage of the drive transistor T1. Correspondingly, the pull-up and pull-down currents obtained by replicating the bias current Ivgs also include process deviations. Therefore, the pull-up and pull-down currents containing process deviations charge and discharge the control terminal of the drive transistor T1, which can compensate for the process deviations and make the speed and time required for different drive transistors T1 to provide stable drive current more consistent.

[0062] It should be noted that, in some embodiments, the initial selection signal may be set before the chip to which the driving circuit 100 belongs is shipped. The output node of the resistor string 111b selected according to the initial selection signal is the output node corresponding to the set value when the resistor string 111b has the ideal resistance value.

[0063] In actual operation, the resistance value of resistor string 111b will also deviate from the ideal resistance value due to process variations. Therefore, the deviation between the actual and ideal resistance values ​​of resistor string 111b can be obtained based on the deviation between the actual current and the ideal current in resistor string 111b. In other words, the deviation between the actual resistance value and the set value between the first power supply terminal AVDD and node B under the initial selection signal can be obtained, and the initial selection signal can be adjusted based on this deviation to obtain the target selection signal CS.

[0064] Accordingly, in some embodiments, the bias unit 111 further includes a third transistor MP3. The first terminal of the third transistor MP3 is connected to the first power supply terminal AVDD, and the second terminal is connected to the control terminal (node ​​B) of the first transistor MP1. The control terminal is connected to the enable signal PD.

[0065] During the active level of the enable signal PD, the first end of the resistor string 111b is connected to the first power supply terminal AVDD, the second end is left floating, and the third transistor MP3 is turned off. At this time, the bias unit 111 provides the bias current Ivgs.

[0066] During the invalid level of the enable signal PD, the first end of resistor string 111b is connected to the first power supply terminal AVDD, the second end is grounded, and the third transistor MP3 is turned on. At this time, since the current in resistor string 111b can characterize the deviation between the actual resistance value and the ideal resistance value of resistor string 111b, it can also characterize the deviation between the actual resistance value and the set value between the first power supply terminal AVDD and node B under the initial selection signal.

[0067] In some embodiments, to facilitate adjustment of the connection state of the second end of the resistor string 111b, the second end of the resistor string 111b can be used as an external terminal of the chip where the auxiliary drive circuit 110 is located. In other embodiments, the second end of the resistor string 111b can also be grounded via an enable switch. This enable switch is also controlled by the enable signal PD, closing during the invalid level of the enable signal PD and opening during the active level of the enable signal PD.

[0068] In some embodiments, the target selection signal CS can be provided manually based on the current in the resistor string 111b while the enable signal PD is at an active level. Specifically, the effective code value of the initial selection signal is, for example, 8, which may indicate that 8 resistors are connected between the first power supply terminal AVDD and node B. When the current in the resistor string 111b is less than the ideal current, it indicates that the actual resistance between the first power supply terminal AVDD and node B is greater than a set value. Therefore, the initial selection signal CS can be decreased to reduce the number of resistors between the first power supply terminal AVDD and node B until the actual resistance between the first power supply terminal AVDD and node B equals the set value. Similarly, when the current in the resistor string 111b is greater than the ideal current, the number of resistors between the first power supply terminal AVDD and node B can be increased by increasing the initial selection signal CS.

[0069] In some other embodiments, the auxiliary drive circuit 110 may also include a processing unit for automatically adjusting the initial selection signal based on the current of the resistor string 111b to obtain the target selection signal CS.

[0070] Furthermore, in some embodiments, the bias unit 111 further includes a logic gate, whose input terminal receives a target selection signal CS and an enable signal PD respectively, and whose output terminal is connected to a multiplexer 111a, so that when the third transistor is turned off, the multiplexer 111a connects the corresponding output node in the resistor string 111b and the control terminal of the first transistor MP1.

[0071] Specifically, such as Figure 4As shown, when the third transistor MP3 is a PMOS transistor, the effective level of the enable signal PD is high (providing Ivgs), and the ineffective level is low (not providing Ivgs). The logic gate is the second AND gate, AND2. It should be noted that... Figure 4 In this context, CS<1:m> represents a set of target selection signals, which includes the control signal for each switching element in multiplexer 111a. Similarly, it should be understood that AND2<1:m> represents a set of second AND gates, and PDP<1:m> represents a set of output signals. That is, the output signal PDP of each second AND gate is used to control the corresponding switching element connected to multiplexer 111a.

[0072] The pull-down signal generation unit 114 is used to provide a pull-down signal VD. Specifically, the pull-down signal generation unit 114 provides an effective pull-down signal when the pulse width modulation signal PWM is at the second level and the control terminal voltage of the driving transistor T1 is greater than the reference voltage Vref.

[0073] Figure 5 A schematic circuit diagram of the bias voltage generation unit is shown. (Reference) Figure 5 The pull-down signal generation unit 114 may include a comparator AMP and a first AND gate AND1. The non-inverting input of the comparator AMP is connected to the control terminal of the driving transistor T1, and the inverting input receives the reference voltage Vref. The first input of the first AND gate AND1 is connected to the output of the comparator AMP to receive the comparison signal Vcomp output by the comparator, the second input receives the pulse width modulation signal PWM, and the output provides the pull-down signal VD.

[0074] For example, when the pulse width modulation signal PWM is at its second level, the driving transistor T1 provides the driving current Iout. Furthermore, the first level of the pulse width modulation signal PWM is low, the second level is high, and the effective level of the pull-down signal VD is high, while the ineffective level is low. The following combines... Figures 2 to 5 The working process of the auxiliary drive circuit of this application will be further described.

[0075] When the pulse width modulation signal PWM is at its first level, the ninth transistor MCP is turned on, providing pull-up current. At this time, the pull-down signal VD is inactive, and the tenth transistor MCN is turned off. The control terminal voltage of the drive transistor T1 is pulled high, and the drive transistor T1 is turned off, providing no drive current Iout.

[0076] When the pulse width modulation signal PWM is at the second level, the ninth transistor MCP is turned off. At this time, the control terminal voltage of the driving transistor T1 is greater than the reference voltage Vref, the comparator AMP outputs a high level, and the pull-down signal generation unit 114 provides a valid pull-down signal VD. The tenth transistor MCN is turned on to provide pull-down current. Until the control terminal voltage of the driving transistor T1 is pulled down to below the reference voltage Vref, the comparator AMP flips, causing the pull-down signal generation unit 114 to provide an invalid pull-down signal VD, and the auxiliary driving circuit 110 stops working. Under the feedback control of the first operational amplifier OP1, the driving transistor T1 tends to a stable conducting state, that is, the driving current Iout is in a stable stage.

[0077] Because the magnitudes of the pull-up and pull-down currents change synchronously with the threshold voltage of the driving transistor—that is, when a stable driving current is provided, the control terminal voltage of the driving transistor is matched—the speed and time required for different driving transistors to provide stable driving current can be made more consistent. This eliminates brightness deviations in the light-emitting elements caused by mismatch in the driving transistors. In particular, it can significantly improve display consistency under low grayscale conditions, thus enhancing the user experience.

[0078] Furthermore, a first switching signal PULL and a second switching signal DOWN can be provided according to the actual working conditions, thereby adjusting the number of the eleventh or twelfth transistors that are turned on, and further adjusting the charging and discharging speeds of the drive transistor control terminals.

[0079] It should be noted that the driver chip provided in this application can also be used to provide drive current for other types of loads besides display panels. Accordingly, the output node of the resistor string can be selected according to the load size.

[0080] Figure 6 A schematic flowchart of an auxiliary driving method according to an embodiment of this application is shown. This driving method can be used to assist driving transistors in providing drive current to a load. (Reference) Figure 6 The auxiliary driving method provided in this application includes the following steps:

[0081] Step S11: Provide a bias current, which changes synchronously with the threshold voltage of the driving transistor.

[0082] Step S12: Copy the bias current to provide pull-up or pull-down current.

[0083] Step S13: Charge the control terminal of the driving transistor according to the pull-up current, or discharge the control terminal of the driving transistor according to the pull-down current.

[0084] This auxiliary driving method can be implemented, for example, through the auxiliary driving circuit provided in the embodiments of this application. By providing pull-up and pull-down currents to the control terminal of the driving transistor, the driving transistor is assisted in rapid turn-on. Furthermore, the magnitudes of the pull-up and pull-down currents are synchronously varied with the threshold voltage of the driving transistor, that is, adapted to the control terminal voltage of the driving transistor when a stable driving current is provided. This allows the speed and time required for different driving transistors to provide stable driving currents to become more consistent, thereby eliminating brightness deviations in the light-emitting element caused by mismatch in the driving transistors. In particular, it can significantly improve display consistency under low grayscale conditions, thus enhancing the user experience.

[0085] As described above, these embodiments of this application do not exhaustively cover all details, nor do they limit this application to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. The scope of protection of this application should be determined by the scope defined in the claims of this application.

Claims

1. An auxiliary drive circuit, wherein, The auxiliary driving circuit is used to assist the driving transistor in providing driving current to the load. The auxiliary driving circuit includes: A biasing unit is used to provide a bias current, which changes synchronously with the threshold voltage of the driving transistor; A mirror unit is used to replicate the bias current to provide a pull-up current or a pull-down current; and A control terminal charging / discharging unit is configured to charge the control terminal of the driving transistor according to the pull-up current, and to discharge the control terminal of the driving transistor according to the pull-down current. The bias unit includes: A resistor string, the resistor string comprising a plurality of resistors, wherein the output node of the resistor string comprises at least a portion of the common nodes of adjacent resistors; A multiplexer, with each input connected to the corresponding output node; A first transistor, with its control terminal connected to the output terminal of the multiplexer, its first terminal connected to a first power supply terminal, and its second terminal connected to a first signal; and The second transistor has its control terminal connected to the second terminal of the first transistor, and its first terminal connected to the control terminal of the first transistor. The second terminal provides the bias current. The multiplexer connects the control terminal of the first transistor and the corresponding output node according to the target selection signal, so that the actual resistance of the resistor string between the first power supply terminal and the control terminal of the first transistor is a set value.

2. The auxiliary drive circuit according to claim 1, wherein, The bias unit further includes: The third transistor has a first terminal connected to the first power supply terminal and a second terminal connected to the control terminal of the first transistor, with the control terminal connected to an enable signal. During the active level of the enable signal, the third transistor is off, the first end of the resistor string is connected to the first power supply terminal, the second end is floating, and the bias unit provides the bias current. During the invalid level of the enable signal, the third transistor is turned on, the first end of the resistor string is connected to the first power supply terminal, the second end is grounded, and the current of the resistor string represents the difference between the actual resistance value and the set value under the initial selection signal.

3. The auxiliary drive circuit according to claim 2, wherein, The auxiliary drive circuit further includes a processing unit for adjusting the initial selection signal according to the difference to obtain the target selection signal.

4. The auxiliary drive circuit according to claim 3, wherein, The bias unit further includes: The logic gate receives the target selection signal and the enable signal at its input terminal and is connected to the multiplexer at its output terminal.

5. The auxiliary drive circuit according to claim 1, wherein, The mirror unit includes: The first mirror branch is connected to the bias current; The second mirror branch, connected to the first mirror branch, is used to provide a mirror current for the bias current; A third mirror branch, connected to the second mirror branch, is used to replicate the mirror current to provide the pull-up current; and The fourth mirror branch, connected to the first mirror branch, is used to replicate the bias current to provide the pull-down current.

6. The auxiliary drive circuit according to claim 5, wherein, The first mirror branch includes: a fourth transistor, with its first terminal connected to the control terminal and receiving the bias current, and its second terminal connected to the second power supply terminal. The second mirror branch includes: The fifth transistor has its control terminal connected to the control terminal of the fourth transistor, and its second terminal connected to the second power supply terminal; and The sixth transistor has its first end connected to the first power supply terminal and its second end connected to the first end of the fifth transistor.

7. The auxiliary drive circuit according to claim 6, wherein, The third mirror branch includes at least one seventh transistor, the control terminal of each seventh transistor is connected to the control terminal of the sixth transistor, the first terminal is connected to the first power supply terminal, and the second terminal provides the pull-up current. The fourth mirror branch includes at least one eighth transistor, the control terminal of each eighth transistor is connected to the control terminal of the fourth transistor, the second terminal is connected to the second power supply terminal, and the first terminal provides the pull-down current.

8. The auxiliary drive circuit according to claim 7, wherein, The control terminal charging / discharging unit includes: A ninth transistor has a first terminal connected to the pull-up current and a second terminal connected to the control terminal of the driving transistor. The control terminal is connected to a pulse width modulation signal. The ninth transistor turns on according to a first level of the pulse width modulation signal, thereby charging the control terminal of the driving transistor according to the pull-up current. The tenth transistor has a first terminal connected to the control terminal of the driving transistor and a second terminal connected to the pull-down current. The control terminal is connected to a pull-down signal. The tenth transistor is turned on according to the valid pull-down signal, thereby discharging the control terminal of the driving transistor according to the pull-down current.

9. The auxiliary drive circuit according to claim 8, wherein, The control terminal charging and discharging unit further includes: At least one eleventh transistor, with its control terminal connected to a first switching signal and its second terminal connected to the control terminal of the driving transistor; the first terminal of the ninth transistor and the first terminal of each of the eleventh transistors are connected to the second terminal of their respective seventh transistors; and At least one twelfth transistor has a control terminal connected to a second switching signal, a first terminal connected to the second terminal of the tenth transistor, and the second terminal of the tenth transistor and the second terminal of each of the twelfth transistors are connected to the first terminal of their respective eighth transistors. The eleventh transistor is used to turn on when the first switch signal is valid, and the twelfth transistor is used to turn on when the second switch signal is valid.

10. The auxiliary drive circuit according to claim 9, wherein, The first switch signal and the second switch signal both include multiple bits of binary data. Each of the eleventh transistors is turned on when the corresponding bit in the first switching signal is a valid code value. Each of the twelfth transistors is turned on when the corresponding bit in the second switching signal is a valid code value.

11. The auxiliary drive circuit according to claim 8, wherein, The auxiliary drive circuit further includes: a pull-down signal generation unit, used to provide the pull-down signal. The pull-down signal generation unit provides an effective pull-down signal when the pulse width modulation signal is at the second level and the control terminal voltage of the driving transistor is greater than the reference voltage.

12. The auxiliary drive circuit according to claim 11, wherein, The pull-down signal generation unit includes: The comparator has its non-inverting input connected to the control terminal of the driving transistor, and its inverting input receiving the reference voltage; and The first AND gate has its input terminals connected to the pulse width modulation signal and the output terminal of the comparator, respectively, and its output terminal provides the pull-down signal.

13. A chip, wherein, include: A drive transistor is used to provide drive current to the load. as well as The auxiliary driving circuit as described in any one of claims 1-12, wherein the auxiliary driving circuit is connected to the control terminal of the driving transistor.

14. A display device, wherein, include: The display panel includes multiple light-emitting elements; as well as The chip as described in claim 13 is used to provide a driving current for the light-emitting element.

15. An auxiliary driving method, wherein, The auxiliary driving method provides driving current to the load through the auxiliary driving transistor as described in any one of claims 1-14. The auxiliary driving method includes: A bias current is provided, which changes synchronously with the threshold voltage of the driving transistor; The bias current is replicated to provide pull-up or pull-down current; and The control terminal of the driving transistor is charged according to the pull-up current, or the control terminal of the driving transistor is discharged according to the pull-down current.

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