Display panel and display device

Abstract

The invention provides a display panel and a display device.The display panel carries out display based on various display refresh frequencies, the display panel comprises a plurality of pixel units arranged in an array and a driving unit connected with the pixel units, each pixel unit comprises a pixel electrode and a common electrode, and the common electrode is connected with the pixel units. The driving unit is respectively connected with the pixel electrode and the common electrode; wherein the driving unit is used for applying a first voltage signal to the pixel electrode and applying a second voltage signal to the common electrode; in a vertical blanking interval of a frame display period, the first voltage signal and / or the second voltage signal comprise / comprises at least one group of pulse signals, and the number of the pulse signals is determined based on the display refresh frequency of the current frame. The brightness difference during refresh frequency change can be improved, ghosting is eliminated, and the display effect is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] FreeSync is a display frequency scaling technology that enables dynamic refresh rates. Dynamic refresh rates synchronize the refresh rate of compatible monitors with the frame rate of the user's graphics card, minimizing input latency and reducing or completely eliminating stuttering, screen tearing, and glitches during gameplay and video playback.

[0003] Displaying a frame consists of the display time and the pause time before moving to the next frame. Freesync changes the refresh rate by altering the pause time. However, after scanning and charging, a voltage difference needs to be maintained across the LCD to maintain brightness.

[0004] However, during the pause time, the charged power will slowly leak out. The pause time varies at different refresh rates. The longer the pause time, the more power is leaked. This will cause a visible change in brightness when switching between different refresh rates, resulting in ghosting and affecting the display effect. Summary of the Invention

[0005] This invention mainly provides a display panel and a display device that can improve the brightness difference when the refresh rate changes, eliminate ghosting, and improve the display effect.

[0006] To solve the above-mentioned technical problems, the first technical solution adopted by the present invention is: to provide a display panel, the display panel displays based on multiple display refresh rates, and the display panel includes multiple pixel units arranged in an array and a driving unit connected to the pixel units, each pixel unit including a pixel electrode and a common electrode, and the driving unit is connected to the pixel electrode and the common electrode respectively;

[0007] The driving unit is configured to: apply a first voltage signal to the pixel electrode and apply a second voltage signal to the common electrode; in the vertical blanking interval of a frame display cycle, the first voltage signal and / or the second voltage signal includes at least one set of pulse signals, and the number of pulse signals is determined based on the display refresh frequency of the current frame.

[0008] In one embodiment, when both the first voltage signal and the second voltage signal include pulse signals, the pulse signals in the first voltage signal are opposite to the pulse signals in the second voltage signal.

[0009] In one embodiment, during the vertical blanking interval of a display frame, the first voltage signal further includes at least one set of DC signals, and the second voltage signal further includes at least one set of DC signals, with the DC signals and pulse signals alternately set at intervals.

[0010] In one embodiment, at the same display refresh rate, the duration of each group of pulse signals is the same, and the duration of the DC signal between two adjacent pulse signals is the same;

[0011] The pulse signal includes positive pulse signals and negative pulse signals.

[0012] In one embodiment, the number of pulse signals is negatively correlated with the display refresh rate of the current frame.

[0013] In one embodiment, the driving unit includes:

[0014] The timing control chip is used to detect the vertical blanking interval of the display panel and generate the first voltage output command and the second voltage output command.

[0015] The control chip is connected to the timing control chip and the common electrode. It outputs a pulse signal to the common electrode based on a first voltage output command and outputs a DC signal to the common electrode based on a second voltage output command.

[0016] In one embodiment, the driving unit includes:

[0017] The timing control chip is used to detect the vertical blanking interval of the display panel and generate a first reference voltage and a second reference voltage.

[0018] A common voltage generation unit is connected to a common electrode and a timing control chip. It is used to output a pulse signal to the common electrode according to a first reference voltage and to output a DC signal to the common electrode according to a second reference voltage.

[0019] In one embodiment, the common voltage generating unit includes:

[0020] The capacitor's first terminal is connected to a timing control chip to receive voltage output commands.

[0021] The first resistor has its first end connected to the second end of the capacitor.

[0022] The second resistor has its first end connected to the second end of the first resistor.

[0023] An operational amplifier (op-amp) has its first input terminal connected to the second terminal of a first resistor; its second input terminal receives a DC signal; and its output terminal is connected to the second terminal of a second resistor.

[0024] In one embodiment, the driving unit includes:

[0025] The timing control chip is used to detect the vertical blanking interval of the display panel and generate AC and DC output signals.

[0026] The driver chip is connected to the timing control chip and to the pixel electrode via a data line. It is used to output pulse signals to the pixel electrode based on AC output signals and to output DC signals to the pixel electrode based on DC output signals.

[0027] To solve the above-mentioned technical problems, the second technical solution adopted by the present invention is to provide a display device, including a backlight device and a display panel of any of the above-mentioned components.

[0028] The beneficial effects of this invention are as follows: Unlike existing technologies, the display panel provided by this invention displays based on multiple display refresh rates, and the display panel includes multiple pixel units arranged in an array and a driving unit connected to the pixel units. Each pixel unit includes a pixel electrode and a common electrode, and the driving unit is connected to the pixel electrode and the common electrode respectively. The driving unit is used to: apply a first voltage signal to the pixel electrode and apply a second voltage signal to the common electrode; in the vertical blanking interval of a frame display cycle, the first voltage signal and / or the second voltage signal includes at least one set of pulse signals, and the number of pulse signals is determined based on the display refresh rate of the current frame. Switching between refresh rates with large differences in refresh rate will result in a perceptible change in brightness. This application applies at least one set of pulse signals to the pixel electrode and / or the common electrode in the vertical blanking interval, so that it exhibits an AC waveform, offsetting some leakage current and compensating for some brightness. Furthermore, determining the number of pulse signals based on the display refresh rate of the current frame can improve the brightness difference when the refresh rate changes, eliminate ghosting, and improve the display effect. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 A schematic diagram of the structure of the first embodiment of the display panel provided in this application;

[0031] Figure 2 This is a schematic diagram of a pixel unit in this application;

[0032] Figure 3 This is a schematic diagram of the structure of the first embodiment of the driving unit of this application;

[0033] Figure 4 This is a schematic diagram of the structure of the second embodiment of the driving unit of this application;

[0034] Figure 5 This is a schematic diagram of the structure of the third embodiment of the driving unit of this application;

[0035] Figure 6 This is a timing diagram of the first voltage signal received by the pixel electrode of this application;

[0036] Figure 7 This is a timing diagram of the second voltage signal received by the common electrode of this application;

[0037] Figure 8 This is a timing diagram of the second voltage signal received by the common electrode and the first voltage signal received by the pixel electrode in this application;

[0038] Figure 9 This is a schematic diagram of the structure of an embodiment of the display device of this application.

[0039] Explanation of reference numerals in the attached figures: Pixel unit 10, Driving unit 11, Scan line G, nth scan line Gn, (n+1)th scan line Gn+1, Data line Data, (n-1)th data line Data n-1, nth data line Data n, (n+1)th data line Data n+1, Pixel electrode A, Common electrode B, Driving transistor T, Timing control chip 111, Control chip 112, Common voltage generation unit 113, Capacitor C, First resistor R1, Second resistor R2, Operational amplifier OP, Fixed DC signal Com_in, Driving chip 114, Display time DE, Vertical blanking interval Vblank, Display device 90, Backlight device 91, Display panel 92. Detailed Implementation

[0040] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0041] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.

[0042] In this article, the term "and / or" simply describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. Additionally, the character " / " generally indicates that the preceding and following related objects have an "or" relationship. Furthermore, "more" in this article means two or more objects.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0044] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.

[0045] Displaying a frame involves both the display time and the pause time before moving to the next frame. Freesync changes the refresh rate by altering this pause time. However, after scanning and charging, a voltage difference needs to be maintained across the LCD to preserve brightness. During the pause time, the charged power slowly leaks out. Since the pause time varies at different refresh rates, a longer pause time results in greater power leakage, causing noticeable changes in brightness when switching between refresh rates.

[0046] Taking a display panel with a refresh rate of 48Hz-240Hz as an example, and a resolution of 1920*1080, it needs to scan and charge 1080 lines during display time, then pause for 45 lines. This 45-line charging time is the pause time. Freesync changes the refresh rate by altering the number of charging lines during the pause time. For a 240Hz frame, the number of scan lines during display time is 1125. If the pause time is 1125 lines, the number of lines per frame is 2250. Since the time per line is the same, the refresh rate changes from 240Hz to 120Hz. When maintaining brightness by keeping the voltage difference across the LCD after scanning and charging, the charging power will slowly leak. The leakage time differs significantly between 240Hz and 48Hz, resulting in a perceptible change in brightness when switching between refresh rates with large differences.

[0047] In view of this, this application provides a display panel that displays based on multiple display refresh rates. The display panel includes multiple pixel units arranged in an array and a driving unit connected to the pixel units. Each pixel unit includes a pixel electrode and a common electrode, and the driving unit is connected to the pixel electrode and the common electrode respectively. The driving unit is used to: apply a first voltage signal to the pixel electrode and apply a second voltage signal to the common electrode; during the vertical blanking interval of a frame display cycle, the first voltage signal and / or the second voltage signal includes at least one set of pulse signals, and the number of pulse signals is determined based on the display refresh rate of the current frame. The display panel of this application, during the vertical blanking interval (i.e., pause time) of a frame display cycle, sets the second voltage signal applied to the common electrode and the first voltage signal of the pixel electrode to include at least one set of pulse signals, and the number of pulse signals is determined based on the display refresh rate of the current frame. This can improve the brightness difference when the refresh rate changes, eliminate ghosting, and improve the display effect.

[0048] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0049] See Figure 1 , Figure 1 This is a schematic diagram of the structure of a first embodiment of the display panel provided in this application. The display panel provided in this application displays based on multiple display refresh rates, and includes multiple pixel units 10 arranged in an array and driving units 11 connected to the pixel units 10. Each pixel unit 10 includes a pixel electrode and a common electrode, and the driving unit 11 is connected to the pixel electrode and the common electrode respectively. The driving unit 11 is used to apply a first voltage signal to the pixel electrode and a second voltage signal to the common electrode. In the vertical blanking interval of a frame display cycle, the first voltage signal and / or the second voltage signal includes at least one set of pulse signals, and the number of pulse signals is determined based on the display refresh rate of the current frame. It should be noted that the vertical blanking interval corresponds to the aforementioned pause time.

[0050] Specifically, in combination Figure 2 , Figure 2 This is a schematic diagram of a pixel unit according to this application. Specifically, the display panel includes multiple vertically spaced scan lines G. Figure 2 Only the nth scan line Gn and the (n+1)th scan line Gn+1 are shown. The display panel also includes multiple horizontally spaced data lines Data that are perpendicular to the scan lines. Figure 2 Only the (n-1)th data line Data n-1, the nth data line Data n, and the (n+1)th data line Data n+1 are shown. Each scan line G is connected to a row of pixel units 10, and each data line Data is connected to a column of pixel units 10. Each pixel unit 10 includes a pixel electrode A and a common electrode B, as well as a driving transistor T. For the nth row of pixel units 10, the control terminal of the driving transistor T is connected to the nth scan line Gn. For the nth column of pixel units 10, the first terminal of the driving transistor T is connected to the nth data line Data n, and the second terminal of the pixel unit 10 is connected to the pixel electrode A.

[0051] Specifically, pixel electrode A of pixel unit 10 is connected to driving unit 11 via driving transistor T and data line Data, while common electrode B of pixel unit 10 is connected to driving unit 11 via signal line. The display cycle of one frame is divided into a display interval and a vertical blanking interval. During the display interval, scan line G scans line by line to turn on driving transistor T. Driving unit 11 applies a first voltage signal to pixel electrode A via data line Data; and driving unit 11 applies a second voltage signal to common electrode B via signal line. It should be noted that the first voltage signal during the display interval is the display signal corresponding to the displayed image. During the vertical blanking interval, the first voltage signal during the display interval is the display signal corresponding to the black image.

[0052] In one embodiment of this application, during the vertical blanking interval, the first voltage signal includes at least one set of pulse signals, such that during the vertical blanking interval, the voltage signal applied to pixel electrode A partially exhibits an AC waveform. It is worth noting that the pulse signals include positive pulse signals and negative pulse signals.

[0053] In another embodiment of this application, during the vertical blanking interval, the second voltage signal includes at least one set of pulse signals, such that during the vertical blanking interval, the voltage signal applied to the common electrode B partially exhibits an AC waveform.

[0054] In another embodiment of this application, during the vertical blanking interval, both the first voltage signal and the second voltage signal include at least one set of pulse signals, such that during the vertical blanking interval, the voltage signal applied to pixel electrode A partially exhibits an AC waveform, and simultaneously, the voltage signal applied to common electrode B also partially exhibits an AC waveform. It should be noted that when both the first voltage signal and the second voltage signal include pulse signals, the pulse signals in the first voltage signal are opposite to those in the second voltage signal. Specifically, when the first voltage signal contains a positive pulse signal, the second voltage signal contains a negative pulse signal; and when the first voltage signal contains a negative pulse signal, the second voltage signal contains a positive pulse signal.

[0055] Furthermore, the number of pulse signals is determined based on the display refresh rate of the current frame. Specifically, switching between refresh rates with large differences will result in perceptible changes in brightness. This application applies at least one set of pulse signals to the pixel electrode and / or common electrode in the vertical blanking interval, so that it exhibits an AC waveform, offsetting some leakage current and compensating for some brightness. Moreover, determining the number of pulse signals based on the display refresh rate of the current frame can improve the brightness difference when the refresh rate changes, eliminate ghosting, and improve the display effect.

[0056] In one embodiment of this application, the number of pulse signals is negatively correlated with the display refresh rate of the current frame. Specifically, a higher display refresh rate results in a shorter duration of the corresponding vertical blanking interval, which also means a shorter leakage time. Therefore, a smaller number of pulse signals can compensate for the leakage. Conversely, a lower display refresh rate results in a longer duration of the corresponding vertical blanking interval, which also means a longer leakage time. Therefore, a larger number of pulse signals can compensate for more leakage. In this way, the brightness difference when the refresh rate changes can be improved, ghosting can be eliminated, and the display effect can be improved.

[0057] Furthermore, within the vertical blanking interval of one frame display cycle, the first voltage signal further includes at least one set of DC signals, and the second voltage signal further includes at least one set of DC signals, with the DC signals and pulse signals alternating. Specifically, if only the first voltage signal includes at least one set of pulse signals, the first voltage signal also includes at least one set of DC signals, with the DC signals and pulse signals alternating. If only the second voltage signal includes at least one set of pulse signals, the second voltage signal also includes at least one set of DC signals, with the DC signals and pulse signals alternating. If both the first and second voltage signals include at least one set of pulse signals, the first voltage signal also includes at least one set of DC signals, and the second voltage signal also includes at least one set of DC signals, with the DC signals and pulse signals alternating. This embodiment sets the first and / or second voltage signals within the vertical blanking interval to alternate between DC signals and pulse signals, rather than continuously setting pulse signals, which can improve the brightness difference when the refresh rate changes, eliminate ghosting, and improve the display effect.

[0058] It is worth noting that if the pulse signal is continuously set, meaning the first voltage signal and / or the second voltage signal always appear as an AC waveform, and if the display refresh rate is low (i.e., the duration of the corresponding vertical blanking interval is longer), coupled with leakage current, the screen brightness will change. This is equivalent to adding a new display image within the vertical blanking interval, affecting the display effect. This application sets an alternating interval between the DC signal and the pulse signal, which can improve this situation.

[0059] See Figure 3 , Figure 3 This is a schematic diagram of the structure of the first embodiment of the driving unit of this application. The driving unit 11 includes a timing control chip 111 and a control chip 112. The timing control chip 111 is used to detect the vertical blanking interval of the display panel and generate a first voltage output command and a second voltage output command. The control chip 112 is connected to the timing control chip 111 and the common electrode B, and outputs a pulse signal to the common electrode B based on the first voltage output command and outputs a DC signal to the common electrode B based on the second voltage output command.

[0060] It is worth noting that the timing control chip 111 can be, for example, a TCON chip, and the control chip 112 can be, for example, a PowerIC power management chip.

[0061] During the vertical blanking interval, timing control chip 111 outputs a first voltage output command to control chip 112 upon detecting the vertical blanking interval. Control chip 112 generates a pulse signal based on the first voltage output command and transmits it to the common electrode B. Then, timing control chip 111 outputs a second voltage output command, and control chip 112 generates a DC signal based on the second voltage output command and transmits it to the common electrode B.

[0062] Specifically, when the display refresh rate changes, the timing control chip 111 detects the vertical blanking interval of the first frame after the display refresh rate change. After determining the vertical blanking interval, it generates a first voltage output command and a second voltage output command. Based on the first voltage output command and the second voltage output command, the control chip 112 generates a pulse signal and a DC signal in the vertical blanking interval of the next frame and transmits them to the common electrode B.

[0063] See Figure 4 , Figure 4 This is a schematic diagram of the structure of a second embodiment of the driving unit of this application. The driving unit includes a timing control chip 111 and a common voltage generation unit 113. The timing control chip 111 is used to detect the vertical blanking interval of the display panel and generate a first reference voltage vref1 and a second reference voltage vref2. The common voltage generation unit 113 is connected to a common electrode B and the timing control chip 111, and is used to output a pulse signal to the common electrode B according to the first reference voltage vref1, and to output a DC signal to the common electrode B according to the second reference voltage vref2.

[0064] Specifically, the common voltage generation unit 113 includes a capacitor C, a first resistor R1, a second resistor R2, and an operational amplifier OP. The first terminal of capacitor C is connected to the timing control chip 111; the first terminal of the first resistor R1 is connected to the second terminal of capacitor C; the first terminal of the second resistor R2 is connected to the second terminal of the first resistor R1; the first input terminal of the operational amplifier OP is connected to the second terminal of the first resistor R1; the second input terminal of the operational amplifier OP receives the DC signal Com_in; and the output terminal of the operational amplifier OP is connected to the second terminal of the second resistor R2.

[0065] Specifically, when the timing control chip 111 detects the vertical blanking interval, it outputs a first reference voltage vref1. At this time, the first reference voltage vref1 is superimposed with an AC signal component. After the DC component is isolated by capacitor C, the AC component is output and then passes through the first resistor R1 to the first input terminal (inverting input terminal) of the op-amp. The op-amp amplifies the voltage difference between the inverting input terminal and the non-inverting input terminal (second input terminal) using the amplification formula Vcfcom*R1=Vref1*R2, where Vcfcom is a pulse signal. Since the non-inverting input terminal is a fixed DC signal Com_in, the AC signal causes the voltage at the inverting input terminal to change relative to the non-inverting input terminal. The op-amp amplifies and outputs this change. For example, the positive half-cycle of the AC signal increases the voltage at the inverting input terminal, increasing the op-amp output; the negative half-cycle decreases the voltage at the inverting input terminal, decreasing the op-amp output. In this way, the common electrode B receives the amplified pulse signal, realizing the AC output. At the same time, the DC signal in the circuit provides a reference level for the AC signal, ensuring that the AC signal is output within a suitable voltage range. It should be noted that the final output pulse signal is the positive and negative voltage signal of the black screen.

[0066] After outputting the first reference voltage vref1, the timing control chip 111 outputs a second reference voltage vref2, which includes a DC component. The second reference voltage vref2 passes through capacitor C and the first resistor R1. Capacitor C has DC blocking and AC passing characteristics, theoretically allowing the DC signal to pass smoothly. It then passes through the first resistor R1 to reach the inverting input of the operational amplifier. A fixed DC signal Com_in is connected to the non-inverting input of the operational amplifier. Based on the operational amplifier's "virtual short" characteristic, the voltage at the inverting input will approach the voltage at the non-inverting input. The operational amplifier adjusts its output through a feedback mechanism (via the second resistor R2) to stabilize the voltage at the inverting input at a level close to the DC signal Com_in, thereby outputting a stable DC signal to the common electrode B.

[0067] Specifically, when the display refresh rate changes, the timing control chip 111 detects the vertical blanking interval of the first frame after the display refresh rate change. After determining the vertical blanking interval, it generates a first reference voltage vref1 and a second reference voltage vref2. Based on the first reference voltage vref1 and the second reference voltage vref2, the control chip 112 generates a pulse signal and a DC signal in the vertical blanking interval of the next frame and transmits them to the common electrode B.

[0068] See Figure 5 , Figure 5 This is a schematic diagram of the structure of the third embodiment of the driving unit of this application. The driving unit 11 includes a timing control chip 111 and a driving chip 114. The driving chip 114 can be, for example, a driver integrated chip (DriverIC).

[0069] In this embodiment, the timing control chip 111 is used to detect the vertical blanking interval of the display panel and generate an AC output signal and a DC output signal; the driver chip 114 is connected to the timing control chip 111 and connected to the pixel electrode A through the data line Data, and is used to output a pulse signal to the pixel electrode A based on the AC output signal and to output a DC signal to the pixel electrode A based on the DC output signal.

[0070] Specifically, in combination Figure 2 During the vertical blanking interval, the scan drive circuit controls the drive transistor T to turn on. Simultaneously, when the vertical blanking interval is detected, the timing control chip 111 outputs an AC output signal to the drive chip 114. The drive chip 114 generates a pulse signal based on this AC output signal, which is transmitted to the pixel electrode A via the data line Data and the drive transistor T. Then, the timing control chip 111 outputs a DC output signal, and the drive chip 114 generates a DC signal based on this DC output signal, which is transmitted to the pixel electrode A via the data line Data and the drive transistor T.

[0071] In existing liquid crystal structures, in addition to pixel electrodes and common electrodes, alignment films are also disposed above and below the liquid crystal. Voltage is applied not only to the liquid crystal but also to the alignment films. This is because the resistivity of the alignment film is 10⁻⁶. 15 The resistivity is on the order of magnitude, while that of liquid crystal is 10⁻⁶. 13 The thickness of the alignment layer is on the order of magnitude smaller than that of the liquid crystal, and the thickness of the alignment layer is two orders of magnitude smaller than that of the liquid crystal. In this case, the resistance RPI of the alignment layer is approximately equal to the resistance RLC of the liquid crystal. If the liquid crystal is driven by a DC voltage, the actual voltage applied to it is only 1 / 3. At low refresh rates, the vertical blanking interval is very long, and the liquid crystal is continuously driven by DC. In this situation, not only is the leakage current large due to the long leakage time, but the voltage is also low due to the DC state. With long leakage current and long DC drive, the brightness of low refresh rates will be much worse than that of high refresh rates, and low refresh rates will also flicker due to their own leakage current. This application inserts pulse signals into the vertical blanking interval, which not only has a black insertion effect but also cancels out some leakage current and compensates for some brightness. Furthermore, determining the number of pulse signals based on the current frame's refresh rate can improve the brightness difference when the refresh rate changes, eliminate ghosting, and improve the display effect. At this time, the liquid crystal also indirectly increases the viewing angle because it is constantly rotating between the voltage direction of the normal display and the black screen.

[0072] See Figure 6 , Figure 6This is a timing diagram of the first voltage signal received by the pixel electrode in this application. Taking a white display screen as an example, during the display period of one frame, at display time DE, the first voltage signal corresponds to the display voltage of the white screen. During the vertical blanking interval Vblank, the first voltage signal includes a pulse signal and a DC signal. In one embodiment of this application, at the same display refresh rate, the duration of each group of pulse signals is the same, and the duration of the DC signal between two adjacent pulse signals is the same. Figure 6 In the illustrated embodiment, three different display refresh rates are used as examples. 200Hz is the highest display refresh rate, and 48Hz is the lowest. It can be understood that the vertical blanking interval Vblank corresponding to 48Hz is greater than that corresponding to 100Hz, and the vertical blanking interval Vblank corresponding to 100Hz is greater than that corresponding to 200Hz. The larger the vertical blanking interval Vblank, the more pulse signal groups it corresponds to. In this embodiment, there are 3 pulse signals for the vertical blanking interval Vblank corresponding to 48Hz, 2 pulse signals for the vertical blanking interval Vblank corresponding to 100Hz, and 1 pulse signal for the vertical blanking interval Vblank corresponding to 200Hz.

[0073] Assume the duration of a pulse signal is t1, and the duration of a DC signal is t2. Figure 5Taking the driving unit shown as an example, at each display refresh rate, the timing control chip 111 detects the vertical blanking interval Vblank (specifically, the duration of the vertical blanking interval Vblank is detected), determines the number of pulse signals to be inserted based on the detected vertical blanking interval Vblank, and generates AC and DC output signals. Specifically, when displaying the first frame at 200Hz, based on the detection result of the vertical blanking interval Vblank of the first frame, it is determined that only one set of pulse signals needs to be inserted. At this time, the timing control chip 11 outputs AC and DC output signals. The driving chip 114 outputs pulse signal t1 and DC signal t2 to pixel electrode A based on the AC and DC output signals within the vertical blanking interval Vblank. When displaying the first frame at 48Hz, based on the detection result of the vertical blanking interval Vblank of the first frame, it is determined that three sets of pulse signals need to be inserted. At this time, the timing control chip 11 outputs AC and DC output signals. The driver chip 114 outputs a pulse signal t1 and a DC signal t2 to the pixel electrode A within the vertical blanking interval Vblank, based on the AC and DC output signals. During the first frame display at 100Hz, based on the detection result of the vertical blanking interval Vblank of the first frame, it is determined that two sets of pulse signals need to be inserted. At this time, the timing control chip 11 outputs both the AC and DC output signals. The driver chip 114 then outputs the pulse signal t1 and the DC signal t2 to the pixel electrode A within the vertical blanking interval Vblank, based on the AC and DC output signals.

[0074] It should be noted that, within the same display refresh rate, the duration of each group of pulse signals can be determined based on the display refresh rate. To simplify the driving method, within the same display refresh rate, the duration of each group of pulse signals is the same, and the duration of the DC signal between two adjacent pulse signals is also the same.

[0075] See Figure 7 , Figure 7 This is a timing diagram of the second voltage signal received by the common electrode of this application. Figure 7 In the illustrated embodiment, three different display refresh rates (200Hz, 48Hz, and 100Hz) are used as examples for explanation. In this embodiment, the vertical blanking interval Vblank pulse signal corresponding to 48Hz consists of 3 sets, the vertical blanking interval Vblank pulse signal corresponding to 100Hz consists of 2 sets, and the vertical blanking interval Vblank pulse signal corresponding to 200Hz consists of 1 set.

[0076] Figure 3 and Figure 4 The drive unit is capable of outputting pulse signals and DC signals that meet the above requirements to the common electrode.

[0077] See Figure 8 , Figure 8 This is a timing diagram of the second voltage signal received by the common electrode and the first voltage signal received by the pixel electrode in this application. Figure 8 In the illustrated embodiment, three different display refresh rates (200Hz, 48Hz, and 100Hz) are used as examples. In this embodiment, the vertical blanking interval Vblank pulse signal corresponding to 48Hz consists of 3 sets, the vertical blanking interval Vblank pulse signal corresponding to 100Hz consists of 2 sets, and the vertical blanking interval Vblank pulse signal corresponding to 200Hz consists of 1 set. Figure 8 In the illustrated embodiment, both the first voltage signal and the second voltage signal include pulse signals and DC signals. It should be noted that when both the first and second voltage signals include pulse signals, the pulse signals in the first voltage signal are opposite to those in the second voltage signal. Specifically, when the first voltage signal contains a positive pulse signal, the second voltage signal contains a negative pulse signal; conversely, when the first voltage signal contains a negative pulse signal, the second voltage signal contains a positive pulse signal.

[0078] See Figure 9 , Figure 9 This is a schematic diagram of the structure of an embodiment of the display device of this application. The display device 90 specifically includes a backlight device 91 and a display panel 92. The display device 90 of this application is, for example, a liquid crystal display (LCD), and the backlight device 91 provides a light source. The display panel 92 includes the display panel shown in any of the above embodiments.

[0079] The above are merely embodiments of the present invention and do not limit the scope of patent protection of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A display panel, characterized in that, The display panel displays based on multiple display refresh rates, and the display panel includes multiple pixel units arranged in an array and a driving unit connected to the pixel units. Each pixel unit includes a pixel electrode and a common electrode, and the driving unit is connected to the pixel electrode and the common electrode respectively. The driving unit is configured to: apply a first voltage signal to the pixel electrode and apply a second voltage signal to the common electrode; in the vertical blanking interval of a frame display cycle, the first voltage signal and / or the second voltage signal includes at least one set of pulse signals, and the number of pulse signals is determined based on the display refresh frequency of the current frame.

2. The display panel according to claim 1, characterized in that, When both the first voltage signal and the second voltage signal include the pulse signal, the pulse signal in the first voltage signal is opposite to the pulse signal in the second voltage signal.

3. The display panel according to claim 1, characterized in that, In the vertical blanking interval of a display frame cycle, the first voltage signal further includes at least one set of DC signals, and the second voltage signal further includes at least one set of DC signals, wherein the DC signals and the pulse signal are alternately set at intervals.

4. The display panel according to claim 3, characterized in that, At the same display refresh rate, the duration of each group of pulse signals is the same, and the duration of the DC signal between two adjacent pulse signals is the same; The pulse signal includes positive pulse signals and negative pulse signals.

5. The display panel according to claim 1, characterized in that, The number of pulse signals is negatively correlated with the display refresh rate of the current frame.

6. The display panel according to claim 3, characterized in that, The driving unit includes: A timing control chip is used to detect the vertical blanking interval of the display panel and generate a first voltage output command and a second voltage output command. The control chip is connected to the timing control chip and the common electrode, and outputs the pulse signal to the common electrode based on the first voltage output command and outputs a DC signal to the common electrode based on the second voltage output command.

7. The display panel according to claim 3, characterized in that, The driving unit includes: A timing control chip is used to detect the vertical blanking interval of the display panel and generate a first reference voltage and a second reference voltage. A common voltage generating unit is connected to the common electrode and the timing control chip, and is used to output the pulse signal to the common electrode according to the first reference voltage, and to output the DC signal to the common electrode according to the second reference voltage.

8. The display panel according to claim 7, characterized in that, The common voltage generating unit includes: A capacitor, the first end of which is connected to the timing control chip to receive the voltage output command; A first resistor, the first end of which is connected to the second end of the capacitor; A second resistor, the first end of which is connected to the second end of the first resistor; An operational amplifier, wherein the first input terminal of the operational amplifier is connected to the second terminal of the first resistor; the second input terminal of the operational amplifier receives the DC signal, and the output terminal of the operational amplifier is connected to the second terminal of the second resistor.

9. The display panel according to claim 3, characterized in that, The driving unit includes: A timing control chip is used to detect the vertical blanking interval of the display panel and generate AC output signal and DC output signal; A driver chip, connected to the timing control chip and connected to the pixel electrode via a data line, is used to output the pulse signal to the pixel electrode based on the AC output signal, and to output the DC signal to the pixel electrode based on the DC output signal.

10. A display device, characterized in that, It includes a backlight device and a display panel as described in any one of claims 1 to 9.

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