Automatic testing method and platform system for computing performance of domain control chip

Abstract

The invention relates to the technical field of vehicle chip testing, and discloses an automatic testing method and platform system for computing performance of a domain control chip, and the platform system comprises a to-be-tested domain control chip system which is used for executing a preset computing task and outputting real-time performance data; the data connection system comprises a power analyzer and a protocol analyzer and is used for acquiring electrical parameters and communication load data; the automatic platform system is used for dynamically scheduling test cases, converging multi-source data and triggering an exception protection mechanism; the test upper computer system is used for configuring a test strategy, generating a visual report and supporting historical data comparison and performance trend analysis; the to-be-tested domain control chip system, the data connection system, the automatic platform system and the test upper computer system are interconnected through physical or communication links to form a closed-loop test architecture. The full-stack closed-loop automatic test can be realized, the test indexes are comprehensive, the test result is reliable, and the test efficiency is relatively high.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of vehicle chip testing, and in particular to a domain control chip computing performance automatic testing method and platform system. BACKGROUND

[0002] With the evolution of automotive electronic architecture towards domain controller centralization, domain control chips need to handle complex computing tasks such as perception fusion and path planning, and their computing power demand is growing exponentially. Traditional testing methods rely heavily on manual script execution and decentralized instrument operation, resulting in long testing cycles and limited scene coverage. Especially in multi-core concurrent load testing, due to the lack of automatic scheduling mechanism, it is difficult to synchronize the collection of key parameters such as computing power, power consumption and temperature, making it difficult to evaluate the real performance of the chip under sudden traffic pressure. The more prominent contradiction is that the test data is scattered in independent devices such as power analyzers and protocol analyzers, and there is a lack of unified timing alignment mechanism, which not only makes it difficult to locate performance bottlenecks (such as distinguishing between insufficient memory bandwidth or cache invalidation problems), but also causes the test results of boundary conditions such as high temperature / high pressure to be disconnected from real driving conditions. The current industry has tried to introduce basic automation tools, but due to the heterogeneity of hardware interfaces and the closedness of software stacks, it has not yet formed a full-process solution covering "instruction injection-environment simulation-data analysis".

[0003] Specifically, the existing testing framework has three faults at the architecture level: first, the testing index system is single, and the mainstream solution still focuses on peak computing power (TOPS) and theoretical energy efficiency ratio (TOPS / W), ignoring real-time indicators such as frame delay and multi-thread throughput, which cannot meet the core needs of millisecond-level response in intelligent driving scenarios; second, the environmental simulation capability is weak, and the manual adjustment of voltage and temperature cannot accurately reproduce the performance fluctuations of the chip under transient conditions such as cold start and sudden acceleration, and there is a lack of coordinated injection mechanism for communication load, resulting in the lack of "chip-bus" cooperative performance verification; third, the data analysis link is fragmented, and the test report relies on manual integration of multi-source data such as power meters and power meters, which cannot establish a correlation model between computing power, power consumption and temperature, and it is also difficult to realize trend analysis of historical version data, greatly restricting the efficiency of chip iteration optimization. These problems cause the existing test results to often deviate from the actual application scenario, becoming a key obstacle to the functional safety certification (such as ISO26262) of domain control chips.

[0004] Existing automation tools suffer from three major flaws at the application level: First, the toolchain integration is loose. Test tools from different vendors (such as Horizon Robotics' hb_perf and NVIDIA's Nsight) rely on independent command-line interfaces and data formats, forcing testers to manually write adaptation scripts, resulting in low cross-platform testing efficiency and increased error rates. Second, the problem of data silos is prominent. For example, electrical parameters collected by power analyzers, bus loads captured by protocol analyzers, and computing power indicators recorded by chip-built-in counters are often stored in heterogeneous databases. Due to the lack of a unified timing alignment mechanism, it is impossible to quickly establish correlations. Third, central scheduling is difficult. Traditional solutions rely on manual triggering of the execution sequence of each tool, making it difficult to dynamically coordinate the collaborative work of peripherals, especially in multi-chip parallel verification scenarios where resource contention is severe. These flaws mean that existing automation solutions can only achieve partial process optimization and cannot achieve full-process automation and full-process traceability.

[0005] To meet the stringent requirements of L3+ autonomous driving on chip computing performance, there is an urgent need to build an automated testing platform that combines depth and breadth. Summary of the Invention

[0006] The present invention aims to provide an automated testing method and platform system for the computing performance of domain controller chips, which can realize full-stack closed-loop automated testing, and has comprehensive test indicators, reliable test results, and high testing efficiency.

[0007] To achieve the above objectives, the present invention provides the following basic solution.

[0008] Option 1 An automated testing platform system for the computing performance of a domain controller chip includes: The domain controller chip system under test is used to execute preset computing tasks and output real-time performance data. It includes a main controller SoC, coprocessor, memory and peripheral interfaces, and has built-in performance counters and temperature sensors. The data connection system connects to the domain controller chip system under test via a high-speed interface and includes a power analyzer and a protocol analyzer for collecting electrical parameters and communication load data. The automated platform system includes a test scheduling engine, data acquisition middleware, and real-time analysis module, which is used to dynamically schedule test cases, aggregate multi-source data, and trigger anomaly protection mechanisms. The host computer system is used to configure test strategies and generate visual reports, supporting historical data comparison and performance trend analysis. The domain controller chip system under test, data connection system, automation platform system, and test host computer system are interconnected through physical or communication links to form a closed-loop test architecture.

[0009] Option 2 A domain control chip computing performance automatic test method, which applies a domain control chip computing performance automatic test platform system as described in scheme one to perform automatic test, comprises the following steps: S1, system installation stage: configure the physical connection of the to-be-tested domain control chip system and the data connection system, deploy the automatic platform system and the test host computer system, and verify the communication link; S2, start debugging stage: initialize the test environment, configure the performance test type, load parameter and environmental condition through the test host computer system, calibrate the sensor data and verify the instruction issuing stability; S3, test execution stage: The automatic platform system dynamically schedules test cases, and injects preset algorithm model reasoning tasks; Real-time collection of computing power, frame delay, power consumption and core utilization rate data, triggering of the protection mechanism through the abnormality detection model; Synchronous generation of computing power-power consumption-temperature three-dimensional performance curve; S4, end stage: automatically terminate the task and generate a structured test report, and archive the original data to the version management system.

[0010] The working principle and advantages of the present application are as follows: The domain control chip computing performance automatic test method and platform system can realize full-stack closed-loop automatic test, and the test index is comprehensive, the test result is reliable, and the test efficiency is high. The key points are as follows: Through the deep cooperation of the to-be-tested domain control chip system, the data connection system, the automatic platform system and the test host computer system, the present application can realize full-process automatic operation from test instruction injection to performance report generation, has high automation degree and high test efficiency. Moreover, the data connection system is connected with the to-be-tested domain control chip system through a high-speed interface, can ensure millisecond-level synchronous collection of electrical parameters and communication load data, solves the problem of data fragmentation caused by device heterogeneity. Secondly, the present application supports systematic simulation of complex working conditions, can establish a closed-loop control integrated with temperature-voltage-communication load to restore the real scene, and can provide quantitative basis for the collaborative optimization of "chip-algorithm-scene". BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 It is a platform system structure schematic diagram of the domain control chip computing performance automatic test method and platform system embodiment one of the present application. Figure 2 It is a method flow schematic diagram of the domain control chip computing performance automatic test method and platform system embodiment one of the present application. Figure 3 It is a computing power-power consumption-temperature three-dimensional performance curve schematic diagram of the domain control chip computing performance automatic test method and platform system embodiment one of the present application. Detailed Implementation

[0012] The following detailed explanation illustrates the specific implementation methods: Example 1 The basic implementation examples are as follows: Figure 1 As shown: An automated testing platform system for the computing performance of a domain controller chip includes a domain controller chip system under test, a data connection system, an automated platform system, and a testing host computer system.

[0013] The domain controller chip system under test, data connection system, automation platform system, and test host computer system are interconnected through physical or communication links to form a closed-loop test architecture.

[0014] Specifically, the domain controller chip system under test is used to execute preset computing tasks and output real-time performance data. It includes a main control SoC, a coprocessor (GPU / NPU), memory, and peripheral interfaces (CAN FD, Ethernet), and has a built-in performance counter (PMC) and temperature sensor. Its hardware carrier can be a development board or a mass-produced module, and its software layer carries an operating system that meets the requirements of the AutoSAR architecture and target perception fusion model.

[0015] The real-time performance data includes computing power, frame latency, power consumption, kernel utilization, and cache hit rate; the injected preset computing tasks include YOLO V5 or Faster RCNN algorithm model inference.

[0016] During testing, the domain controller chip system under test (DDT) receives test commands from the host computer system, performs calculations, and outputs real-time performance data. It also collects micro-indicators such as core utilization and cache hit rate through its built-in performance counter (PMC) and temperature sensor. As the direct object of performance evaluation, the DDT chip system's output data is used to verify whether the chip meets design specifications (such as ISO 26262 functional safety) and provides a basis for adjusting CPU / NPU task allocation and optimizing the architecture.

[0017] The data connection system connects to the domain controller chip system under test via a high-speed interface and includes a power analyzer and a protocol analyzer for collecting electrical parameters and communication load data.

[0018] The high-speed interface of the data connection system includes PCIe or USB4 protocols. The power analyzer monitors the voltage and current of the core / IO / memory power rails in real time, the protocol analyzer analyzes the CAN / Ethernet communication load, and is equipped with signal conditioning circuitry to ensure the accuracy of sensor data.

[0019] The protocol analyzer is used for simulating a real scene communication environment, isolating test deviation caused by power supply ripple, and ensuring data reliability under extreme conditions such as high temperature and high pressure. The protocol analyzer adopts a power analyzer to realize communication environment simulation by providing voltage and closed-loop current loop.

[0020] The automatic platform system comprises a test scheduling engine, a data collection middleware and a real-time analysis module, and is used for dynamically scheduling test cases, converging multi-source data and triggering an abnormal protection mechanism.

[0021] The test scheduling engine of the automatic platform system is realized based on Jenkins, the data collection middleware adopts a ROS2 architecture, the real-time analysis module uses a time series database to store multi-source data aligned at a millisecond level, and supports distributed deployment to cope with large-scale test requirements.

[0022] The data collection middleware identifies a performance inflection point through an abnormal detection model, and dynamically adjusts a chip working mode; and the test scheduling engine is used for analyzing preset test cases, and dynamically configuring chip supply voltage, thread number and computing core number.

[0023] Specifically, the abnormal detection model adopts an isolation forest algorithm, and input features of the abnormal detection model include time series indicators and state indicators. The time series indicators include TOPS (tera operations per second) sliding variance, frame delay (ms) first-order difference and power consumption (W) gradient; and the state indicators include cache hit rate and temperature gradient (BPU core temperature).

[0024] When an abnormal score output by the abnormal detection model is greater than 0.65 and a TOPS difference value of adjacent sampling points is greater than a set threshold (such as 50 TOPS), it is determined that a performance inflection point is reached, and a chip working mode is dynamically adjusted according to a preset strategy library.

[0025] The preset strategy library stores abnormal types and corresponding dynamic adjustment actions. For example, when the detected abnormal type is a cache hit rate < 60%, the corresponding dynamic adjustment action is to reduce CPU frequency and release memory bandwidth; when the detected abnormal type is core temperature > 110℃, the corresponding dynamic adjustment action is to close hyper-threading and migrate computing tasks to an idle core; when the detected abnormal type is voltage fluctuation > ±5%, the corresponding dynamic adjustment action is to lock the supply voltage to a safe value; when the detected abnormal type is TOPS variance > 20%, the corresponding dynamic adjustment action is to inject idle threads to balance the load; when the detected abnormal type is DDR bandwidth utilization rate > 90%, the corresponding dynamic adjustment action is to reduce batch size; and when the detected abnormal type is BPU usage rate sudden drop, the corresponding dynamic adjustment action is to reset the PCIe link and reload the driver.

[0026] The automation platform system is based on a self-developed Alltest system; the Alltest system comprises an intelligent scheduling engine, a real-time control kernel and a multi-source data analysis platform module.

[0027] The intelligent scheduling engine dynamically allocates test tasks to the computing core through a time window priority algorithm (the time window refers to the time constraint for task execution, and the priority is calculated according to the key attributes of the task to ensure that important tasks are processed first); in this embodiment, the weight calculation function is set as: weight = 0.6 x frame delay requirement + 0.3 x power consumption budget + 0.1 x safety level.

[0028] The real-time control kernel is responsible for executing real-time control instructions (such as voltage adjustment and peripheral communication) during the test process, to ensure the accuracy and timeliness of the control action. The real-time control kernel uses a Linux system with a Preempt-RT patch, and realizes instruction decoding and DA conversion through FPGA.

[0029] The multi-source data analysis platform is used to integrate multi-dimensional test data (including aligned power data, chip registers and clock sources), establish a performance correlation model, and finally locate the bottleneck (such as performance short board and fault point) in the test. The establishment of the performance correlation model comprises: establishing a performance correlation through a polynomial regression model and outputting a topology graph with bottleneck positioning marks. Wherein, V = voltage, T = temperature, H = cache hit rate; a, b, c and d are constants.

[0030] The Alltest system optimizes task allocation through the intelligent scheduling engine, guarantees high-precision real-time control through the real-time control kernel, and realizes data correlation and bottleneck positioning through the multi-source data analysis platform, so as to form a complete and high-precision test architecture through the cooperation of the three, which is suitable for scenarios with high requirements for real-time performance, precision and data analysis capability.

[0031] The automation platform system further comprises: a cross-platform tool integration layer, which builds a unified calling interface through Python encapsulation of Shell commands, and is used to realize standardized extraction of original performance data; after the data is extracted through the unified interface, it is converted into a standardized format (such as uniform fields, units and structures), to provide a consistent data basis for subsequent data analysis (such as processing by the data hub module). Moreover, users do not need to pay attention to the differences between underlying platforms, and only need to call the Python interface to perform data extraction operations.

[0032] The data hub module deploys a web-based management program using a front-end and back-end separation architecture. The back-end integrates a MySQL database through a Flask framework. The MySQL database is used as a relational database to store various types of test data (such as power values, timestamps, and device identifiers) in a structured manner, ensuring data persistence and consistency. The front-end uses WebSocket to push real-time multi-source data to the browser interface, eliminating the storage barriers between power data, bus load, and computing power indicators. In traditional testing, different types of data may be scattered across multiple systems (such as local storage of power meters and storage of computing power data on servers), making it difficult to correlate and analyze. This solution centrally stores and uniformly manages these data through the data hub module, supports real-time linkage display, and provides a complete perspective for data analysis.

[0033] The agile scheduling engine is set up at the workstation and is used to dynamically analyze test cases and generate tool execution sequences (such as calling a voltage adjustment tool to set 1.2V, starting a computing power monitoring tool, recording data, and ending the tool). Through a priority queue, the engine coordinates peripheral control instructions and chip tool calls to complete multi-chip compatible testing.

[0034] Through the automated platform system, the testing process can be fully automated, significantly improving efficiency (supporting 7x24 unattended testing) and ensuring consistency and repeatability of testing. Real-time data analysis performed by the real-time analysis module helps quickly locate chip bottlenecks (such as insufficient cache hit rates) and provides quantitative basis for design iteration.

[0035] The test host computer system is used to configure testing strategies and generate visual reports, supporting historical data comparison and performance trend analysis.

[0036] The test host computer system integrates a use case editor, a data visualization tool, and a report generator. Through a GUI, the system configures testing parameters, generates an HTML report containing a computing power-power-temperature three-dimensional performance curve (such as Figure 3 The system also implements a pipeline operation of code submission to report generation in conjunction with a version management system.

[0037] Specifically, the test host computer system communicates with the domain control chip system to be tested through SSH+ADB protocols and uses Python to build a MySQL database to manage testing environment configurations, compatible with multiple manufacturers' domain control chips such as Horizon and Black Sesame.

[0038] When performing performance trend analysis, the test host computer system first calculates key performance parameters of the chip based on real-time performance data, and then generates performance trend analysis results based on the key performance parameters. The key performance parameters include the power consumption ratio of the domain control chip system to be tested. ; ; ; Wherein, WP is the power consumption ratio, TOPS is the total computing power; BPU is the intelligent processor of the domain control chip system to be tested; fps is the frame rate, Mac_count is the calculation amount per frame, ratio is the BPU usage rate, P is the running power of the domain control chip system to be tested, and C is the chip feature related constant.

[0039] The present scheme fills the systematic gap in performance evaluation of automotive-grade chips. Unlike the rough evaluation that only focuses on peak computing power, the performance trend analysis method defined in the present scheme deeply integrates real-time indicators such as frame delay, throughput, and cache hit rate, and combines power consumption ratio algorithms (such as dynamic computing power conversion based on BPU usage rate and frame rate) to complete the correlation analysis of the full-dimensional performance of the chip in a single test. And it can form a visual report content, which can meet the strict requirements of ISO 26262 functional safety certification for performance traceability.

[0040] As shown in Figure 2 , the present embodiment also provides a domain control chip computing performance automatic test method, which applies the above-mentioned domain control chip computing performance automatic test platform system to perform automatic test, including the following steps: S1, system installation stage: configure the physical connection of the domain control chip system to be tested and the data connection system, deploy the automatic platform system and the test host computer system, and verify the communication link.

[0041] Specifically, first, the hardware environment is built, including the physical connection and power supply configuration of the domain control chip system to be tested, the data connection system, etc. Then, the automatic platform system and the test host computer system are deployed, the necessary drivers and CAN / Ethernet communication protocol stack drivers are installed, and the communication link between the systems is verified to be normal. Finally, the wiring harness connection of the host, virtual machine and host computer part is configured, providing a hardware basis for chip performance testing.

[0042] S2, start debugging stage: initialize the test environment, configure the performance test type, load parameter and environment condition through the test host computer system, calibrate the sensor data and verify the stability of the instruction issuing.

[0043] Specifically, based on the existing firmware connection, the domain control chip system to be tested, the automatic platform system and the data connection system are independently tested for basic configuration environment and signal open-loop test, including network communication and chip internal feature signal input and output function test. On the basis of passing the open-loop test, the test host computer system is used to debug each participating part, so as to ensure the closed-loop flow of the test platform signal.

[0044] System initialization and test case configuration are then performed. First, the automation platform system is started, the firmware or operating system of the domain control chip to be tested is loaded, and the temperature sensor data is calibrated through the test host system. Subsequently, the test host system configures the experimental items in the test management interface, including performance test type, batch size and thread number in load parameter, environmental condition voltage, and cycle test number. In the debugging stage, it is verified whether the test instructions can be correctly issued to the chip, and the data return link is ensured to be stable, and necessary parameter adjustment is performed. Only when the system is fault-free, the next step is executed, and when uploading fault information is detected, the test personnel is informed through the early warning module, and the current test is terminated.

[0045] S3, test execution phase: The automation platform system dynamically schedules test cases, and injects preset algorithm model reasoning tasks; Real-time collection of computing power, frame delay, power consumption, and core utilization rate data, triggering of protection mechanism through abnormality detection model; Synchronization of generating computing power-power-temperature three-dimensional performance curve.

[0046] Specifically, the test execution phase is dominated by the automation platform system and based on the self-developed Alltest system.

[0047] The automation platform system dynamically controls the chip working mode (such as switching bin file name), selects the test thread number and execution core number, injects computing tasks (such as YOLO V5 and Faster RCNN algorithm model reasoning), and synchronously collects performance data (running frame number, model reasoning total time, model reasoning average latency, frame rate information). The real-time analysis module triggers the protection mechanism for abnormal events (such as temperature overrun, computing power drop), and records the original data to the database.

[0048] The execution process of the protection mechanism includes: (1) Real-time discovery of abnormalities: dangerous signals are identified by monitoring computing power variance > 20% or temperature > safety threshold; (2) Intelligent decision response: matching layered strategies according to event severity: Level 1 mild abnormality: only record logs, no active intervention; Level 2 moderate risk: execute frequency reduction to preset value and migrate computing tasks to idle core; Level 3 serious fault: trigger forced power-off and start board-level protection, including eFuse fuse; Automatic execution of protection: physical measures or logical measures are executed according to the selected strategy, physical measures include starting cooling devices, logical measures include frequency reduction, task migration, process isolation or chip reset, to achieve loss-limiting target and service protection target; Monitoring recovery state: After verifying that the fluctuation of computing power is less than 5% and the temperature is less than the safety threshold in real time, gradually recover to the normal operation mode.

[0049] The test process supports the parallel execution of repeated scenario use cases, and displays key parameter graphs (computing power-power consumption-temperature) in real time through the test host computer system for real-time monitoring.

[0050] This process continues until the test is completed or the maximum test duration of this test case is reached, and when the system single test is completed or exceeds the set maximum time limit (2 hours), the next step is automatically executed.

[0051] S4, end phase: automatically terminate the task and generate a structured test report, and archive the raw data to the version management system.

[0052] Specifically, after the test is completed, the system automatically terminates all tasks, generates a structured test report containing key indicator statistics, process curves and abnormal logs.

[0053] The report is exported to the test host computer system in a standardized html format, and supports comparison with historical data.

[0054] Finally, clean up the test environment (such as resetting the chip state, turning off the power), archive the raw data to the version management system, and the operator subsequently modifies and optimizes the chip computing performance test parameters according to the test results.

[0055] The domain control chip computing performance automatic test method and platform system provided in this embodiment can realize full-stack closed-loop automatic testing, and has comprehensive test indicators, reliable test results and high test efficiency.

[0056] Embodiment Two The embodiment provides a domain control chip computing performance automatic test method, which is adjusted based on embodiment one.

[0057] The domain control chip computing performance automatic test platform system as described in embodiment one is applied to work condition testing of Horizon-type chips, including the following steps: S1, system installation phase: configure the physical connection of the domain control chip system to be tested and the data connection system, deploy the automatic platform system and the test host computer system, and verify the communication link.

[0058] S2, start debugging phase - system start and connection verification: Enter the host terminal, switch to the OE package directory, start the Docker container, create a new terminal to perform network connectivity testing, confirm that the packet loss rate is less than 0.1%, and then load the pre-audit test case through the Alltest software to initialize the test platform.

[0059] S3, test execution stage: The converted.bin algorithm file is stored in the specified path, and the model inference task is executed to obtain the model inference result. In the model directory, the horizon special tool chain hb_perf is called to perform model performance analysis, generate a performance analysis report, and obtain the performance analysis result.

[0060] Real-time performance data and key parameters are extracted, and the performance constant C is calculated: the Model SubgraphCalculation Load model subgraph calculation load (OPf) parameter information is captured as the calculation performance constant C. The key parameters include: BPU usage ratio, frame rate fps, and running power P.

[0061] The key performance parameters are calculated based on the following formula, i.e. the power consumption ratio of the domain control chip system to be tested: ; .

[0062] S4, end stage: automatically terminate the task and generate a structured test report, and archive the original data to the version management system.

[0063] Example Three The embodiment provides a domain control chip computing performance automatic test method, which is based on the embodiment one and makes the following adjustments.

[0064] A domain control chip computing performance automatic test platform system as described in embodiment one is applied to test the working conditions of black sesame chips, including the following steps: S1, system installation stage: configure the physical connection of the domain control chip system to be tested and the data connection system, deploy the automatic platform system and the test host computer system, and verify the communication link.

[0065] S2, start debugging stage - system start and connection verification: Enter the host terminal and switch to the OE package directory; start the Docker container; create a new terminal to perform network connectivity test and confirm that the packet loss rate is less than 0.1%; then load the pre-audit test cases through the Alltest software to initialize the test platform.

[0066] S3, test execution stage: Configure the training data set, perform model quantization training, enter the model conversion container to complete the ONNX format conversion, and configure the test scene through the Alltest software.

[0067] Extracting black sesame unique parameters: each frame calculation amount Mac_count (by reading the "Mac_count" field to obtain) and analog frame rate fps. And real-time acquisition BPU usage ratio (by obtaining the input and output information of the model, running instructions to obtain the usage ratio of the development board BPU ratio), running power P.

[0068] And based on the following formula to calculate the key performance parameters, namely the power consumption ratio of the domain control chip system to be tested: ; .

[0069] S4, end phase: automatically terminate the task and generate a structured test report, and archive the original data to the version management system.

[0070] The above only describes the embodiments of the present application, and the common knowledge of the specific structure and characteristics in the scheme is not described in detail. The ordinary skilled person in the art knows all the ordinary technical knowledge in the field of the present application before the application date or the priority date, can know all the prior art in the field, and has the ability to apply conventional experimental means before that date. The ordinary skilled person in the art can improve and implement the present scheme based on the disclosure given in this application, and some typical known structures or known methods should not be an obstacle to the implementation of the present application by the ordinary skilled person in the art. It should be pointed out that for those skilled in the art, without departing from the structure of the present application, a number of modifications and improvements can be made, which should be considered as the protection scope of the present application. These will not affect the effect and practicality of the present application.

Claims

1. An automated testing platform system for the computing performance of a domain controller chip, characterized in that, include: The domain controller chip system under test is used to execute preset computing tasks and output real-time performance data. It includes a main controller SoC, coprocessor, memory and peripheral interfaces, and has built-in performance counters and temperature sensors. The data connection system connects to the domain controller chip system under test via a high-speed interface and includes a power analyzer and a protocol analyzer for collecting electrical parameters and communication load data. The automated platform system includes a test scheduling engine, data acquisition middleware, and real-time analysis module, which is used to dynamically schedule test cases, aggregate multi-source data, and trigger anomaly protection mechanisms. The host computer system is used to configure test strategies and generate visual reports, supporting historical data comparison and performance trend analysis. The domain controller chip system under test, data connection system, automation platform system, and test host computer system are interconnected through physical or communication links to form a closed-loop test architecture.

2. The automated testing platform system for the computing performance of a domain controller chip according to claim 1, characterized in that, The automated platform system also includes: The cross-platform tool integration layer uses Python to encapsulate shell commands and build a unified calling interface to achieve standardized extraction of raw performance data. The data hub module adopts a front-end and back-end separation architecture to deploy a web-based management program. The back-end integrates a MySQL database through the Flask framework, while the front-end pushes multi-source data to the browser interface in real time through WebSocket, which is used to eliminate the storage barrier between power data, bus load and computing power indicators. The agile scheduling engine, set up on the workstation, is used to dynamically parse test cases and generate tool execution sequences. It coordinates peripheral control commands and chip tool calls through a priority queue to complete multi-chip compatibility testing.

3. The automated testing platform system for the computing performance of a domain controller chip according to claim 1, characterized in that, The test scheduling engine of the automated platform system is based on Jenkins, the data acquisition middleware adopts the ROS2 architecture, and the real-time analysis module uses a time-series database to store multi-source data aligned to milliseconds and supports distributed deployment.

4. The automated testing platform system for the computing performance of a domain controller chip according to claim 1, characterized in that, The test host computer system integrates a test case editor, data visualization tools, and a report generator. It can configure test parameters through a GUI, generate HTML reports containing three-dimensional performance curves of computing power, power consumption, and temperature, and link with the version management system to realize a pipeline operation from code submission to report generation.

5. The automated testing platform system for the computing performance of a domain controller chip according to claim 1, characterized in that, The real-time performance data includes computing power, frame latency, power consumption, kernel utilization, and cache hit rate; the injected preset computing tasks include YOLO V5 or Faster RCNN algorithm model inference.

6. The automated testing platform system for the computing performance of a domain controller chip according to claim 1, characterized in that, The data acquisition middleware identifies performance inflection points through an anomaly detection model and dynamically adjusts the chip's operating mode; the test scheduling engine is used to parse preset test cases and dynamically configure the chip's power supply voltage, number of threads, and number of computing cores.

7. The automated testing platform system for the computing performance of a domain controller chip according to claim 1, characterized in that, The protocol analyzer is used to simulate the communication environment of real-world scenarios and isolate test deviations caused by power supply ripple. The protocol analyzer uses a power analyzer to simulate the communication environment by providing voltage and closed-loop current circuits.

8. The automated testing platform system for the computing performance of a domain controller chip according to claim 1, characterized in that, The automated platform system operates based on the self-developed Alltest system. The Alltest system includes: an intelligent scheduling engine, a real-time control kernel, and a multi-source data analysis platform module.

9. The automated testing platform system for the computing performance of a domain controller chip according to claim 1, characterized in that, When performing performance trend analysis, the test host computer system first calculates the key performance parameters of the chip based on real-time performance data, and then generates performance trend analysis results based on the key performance parameters. The key performance parameters include the power consumption ratio of the domain controller chip system under test; ； ； ； Where WP is the power consumption ratio, TOPS is the total computing power, BPU is the intelligent processor of the domain controller chip system under test, fps is the frame rate, Mac_count is the computation per frame, ratio is the BPU utilization rate, P is the operating power of the domain controller chip system under test, and C is the chip characteristic correlation constant.

10. An automated testing method for the computing performance of a domain controller chip, characterized in that, The automated testing of a domain controller chip computing performance using the automated testing platform system described in any one of claims 1-9 includes the following steps: S1, System Installation Phase: Configure the physical connection between the domain controller chip system under test and the data connection system, deploy the automated platform system and the host computer system for testing, and verify the communication link; S2, Start-up and debugging phase: Initialize the test environment, configure the performance test type, load parameters and environmental conditions through the test host computer system, calibrate sensor data and verify the stability of command issuance; S3, Test Execution Phase: The automated platform system dynamically schedules test cases and injects pre-set algorithm model inference tasks. Real-time collection of computing power, frame latency, power consumption, and kernel utilization data; triggering protection mechanisms through anomaly detection models. Simultaneously generate three-dimensional performance curves of computing power, power consumption, and temperature; S4, End Phase: Automatically terminates the task and generates a structured test report, archiving the raw data to the version control system.

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