Task scheduling method and device, electronic equipment and storage medium
By allocating tasks based on task priority and status in the CPU core load balancing method, the problem of uneven CPU core load is solved, thereby improving the performance and resource utilization of the central processing unit.
Patent Information
- Application Number
- CN202410627957.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-20
- Publication Date
- 2025-11-21
AI Technical Summary
The uneven workload on each CPU core leads to an uneven CPU core load, affecting the performance and resource utilization of the central processing unit.
By determining whether all CPU cores are idle, the execution priority of the task to be scheduled and the priority of the already scheduled task are obtained. Based on the priority and the amount of task, the task is allocated to the target CPU core to achieve load balancing.
It improves the response speed and overall performance of the central processing unit, optimizes resource utilization, ensures that high-priority tasks are executed quickly, and avoids core overload and idle states.
Smart Images
Figure CN120994319A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of data processing technology, and in particular to a task scheduling method and apparatus, electronic device and storage medium. Background Technology
[0002] During application execution, a large number of tasks are generated. These tasks are scheduled to the Central Processing Unit (CPU) for execution. During execution, tasks need to be randomly scheduled to any of the multiple CPU cores within the CPU. However, since the amount of tasks executed by each CPU core is different, randomly scheduling tasks to any CPU core results in an uneven load across the CPU cores. Summary of the Invention
[0003] This disclosure provides a task scheduling method, apparatus, electronic device, and storage medium. Its main objective is to solve the problem of uneven load distribution across CPU cores caused by randomly scheduling tasks to any CPU core when the workload executed by each CPU core is different.
[0004] According to a first aspect of this disclosure, a task scheduling method is provided, comprising:
[0005] Determine whether all CPU cores are non-idle CPU cores, wherein a non-idle CPU core is any CPU core among all CPU cores that has a scheduled task.
[0006] If it is determined that all the central processing unit cores are non-idle central processing unit cores, the first execution priority of the task to be scheduled is obtained, and the second execution priority of the scheduled task is obtained.
[0007] The task to be scheduled is assigned to a target CPU core, wherein the target CPU core is a non-idle CPU core determined according to the second execution priority and the first execution priority.
[0008] Optionally, before assigning the task to be scheduled to the target central processing unit core, the method further includes:
[0009] Compare the first execution priority with the second execution priority;
[0010] If the second execution priority is lower than the first execution priority, then the non-idle CPU core with the second execution priority is determined as the target CPU core.
[0011] Optionally, after comparing the first execution priority with the second execution priority, the method further includes:
[0012] If the second execution priority is greater than or equal to the first execution priority, then the number of scheduled tasks corresponding to the non-idle central processing unit cores is obtained respectively.
[0013] The non-idle CPU core corresponding to the minimum value among the scheduled tasks is determined as the target CPU core.
[0014] Optionally, after determining whether all CPU cores are non-idle CPU cores, the method further includes:
[0015] If it is determined that there is an idle CPU core among all the CPU cores, the idle CPU core is identified as the target CPU core.
[0016] The task to be scheduled is assigned to the target central processing unit core.
[0017] Optionally, determining the idle CPU core as the target CPU core includes:
[0018] Determine whether the task to be scheduled carries preset identification information;
[0019] If it is determined that the task to be scheduled carries the preset identification information, the CPU core in the idle CPU core that contains the CPU core corresponding to the preset identification information is determined as the target CPU core.
[0020] Optionally, after assigning the task to be scheduled to the target central processing unit core, the method further includes:
[0021] When the target CPU core finishes executing the scheduled task and does not execute a new scheduled task within a preset period, the target CPU core is initialized as the idle CPU core.
[0022] Optionally, after obtaining the first execution priority of the task to be scheduled, the method further includes:
[0023] Obtain the virtual time of the task to be scheduled;
[0024] Based on the pre-established mapping relationship between execution priority and weakening time, find the target weakening time corresponding to the first execution priority;
[0025] The difference between the virtual time and the target reduction time is calculated to obtain the updated virtual time, so that the task to be scheduled can preempt the central processing unit core where the scheduled task is located based on the updated virtual time.
[0026] According to a second aspect of this disclosure, a task scheduling apparatus is provided, comprising:
[0027] The first determining unit is used to determine whether all central processing unit cores are non-idle central processing unit cores, wherein the non-idle central processing unit core is any central processing unit core among all central processing unit cores that has a scheduled task.
[0028] The acquisition unit is used to acquire the first execution priority of the task to be scheduled and the second execution priority of the scheduled task when it is determined that all the central processing unit cores are non-idle central processing unit cores.
[0029] An allocation unit is used to allocate the task to be scheduled to a target CPU core, wherein the target CPU core is a non-idle CPU core determined according to the second execution priority and the first execution priority.
[0030] Optionally, the device further includes:
[0031] The comparison unit is used to compare the first execution priority with the second execution priority before assigning the task to be scheduled to the target central processing unit core;
[0032] The second determining unit is used to determine the non-idle CPU core of the second execution priority as the target CPU core when the second execution priority is less than the first execution priority.
[0033] Optionally, the device further includes:
[0034] The acquisition unit is further configured to, after comparing the first execution priority with the second execution priority, acquire the number of scheduled tasks corresponding to the non-idle central processing unit core when the second execution priority is greater than or equal to the first execution priority;
[0035] The second determining unit is further configured to determine the non-idle CPU core corresponding to the minimum value among the scheduled task quantities as the target CPU core.
[0036] Optionally, the device further includes:
[0037] The second determining unit is further configured to, after determining whether all CPU cores are non-idle CPU cores, determine the idle CPU core as the target CPU core if it is determined that there is an idle CPU core among all CPU cores.
[0038] The allocation unit is further configured to allocate the task to be scheduled to the target central processing unit core.
[0039] Optionally, the second determining unit includes:
[0040] The judgment module is used to determine whether the task to be scheduled carries preset identification information;
[0041] The determination module is used to determine, when it is determined that the task to be scheduled carries the preset identification information, the CPU core in the idle CPU core that contains the CPU core corresponding to the preset identification information as the target CPU core.
[0042] Optionally, the device further includes:
[0043] An initialization unit is configured to initialize the target CPU core as the idle CPU core after the scheduled task is assigned to the target CPU core, provided that the target CPU core has completed executing the scheduled task and has not executed any new scheduled tasks within a preset period.
[0044] Optionally, the device further includes:
[0045] The acquisition unit is further configured to acquire the virtual time of the task to be scheduled after acquiring the first execution priority of the task to be scheduled;
[0046] The lookup unit is used to find the target weakening time corresponding to the first execution priority based on the pre-established mapping relationship between execution priority and weakening time.
[0047] The computing unit is used to calculate the difference between the virtual time and the target weakening time to obtain the updated virtual time, so that the task to be scheduled can preempt the central processing unit core where the scheduled task is located based on the updated virtual time.
[0048] According to a third aspect of this disclosure, an electronic device is provided, comprising:
[0049] At least one processor; and
[0050] A memory communicatively connected to the at least one processor; wherein,
[0051] The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method described in the first aspect above.
[0052] According to a fourth aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are configured to cause the computer to perform the method described in the first aspect above.
[0053] According to a fifth aspect of this disclosure, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the method described in the first aspect above.
[0054] The task scheduling method, apparatus, electronic device, and storage medium disclosed herein determine whether all CPU cores are non-idle CPU cores, wherein a non-idle CPU core is any CPU core among all CPU cores that has a scheduled task; when all CPU cores are determined to be non-idle CPU cores, a first execution priority of the task to be scheduled is obtained, and a second execution priority of the scheduled task is obtained; the task to be scheduled is assigned to a target CPU core, wherein the target CPU core is the non-idle CPU core determined according to the second execution priority and the first execution priority. Compared with related technologies, the embodiments of this disclosure, when all CPU cores are determined to be non-idle CPU cores, assign the task to a non-idle CPU core whose second execution priority is lower than its first execution priority, thereby achieving load balancing of CPU cores by allocating the task to be scheduled based on the state of the CPU cores.
[0055] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description
[0056] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:
[0057] Figure 1 A flowchart illustrating a task scheduling method provided in an embodiment of this disclosure;
[0058] Figure 2 A flowchart illustrating a method for determining a target central processing unit core provided in an embodiment of this disclosure;
[0059] Figure 3 This is a schematic diagram illustrating the execution priority and virtual time of a task provided in an embodiment of this disclosure;
[0060] Figure 4 A schematic diagram illustrating a method for selecting a central processing unit for critical tasks, provided in an embodiment of this disclosure;
[0061] Figure 5 A schematic diagram of the structure of a task scheduling device provided in an embodiment of this disclosure;
[0062] Figure 6 A schematic diagram of the structure of another task scheduling device provided in an embodiment of this disclosure;
[0063] Figure 7 A schematic block diagram of an example electronic device provided for embodiments of this disclosure. Detailed Implementation
[0064] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.
[0065] The following description, with reference to the accompanying drawings, describes a task scheduling method and apparatus, electronic device, and storage medium according to embodiments of the present disclosure.
[0066] Figure 1 This is a flowchart illustrating a task scheduling method provided in an embodiment of the present disclosure.
[0067] like Figure 1 As shown, this method is applied to a processor and includes the following steps:
[0068] Step 101: Determine whether all CPU cores are non-idle CPU cores. A non-idle CPU core is any CPU core among all CPU cores that has a scheduled task.
[0069] Non-idle CPU cores are CPU cores with scheduled tasks, i.e., CPU cores that are currently executing tasks. Scheduled tasks are tasks that have been assigned to a CPU core. Scheduled tasks can be tasks that are currently being executed in a CPU core, or tasks that are waiting to be executed in a CPU core. A CPU can have multiple CPU cores. For example, an eight-core CPU has eight CPU cores. Each CPU core can execute scheduled tasks. However, it should be clarified that this statement is not intended to limit the number of CPU cores to eight; other numbers are also possible.
[0070] In this context, a task is the smallest unit of computation that the operating system can schedule, namely a thread. A task is contained within a process and is the actual unit of operation within the process. Each task has its own independent program counter, register set, and stack space to support its independent execution path. Tasks share the resources of the process, such as memory space and file handles, which makes communication and cooperation between tasks relatively easy. Through multitasking programming, the parallel computing capabilities of multi-core central processing units can be fully utilized to improve the execution efficiency of the program.
[0071] By monitoring in real time whether there are scheduled tasks in each CPU core, it is possible to determine whether there are any idle CPU cores among all CPU cores.
[0072] Determining whether all CPU cores are non-idle CPU cores helps in CPU load balancing, ensuring that tasks are evenly distributed across different CPU cores. This avoids overloading some CPU cores and causing performance degradation, while keeping other CPU cores idle, which helps optimize CPU performance and resource utilization.
[0073] Step 102: If it is determined that all the central processing unit cores are non-idle central processing unit cores, obtain the first execution priority of the task to be scheduled and obtain the second execution priority of the scheduled task.
[0074] Execution priority is the order in which tasks are executed in the central processing unit (CPU) core. When multiple tasks exist in the CPU core at the same time, the task with the higher execution priority is executed first. Each task has a unique corresponding execution priority. The second execution priority is the execution priority of the highest-priority scheduled task among multiple scheduled tasks in a non-idle CPU core.
[0075] To facilitate understanding, an example is provided. Assume that the smaller the execution priority value, the higher the execution priority. In the CPU core, there are two tasks waiting to be executed, namely a and b. Assume that the execution priority of a is 1 and the execution priority of b is 10. Then a will be executed.
[0076] Non-idle CPU cores are CPU cores that are currently executing tasks. If it is determined that there are no idle CPU cores among all CPU cores, a non-core CPU core needs to be selected from the non-idle CPU cores to allocate the scheduled task.
[0077] Based on the first execution priority of the task to be scheduled and the second priority of the already scheduled tasks, a suitable CPU core is selected to execute the task to be scheduled, thereby optimizing the performance and resource utilization of the CPU, ensuring that high-priority tasks can be executed as soon as possible, and at the same time balancing the load of each CPU core as much as possible.
[0078] Step 103: Assign the task to be scheduled to a target CPU core, wherein the target CPU core is a non-idle CPU core determined according to the second execution priority and the first execution priority.
[0079] In order to execute high-priority scheduled tasks as quickly as possible, given that all CPU cores are non-idle CPU cores, the scheduled tasks need to be assigned to target CPU cores where the second execution priority of the scheduled tasks is lower than the first priority of the scheduled tasks. This allows high-priority tasks to be executed faster, thereby improving the CPU's response speed and efficiency.
[0080] To facilitate understanding, an example is provided. Assume that the smaller the execution priority value, the higher the execution priority. The first execution priority of the task to be scheduled, a, is 2. There are two CPU cores, A and B, both of which are non-idle CPU cores. There is a scheduled task b in A, and the second execution priority of b is 1. There is a scheduled task c in B, and the second execution priority of c is 3. Since the first execution priority of a is higher than the second execution priority of c, and the first execution priority of a is lower than the second execution priority of b, a is assigned to B.
[0081] The task scheduling method provided in this disclosure determines whether all CPU cores are non-idle CPU cores, wherein a non-idle CPU core is any CPU core among all CPU cores that has a scheduled task; if all CPU cores are determined to be non-idle CPU cores, a first execution priority of the task to be scheduled is obtained, and a second execution priority of the scheduled task is obtained; the task to be scheduled is assigned to a target CPU core, wherein the target CPU core is the non-idle CPU core determined according to the second execution priority and the first execution priority. Compared with related technologies, the embodiments of this disclosure, when determining that all CPU cores are non-idle CPU cores, assign the task to a non-idle CPU core whose second execution priority is lower than its first execution priority, thereby achieving load balancing of CPU cores by allocating the task to be scheduled based on the state of the CPU cores.
[0082] As a refinement of step 103, before assigning the task to be scheduled to the target CPU core, it is necessary to select a CPU core from all non-idle CPU cores as the target CPU core. This can be achieved in ways that are not limited to the following: Figure 2 As shown, Figure 2 A flowchart illustrating a method for determining a target central processing unit core provided in this disclosure, comprising:
[0083] Step 201: Compare the first execution priority with the second execution priority.
[0084] The execution priority has an execution order. The execution order can be divided according to the execution priority value from small to large, or according to the execution priority value from large to small. This embodiment of the disclosure does not limit the method of dividing the execution priority order.
[0085] The execution priority order defines the rules for comparing execution priorities. By using the preset execution priority order, the first execution priority can be compared with the second execution priority to determine whether there is a second execution priority that is lower than the first execution priority. By considering the execution priority order of tasks, tasks can be scheduled more intelligently, enabling the central processing unit to run more efficiently.
[0086] Step 202: If the second execution priority is less than the first execution priority, then the non-idle CPU core with the second execution priority is determined as the target CPU core.
[0087] To maximize the utilization of CPU resources and ensure that high-priority tasks are processed first, the non-idle CPU core with the second execution priority is identified as the target CPU core. The scheduled tasks are then assigned to the non-idle CPU core that is executing lower-priority tasks. This avoids high-priority tasks waiting for idle CPU cores for a long time, thereby improving the CPU core response speed and overall performance.
[0088] If there are multiple primary target non-idle CPU cores, one primary target non-idle CPU core can be randomly selected from among the multiple primary target non-idle CPU cores for scheduling the task to be scheduled.
[0089] By assigning tasks to be scheduled to the first non-idle CPU core, high-priority tasks can be prevented from waiting for CPU cores for a long time, thereby improving the CPU's response speed and overall performance.
[0090] In practical applications, after comparing the first execution priority with the second execution priority, there may be a situation where the second execution priority is greater than or equal to the first execution priority. This can be achieved in the following way, but is not limited to: if the second execution priority is greater than or equal to the first execution priority, then obtain the number of scheduled tasks corresponding to the non-idle CPU cores respectively; determine the non-idle CPU core corresponding to the minimum value among the scheduled tasks as the target CPU core; wherein, the number of scheduled tasks corresponding to the non-idle CPU core is the sum of the data sizes of all scheduled tasks in the non-idle CPU core. By determining the non-idle CPU core corresponding to the minimum value of the scheduled tasks as the target CPU core, it is helpful to balance the load of each CPU core, avoid overloading some CPU cores, and thus improve the overall performance and stability of the CPU.
[0091] To facilitate understanding, an example is provided. Suppose there are two non-idle CPU cores, A and B. A has one scheduled task a with a data size of 10, so the total number of scheduled tasks in A is 10. B has two scheduled tasks b and c, with b having a data size of 3 and c having a data size of 4, so the total number of scheduled tasks in B is 7. Since the number of scheduled tasks in B is smaller than that in A, the unscheduled task is assigned to B.
[0092] In practical applications, after determining whether all CPU cores are non-idle CPU cores, if there are idle CPU cores among all CPU cores, in order to balance the load of the CPU cores, the tasks to be scheduled need to be allocated to the idle CPU cores. This can be achieved in the following ways, but is not limited to: if it is determined that there are idle CPU cores among all CPU cores, the idle CPU core is identified as the target CPU core; the tasks to be scheduled are allocated to the target CPU core; the tasks to be scheduled are tasks that have not yet been allocated to any CPU core for execution. The number of idle CPU cores among all CPU cores can be one or more. This embodiment of the disclosure does not limit the number of idle CPU cores among all CPU cores.
[0093] If there is only one idle CPU core, the task to be scheduled will be directly assigned to that idle CPU core. If there are multiple idle CPU cores, the task to be scheduled can be randomly assigned to any of the multiple idle CPU cores, or it can be assigned to the idle CPU core with the smallest or largest number according to the numbering order of the idle CPU cores.
[0094] Assigning tasks to idle CPU cores can fully utilize CPU computing resources and improve task execution efficiency and response speed. When idle CPU cores exist, tasks can be directly assigned to them without waiting for other non-idle CPU cores to finish executing their scheduled tasks. This reduces task waiting time and speeds up task execution.
[0095] In practical applications, after determining that there are idle CPU cores among all CPU cores, the task to be scheduled may be a critical task. Critical tasks are very urgent and need to be executed promptly. To enable critical tasks to be executed as quickly as possible, when determining the idle CPU core as the target CPU core, the following methods can be used, but are not limited to: determining whether the task to be scheduled carries preset identification information; a task to be scheduled carrying preset identification information is a critical task, wherein the preset identification information can be a special symbol, and this embodiment does not limit the specific form of the preset identification information; if it is determined that the task to be scheduled carries the preset identification information, the CPU core corresponding to the preset identification information among the idle CPU cores is determined as the target CPU core; by setting the target CPU core, critical tasks can be executed as quickly as possible, improving the execution efficiency of critical task pairs.
[0096] In practical applications, after the scheduled task is assigned to the target CPU core, if no new critical task arrives, to avoid wasting the resources of the target CPU core, it can be implemented in the following way, but not limited to: when the target CPU core has finished executing the scheduled task and the target CPU core has not executed a new scheduled task within a preset period, the target CPU core is initialized as an idle CPU core; wherein, the specific value of the preset period is not limited in this embodiment; by initializing the target CPU core as a normal idle CPU core when the target CPU core has not executed a new scheduled task within the preset period, it is helpful to improve the utilization efficiency of system resources, avoid resource waste, and optimize the task scheduling process.
[0097] In practical applications, after obtaining the first execution priority of the task to be scheduled, the task to be scheduled will preempt the already scheduled task, that is, kick the already scheduled task out of the CPU core and put the task to be scheduled into the CPU core. In order to reduce the occurrence of the already scheduled task being preempted by the task to be scheduled, the following methods can be used, but are not limited to: obtaining the virtual time of the task to be scheduled; the virtual time is a timestamp or counter used to record when the task is created or added to the CPU core. The virtual time is usually not the real time, but a time concept maintained internally by the CPU to measure the waiting time, execution time or other scheduling-related time quantities of the task; according to the pre-established mapping relationship between execution priority and reduction time, find the target reduction time corresponding to the first execution priority; calculate the difference between the virtual time and the target reduction time to obtain the updated virtual time, so that the task to be scheduled can preempt the CPU core where the already scheduled task is located based on the updated virtual time; through a reasonable task scheduling and preemption mechanism, the CPU can effectively utilize CPU resources according to the execution priority and virtual time of the task, thereby improving the performance and response speed of the CPU.
[0098] In one possible implementation of this disclosure, to facilitate a better understanding of task execution priorities and virtual time, such as... Figure 3 As shown, Figure 3This is a schematic diagram illustrating the execution priority and virtual time of a task provided in an embodiment of this disclosure. Assume that the two tasks in Group 1 have the same execution priority, share a 10ms scheduling period, and thus have the same virtual time. Assume that the two tasks in Group 2 have significantly different execution priorities and execution times, but little difference in virtual time, which cannot meet real-time scheduling requirements. Execution time accumulates into virtual time, meaning that a task that executes for a long time, even with a high weight, continues to increase its virtual time, potentially being preempted by other long-dormant tasks. Even if a task has a high weight, it cannot always be allocated the entire time slice within a period, and the allocated time is relatively small.
[0099] By setting a target idle CPU core, all newly added key personnel are placed in the target idle CPU core.
[0100] Avoid scheduling tasks with high execution priority: When selecting CPU cores for critical tasks, avoid CPU cores where scheduled tasks with higher execution priority reside. To better understand CPU core selection for critical tasks, such as... Figure 4 As shown, Figure 4 This is a schematic diagram of a method for selecting a central processing unit for critical tasks, provided in an embodiment of this disclosure.
[0101] In summary, the embodiments disclosed herein can achieve the following effects:
[0102] In this embodiment of the disclosure, when it is determined that all the CPU cores are non-idle CPU cores, the task to be scheduled is assigned to a non-idle CPU core with a second execution priority lower than the first execution priority. This realizes the allocation of tasks to be scheduled according to the state of the CPU cores, thereby achieving load balancing of the CPU cores.
[0103] Corresponding to the task scheduling method described above, this invention also proposes a task scheduling apparatus. Since the apparatus embodiments of this invention correspond to the method embodiments described above, details not disclosed in the apparatus embodiments can be referred to in the method embodiments described above, and will not be repeated here.
[0104] Figure 5 This is a schematic diagram of a task scheduling device provided in an embodiment of the present disclosure. The device is applied to a processor, such as... Figure 5 As shown, it includes:
[0105] The first determining unit 31 is used to determine whether all central processing unit cores are non-idle central processing unit cores, wherein the non-idle central processing unit core is any central processing unit core among all central processing unit cores that has a scheduled task.
[0106] The acquisition unit 32 is used to acquire the first execution priority of the task to be scheduled and the second execution priority of the scheduled task when it is determined that all the central processing unit cores are non-idle central processing unit cores.
[0107] Allocation unit 33 is used to allocate the task to be scheduled to a target CPU core, wherein the target CPU core is the non-idle CPU core determined according to the second execution priority and the first execution priority.
[0108] The task scheduling apparatus provided in this disclosure determines whether all CPU cores are non-idle CPU cores, wherein a non-idle CPU core is any CPU core among all CPU cores that has a scheduled task; if all CPU cores are determined to be non-idle CPU cores, a first execution priority of the task to be scheduled is obtained, and a second execution priority of the scheduled task is obtained; the task to be scheduled is assigned to a target CPU core, wherein the target CPU core is the non-idle CPU core determined according to the second execution priority and the first execution priority. Compared with related technologies, the embodiments of this disclosure, when determining that all CPU cores are non-idle CPU cores, assign the task to a non-idle CPU core whose second execution priority is lower than its first execution priority, thereby achieving load balancing of CPU cores by allocating the task to be scheduled based on the state of the CPU cores.
[0109] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 6 As shown, the device further includes:
[0110] The comparison unit 34 is used to compare the first execution priority with the second execution priority before allocating the task to be scheduled to the target central processing unit core;
[0111] The second determining unit 35 is used to determine the non-idle CPU core of the second execution priority as the target CPU core when the second execution priority is less than the first execution priority.
[0112] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 6 As shown, the device further includes:
[0113] The acquisition unit 32 is further configured to, after comparing the first execution priority with the second execution priority, acquire the number of scheduled tasks corresponding to the non-idle central processing unit core when the second execution priority is greater than or equal to the first execution priority;
[0114] The second determining unit 35 is further configured to determine the non-idle CPU core corresponding to the minimum value among the scheduled task quantities as the target CPU core.
[0115] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 6 As shown, the device further includes:
[0116] The second determining unit 35 is further configured to, after determining whether all central processing unit cores are non-idle central processing unit cores, determine the idle central processing unit core as the target central processing unit core if it is determined that there is an idle central processing unit core among all the central processing unit cores.
[0117] The allocation unit 33 is further configured to allocate the task to be scheduled to the target central processing unit core.
[0118] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 6 As shown, the second determining unit 35 includes:
[0119] The judgment module 351 is used to determine whether the task to be scheduled carries preset identification information after determining that there is an idle central processing unit core among all the central processing unit cores.
[0120] The determining module 352 is used to determine the CPU core corresponding to the preset identification information among the idle CPU cores as the target CPU core when it is determined that the task to be scheduled carries the preset identification information.
[0121] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 6 As shown, the device further includes:
[0122] The initialization unit 36 is configured to initialize the target CPU core as the idle CPU core after the scheduled task is assigned to the target CPU core, provided that the target CPU core has completed executing the scheduled task and has not executed any new scheduled task within a preset period.
[0123] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 6As shown, the device further includes:
[0124] The acquisition unit 32 is further configured to acquire the virtual time of the task to be scheduled after acquiring the first execution priority of the task to be scheduled;
[0125] The lookup unit 37 is used to look up the target weakening time corresponding to the first execution priority according to the pre-established mapping relationship between execution priority and weakening time;
[0126] The calculation unit 38 is used to calculate the difference between the virtual time and the target weakening time to obtain the updated virtual time, so that the task to be scheduled can preempt the central processing unit core where the scheduled task is located based on the updated virtual time.
[0127] It should be noted that the foregoing explanation of the method embodiments also applies to the apparatus of the embodiments of this disclosure, and the principle is the same. Therefore, the embodiments of this disclosure are not limited thereto.
[0128] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.
[0129] Figure 7 A schematic block diagram of an example electronic device 400 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.
[0130] like Figure 7 As shown, device 400 includes a computing unit 401, which can perform various appropriate actions and processes based on a computer program stored in ROM (Read-Only Memory) 402 or a computer program loaded from storage unit 408 into RAM (Random Access Memory) 403. RAM 403 may also store various programs and data required for the operation of device 400. The computing unit 401, ROM 402, and RAM 403 are interconnected via bus 404. I / O (Input / Output) interface 405 is also connected to bus 404.
[0131] Multiple components in device 400 are connected to I / O interface 405, including: input unit 406, such as keyboard, mouse, etc.; output unit 407, such as various types of monitors, speakers, etc.; storage unit 408, such as disk, optical disk, etc.; and communication unit 409, such as network card, modem, wireless transceiver, etc. Communication unit 409 allows device 400 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.
[0132] The computing unit 401 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 401 include, but are not limited to, CPUs (Central Processing Units), GPUs (Graphics Processing Units), various special-purpose AI (Artificial Intelligence) computing chips, various computing units running machine learning model algorithms, DSPs (Digital Signal Processors), and any suitable processor, controller, microcontroller, etc. The computing unit 401 performs the various methods and processes described above, such as task scheduling methods. For example, in some embodiments, the task scheduling method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 408. In some embodiments, part or all of the computer program may be loaded and / or installed on device 400 via ROM 402 and / or communication unit 409. When the computer program is loaded into RAM 403 and executed by the computing unit 401, one or more steps of the methods described above may be performed. Alternatively, in other embodiments, computing unit 401 may be configured by any other suitable means (e.g., by means of firmware) to perform the scheduling method for the aforementioned tasks.
[0133] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, FPGAs (Field Programmable Gate Arrays), ASICs (Application-Specific Integrated Circuits), ASSPs (Application-Specific Standard Products), SOCs (System-on-Chips), CPLDs (Complex Programmable Logic Devices), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.
[0134] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.
[0135] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, RAM, ROM, EPROM (Electrically Programmable Read-Only Memory) or flash memory, optical fiber, CD-ROM (Compact Disc Read-Only Memory), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.
[0136] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (Cathode-Ray Tube) or LCD (Liquid Crystal Display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).
[0137] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include LANs (Local Area Networks), WANs (Wide Area Networks), the Internet, and blockchain networks.
[0138] Computer systems can include clients and servers. Clients and servers are generally geographically separated and typically interact via communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. A server can be a cloud server, also known as a cloud computing server or cloud host, a hosting product within the cloud computing service ecosystem, addressing the shortcomings of traditional physical hosts and VPS (Virtual Private Server, or simply "VPS") services, such as high management difficulty and weak business scalability. Servers can also be servers for distributed systems or servers incorporating blockchain technology.
[0139] It's important to note that artificial intelligence (AI) is the study of enabling computers to simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, and planning). It encompasses both hardware and software technologies. AI hardware technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, and big data processing. AI software technologies primarily include computer vision, speech recognition, natural language processing, machine learning / deep learning, big data processing, and knowledge graph technologies.
[0140] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.
[0141] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.
Claims
1. A task scheduling method, characterized in that, include: Determine whether all CPU cores are non-idle CPU cores, wherein a non-idle CPU core is any CPU core among all CPU cores that has a scheduled task. If it is determined that all the central processing unit cores are non-idle central processing unit cores, the first execution priority of the task to be scheduled is obtained, and the second execution priority of the scheduled task is obtained. The task to be scheduled is assigned to a target CPU core, wherein the target CPU core is a non-idle CPU core determined according to the second execution priority and the first execution priority.
2. The method according to claim 1, characterized in that, Before assigning the scheduled task to the target central processing unit core, the method further includes: Compare the first execution priority with the second execution priority; If the second execution priority is lower than the first execution priority, then the non-idle CPU core with the second execution priority is determined as the target CPU core.
3. The method according to claim 2, characterized in that, After comparing the first execution priority with the second execution priority, the method further includes: If the second execution priority is greater than or equal to the first execution priority, then the number of scheduled tasks corresponding to the non-idle central processing unit cores is obtained respectively. The non-idle CPU core corresponding to the minimum value among the scheduled tasks is determined as the target CPU core.
4. The method according to claim 1, characterized in that, After determining whether all CPU cores are non-idle CPU cores, the method further includes: If it is determined that there is an idle CPU core among all the CPU cores, the idle CPU core is identified as the target CPU core. The task to be scheduled is assigned to the target central processing unit core.
5. The method according to claim 4, characterized in that, The step of identifying the idle CPU core as the target CPU core includes: Determine whether the task to be scheduled carries preset identification information; If it is determined that the task to be scheduled carries the preset identification information, the CPU core in the idle CPU core that contains the CPU core corresponding to the preset identification information is determined as the target CPU core.
6. The method according to claim 5, characterized in that, After assigning the scheduled task to the target central processing unit core, the method further includes: When the target CPU core finishes executing the scheduled task and does not execute a new scheduled task within a preset period, the target CPU core is initialized as the idle CPU core.
7. The method according to claim 1, characterized in that, After obtaining the first execution priority of the task to be scheduled, the method further includes: Obtain the virtual time of the task to be scheduled; Based on the pre-established mapping relationship between execution priority and weakening time, find the target weakening time corresponding to the first execution priority; The difference between the virtual time and the target reduction time is calculated to obtain the updated virtual time, so that the task to be scheduled can preempt the central processing unit core where the scheduled task is located based on the updated virtual time.
8. A task scheduling device, characterized in that, include: The first determining unit is used to determine whether all central processing unit cores are non-idle central processing unit cores, wherein the non-idle central processing unit core is any central processing unit core among all central processing unit cores that has a scheduled task. The acquisition unit is used to acquire the first execution priority of the task to be scheduled and the second execution priority of the scheduled task when it is determined that all the central processing unit cores are non-idle central processing unit cores. An allocation unit is used to allocate the task to be scheduled to a target CPU core, wherein the target CPU core is a non-idle CPU core determined according to the second execution priority and the first execution priority.
9. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-7.
10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-7.
11. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method according to any one of claims 1-7.