Resource access method and electronic equipment

Abstract

The embodiment of the invention is applicable to the technical field of data processing, and provides a resource access method and electronic equipment, the electronic equipment comprises at least two processors and at least one first chip, the at least two processors comprise a first processor and a second processor, and the first processor and the second processor are connected with the first chip respectively. In response to a first request, a first chip obtains first indication information, if the first indication information indicates that the first chip is in an idle state, a processor corresponding to the first request is allowed to access the first chip, and the first request is a request of accessing the first chip by a first processor or a second processor. Under the condition that the at least two processors can access the first chip, the management chip does not need to schedule the sequence of accessing the first chip by the at least two processors, so that the condition that conflicts occur when the at least two processors access the first chip is effectively avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of data processing, and more particularly, to a resource access method and an electronic device. BACKGROUND

[0002] With the continuous development of communication technology, an electronic device can usually include multiple processors. The multiple processors can access a chip to obtain relevant data for data processing, thereby realizing corresponding functions.

[0003] In this case, in order to avoid the conflict situation that multiple processors access the same chip at the same time, the electronic device usually further configures a management chip to arbitrate the order of each processor accessing the same chip through the management chip. However, in some possible cases, the electronic device cannot be configured with the above management chip, which leads to the inability to arbitrate the order of each processor accessing the same chip through the management chip, and further leads to the conflict situation of multiple processors.

[0004] Therefore, how to arbitrate the access of each processor to the same chip in the case that the electronic device includes multiple processors and has no management chip has become a problem to be solved. SUMMARY

[0005] The present application provides a resource access method, which can arbitrate the access of each processor to the same chip in the case that the electronic device includes multiple processors and has no management chip.

[0006] In a first aspect, a resource access method is provided. The method is applied to an electronic device, and the electronic device includes at least two processors, at least one first chip, and at least two processors including a first processor and a second processor. The first processor and the second processor are connected with the first chip respectively. The method includes the following steps:

[0007] In response to a first request, the first chip obtains first indication information. The first request is a request of the first processor or the second processor accessing the first chip, and the first indication information is used to indicate that the first chip is in a working state or an idle state.

[0008] If the first indication information indicates that the first chip is in the idle state, the processor corresponding to the first request is allowed to access the first chip.

[0009] The resource access method provided in the embodiments of the present application is applied to an electronic device, wherein the electronic device comprises at least two processors, at least one first chip, the at least two processors comprise a first processor and a second processor, the first processor and the second processor are connected with the first chip respectively, the first chip acquires first indication information in response to a first request, and if the first indication information indicates that the first chip is in an idle state, a processor corresponding to the first request is allowed to access the first chip, wherein the first request is a request of the first processor or the second processor to access the first chip, and the first indication information is used to indicate that the first chip is in a working state or an idle state. In this way, in the case that the at least two processors can access the first chip, it is not necessary to manage chip scheduling of the order of the at least two processors to access the first chip, and it is only necessary to allow the processor corresponding to the first request to access the first chip in the case that the first chip is determined to be in the idle state, that is, the case that there is no conflict of accessing the first chip, thereby effectively avoiding the case that the at least two processors access the first chip in conflict in the case that there is no management chip scheduling of the order of the at least two processors to access the first chip.

[0010] With reference to the first aspect, in some embodiments of the first aspect, the electronic device comprises a first region and a second region, the first processor and the second processor are arranged in the first region, and the first chip is arranged in the second region. The first processor and the second processor are connected with the first chip through a system power management interface respectively.

[0011] The electronic device can be a folding screen mobile phone, the first region can be a main screen region, the second region can be a sub-screen region, the first processor and the second processor can be arranged in the main screen region or the sub-screen region, and the embodiments of the present application do not limit this. Correspondingly, the first chip can be arranged in the sub-screen region or the main screen region, and the embodiments of the present application do not limit this. In the case that the first processor and the second processor are arranged in the main screen region, the first chip is arranged in the sub-screen region. In the case that the first processor and the second processor are arranged in the sub-screen region, the first chip is arranged in the main screen region.

[0012] With reference to the first aspect, in some embodiments of the first aspect, the first chip comprises a first register, and the acquiring of the first indication information in response to the first request comprises: acquiring a value of the first register in response to the first request; and determining the first indication information according to the value of the first register.

[0013] The first register can be a semi-hardware mutual exclusion semaphore register CH_SEL_CTL.

[0014] In conjunction with the first aspect, in some embodiments of the first aspect, the value of the first register includes a first value and a second value, wherein the first value indicates that the first chip is in an idle state and the second value indicates that the first chip is in an operating state.

[0015] The first value can be 0. When the value of the first register is 0, it indicates that the first chip has not been accessed and is in an idle state.

[0016] The second value can be a non-zero value, such as 1. When the value of the first register is a non-zero value, it indicates that the first chip is being accessed and is in a working state.

[0017] In conjunction with the first aspect, in some embodiments of the first aspect, the method further includes: setting the value of the first register to a first value when the processor corresponding to the first request finishes accessing the first chip.

[0018] The resource access method provided in this application embodiment, when the processor corresponding to the first request finishes accessing the first chip, the first chip is in an idle state. The value of the first register is modified to a first value, so that when the first chip obtains the first indication information based on the first request the next time, it can determine that the first indication information indicates that the first chip is in an idle state based on the value of the first register, allowing the processor corresponding to the first request to access the first chip. In this way, after the processor corresponding to the first request finishes accessing the first chip, the value of the first register indicating the state of the first chip can be modified in time to avoid the situation where subsequent processors cannot access the first chip in time.

[0019] In conjunction with the first aspect, in some embodiments of the first aspect, the method further includes: if the first indication information indicates that the first chip is in a working state, sending a waiting message to the processor corresponding to the first request, and the processor corresponding to the first request periodically sending the first request to the first chip according to a first duration period based on the waiting message.

[0020] For example, after receiving a wait message, the processor can periodically send a first request to the first chip according to a first duration period until the first chip allows the processor to access it.

[0021] For example, after receiving the wait message, the processor can periodically send a first request to the first chip according to a first duration period. If the first chip does not allow the processor to access the first chip, the processor can directly access the first chip after a second duration period.

[0022] In conjunction with the first aspect, in some embodiments of the first aspect, the electronic device is an electronic device employing a foldable screen.

[0023] In conjunction with the first aspect, in some embodiments of the first aspect, at least two processors include a main processor and a coprocessor.

[0024] In conjunction with the first aspect, in some embodiments of the first aspect, the first chip includes a digital-to-analog converter (ADC).

[0025] In conjunction with the first aspect, in some embodiments of the first aspect, the electronic device further includes a temperature sensor, a first chip connected to the temperature sensor, and a first processor or a second processor acquiring sampling data from the temperature sensor by accessing the first chip.

[0026] In a second aspect, a resource access apparatus is provided, including a unit for performing any of the methods in the first aspect. The apparatus may be a server, a terminal device, or a chip within a terminal device. The apparatus may include an input unit and a processing unit.

[0027] When the device is a terminal device, the processing unit may be a processor, and the input unit may be a communication interface; the terminal device may also include a memory for storing computer program code, which, when the processor executes the computer program code stored in the memory, causes the terminal device to perform any of the methods in the first aspect.

[0028] When the device is a chip within a terminal device, the processing unit can be an internal processing unit of the chip, and the input unit can be an output interface, pin, or circuit, etc.; the chip may also include a memory, which can be an internal memory of the chip (e.g., a register, cache, etc.) or an external memory (e.g., a read-only memory, random access memory, etc.); the memory is used to store computer program code, and when the processor executes the computer program code stored in the memory, the chip performs any of the methods in the first aspect.

[0029] In one possible implementation, the memory is used to store computer program code; the processor executes the computer program code stored in the memory, and when the computer program code stored in the memory is executed, the processor is used to execute:

[0030] Thirdly, a computer-readable storage medium is provided, the computer-readable storage medium storing computer program code, which, when executed by a resource access device, causes the resource access device to perform any of the resource access methods in the first aspect.

[0031] Fourthly, a computer program product is provided, the computer program product comprising: computer program code, which, when executed by a resource access device, causes the resource access device to perform any of the apparatus methods in the first aspect.

[0032] The resource access method and electronic device provided in this application are applied to an electronic device, wherein the electronic device includes at least two processors and at least one first chip. The at least two processors include a first processor and a second processor, which are respectively connected to the first chip. In response to a first request, the first chip obtains first indication information. If the first indication information indicates that the first chip is in an idle state, the processor corresponding to the first request is allowed to access the first chip. The first request is a request from either the first processor or the second processor to access the first chip, and the first indication information is used to indicate whether the first chip is in a working state or an idle state. Thus, when at least two processors can access the first chip, there is no need for a management chip to schedule the order in which the at least two processors access the first chip. Access to the first chip is only allowed when it is determined that the first chip is in an idle state, that is, when there is no conflict in accessing the first chip. This effectively avoids the situation where at least two processors access the first chip in the absence of a management chip to schedule the order in which the at least two processors access the first chip. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the structure of an electronic device;

[0034] Figure 2 This is a schematic diagram showing the connection relationship between a main processor, a slave processor, and a first chip.

[0035] Figure 3 This is a schematic diagram showing the connection relationship between a multi-core processor and a first chip;

[0036] Figure 4 This is a schematic diagram showing the connection relationship between a main processor, a slave processor, and a first chip.

[0037] Figure 5 This is a schematic diagram of a hardware system for an electronic device applicable to this application;

[0038] Figure 6 This is a schematic diagram of a software system applicable to an electronic device of this application;

[0039] Figure 7 This is a schematic diagram illustrating an application scenario provided in an embodiment of this application;

[0040] Figure 8 This is a flowchart illustrating a resource access method provided in an embodiment of this application;

[0041] Figure 9 This is a flowchart illustrating another resource access method provided in an embodiment of this application;

[0042] Figure 10 This is a flowchart illustrating another resource access method provided in an embodiment of this application;

[0043] Figure 11 This is a schematic diagram of a resource access device provided in this application;

[0044] Figure 12 This is a schematic diagram of an electronic device for accessing resources provided in this application. Detailed Implementation

[0045] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. In the description of the embodiments of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B; "and / or" in this text is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, in the description of the embodiments of this application, "multiple" refers to two or more than two.

[0046] Hereinafter, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature.

[0047] For ease of understanding, the examples provided are for reference only and are related to the concepts in the embodiments of this application.

[0048] 1. Multi-core processor.

[0049] A multi-core processor, also known as a multi-microprocessor core, incorporates two or more independent central processing units into a single computing component. These independent central processing units, also called processor cores, are the most important components of a CPU; all CPU calculations, command reception / storage, and data processing are performed by the processor cores.

[0050] It should be noted that each processor core in a multi-core processor can independently complete a processing task. Therefore, electronic devices usually manage the individual processor cores in a multi-core processor through a management chip to avoid multiple processing cores accessing a peripheral chip at the same time.

[0051] 2. Main processor.

[0052] The main processor is also known as the application processor (AP). The AP is the main processor in the mobile phone, and the operation of the mobile phone's operating system and applications both rely on the AP.

[0053] 3. Coprocessor (CP).

[0054] The CP is the processor in a mobile phone that assists the AP in its work. It usually handles simple tasks such as virtual reality, image processing, high-fidelity audio (HiFi), high dynamic range imaging (HDR), and driving sensors.

[0055] It should be noted that since the AP and CP are two independent processors, there is usually no chip between the main processor and the coprocessor to manage them. Therefore, the execution order of the main processor and the coprocessor cannot be coordinated, and the main processor and the coprocessor usually perform processing tasks independently.

[0056] In one possible scenario, both processor core 1 and processor core 2 in a multi-core processor need to access an analog-to-digital converter (ADC) to acquire data from sensors connected to the ADC, such as temperature data collected by a temperature sensor. In this case, the electronic device typically requires a management chip to manage the order in which processor core 1 and processor core 2 access the ADC, to avoid timing errors caused by simultaneous access by both processor cores.

[0057] In one possible scenario, both the main processor (AP) and the coprocessor (CP) need to access an analog-to-digital converter (ADC) to acquire data from a sensor connected to the ADC, such as temperature data collected by a temperature sensor. In this case, the electronic device typically requires a management chip to manage the order in which the main processor and coprocessor access the ADC, to avoid timing errors caused by simultaneous access to the ADC by both.

[0058] With the continuous development of communication technology, foldable screen phones have become a widely used new type of mobile phone. Foldable screen phones typically consist of two display areas connected by a hinge. For example, ... Figure 1As shown, the foldable phone 100 includes a main screen area, a secondary screen area, and a hinge 1A connecting the main screen area and the secondary screen area. A motherboard A1 can be located on the main screen area, and a secondary motherboard B1 can be located on the secondary screen area. Understandably, due to the limitations of the width and thickness of the hinge 1A, the wiring between the motherboard A1 and the secondary motherboard B1 is also limited. For example, there is an upper limit to the number of wiring between the motherboard A1 and the secondary motherboard B1.

[0059] In one possible scenario, both the main processor (AP) and the coprocessor (CP) located in the main screen area need to read the first temperature data from the temperature sensor 1 located in the secondary screen area, such as... Figure 2 As shown. Since the data collected by temperature sensor 1 is usually analog signal data, when temperature sensor 1 sends the first temperature data to the main processor AP or from the processor CP, it usually needs to be converted into second temperature data (digital data) by the analog-to-digital sensor ADC before being sent to the main processor AP or from the processor CP, so that the main processor AP or from the processor CP can process the second temperature data correctly. Typically, the analog-to-digital sensor ADC is housed in a single chip, such as the PM7550B. The chip containing the analog-to-digital sensor ADC also includes multiple channels for receiving signals, such as... Figure 2 Channels -1 to -N are shown in the diagram. These channels can be used to receive data from external sensors. For example, channel -1 in the chip housing the analog-to-digital sensor (ADC) can receive the first temperature data sent by temperature sensor 1. Then, channel -1 sends the first temperature data to the ADC. After receiving the first temperature data, the ADC can convert it into digital data, i.e., the second temperature data. It should be noted that the chip housing the ADC needs to interact with the processor via the System Power Management Interface (SPMI). A management chip is also connected to the SPMI to schedule the data interaction between the ADC and the processor. Figure 2 As shown, the ADC interacts with the master processor AP via SPMI-0, or with the slave processor CP via SPMI-0. Simultaneously, the management chip schedules the data interaction sequence between the ADC and the master and slave processors CP. It can be understood that SPMI controller 1 within the ADC chip interacts with the management chip via SPMI-0; similarly, the management chip can also interact with the master processor AP or slave processor CP via SPMI controller 2.

[0060] In one possible scenario, both processor core 1 and processor core 2 in the processor located in the main screen area need to read the first temperature data from temperature sensor 1 located in the secondary screen area, such as... Figure 3 As shown. With Figure 2 Similar to how the main processor AP and coprocessor CP read the first temperature data from temperature sensor 1 located in the secondary screen area, processor core 1 and processor core 2 also need to convert the first temperature data (analog data) from the analog-to-digital sensor ADC into second temperature data (digital data). Therefore, processor core 1, processor core 2, and temperature sensor 1 can also use a similar communication mechanism. Figure 2 The ADC and management chip connections shown are as follows: Figure 3 As shown, it will not be elaborated further here.

[0061] However, with the continuous development of electronic devices, the number of temperature sensors installed on these devices will also increase. For example, ... Figure 4 As shown, there are N3 temperature sensors in the secondary screen area, namely temperature sensor 1, temperature sensor 2... temperature sensor N3. However, the number of channels of the chip used for digital-to-analog conversion in the main screen area is limited, and it is not possible to provide a channel for each temperature sensor. In this case, the electronic device can also set up a first chip for digital-to-analog conversion in the secondary screen area, such as PM7550B, and use the analog-to-digital sensor ADC of the first chip in the secondary screen area to convert the first temperature data (analog data) into second temperature data (digital data). Since the first chip needs to interact with the processor through SPMI, for example, Figure 4 The SPMI-1 shown above requires a management chip to be connected to it. The management chip schedules the execution order of the processors or processor cores connected to the first chip. However, due to the limitations of the width and thickness of the hinge 1A connecting the main screen area and the secondary screen area, there is an upper limit to the number of traces on the SPMI-1 that cross the main screen area and the secondary screen area. Usually, it is not possible to leave a single trace to connect to the management chip. This will result in no management chip scheduling the data interaction between the first chip in the secondary screen area and the main processor AP and coprocessor CP, which will lead to access conflicts when the main processor AP and coprocessor CP access the first chip to obtain the corresponding data.

[0062] In view of this, the resource access method provided in this application embodiment is applied to an electronic device, wherein the electronic device includes at least two processors and at least one first chip. The at least two processors include a first processor and a second processor, which are respectively connected to the first chip. In response to a first request, the first chip obtains first indication information. If the first indication information indicates that the first chip is in an idle state, the processor corresponding to the first request is allowed to access the first chip. The first request is a request from either the first processor or the second processor to access the first chip, and the first indication information is used to indicate whether the first chip is in a working state or an idle state. Thus, when at least two processors can access the first chip, there is no need for a management chip to schedule the order in which the at least two processors access the first chip. Access to the first chip is only allowed when it is determined that the first chip is in an idle state, that is, when there is no conflict in accessing the first chip. This effectively avoids the situation where at least two processors access the first chip in the absence of a management chip to schedule the order in which the at least two processors access the first chip.

[0063] The resource access method provided in this application can be applied to electronic devices. Optionally, the electronic device includes a terminal device, which may also be referred to as a terminal, user equipment (UE), mobile station (MS), mobile terminal (MT), etc. The terminal device can be a mobile phone, smart TV, wearable device, tablet computer, computer with wireless transceiver function, virtual reality (VR) terminal device, augmented reality (AR) terminal device, wireless terminal in industrial control, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, etc. The embodiments of this application do not limit the specific technology or device form used in the terminal device.

[0064] For example, Figure 5A schematic diagram of the structure of electronic device 100 is shown. Electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, antenna 1, antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, a headphone jack 170D, a sensor module 180, buttons 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, a barometric pressure sensor 180C, a magnetic sensor 180D, an accelerometer sensor 180E, a distance sensor 180F, a proximity sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc.

[0065] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0066] Processor 110 may include one or more processing units, such as: application processor (AP), modem processor, graphics processing unit (GPU), image signal processor (ISP), controller, memory, video codec, digital signal processor (DSP), baseband processor, and / or neural network processing unit (NPU), etc. Different processing units may be independent devices or integrated into one or more processors. These processing units may also be referred to as processor cores.

[0067] In some embodiments, the processor of an electronic device may include multiple processor cores, each of which can independently complete a processing task.

[0068] The processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. This memory can store instructions or data that the processor 110 has just used or that are used repeatedly. If the processor 110 needs to use the instruction or data again, it can retrieve it directly from the memory. This avoids repeated accesses, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0069] In some embodiments, an electronic device may include multiple processors, such as a main processor (AP) and a slave processor (CP). The main processor (AP) is the primary processor in the phone, responsible for the operation of the operating system and applications. The CP is a processor that assists the AP, typically handling simple tasks such as virtual reality, image processing, high-fidelity audio, high dynamic range imaging, and driving sensors.

[0070] In some embodiments, the processor 110 may include one or more interfaces. Interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0071] The I2C interface is a bidirectional synchronous serial bus, including a serial data line (SDA) and a serial clock line (SCL). In some embodiments, the processor 110 may include multiple I2C buses. The processor 110 can couple to the touch sensor 180K, charger, flash, camera 193, etc., through different I2C bus interfaces. For example, the processor 110 can couple to the touch sensor 180K through the I2C interface, enabling the processor 110 and the touch sensor 180K to communicate through the I2C bus interface, realizing the touch function of the electronic device 100. For example, the PM7550B chip can be connected to a temperature sensor through the I2C bus interface, and the analog-to-digital converter (ADC) in the PM7550B chip converts the analog voltage signal collected by the temperature sensor into a digital signal.

[0072] It is understood that the interface connection relationships between the modules illustrated in the embodiments of this application are merely illustrative and do not constitute a structural limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may also employ different interface connection methods or combinations of multiple interface connection methods as described in the above embodiments.

[0073] The wireless communication function of electronic device 100 can be realized through antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, modem processor and baseband processor, etc.

[0074] Electronic device 100 implements display functions through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing, connected to the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations and for graphics rendering. Processor 110 may include one or more GPUs, which execute program instructions to generate or modify display information.

[0075] Display screen 194 is used to display images, videos, etc. Display screen 194 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a miniature LED, a microLED, a quantum dot light-emitting diode (QLED), etc. In some embodiments, electronic device 100 may include one or N displays 194, where N is a positive integer greater than 1. For example, a foldable phone may include two displays or three displays.

[0076] Electronic device 100 can perform shooting functions through ISP, camera 193, video codec, GPU, display 194 and application processor.

[0077] Electronic device 100 can implement audio functions, such as music playback and recording, through audio module 170, speaker 170A, receiver 170B, microphone 170C, headphone jack 170D, and application processor.

[0078] Temperature sensor 180J is used to detect temperature. In some embodiments, electronic device 100 uses the temperature detected by temperature sensor 180J to execute a temperature handling strategy. For example, when the temperature reported by temperature sensor 180J exceeds a threshold, electronic device 100 performs thermal protection by reducing the performance of a processor located near temperature sensor 180J to reduce power consumption. In other embodiments, when the temperature is below another threshold, electronic device 100 heats battery 142 to prevent abnormal shutdown of electronic device 100 due to low temperature. In still other embodiments, when the temperature is below yet another threshold, electronic device 100 boosts the output voltage of battery 142 to prevent abnormal shutdown due to low temperature.

[0079] It is understandable that electronic devices may include multiple temperature sensors 180J. The electronic device can obtain the temperature of a corresponding area by using temperature sensors 180J positioned in different areas.

[0080] It should be noted that any electronic device mentioned in the embodiments of this application may include more or fewer modules in electronic device 100.

[0081] The software system of electronic device 100 can adopt a layered architecture, event-driven architecture, microkernel architecture, microservice architecture, or cloud architecture. This application embodiment uses the layered architecture Android system as an example to exemplify the software structure of electronic device 100.

[0082] Figure 6 This is a software structure block diagram of the electronic device 100 according to an embodiment of this application.

[0083] The layered architecture of the electronic device 100 divides the software into several layers, each with a clear role and division of labor. Layers communicate with each other through software interfaces. In some embodiments, the Android system is divided into four layers, from top to bottom: the application layer, the application framework layer, the Android runtime and system libraries, and the kernel layer.

[0084] The application layer can include a series of application packages.

[0085] like Figure 6 As shown, the application package may include applications such as camera, gallery, calendar, call, map, navigation, WLAN, Bluetooth, music, video, and SMS.

[0086] The application framework layer provides application programming interfaces (APIs) and a programming framework for applications in the application layer. The application framework layer includes some predefined functions.

[0087] like Figure 6 As shown, the application framework layer may include a window manager, content provider, view system, phone manager, resource manager, notification manager, etc.

[0088] The Android Runtime consists of core libraries and a virtual machine. The Android runtime is responsible for the scheduling and management of the Android system.

[0089] The core library consists of two parts: one part is the functionalities that need to be called by the Java language, and the other part is the Android core library.

[0090] The application layer and application framework layer run in a virtual machine. The virtual machine executes the Java files of the application layer and application framework layer as binary files. The virtual machine is used to perform functions such as object lifecycle management, stack management, thread management, security and exception management, and garbage collection.

[0091] System libraries can include multiple functional modules. For example: surface manager, media libraries, 3D graphics processing libraries (e.g., OpenGL ES), 2D graphics engines (e.g., SGL), etc.

[0092] The kernel layer is the layer between hardware and software. At a minimum, the kernel layer includes display drivers, camera drivers, audio drivers, ADC drivers, etc. The hardware layer may include analog-to-digital converters (ADCs) and temperature sensors.

[0093] Among them, the ADC driver is used to drive the ADC to convert analog data into digital data. For example, the ADC driver is used to drive the ADC to convert the first temperature data (analog data) collected by the temperature sensor into the second temperature data (digital data).

[0094] The temperature sensor in the hardware layer can be used to collect temperature data in the area where the sensor is located. It should be noted that the temperature data collected by the temperature sensor is usually analog data, which needs to be converted into digital data by the ADC in the hardware layer.

[0095] It is understandable that electronic devices can include multiple processors, such as a main processor (AP) and slave processors (CP). Typically, the main processor (AP) is the primary processor in a mobile phone, and the operation of the operating system and applications relies on it. Therefore, the Android system runs on the main processor (AP). That is to say, the application layer, application framework layer, Android runtime and system libraries, and kernel layer are the software structure layers within the main processor (AP).

[0096] The software framework of the coprocessor CP may include a Sensor Hub layer, which may include a temperature management module. The temperature management module functions similarly to the ADC driver, and can be used to drive the ADC to convert analog data into digital data. For example, the temperature management module can be used to drive the ADC to convert the first temperature data (analog data) collected by the temperature sensor into the second temperature data (digital data).

[0097] It should be noted that the electronic device mentioned in the embodiments of this application may include more or fewer modules of the above-mentioned electronic device.

[0098] The application scenarios provided by the embodiments of this application are described below with reference to the accompanying drawings.

[0099] Figure 7 This is a schematic diagram illustrating the connection relationship between a processor and a temperature sensor in an electronic device that applies the resource access method provided in the embodiments of this application. Figure 7As shown, when the main processor AP or coprocessor CP located in the main screen area needs to read data from the temperature sensor 1 located in the secondary screen area, the temperature sensor 1 first sends the collected first temperature data (analog data) to the first chip used for analog-to-digital conversion, such as PM7550B. The first chip includes multiple data channels, an analog-to-digital converter (ADC), and an SPMI controller-2. Specifically, the temperature sensor 1 can send the collected first temperature data to the ADC through channel-1. Upon receiving the first temperature data, the ADC, based on the instruction from the main processor AP or coprocessor CP, converts the first temperature data (analog data) into second temperature data (digital data). Then, the ADC sends the second temperature data to the SPMI controller-2 in the first chip, so that the SPMI controller-2 can transmit the second temperature data to the SPMI controller-1 located in the main screen area via SPMI. The SPMI controller-1 in the main screen area then sends the second temperature data to the corresponding main processor AP or coprocessor CP.

[0100] It is understood that the electronic device using the resource access method provided in the embodiments of this application may also include only one multi-core processor, in which at least two processor cores can simultaneously access the temperature sensor 1 to read temperature data. The embodiments of this application do not impose any restrictions on this.

[0101] It is understood that electronic devices using the resource access method provided in the embodiments of this application may include multiple temperature sensors. Figure 7 The temperature sensor shown is just one example. Various sensors can be used with... Figure 7 A similar connection method is used to connect to the processor.

[0102] It should be understood that the above are illustrative examples of application scenarios and do not limit the application scenarios of this application in any way.

[0103] The following is combined Figure 8 to Figure 10 The resource access method provided in the embodiments of this application will be described in detail.

[0104] The resource access method provided in this application can be applied to electronic devices. In one possible scenario, the electronic device may include at least two processors and at least one first chip. The at least two processors include a first processor and a second processor, which are respectively connected to the first chip. In another possible scenario, the resource access method provided in this application can also be applied to electronic devices including multi-core processors, wherein the multi-core processor includes at least two processor cores, which are respectively connected to the first chip. Optionally, the electronic device is an electronic device using a foldable screen, such as a foldable screen mobile phone.

[0105] The following explanation uses an electronic device that includes at least two processors as an example. Figure 8 This is a flowchart illustrating a resource access method provided in an embodiment of this application, such as... Figure 8 As shown, the method includes:

[0106] S101. In response to the first request, the first chip obtains the first indication information. The first request is a request for the first chip to be accessed by the first processor or the second processor. The first indication information is used to indicate whether the first chip is in a working state or an idle state.

[0107] At least two processors may include a main processor (AP) and a coprocessor (CP). Taking the first processor as the main processor (AP) and the second processor as the coprocessor (CP) as an example, the connection methods between the first processor and the second processor and the first chip can be as follows: Figure 7 As shown. The first chip can be used to convert analog data collected by the temperature sensor into digital data. For example, the first chip can be as follows: Figure 7 As shown, this includes an SPMI controller, an ADC, and multiple channels. Any one of the multiple channels can be used to receive first temperature data (analog data) sent by a temperature sensor. The ADC can be used to convert the first temperature data (analog data) into second temperature data (digital data). The SPMI controller can be used to send data to the processor via SPMI. It is understood that the first chip can also be an ADC, and this embodiment of the application does not limit this.

[0108] The first request can refer to a request from the processor to access the first chip. The first request can be sent to the first chip by either the main processor (AP) or the coprocessor (CP). When the first request is sent by the main processor (AP), it instructs the AP to request access to the first chip; when the first request is sent by the coprocessor (CP), it instructs the CP to request access to the first chip. It is understood that, in some possible cases, the first request may also carry processor identification information to indicate that the first request was sent to the first chip by the processor indicated by the identification information.

[0109] When the first chip receives the first request, the first chip can obtain first indication information indicating whether the first chip is in a working state. The first indication information can be a value stored in a register of the first chip, or it can be the value of a parameter indicating the working state of the first chip; this embodiment does not impose any limitations on this.

[0110] S102. If the first indication information indicates that the first chip is in an idle state, the processor corresponding to the first request is allowed to access the first chip.

[0111] As can be seen from the description in S101, the first indication information may be a value stored in a register in the first chip, or it may be the value of a parameter indicating the working state of the first chip. This application embodiment does not limit this.

[0112] If the first indication is a value stored in a register of the first chip, and the value stored in the register of the first chip indicates that the first chip is in an idle state, then the first chip allows the processor corresponding to the first request to access the first chip; if the value stored in the register of the first chip indicates that the first chip is in an active state, then the first chip can send a message to the processor corresponding to the first request instructing the processor to wait to access the first chip, so that the processor temporarily does not access the first chip and is in a state of waiting to access the first chip.

[0113] When the first indication information is the value of a parameter indicating the working state of the first chip, the first chip can read the value of the parameter in response to the first request. If the value of the parameter indicating the working state of the first chip indicates that the first chip is in an idle state, the first chip allows the processor corresponding to the first request to access the first chip. If the value stored in a register of the first chip indicates that the first chip is in a working state, the first chip can send information to the processor corresponding to the first request instructing the processor to wait to access the first chip, so that the processor temporarily does not access the first chip and is in a state of waiting to access the first chip.

[0114] It should be understood that the first chip being in an idle state means that no processor is currently accessing the first chip, and the first chip can receive access from the processor without any access conflict. The first chip being in an active state means that a processor is currently accessing the first chip; if the first chip receives access from the processor at this time, an access conflict may occur.

[0115] The following explanation uses the example of the main processor AP (first processor) requesting access to the first chip.

[0116] When the main processor AP needs to acquire temperature data from the temperature sensor, it sends a first request to the SPMI controller-2 in the first chip via SPMI controller-1 to access the first chip. The first chip responds to the first request by acquiring first indication information indicating its operating status. It can be understood that since the first request is sent when the main processor AP needs to acquire temperature data from the temperature sensor, it actually requests access to the ADC in the first chip to acquire the first temperature data collected by the temperature sensor-1. In this case, the first indication information can indicate the operating status of the ADC in the first chip. If the first indication information indicates that the ADC is in an idle state, it can return information indicating that the ADC is in an idle state to the main processor AP. Based on this information, the main processor AP accesses the ADC to acquire second temperature data, which is the second temperature data obtained after analog-to-digital conversion of the first temperature data collected by the temperature sensor-1. If the first indication information indicates that the ADC is in a working state, such as when the ADC is being accessed by the coprocessor CP, then the main processor AP can return information indicating that the ADC is in a working state. Based on the information indicating that the ADC is in a working state, the main processor AP will temporarily not access the first chip. At this time, the main processor AP can also periodically send the first request to the first chip according to a preset time period until the first chip receives the first indication information indicating that the first chip is in an idle state.

[0117] The resource access method provided in this application is applied to an electronic device, wherein the electronic device includes at least two processors and at least one first chip. The at least two processors include a first processor and a second processor, which are respectively connected to the first chip. In response to a first request, the first chip obtains first indication information. If the first indication information indicates that the first chip is in an idle state, the processor corresponding to the first request is allowed to access the first chip. The first request is a request from either the first processor or the second processor to access the first chip, and the first indication information is used to indicate whether the first chip is in a working state or an idle state. Thus, when at least two processors can access the first chip, there is no need for a management chip to schedule the order in which the at least two processors access the first chip. Access to the first chip is only allowed when it is determined that the first chip is in an idle state, that is, when there is no conflict in accessing the first chip. This effectively avoids the situation where at least two processors access the first chip in a conflict when there is no management chip to schedule the order in which the at least two processors access the first chip.

[0118] In one embodiment, the above-described resource access method can be applied to an electronic device as shown in Figure 7. Figure 7As shown, the electronic device includes a main screen area and a secondary screen area. The main screen area can be equivalent to the first area, and the secondary screen area can be equivalent to the second area. The first area and the second area can be connected by a hinge. A first processor and a second processor are located in the first area, and a first chip is located in the second area. The first processor and the second processor are respectively connected to the first chip through the system power management interface SPMI.

[0119] Since the first and second processors are located in the first region, and the first chip is located in the second region, and the first and second regions are connected by a hinge, the SPMI connecting the first processor and the first chip must pass through the hinge. Similarly, the SPMI connecting the second processor and the first chip must also pass through the hinge. In this case, the number of SPMI connections is limited by the width and thickness of the hinge, and there is an upper limit. Therefore, it is impossible to retain the connections of the management chip, resulting in the electronic device not having a management chip to schedule the order in which at least two processors access the first chip. In this case, the resource access method provided in this application embodiment obtains first indication information indicating whether the first chip is in a working state or an idle state before the processor accesses the first chip. When the first chip is in an idle state, the processor currently sending the first request is allowed to access the first chip, thus avoiding conflicts in accessing the first chip.

[0120] In one embodiment, the first indication information may refer to a value stored in a register of the first chip. When the first chip receives a first request, it can read the value stored in the register to obtain the first indication information, thereby determining whether to allow the processor corresponding to the first request to access the first chip. The following describes... Figure 9 The embodiments shown will be described in detail.

[0121] Figure 9 This is a flowchart illustrating another resource access method provided in an embodiment of this application. This method can be applied to an electronic device. In one possible scenario, the electronic device may include at least two processors and at least one first chip. The at least two processors include a first processor and a second processor, which are respectively connected to the first chip. In another possible scenario, the resource access method provided in this application can also be applied to an electronic device including a multi-core processor, wherein the multi-core processor includes at least two processor cores, and the at least two processor cores are respectively connected to the first chip. The following description uses an electronic device including at least two processors as an example.

[0122] The method includes:

[0123] S201. In response to the first request, the first chip obtains the value of the first register.

[0124] Taking the PM7550B chip as an example, the first register can refer to the semi-hardware mutex semaphore register CH_SEL_CTL.

[0125] The first request can be sent to the first chip by the main processor (AP) or the coprocessor (CP); this embodiment does not limit this. The first chip can read the value stored in the first register and use the read value as the value of the first register.

[0126] S202. Determine the first indication information based on the value of the first register.

[0127] The first chip can determine the first indication information based on the correspondence between the value of the first register and the state of the first chip.

[0128] The first chip being in an active state can mean that it is being accessed by the main processor (AP) or the coprocessor (CP), or that it is being accessed by any processor core in the processor. The first chip being in an idle state can mean that it is not being accessed by the main processor (AP) or the coprocessor (CP), or that it is not being accessed by any processor core in the processor.

[0129] Optionally, the value of the first register includes a first value and a second value, where the first value indicates that the first chip is in an idle state and the second value indicates that the first chip is in a working state.

[0130] For example, the first value can be 0. When the value of the first register is 0, it indicates that the first chip is not accessed and is in an idle state.

[0131] For example, the second value can be a non-zero value, such as 1. When the value of the first register is non-zero, it indicates that the first chip is being accessed and is in a working state.

[0132] It should be noted that the first value of 0 and the second value of 1 are just examples and do not constitute a limitation on the specific values ​​of the first and second values.

[0133] S203. If the first indication information indicates that the first chip is in an idle state, the processor corresponding to the first request is allowed to access the first chip.

[0134] When the first chip is in an idle state, it is not accessed by any processor. Therefore, allowing the processor corresponding to the first request to access the first chip at this time will not result in an access conflict caused by at least two processors accessing the first chip simultaneously. Thus, when the first indication indicates that the first chip is in an idle state, the processor corresponding to the first request is allowed to access the first chip.

[0135] It should be noted that the processor corresponding to the first request can be the processor that sent the first request to the first chip. For example, if the main processor AP sends the first request to the first chip, then the processor corresponding to the first request is the main processor AP. As another example, if the coprocessor CP sends the first request to the first chip, then the processor corresponding to the first request is the coprocessor CP. In some possible cases, the first request is sent to the first chip by a processor core within the processor; in this case, the processor corresponding to the first request can be the processor core that sent the first request. For instance, if the first request is sent to the first chip by processor core 1 within the processor, then the processor corresponding to the first request can refer to processor core 1 within the processor.

[0136] Understandably, when the processor corresponding to the first request accesses the first chip, the first chip can modify the value of its first register to a second value. This allows the first chip to determine its operational state based on the value of its first register if other processors request access to it, thus preventing access conflicts caused by multiple processors accessing the first chip simultaneously.

[0137] S204. When the processor corresponding to the first request finishes accessing the first chip, set the value of the first register to the first value.

[0138] Taking the processor corresponding to the first request as the main processor AP as an example, when the main processor AP finishes accessing the first chip, that is, after the current moment, the main processor AP will no longer access the first chip. At this time, the main processor AP can notify the first chip to modify the value of the first register to the first value. In this way, when the first chip obtains the first indication information based on the first request again, it can determine that the first indication information indicates that the first chip is in an idle state based on the value of the first register being the first value.

[0139] The resource access method provided in this application embodiment, when the processor corresponding to the first request finishes accessing the first chip, the first chip is in an idle state. The value of the first register is modified to a first value, so that when the first chip obtains the first indication information based on the first request the next time, it can determine that the first indication information indicates that the first chip is in an idle state based on the value of the first register, allowing the processor corresponding to the first request to access the first chip. In this way, after the processor corresponding to the first request finishes accessing the first chip, the value of the first register indicating the state of the first chip can be modified in time to avoid the situation where subsequent processors cannot access the first chip in time.

[0140] S205. If the first indication information indicates that the first chip is in a working state, a waiting message is sent to the processor corresponding to the first request. Based on the waiting message, the processor corresponding to the first request periodically sends the first request to the first chip according to the first duration period.

[0141] If the first register takes the second value, the first indication information indicates that the first chip is in a working state. That is to say, at the current moment, the first chip is in a state of being accessed by the processor. In this case, the first chip can send a wait message to the processor corresponding to the first request. After receiving the wait message, the processor can periodically send the first request to the first chip according to the first duration period.

[0142] For example, after receiving a wait message, the processor can periodically send a first request to the first chip according to a first duration period until the first chip allows the processor to access it.

[0143] For example, after receiving the wait message, the processor can periodically send a first request to the first chip according to a first duration period. If the first chip does not allow the processor to access the first chip, the processor can directly access the first chip after a second duration period.

[0144] Optionally, the electronic device also includes a temperature sensor. A first chip is connected to the temperature sensor, and the main processor (AP) or coprocessor (CP) obtains the sampled data from the temperature sensor by accessing the first chip. The temperature sensor sends the collected sampled data (e.g., first temperature data) to the first chip. It should be noted that the data collected by the temperature sensor is usually analog data. The first chip converts the first temperature data (analog data) into second temperature data (digital data) and then sends the second temperature data to the main processor (AP) or coprocessor (CP).

[0145] The following is through Figure 10 The example shown illustrates how the PM7550B allows processor access, using multiple processors accessing the PM7550B as an example. Figure 10 As shown, the method includes:

[0146] S301, The first chip responds to the first request sent by the processor and obtains the value of the CH_SEL_CTL register.

[0147] S302. Determine whether the value of the CH_SEL_CTL register is not non-zero.

[0148] If the value of the CH_SEL_CTL register is non-zero, for example, if the value of the CH_SEL_CTL register is 1, it indicates that the first chip is in a working state, that is, a processor is currently accessing the first chip. At this time, the first chip can notify the processor that sent the first request to wait, and resend the first request after sleeping for a period of time, that is, execute S303.

[0149] If the CH_SEL_CTL register is 0, it indicates that the first chip is in an idle state, meaning that no processor is currently accessing the first chip. In this case, the processor that sent the first request at the current moment can be allowed to access the first chip, with the retry count set to 0, and then access the first chip, which is to execute S305.

[0150] S303, resend the first request after a 1ms hibernation period.

[0151] Understandably, the processor could resend the first request every 1ms, that is, periodically send the first request according to a preset first duration. This would result in the processor sending the first request multiple times.

[0152] S304. Determine whether the number of times the processor resends the first request to the first chip exceeds the resend threshold.

[0153] If the processor sends the first request multiple times, a retransmission threshold can be set in the first chip. If the number of times the processor retransmits the first request to the first chip exceeds the retransmission threshold, the retransmission count can be set to 0, and the first chip can be accessed directly, i.e., S305 is executed. If the number of times the processor retransmits the first request to the first chip is less than or equal to the retransmission threshold, the value of the CH_SEL_CTL register is read again, i.e., the process returns to execute S301. The retransmission threshold can be 20 times, and this embodiment does not limit it.

[0154] S305: Set the retry count to 0 and access the first chip.

[0155] S306. Set the value of the CH_SEL_CTL register to a non-zero value.

[0156] At this time, the processor is accessing the first chip. Setting the value of the CH_SEL_CTL register to a non-zero value indicates that the first chip is being accessed by the processor, prohibiting other processors from accessing the first chip, and avoiding access conflicts that would occur if other processors access the first chip during the current time period.

[0157] S307. Initialize ADC.

[0158] Initializing the ADC can refer to the ADC acquiring the first temperature data collected by the temperature sensor based on the first request.

[0159] S308 and ADC perform analog-to-digital conversion.

[0160] An ADC can convert the first temperature data (analog data) collected by a temperature sensor into a second temperature data (digital data). It's understood that the first and second temperature data indicate the same temperature value, only differing in their data formats.

[0161] S309. Confirm that the analog-to-digital conversion is complete.

[0162] S310. When access to the first chip is stopped, set the value of the CH_SEL_CTL register to 0.

[0163] When access to the first chip is stopped, the value of the CH_SEL_CTL register can be set to 0 to indicate that the first chip is in an idle state. At this time, if other processors request access to the first chip, the other processors can be allowed to access the first chip based on the value of CH_SEL_CTL register being 0.

[0164] S311, Read the second temperature data after analog-to-digital conversion.

[0165] S312, Convert the second temperature data into voltage data, current data, or temperature data.

[0166] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0167] It is understood that, in order to achieve the above functions, the electronic device includes hardware and / or software modules that perform the respective functions. Based on the algorithmic steps of the examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is implemented in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in conjunction with the embodiments, but such implementation should not be considered beyond the scope of this application.

[0168] This application embodiment can divide an electronic device into functional modules based on the above method examples. For example, each function can be divided into its own functional modules, or two or more functions can be integrated into one module. It should be noted that the module division in this application embodiment is illustrative and represents only one logical functional division; other division methods may be used in actual implementation. It should also be noted that the module names in this application embodiment are illustrative, and the names of the modules are not limited in actual implementation.

[0169] Figure 11 This is a schematic diagram of a resource access device provided in an embodiment of this application.

[0170] It should be understood that resource access device 600 can perform... Figure 8 to Figure 10 The resource access method shown; the resource access device 600 includes: an acquisition unit 610 and a processing unit 620.

[0171] The processing unit 620 is configured to respond to a first request, wherein the first chip obtains first indication information, the first request being a request from the first processor or the second processor to access the first chip, and the first indication information being used to indicate whether the first chip is in a working state or an idle state; if the first indication information indicates that the first chip is in an idle state, the processor corresponding to the first request is allowed to access the first chip.

[0172] The resource access device provided in this embodiment is used to execute the resource access method of the above embodiment. The technical principle and technical effect are similar, and will not be described again here.

[0173] It should be noted that the resource access device 600 described above is embodied in the form of a functional unit. The term "unit" here can be implemented in software and / or hardware, and there is no specific limitation on this.

[0174] For example, a "unit" can be a software program, a hardware circuit, or a combination of both that implements the above functions. The hardware circuit may include an application-specific integrated circuit (ASIC), electronic circuitry, a processor (e.g., a shared processor, a proprietary processor, or a group processor) and memory for executing one or more software or firmware programs, integrated logic circuitry, and / or other suitable components that support the described functions.

[0175] Therefore, the units of the various examples described in the embodiments of this application can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0176] Figure 12 A schematic diagram of the structure of an electronic device provided in this application is shown. Figure 12 The dashed lines in the diagram indicate that the unit or module is optional. The electronic device 700 can be used to implement the resource access method described in the above method embodiments.

[0177] The electronic device 700 includes one or more processors 701, which support the resource access methods in the method embodiments of the electronic device 700. The processor 701 can be a general-purpose processor or a special-purpose processor. For example, the processor 701 can be a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, such as discrete gates, transistor logic devices, or discrete hardware components.

[0178] The processor 701 can be used to control the electronic device 700, execute software programs, and process data from the software programs. The electronic device 700 may also include a communication unit 705 for inputting (receiving) and outputting (transmitting) signals.

[0179] For example, electronic device 700 may be a chip, communication unit 705 may be the input and / or output circuit of the chip, or communication unit 705 may be the communication interface of the chip, and the chip may be a component of terminal device or other electronic device.

[0180] For example, electronic device 700 can be a terminal device, communication unit 705 can be the transceiver of the terminal device, or communication unit 705 can be the transceiver circuit of the terminal device.

[0181] The electronic device 700 may include one or more memories 702, which store a program 704. The program 704 can be executed by the processor 701 to generate instructions 703, causing the processor 701 to execute the impedance matching method described in the above method embodiments according to the instructions 703.

[0182] Optionally, the memory 702 may also store data. Optionally, the processor 701 may also read the data stored in the memory 702, which may be stored at the same memory address as the program 704, or the data may be stored at a different memory address than the program 704.

[0183] The processor 701 and memory 702 can be configured separately or integrated together; for example, integrated on the system on chip (SOC) of the terminal device.

[0184] For example, the memory 702 can be used to store the relevant program 704 of the resource access method provided in the embodiments of this application, and the processor 701 can be used to call the relevant program 704 of the resource access method stored in the memory 702 when performing resource access, and execute the resource access method of the embodiments of this application; including: in response to a first request, the first chip obtains first indication information, the first request being a request from the first processor or the second processor to access the first chip, the first indication information being used to indicate that the first chip is in a working state or an idle state; if the first indication information indicates that the first chip is in an idle state, allowing the processor corresponding to the first request to access the first chip.

[0185] This application also provides a computer program product that, when executed by processor 701, implements the resource access method described in any of the method embodiments of this application.

[0186] The computer program product can be stored in memory 702, for example, program 704. Program 704 is finally converted into an executable object file that can be executed by processor 701 after processing such as preprocessing, compilation, assembly and linking.

[0187] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, implements the resource access method described in any of the method embodiments of this application. The computer program may be a high-level language program or an executable object program.

[0188] The computer-readable storage medium is, for example, memory 702. Memory 702 can be volatile memory or non-volatile memory, or memory 702 can include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0189] In this application, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0190] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0191] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0192] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0193] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for example, the division of units is merely a logical functional division, and other division methods may exist in actual implementation; for example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0194] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0195] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0196] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A resource access method, characterized in that, The method is applied to an electronic device, the electronic device including at least two processors and at least one first chip, the at least two processors including a first processor and a second processor, the first processor and the second processor being respectively connected to the first chip, the method including: In response to a first request, the first chip obtains first indication information, where the first request is a request from the first processor or the second processor to access the first chip, and the first indication information is used to indicate whether the first chip is in a working state or an idle state. If the first indication information indicates that the first chip is in an idle state, the processor corresponding to the first request is allowed to access the first chip.

2. The method according to claim 1, characterized in that, The electronic device includes a first region and a second region. The first processor and the second processor are disposed in the first region, and the first chip is disposed in the second region. The first processor and the second processor are respectively connected to the first chip through the system power management interface.

3. The method according to claim 1 or 2, characterized in that, The first chip includes a first register, and the step of obtaining the first indication information in response to the first request includes: In response to the first request, the value of the first register is obtained; The first indication information is determined based on the value of the first register.

4. The method according to claim 3, characterized in that, The first register has a first value and a second value. The first value indicates that the first chip is in an idle state, and the second value indicates that the first chip is in a working state.

5. The method according to claim 4, characterized in that, The method further includes: When the processor corresponding to the first request finishes accessing the first chip, the value of the first register is set to the first value.

6. The method according to any one of claims 1 to 5, characterized in that, The method further includes: If the first indication information indicates that the first chip is in a working state, a waiting message is sent to the processor corresponding to the first request. Based on the waiting message, the processor corresponding to the first request periodically sends the first request to the first chip according to a first duration period.

7. The method according to any one of claims 1 to 6, characterized in that, The electronic device is an electronic device that uses a foldable screen.

8. The method according to any one of claims 1 to 7, characterized in that, The at least two processors include a main processor and a coprocessor.

9. The method according to any one of claims 1 to 8, characterized in that, The first chip includes a digital-to-analog converter (ADC).

10. The method according to any one of claims 1 to 9, characterized in that, The electronic device further includes a temperature sensor, the first chip is connected to the temperature sensor, and the first processor or the second processor obtains the sampling data of the temperature sensor by accessing the first chip.

11. An electronic device, characterized in that, include: At least two processors; Memory; And one or more computer programs, wherein the one or more computer programs are stored on the memory, and when the computer programs are executed by the at least two processors, cause the electronic device to perform the method as described in any one of claims 1-10.

12. A chip system, characterized in that, The chip system includes a processor for calling and running a computer program from memory, causing an electronic device on which the chip system is installed to perform the method as described in any one of claims 1-10.

13. A computer-readable storage medium comprising a computer program, characterized in that, When the computer program is run on an electronic device, it causes the electronic device to perform the method as described in any one of claims 1-10.

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