Methods, apparatus, equipment, and media for generating vectors for memory simulation tests.

Abstract

The memory simulation test vector generation method, apparatus, device, and medium provided in this disclosure include: generating an initial simulation test vector based on the memory's operating state, a first proportional information of the memory in an active state, a second proportional information of the memory in a disabled state, a third proportional information of the memory executing each instruction in an active state, and a fourth proportional information of the memory executing each instruction in a disabled state; determining a first actual instruction time interval and a second actual instruction time interval according to an instruction interval formula table; determining the test instruction time interval corresponding to two non-adjacent instructions in the initial simulation test vector; and compensating the instruction time interval corresponding to two non-adjacent instructions in the initial simulation test vector according to the second actual instruction time interval and the test instruction time interval. This ensures that the actual instruction time interval between two adjacent and non-adjacent test instructions in the simulation test vector meets the minimum time interval limit set by the memory.

Description

Technical Field

[0001] This invention relates to the field of memory technology and related technical fields, specifically to a method, apparatus, device, and medium for generating memory simulation test vectors. Background Technology

[0002] With the rapid development of information technology, memory (DRAM), as one of the core components of a computer system, is of paramount importance in terms of performance and stability. To ensure the reliability of memory under various operating conditions, a series of rigorous functional verifications are required, which necessitates the preparation of simulation test vectors.

[0003] In existing technologies, engineers write simulation test vectors based on DRAM product manuals to meet the functional verification requirements. A simulation test vector needs to include functional instructions, addresses, data, and the legality between instructions (the timing between each instruction must meet the minimum value specified in the product manual). Then, the written test vector file, process corners, initial voltage values, parasitic parameters, circuit netlist, and other necessary files are put into the test platform file. Finally, the design tool EDA is used for simulation calculation. If there are connection errors in the actual circuit, the simulation results of the test vectors can reflect which address in the circuit has a read error or timing error, so that engineers can trace the source and troubleshoot the fault.

[0004] However, due to the manual writing of simulation test vectors, the instruction coverage and randomness in the test vectors are not high enough, and the instruction interval time between non-adjacent instructions calculated manually does not meet the minimum time specified in the product manual, all of which will affect the subsequent DRAM verification. Summary of the Invention

[0005] The embodiments described herein provide a method, apparatus, device, and medium for generating memory simulation test vectors, addressing problems existing in the prior art.

[0006] Firstly, based on the content of this disclosure, a method for generating memory simulation test vectors is provided, including:

[0007] Obtain the instruction interval formula table for the target type of memory, as well as the step size information of the initial simulation test vector selected for the target object, the first proportional information of the memory in the active state, the second proportional information of the memory in the closed state, the third proportional information of the memory executing each instruction in the active state, and the fourth proportional information of the memory executing each instruction in the closed state.

[0008] Select a target number of memory addresses, and obtain the data written to the memory addresses and the data read from the memory addresses based on the written data;

[0009] Based on the memory's operating state, first proportional information, second proportional information, third proportional information, and fourth proportional information, an initial simulation test vector that is associated with the memory address is generated.

[0010] Based on the instruction interval formula table, determine the first actual instruction time interval corresponding to two adjacent instructions and the second actual instruction time interval corresponding to two non-adjacent instructions in the initial simulation test vector;

[0011] Based on the first actual instruction time interval, determine the test instruction time interval corresponding to two non-adjacent instructions in the initial simulation test vector;

[0012] Based on the second actual instruction time interval and the test instruction time interval, the instruction time intervals corresponding to two non-adjacent instructions in the initial simulation test vector are compensated to obtain the target simulation test vector.

[0013] In some embodiments of this disclosure, the step of obtaining the instruction interval formula table for the target type of memory includes:

[0014] Obtain the speed, size, and prefetch count of the memory;

[0015] The instruction interval formula table for the memory is determined based on the memory's speed, size, and prefetch quantity.

[0016] In some embodiments of this disclosure, selecting the target number of memory addresses includes:

[0017] In response to receiving the memory unit quantity information, row address quantity information, and column address quantity information submitted by the target object, the target number of selected memory addresses is determined based on the memory unit quantity information, row address quantity information, and column address quantity information.

[0018] Select a target number of memory addresses from the memory, where the memory cell, row address, and column address corresponding to each memory address are different.

[0019] In some embodiments of this disclosure, determining the first actual instruction time interval corresponding to two adjacent instructions and the second actual instruction time interval corresponding to two non-adjacent instructions in the initial simulation test vector according to the instruction interval formula table includes:

[0020] Based on the memory unit group and memory unit corresponding to the memory addresses of two adjacent instructions executed in the initial simulation test vector, determine the first target instruction interval formula table;

[0021] Based on the memory unit group and memory unit corresponding to the memory addresses of two non-adjacent instructions executed in the initial simulation test vector, determine the second target instruction interval formula table;

[0022] Based on the instruction operation information of two adjacent instructions in the initial simulation test vector, the first actual instruction time interval corresponding to the two adjacent instructions is determined from the first target instruction interval formula table;

[0023] Based on the instruction operation information of two non-adjacent instructions in the initial simulation test vector, the second actual instruction time interval corresponding to the two non-adjacent instructions is determined from the second target instruction interval formula table.

[0024] In some embodiments of this disclosure, determining the test instruction time interval corresponding to two non-adjacent instructions in the initial simulation test vector based on the first actual instruction time interval includes:

[0025] Based on the two non-adjacent instructions in the initial simulation test vector, determine the two adjacent instructions included between the two non-adjacent instructions in the initial simulation test vector;

[0026] The test instruction time interval corresponding to two non-adjacent instructions in the initial simulation test vector is determined based on the actual instruction time interval corresponding to two adjacent instructions included between two non-adjacent instructions in the initial simulation test vector.

[0027] In some embodiments of this disclosure, the step of compensating the instruction time intervals corresponding to two non-adjacent instructions in the initial simulation test vector based on the second actual instruction time interval and the test instruction time interval to obtain the target simulation test vector includes:

[0028] Based on the second actual instruction time interval and the test instruction time interval, determine the instruction time interval difference information corresponding to two non-adjacent instructions in the initial simulation test vector;

[0029] Based on the instruction time interval difference information, the instruction time interval difference information is compensated in the actual instruction time interval corresponding to the latter instruction among the two non-adjacent instructions to obtain the target simulation test vector.

[0030] In some embodiments of this disclosure, before determining the first actual instruction time interval according to the instruction interval formula table, the method further includes:

[0031] According to the instruction interval formula table, obtain the maximum instruction time interval value in the instruction interval formula table;

[0032] Determining the second actual instruction time interval according to the instruction interval formula table includes:

[0033] The second actual instruction time interval is determined based on the maximum instruction time interval value and the instruction interval formula table.

[0034] Secondly, according to the present disclosure, a memory simulation test vector generation device is provided, comprising:

[0035] The information acquisition module is used to acquire the instruction interval formula table of the target type memory, as well as the step size information, first scale information, second scale information, third scale information and fourth scale information of the initial simulation test vector selected by the target object. The instruction interval formula table includes the instruction interval formula table corresponding to instructions located in different memory unit groups, the instruction interval formula table corresponding to instructions located in different memory units and the instruction interval formula table corresponding to instructions located in the same memory unit.

[0036] The data pre-read / write module is used to select a target number of memory addresses, and to obtain the data to be written to the memory addresses and the data to be read from the memory addresses based on the written data.

[0037] An initial vector generation module is used to generate an initial simulation test vector that is associated with the memory address based on the memory's working state, first proportional information, second proportional information, third proportional information, and fourth proportional information. The number of instructions included in the initial simulation test vector is determined based on the step size information.

[0038] The first determining module is used to determine, according to the instruction interval formula table, the first actual instruction time interval corresponding to two adjacent instructions and the second actual instruction time interval corresponding to two non-adjacent instructions in the initial simulation test vector.

[0039] The second determining module is used to determine the test instruction time interval corresponding to two non-adjacent instructions in the initial simulation test vector based on the first actual instruction time interval.

[0040] The target vector generation module is used to compensate for the instruction time intervals corresponding to two non-adjacent instructions in the initial simulation test vector based on the second actual instruction time interval and the test instruction time interval, so as to obtain the target simulation test vector.

[0041] Thirdly, according to the present disclosure, a computer device is provided, comprising:

[0042] One or more processors;

[0043] Storage device for storing one or more programs.

[0044] When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any of the first aspects.

[0045] Fourthly, according to the present disclosure, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the methods described in any of the first aspects.

[0046] The memory simulation test vector generation method, apparatus, device, and medium provided in this disclosure first obtain an instruction interval formula table for the target type of memory, as well as step size information of the initial simulation test vector selected for the target object, first proportional information of the memory in the active state, second proportional information of the memory in the closed state, third proportional information of the memory executing each instruction in the active state, and fourth proportional information of the memory executing each instruction in the closed state. Then, a target number of memory addresses are selected, and write data to the memory addresses and read data based on the write data are obtained. An initial simulation test vector associated with the memory addresses is generated according to the memory's working state, the first proportional information, the second proportional information, the third proportional information, and the fourth proportional information. A first actual instruction time interval and a second actual instruction time interval are determined according to the instruction interval formula table. Then, the test instruction time interval corresponding to two non-adjacent instructions in the initial simulation test vector is determined according to the first actual instruction time interval. Finally, the instruction time interval corresponding to two non-adjacent instructions in the initial simulation test vector is compensated according to the second actual instruction time interval and the test instruction time interval to obtain the target simulation test vector. Implement random generation of simulation test vectors, and ensure that the actual instruction time interval between two adjacent and non-adjacent test instructions in the simulation test vectors meets the minimum time interval specified in the memory manual.

[0047] The above description is merely an overview of the technical solutions of the embodiments of this application. In order to better understand the technical means of the embodiments of this application and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of this application more obvious and understandable, specific implementation methods of this application are described below. Attached Figure Description

[0048] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0049] Figure 1 This is a flowchart illustrating a memory simulation test vector generation method provided in an embodiment of this disclosure;

[0050] Figure 2This is a schematic diagram of the structure of a memory simulation test vector generation device provided in an embodiment of this disclosure;

[0051] Figure 3 This is a schematic diagram of the structure of a computer device provided in an embodiment of this disclosure.

[0052] In the accompanying diagram, markers with the same last two digits correspond to the same elements. It should be noted that the elements in the diagram are schematic and not drawn to scale. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0054] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0055] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of the phrase "embodiment" in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0056] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists, A and B exist simultaneously, or B exists. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0057] Furthermore, in all embodiments of this disclosure, terms such as “first” and “second” are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0058] In the description of this application, unless otherwise stated, "multiple" means two or more (including two), and similarly, "multiple groups" means two or more (including two groups).

[0059] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0060] Based on the problems existing in the prior art, this disclosure provides a method for generating memory simulation test vectors. Figure 1 This is a flowchart illustrating a memory simulation test vector generation method provided in an embodiment of this disclosure, as shown below. Figure 1 As shown, the specific process of the memory simulation test vector generation method includes:

[0061] S110. Obtain the instruction interval formula table of the target type memory, as well as the step size information of the initial simulation test vector selected by the target object, the first proportional information of the memory in the active state, the second proportional information of the memory in the closed state, the third proportional information of the memory executing each instruction in the active state, and the fourth proportional information of the memory executing each instruction in the closed state.

[0062] The instruction interval formula table includes instruction interval formula tables corresponding to instructions located in different memory unit groups, instruction interval formula tables corresponding to instructions located in different memory units, and instruction interval formula tables corresponding to instructions located in the same memory unit.

[0063] Specifically, the instruction interval formula table for memory is related to the memory's speed, size, and prefetch count. Therefore, the instruction interval formula table for the target type of memory is determined based on the memory's speed, size, and prefetch count.

[0064] In a specific implementation, the target object can select the memory speed, size, and prefetch quantity. Then, based on the selected memory prefetch quantity, memory speed, and size, the instruction interval formula table for the memory is determined. Table 1 is an example table of instruction interval formulas corresponding to instructions located in different memory unit groups. Table 2 is an example table of instruction interval formulas corresponding to instructions located in different memory units. Table 3 is an example table of instruction interval formulas corresponding to instructions located in the same memory unit.

[0065] Table 1: Instruction Interval Formulas for Instructions Located in Different Memory Unit Groups

[0066]

[0067] Table 2 shows the instruction interval formulas corresponding to instructions located in different memory units.

[0068]

[0069] Table 3. Instruction Interval Formulas for Instructions Located in the Same Memory Unit

[0070]

[0071] It should be noted that in the instruction interval formula table above, ACT is the activation instruction, WR is the write instruction, RD is the read instruction, PRE is the instruction to close a single memory cell, SRF is the self-refresh instruction, PALL is the instruction to close all memory cells, tRRD_S is the time required from activation to activation instruction in different memory cell groups, tRRD_L is the time required from activation to activation instruction in different memory cells within the same memory cell group, tRP is the row precharge time, tRAS is the row activity time, tRC is the row cycle time, tRTP is the read to precharge time, PL (parity latency) is the parity latency, AL (additive latency) is the additional latency, CWL (CAS write latency) is the column address write latency, and tWR (write recovery) is the additional latency. tXS is the write recovery time, tCCD is the column address to column address command delay, CRC is cyclic redundancy check (in this patent, 1 indicates CRC is enabled, 0 indicates CRC is disabled), CL is the column address strobe delay, tXSDLL is the time from self-refresh exit to DLL reset, RDATA is the read data length, tRDPDEN is the read operation to power down command delay, tRFC1 is the refresh cycle time, tRRD is the row activation to row activation command delay, tCCD_L is the address to column address command delay for the same memory unit, and tRCD is the row address to column address command delay.

[0072] In addition, the target object can select the step size information of the initial simulation test vector, the first proportional information of the memory in the active state, the second proportional information of the memory in the closed state, the third proportional information of the memory executing each instruction in the active state, and the fourth proportional information of the memory executing each instruction in the closed state, laying the foundation for the subsequent generation of the initial simulation test vector.

[0073] It should be noted that the step size information of the initial simulation test vector reflects the number of instructions included in the initial simulation test vector.

[0074] Furthermore, because each memory cell can be in an active or disabled state depending on the memory's operating mechanism, the randomness of each instruction in the generated initial simulation test vector is ensured by setting the first proportional information for the memory in the active state, the second proportional information for the memory in the disabled state, the third proportional information for the memory to execute each instruction in the active state, and the fourth proportional information for the memory to execute each instruction in the disabled state. In addition, the instructions that the memory can execute in the active or disabled state are also different. Therefore, setting the proportional information of the instructions executed by the memory in different states further ensures the randomness of the generated initial simulation test vector.

[0075] S120. Select the target number of memory addresses, and obtain the data written to the memory addresses and the data read from the memory addresses based on the written data.

[0076] In the specific implementation, selecting the target number of memory addresses includes: in response to receiving the memory unit quantity information, row address quantity information, and column address quantity information submitted by the target object, determining the total target number of memory addresses to be selected based on the memory unit quantity information, row address quantity information, and column address quantity information; selecting the target number of memory addresses from the memory, wherein the memory unit, row address, and column address corresponding to each memory address are different.

[0077] In the specific implementation process, if the target object submits 2 memory units, 2 row addresses, and 2 column addresses, then the total number of target memory locations is 8. Based on this total number, the target number of memory addresses (i.e., 8 memory addresses) are randomly selected from the memory. Data is then written to these 8 memory addresses, and the corresponding read data is retrieved. The purpose of this step is to write data to the selected addresses and read the corresponding values ​​to ensure that the subsequently generated initial simulation test vector can correctly read and write the data corresponding to these memory addresses.

[0078] It should be noted that in the above implementation process, the number of memory units, row address and column address of the eight selected memory addresses are all different, and the number of selected memory addresses is not specifically limited in this embodiment.

[0079] S130. Based on the memory's operating state, the first proportional information, the second proportional information, the third proportional information, and the fourth proportional information, generate an initial simulation test vector that is associated with the memory address.

[0080] The number of instructions included in the initial simulation test vector is determined based on the step size information.

[0081] Based on the step size information of the initial simulation test vector selected by the target object, N steps of instructions with the same step size information are randomly generated. During the random generation of N steps of instructions with the same step size information, instruction sets corresponding to memory addresses are randomly generated according to the first, second, third, and fourth ratio information selected by the target object. For example, if the memory is in an active state, the instructions [WR, WRA, RD, RDA, PRE, PALL, PDE, PDX] in the active state will be selected with the probability corresponding to the third ratio information selected by the target object. If the memory is in a closed state, the instructions [ZQCS, ZQCL, PDE, PDX, ARF, SRF] in the closed state will be selected with the probability corresponding to the fourth ratio information selected by the target object, so as to ensure the randomness of the generated initial simulation test vector.

[0082] It should be noted that in the initial simulation test vectors generated above, the memory executed by each instruction is the memory corresponding to the memory address. For example, the first instruction in the generated initial simulation test vector is a write instruction, which means writing data to a certain memory address.

[0083] S140. Based on the instruction interval formula table, determine the first actual instruction time interval corresponding to two adjacent instructions and the second actual instruction time interval corresponding to two non-adjacent instructions in the initial simulation test vector.

[0084] In a specific implementation, determining the first actual instruction time interval corresponding to two adjacent instructions and the second actual instruction time interval corresponding to two non-adjacent instructions in the initial simulation test vector, based on the instruction interval formula table, includes: determining a first target instruction interval formula table based on the memory unit group and memory unit corresponding to the memory addresses executed by two adjacent instructions in the initial simulation test vector; determining a second target instruction interval formula table based on the memory unit group and memory unit corresponding to the memory addresses executed by two non-adjacent instructions in the initial simulation test vector; determining the first actual instruction time interval corresponding to two adjacent instructions from the first target instruction interval formula table based on the instruction operation information of two adjacent instructions in the initial simulation test vector; and determining the second actual instruction time interval corresponding to two non-adjacent instructions from the second target instruction interval formula table based on the instruction operation information of two non-adjacent instructions in the initial simulation test vector.

[0085] A specific example is the generated initial simulation test vector:

[0086] Step1 ACT BG0, BK0, ROW 28175 (18tCK)

[0087] Step2 WR BG0, BK0, COL 109, DATA (18tCK)

[0088] Step 3 PRE BG0, BK2 (1tCK)

[0089] Step 4 PRE BG0, BK2 (1tCK)

[0090] Step5 ACT BG0, BK2, ROW 19304 (18tCK)

[0091] Step 6 PRE BG0, BK0 (1tCK)

[0092] The initial simulation test vectors include two adjacent instructions: ACT BG0, BK0, ROW 28175 and WR BG0, BK0, COL 109, DATA; WR BG0, BK0, COL 109, DATA and PRE BG0, BK2; PRE BG0, BK2 and PRE BG0, BK2; PRE BG0, BK2 and ACT BG0, BK2, ROW 19304; ACT BG0, BK2, ROW 19304 and PRE BG0, BK0.

[0093] The two non-adjacent instructions in the initial simulation test vector include ACT BG0, BK0, ROW 28175 and PRE BG0, BK2; ACT BG0, BK0, ROW 28175 and PRE BG0, BK2; ...; PRE BG0, BK2 and PRE BG0, BK0.

[0094] First, determine the instruction interval formula table corresponding to two adjacent instructions in the initial simulation test vector, and the instruction interval formula table corresponding to two non-adjacent instructions in the initial simulation test vector. For example, the instruction interval formula table corresponding to two adjacent instructions, ACT BG0, BK0, ROW28175 and WR BG0, BK0, COL 109, DATA, is the instruction interval formula table corresponding to instructions located in the same memory unit; the instruction interval formula table corresponding to two adjacent instructions, ACT BG0, BK2, ROW19304 and PRE BG0, BK0, is the instruction interval formula table corresponding to instructions located in different memory units; the instruction interval formula table corresponding to two non-adjacent instructions, ACT BG0, BK0, ROW28175 and PRE BG0, BK2, is the instruction interval formula table corresponding to instructions located in different memory units.

[0095] After determining the instruction interval formula table corresponding to two adjacent instructions in the initial simulation test vector, and the instruction interval formula table corresponding to two non-adjacent instructions in the initial simulation test vector, the first actual instruction time interval is determined from the instruction interval formula table, and the second actual instruction time interval is determined from the instruction interval formula table.

[0096] In a specific example, according to the lookup table, the actual instruction time interval between the first and second instructions is 18tCK, the actual instruction time interval between the second and third instructions is 1tCK, the actual instruction time interval between the third and fourth instructions is 1tCK, the actual instruction time interval between the fourth and fifth instructions is 18tCK, and the actual instruction time interval between the fifth and sixth instructions is 1tCK. Furthermore, by looking up the table, the actual instruction time interval between any two non-adjacent instructions in the initial simulation test vector can be determined; for example, the actual instruction time interval between the second and sixth instructions is 42tCK.

[0097] S150. Based on the first actual instruction time interval, determine the test instruction time interval corresponding to two non-adjacent instructions in the initial simulation test vector.

[0098] In a specific implementation, the test instruction time interval corresponding to two non-adjacent instructions in the initial simulation test vector is determined based on the first actual instruction time interval. This includes: determining the two adjacent instructions included between the two non-adjacent instructions in the initial simulation test vector; and determining the test instruction time interval corresponding to the two non-adjacent instructions in the initial simulation test vector based on the cumulative sum of the actual instruction time intervals corresponding to the two adjacent instructions included between the two non-adjacent instructions in the initial simulation test vector.

[0099] Since the actual instruction time interval between two adjacent instructions in the initial simulation test vector has been determined in step S140, the time interval between two non-adjacent test instructions in the initial simulation test vector can be determined based on the actual instruction time interval between two adjacent instructions included between the two non-adjacent instructions in the initial simulation test vector during the memory test based on the initial simulation test vector.

[0100] For example, as can be seen from the table, the actual instruction time interval between the second and sixth instructions in the initial simulation test vector is 42tCK. However, based on the sum of all instructions between these two non-adjacent instructions in the initial simulation test vector, the test instruction time interval between the second and sixth instructions in the initial simulation test vector is determined to be 21tCK (1tCK + 1tCK + 18tCK + 1tCK = 21tCK). This results in a discrepancy between the actual instruction time interval and the test instruction time interval between two non-adjacent test instructions in the simulation test vector.

[0101] S160. Based on the second actual instruction time interval and the test instruction time interval, compensate for the instruction time intervals corresponding to two non-adjacent instructions in the initial simulation test vector to obtain the target simulation test vector.

[0102] In the specific implementation, the instruction time intervals corresponding to two non-adjacent instructions in the initial simulation test vector are compensated according to the second actual instruction time interval and the test instruction time interval to obtain the target simulation test vector. This includes: determining the instruction time difference information corresponding to two non-adjacent instructions in the initial simulation test vector according to the second actual instruction time interval and the test instruction time interval; and compensating the instruction time interval difference information into the actual instruction time interval corresponding to the latter instruction among the two non-adjacent instructions to obtain the target simulation test vector.

[0103] It should be noted that, as another possible approach, the instruction time interval difference information can be compensated into the actual instruction time interval corresponding to the preceding instruction in two non-adjacent instructions to obtain the target simulation test vector. This disclosure does not specifically limit this approach.

[0104] By analyzing step S150, the instruction time interval difference information can be compensated in the actual instruction time interval in step six, ensuring that the actual instruction time interval of two non-adjacent test instructions in the simulation test vector is the same as the test instruction time interval, thereby ensuring that the actual instruction time interval of two non-adjacent test instructions in the simulation test vector also meets the minimum time interval specified by the memory manual.

[0105] The memory simulation test vector generation method provided in this embodiment first obtains the instruction interval formula table of the target type of memory, as well as the step size information of the initial simulation test vector selected for the target object, the first ratio information of the memory in the active state, the second ratio information of the memory in the closed state, the third ratio information of the memory executing each instruction in the active state, and the fourth ratio information of the memory executing each instruction in the closed state. Then, it selects a target number of memory addresses and obtains the write data to the memory addresses and the read data of the memory addresses based on the write data. Then, it generates an initial simulation test vector that is associated with the memory addresses according to the working state of the memory, the first ratio information, the second ratio information, the third ratio information, and the fourth ratio information. Then, it determines the first actual instruction time interval and the second actual instruction time interval according to the instruction interval formula table. Then, it determines the test instruction time interval corresponding to two non-adjacent instructions in the initial simulation test vector according to the first actual instruction time interval. Finally, according to the second actual instruction time interval and the test instruction time interval, if the test instruction interval of a non-adjacent instruction is less than its actual instruction interval, then it is necessary to compensate for the instruction time interval corresponding to two non-adjacent instructions in the initial simulation test vector to obtain the target simulation test vector. Implement random generation of simulation test vectors, and ensure that the actual instruction time interval between two adjacent and non-adjacent test instructions in the simulation test vectors meets the minimum time interval specified in the memory manual.

[0106] Based on the above embodiments, the method provided in this disclosure further includes:

[0107] According to the instruction interval formula table, obtain the maximum instruction interval value in the instruction interval formula table; according to the maximum instruction interval value and the instruction interval formula table, determine the second actual instruction interval.

[0108] When checking the validity of non-adjacent instruction intervals in a loop, it is first necessary to obtain the maximum instruction interval value in the instruction interval formula table. Then, based on the maximum instruction interval value and the instruction interval formula table, the second actual instruction interval is determined.

[0109] Specifically, in determining the actual instruction time interval between the two non-adjacent instructions of the starting instruction in the initial simulation test vector, the instruction time interval between the two non-adjacent instructions with each instruction as the starting instruction should be less than the maximum instruction time interval. In this way, when testing the time interval between the non-adjacent instructions of the instruction, it is not necessary to check all combinations from the starting instruction to all the remaining instructions, thereby improving testing efficiency.

[0110] Based on the above embodiments, Figure 2This is a schematic diagram of the structure of a memory simulation test vector generation device provided in an embodiment of this disclosure, as shown below. Figure 2 As shown, the memory simulation test vector generation device includes:

[0111] The information acquisition module 210 is used to acquire the instruction interval formula table of the target type memory, as well as the step size information of the initial simulation test vector selected by the target object, the first proportional information of the memory in the active state, the second proportional information of the memory in the closed state, the third proportional information of the memory executing each instruction in the active state, and the fourth proportional information of the memory executing each instruction in the closed state.

[0112] The data pre-read / write module 220 is used to select a target number of memory addresses and obtain the data to be written to the memory addresses and the data to be read from the memory addresses based on the written data.

[0113] The initial vector generation module 230 is used to generate an initial simulation test vector that is associated with the memory address based on the working state of the memory, the first proportional information, the second proportional information, the third proportional information and the fourth proportional information.

[0114] The first determining module 240 is used to determine, according to the instruction interval formula table, the first actual instruction time interval corresponding to two adjacent instructions and the second actual instruction time interval corresponding to two non-adjacent instructions in the initial simulation test vector;

[0115] The second determining module 250 is used to determine the test instruction time interval corresponding to two non-adjacent instructions in the initial simulation test vector based on the first actual instruction time interval.

[0116] The target vector generation module 260 is used to compensate for the instruction time intervals corresponding to two non-adjacent instructions in the initial simulation test vector based on the second actual instruction time interval and the test instruction time interval, so as to obtain the target simulation test vector.

[0117] The memory simulation test vector generation apparatus provided in this embodiment first obtains the instruction interval formula table of the target type of memory, as well as the step size information of the initial simulation test vector selected for the target object, the first ratio information of the memory in the active state, the second ratio information of the memory in the closed state, the third ratio information of the memory executing each instruction in the active state, and the fourth ratio information of the memory executing each instruction in the closed state. Then, it selects a target number of memory addresses and obtains the write data to the memory addresses and the read data of the memory addresses based on the write data. Based on the memory's operating state, the first ratio information, the second ratio information, the third ratio information, and the fourth ratio information, it generates an initial simulation test vector that is associated with the memory addresses. Based on the instruction interval formula table, it determines the first actual instruction time interval and the second actual instruction time interval. Then, based on the first actual instruction time interval, it determines the test instruction time interval corresponding to two non-adjacent instructions in the initial simulation test vector. Finally, based on the second actual instruction time interval and the test instruction time interval, it compensates for the instruction time interval corresponding to two non-adjacent instructions in the initial simulation test vector to obtain the target simulation test vector. This achieves random generation of simulation test vectors and ensures that the actual instruction time interval between two adjacent and non-adjacent test instructions in the simulation test vector meets the minimum time interval specified in the memory manual.

[0118] In a specific implementation, the instruction interval formula table for obtaining the target type of memory includes:

[0119] Obtain the speed, size, and prefetch count of the memory;

[0120] The instruction interval formula table for the memory is determined based on the memory's speed, size, and prefetch quantity.

[0121] In a specific implementation, selecting the target number of memory addresses includes:

[0122] In response to receiving the memory unit quantity information, row address quantity information, and column address quantity information submitted by the target object, the target quantity of selected memory is determined based on the memory unit quantity information, row address quantity information, and column address quantity information.

[0123] Select a target number of memory addresses from the memory, where the memory cell, row address, and column address corresponding to each memory address are different.

[0124] In a specific implementation, determining the first actual instruction time interval corresponding to two adjacent instructions and the second actual instruction time interval corresponding to two non-adjacent instructions in the initial simulation test vector according to the instruction interval formula table includes:

[0125] Based on the memory unit group and memory unit corresponding to the memory addresses of two adjacent instructions executed in the initial simulation test vector, determine the first target instruction interval formula table;

[0126] Based on the memory unit group and memory unit corresponding to the memory addresses of two non-adjacent instructions executed in the initial simulation test vector, determine the second target instruction interval formula table;

[0127] Based on the instruction operation information of two adjacent instructions in the initial simulation test vector, the first actual instruction time interval corresponding to the two adjacent instructions is determined from the first target instruction interval formula table;

[0128] Based on the instruction operation information of two non-adjacent instructions in the initial simulation test vector, the second actual instruction time interval corresponding to the two non-adjacent instructions is determined from the second target instruction interval formula table.

[0129] In a specific implementation, determining the test instruction time interval corresponding to two non-adjacent instructions in the initial simulation test vector based on the first actual instruction time interval includes:

[0130] Based on the two non-adjacent instructions in the initial simulation test vector, determine the two adjacent instructions included between the two non-adjacent instructions in the initial simulation test vector;

[0131] The test instruction time interval corresponding to two non-adjacent instructions in the initial simulation test vector is determined based on the actual instruction time interval corresponding to two adjacent instructions included between two non-adjacent instructions in the initial simulation test vector.

[0132] In a specific implementation, the step of compensating the instruction time intervals corresponding to two non-adjacent instructions in the initial simulation test vector based on the second actual instruction time interval and the test instruction time interval to obtain the target simulation test vector includes:

[0133] Based on the second actual instruction time interval and the test instruction time interval, determine the instruction time difference information corresponding to two non-adjacent instructions in the initial simulation test vector;

[0134] Based on the instruction time interval difference information, the instruction time interval difference information is compensated in the actual instruction time interval corresponding to the latter instruction among the two non-adjacent instructions to obtain the target simulation test vector.

[0135] In a specific implementation, before determining the first actual instruction time interval according to the instruction interval formula table, the method further includes:

[0136] According to the instruction interval formula table, obtain the maximum instruction time interval value in the instruction interval formula table;

[0137] Determining the second actual instruction time interval according to the instruction interval formula table includes:

[0138] The second actual instruction time interval is determined based on the maximum instruction time interval value and the instruction interval formula table.

[0139] This application also provides a computer device, please refer to the following for details. Figure 3 , Figure 3 This is a basic structural block diagram of the computer device in this embodiment.

[0140] The computer device includes a memory 510 and a processor 520 that are interconnected via a system bus. It should be noted that only a computer device with components 510-520 is shown in the figure; however, it should be understood that it is not required to implement all the shown components, and more or fewer components may be implemented alternatively. Those skilled in the art will understand that the computer device described herein is a device capable of automatically performing numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes, but is not limited to, microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), embedded devices, etc.

[0141] Computer devices can include desktop computers, laptops, handheld computers, and cloud servers. These devices allow for human-computer interaction with users through keyboards, mice, remote controls, touchpads, or voice-activated devices.

[0142] The memory 510 includes at least one type of readable storage medium, including non-volatile memory or volatile memory, such as flash memory, hard disk, multimedia card, card-type memory (e.g., SD or DX memory), random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, magnetic disk, optical disk, etc. RAM may include static RAM or dynamic RAM. In some embodiments, the memory 510 may be an internal storage unit of a computer device, such as the hard disk or memory of the computer device. In other embodiments, the memory 510 may also be an external storage device of the computer device, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, or flash card equipped on the computer device. Of course, the memory 510 may include both internal storage units and external storage devices of the computer device. In this embodiment, the memory 510 is typically used to store the operating system and various application software installed on the computer device, such as the program code of the method described above. In addition, the memory 510 may also be used to temporarily store various types of data that have been output or will be output.

[0143] The processor 520 is typically used to perform the overall operation of a computer device. In this embodiment, the memory 510 is used to store program code or instructions, including computer operation instructions. The processor 520 is used to execute the program code or instructions stored in the memory 510 or to process data, such as program code that runs the methods described above.

[0144] In this article, the bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. This bus system can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0145] Another embodiment of this application also provides a computer-readable medium, which may be a computer-readable signal medium or a computer-readable medium. A processor in a computer reads computer-readable program code stored in the computer-readable medium, enabling the processor to execute the functional actions specified in each step or combination of steps in the above method; and to generate means for implementing the functional actions specified in each block or combination of blocks in the block diagram.

[0146] Computer-readable media include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared memory or semiconductor systems, devices or apparatuses, or any suitable combination thereof, wherein the memory is used to store program code or instructions, the program code including computer operation instructions, and the processor is used to execute the program code or instructions of the above-described methods stored in the memory.

[0147] The definitions of memory and processor can be found in the description of the foregoing computer device embodiments, and will not be repeated here.

[0148] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0149] In the various embodiments of this application, the functional units or modules can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0150] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0151] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0152] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0153] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A memory emulation test vector generation method, characterized by, The method comprises the following steps: obtaining an instruction interval formula table of a target type of memory, and step length information of an initial simulation test vector selected by a target object, first proportion information of the memory in an active state, second proportion information of the memory in an off state, third proportion information of the memory in the active state for executing each instruction, and fourth proportion information of the memory in the off state for executing each instruction; selecting a target number of memory addresses, and obtaining write data to the memory addresses and read data of the memory addresses based on the write data; generating an initial simulation test vector associated with the memory addresses according to the working state of the memory, the first proportion information, the second proportion information, the third proportion information, and the fourth proportion information; determining a first actual instruction time interval corresponding to two adjacent instructions and a second actual instruction time interval corresponding to two non-adjacent instructions in the initial simulation test vector according to the instruction interval formula table; determining a test instruction time interval corresponding to two non-adjacent instructions in the initial simulation test vector according to the first actual instruction time interval; compensating the instruction time interval corresponding to two non-adjacent instructions in the initial simulation test vector according to the second actual instruction time interval and the test instruction time interval to obtain a target simulation test vector. The third proportion information of the memory in the active state for executing each instruction is the probability of each instruction in the active state being selected by the target object according to the third proportion information, and the fourth proportion information of the memory in the off state for executing each instruction is the probability of each instruction in the off state being selected by the target object according to the fourth proportion information.

2. The method of claim 1, wherein, The method comprises the following steps: obtaining the rate, size, and prefetch quantity of the memory; determining the instruction interval formula table of the memory according to the rate, size, and prefetch quantity of the memory.

3. The method of claim 1, wherein, The method comprises the following steps: in response to receiving the memory cell quantity information, row address quantity information, and column address quantity information submitted by the target object, determining the target number of memory addresses to be selected according to the memory cell quantity information, row address quantity information, and column address quantity information; selecting the target number of memory addresses from the memory, wherein the memory cells, row addresses, and column addresses corresponding to each memory address are different.

4. The method of claim 1, wherein, The method comprises the following steps: determining a first target instruction interval formula table according to the memory cell groups and memory cells corresponding to the memory addresses on which the two adjacent instructions in the initial simulation test vector are executed; determining a second target instruction interval formula table according to the memory cell groups and memory cells corresponding to the memory addresses on which the two non-adjacent instructions in the initial simulation test vector are executed; determining, according to instruction operation information of two adjacent instructions in the initial simulation test vector, a first actual instruction time interval corresponding to the two adjacent instructions from a first target instruction interval formula table; determining, according to instruction operation information of two non-adjacent instructions in the initial simulation test vector, a second actual instruction time interval corresponding to the two non-adjacent instructions from a second target instruction interval formula table.

5. The method of claim 1, wherein, The determining, according to the first actual instruction time interval, of a test instruction time interval corresponding to two non-adjacent instructions in the initial simulation test vector comprises: determining, according to the two non-adjacent instructions in the initial simulation test vector, two adjacent instructions included between the two non-adjacent instructions in the initial simulation test vector; determining, according to an actual instruction time interval corresponding to the two adjacent instructions included between the two non-adjacent instructions in the initial simulation test vector, a test instruction time interval corresponding to the two non-adjacent instructions in the initial simulation test vector.

6. The method of claim 1, wherein, The compensating, according to the second actual instruction time interval and the test instruction time interval, of an instruction time interval corresponding to the two non-adjacent instructions in the initial simulation test vector to obtain a target simulation test vector comprises: determining, according to the second actual instruction time interval and the test instruction time interval, an instruction time interval difference value corresponding to the two non-adjacent instructions in the initial simulation test vector; compensating, according to the instruction time interval difference value, the instruction time interval difference value in an actual instruction time interval corresponding to a latter one of the two non-adjacent instructions to obtain a target simulation test vector.

7. The method of claim 1, wherein, Before the determining, according to the instruction interval formula table, of the first actual instruction time interval, the method further comprises: obtaining, according to the instruction interval formula table, a maximum instruction time interval value in the instruction interval formula table; The determining, according to the instruction interval formula table, of the second actual instruction time interval comprises: determining, according to the maximum instruction time interval value and the instruction interval formula table, the second actual instruction time interval.

8. A memory emulation test vector generation apparatus, characterized by comprising: The method comprises: an information acquisition module, configured to acquire an instruction interval formula table of a target type of memory, and step information of an initial simulation test vector selected by a target object, first proportion information of the memory in an activated state, second proportion information of the memory in a closed state, third proportion information of the memory in the activated state for executing each instruction, and fourth proportion information of the memory in the closed state for executing each instruction; a data pre-reading and writing module, configured to select a target number of memory addresses, and acquire write data to the memory addresses and read data of the memory addresses based on the write data; an initial vector generation module, configured to generate an initial simulation test vector associated with the memory addresses according to a working state of the memory, the first proportion information, the second proportion information, the third proportion information, and the fourth proportion information; a first determination module, configured to determine, according to the instruction interval formula table, a first actual instruction time interval corresponding to two adjacent instructions in the initial simulation test vector and a second actual instruction time interval corresponding to two non-adjacent instructions; A second determining module, configured to determine a test instruction time interval corresponding to non-adjacent two instructions in the initial simulation test vector according to the first actual instruction time interval; A target vector generating module, configured to compensate an instruction time interval corresponding to non-adjacent two instructions in the initial simulation test vector according to the second actual instruction time interval and the test instruction time interval, to obtain a target simulation test vector. The third proportion information of each instruction executed by the memory in the active state is the probability of selection corresponding to the third proportion information selected by the target object for each instruction of the memory in the active state, and the fourth proportion information of each instruction executed by the memory in the closed state is the probability of selection corresponding to the fourth proportion information selected by the target object for each instruction of the memory in the closed state.

9. A computer device, comprising: Comprising: One or more processors; A storage device for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the method in any one of claims 1-7.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The program is executed by the processor to implement the method in any one of claims 1-7.

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