FT test system of LED display screen receiving card control chip

Abstract

The invention relates to the technical field of testing of semiconductor chips, in particular to an FT test system of an LED display screen receiving card control chip, which comprises a test module library, a data acquisition unit, a state evaluation unit and a test process scheduling unit. According to the invention, personalized testing of chips with different quality levels is realized, seriously invalid chips can be quickly removed, and precious testing machine hours are saved; a test path can be optimized for a chip with excellent performance, and a test period is shortened; and for the sub-health chip with the suspected problem, a stricter verification process can be automatically entered, so that the test efficiency and the quality assurance level are improved on the whole.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor chip testing, and particularly relates to an FT test system for an LED display screen receiving card control chip. BACKGROUND

[0002] In a manufacturing process of a semiconductor integrated circuit, FT (Final Test) is the last quality inspection link before a chip is packaged and shipped. For an LED display screen receiving card control chip, its function directly determines the image quality, color performance, refresh rate and long-term stability of the entire LED display screen. Therefore, the FT test link is crucial. The chip is responsible for receiving, processing and distributing massive high-speed image data, and has high requirements for signal integrity, data processing throughput, gray scale control accuracy and synchronization of multiple outputs.

[0003] At present, for the FT test of the chip, a test system executes the same test items for each to-be-tested chip according to a pre-written test sequence, whether the chip has serious functional defects or excellent performance. The entire test process must be completed. Through in-depth analysis, the prior art is difficult to achieve an ideal balance among test efficiency, defect coverage and diagnostic accuracy, and cannot meet the stringent requirements of the LED display screen receiving card control chip for high quality, high reliability and high consistency. SUMMARY

[0004] The application aims to provide an FT test system for an LED display screen receiving card control chip, comprising: a test module library for storing a plurality of independent and callable test modules, each of which corresponds to a test procedure for a certain specific function or performance index of the LED display screen receiving card control chip; a data acquisition unit for connecting to a chip under test during execution of the test module and acquiring test data fed back by the chip under test in real time; a state evaluation unit electrically connected to the data acquisition unit for receiving the real-time test data and analyzing the real-time test data according to a preset evaluation rule set; the evaluation rule set defines a mapping relationship between different test data results and test states of the chip under test; the state evaluation unit determines the current test state of the chip under test based on the mapping relationship, and the current test state at least includes: a termination state indicating that the chip has an unrecoverable defect, a deep verification state indicating that the performance parameter of the chip is in a qualified critical range, and a standard flow state indicating that the performance parameter of the chip is in a normal qualified range; and a test flow scheduling unit connected to the state evaluation unit and the test module library, and configured to: load and execute a preset baseline test module from the test module library when the test flow is started; receive the current test state determined by the state evaluation unit after any test module is executed; when the current test state is the termination state, the test flow scheduling unit generates and sends a termination instruction to stop all subsequent tests on the current chip under test and classify it as a defective product; when the current test state is the deep verification state, the test flow scheduling unit selects and schedules one or more deep test modules for supplementary or enhanced verification from the test module library according to the specific state; when the current test state is the standard flow state, the test flow scheduling unit selects and schedules a next preset standard test module from the test module library; the determination of real-time data by the state evaluation unit and the dynamic selection of test modules by the test flow scheduling unit together form a control loop for adjusting the test path according to real-time feedback of the chip under test.

[0005] By adopting the above technical solution, individualized testing of chips with different quality levels is realized, and severely defective chips can be quickly removed, saving valuable test machine time; for excellent performance chips, the test path can be optimized to shorten the test cycle; for sub-healthy chips suspected of having problems, they can automatically enter a more stringent verification process, thereby improving the overall test efficiency and quality assurance level.

[0006] Optionally, the system further comprises a fault feature matching subsystem, which comprises: a feature extraction module configured to extract a plurality of dimensional feature parameters from the real-time test data acquired by the data acquisition unit to form a real-time feature vector; a fault feature library configured to store a plurality of preset fault feature records, each of which comprises a known physical defect mode and a corresponding historical feature vector; and a matching analysis module configured to compare and match the real-time feature vector with the historical feature vectors stored in the fault feature library to output a matching result; and the state evaluation unit is further configured to receive the matching result and use the matching result as another basis for determining the current test state.

[0007] By using the above technical solutions, the intelligent level and accuracy of the decision of the state evaluation unit are improved, the physical meaning that may be hidden behind the test data can be understood, and therefore the selection of the deep verification process is more targeted.

[0008] Optionally, the fault feature matching subsystem further comprises a fault feature library updating unit, which is configured to: based on the physical fault analysis result of a known failure mode chip, associate the feature vector generated in the test process of the chip, generate a new fault feature record and store the new fault feature record in the fault feature library; and / or based on the simulation feature vector generated by simulating the virtual defects injected in the chip design stage, generate a new fault feature record and store the new fault feature record in the fault feature library.

[0009] By using the above technical solutions, the entire test system is given the ability of self-learning and continuous evolution, and can continuously absorb new failure knowledge, and the diagnosis capability is enhanced, so as to cope with the changing production process and chip design.

[0010] Optionally, the fault feature library updating unit is further configured to: receive an electronic data record of a chip that has failed in a terminal application, combine the physical analysis result of the failed chip, generate or correct a fault feature record corresponding to the field failure mode, so as to realize closed-loop updating of the fault feature library.

[0011] By using the above technical solutions, the test system can learn and prevent failure modes that are only exposed after long-term operation in actual application environment, improve the long-term reliability of the product, and extend the quality control range from the factory to the entire product life cycle.

[0012] Optionally, the multi-dimension feature parameters extracted by the feature extraction module include at least one of the following: a transient power consumption curve feature of the chip under test when executing a specific instruction or state switching; a voltage drop amplitude and recovery time of the power supply voltage of the chip under test when the load changes; a period jitter or phase jitter parameter of the clock output signal of the chip under test; or in a data communication test, a distribution mode of error bits in a data packet when an error check fails.

[0013] Optionally, the system further includes a chip full life cycle test data recording subsystem, which includes: a data record generation module, configured to generate an independent electronic data record for each chip under test; the electronic data record is associated with a unique identification code of the chip, and at least includes: an actual test module sequence executed by the test flow scheduling unit, key parameter values obtained by the data acquisition unit during module test, and a final test conclusion; a data storage unit, configured to persistently save the electronic data record generated by the data record generation module; and a data interface module, configured to provide query and access to the electronic data record according to the unique identification code in response to a request from an external system.

[0014] By adopting the above technical solutions, comprehensive quality traceability from chip manufacturing to terminal application is realized, and these data not only record the factory state of the chip, but also serve as valuable data assets to provide data support for subsequent process optimization, system-level application and on-site maintenance.

[0015] Optionally, the content included in the electronic data record further includes: wafer batch information of the chip, position information of the chip on the wafer, packaging batch information, and a comprehensive performance evaluation result calculated by the system according to all test parameters.

[0016] By adopting the above technical solutions, an analyst can associate the test performance of a chip with its origin in the production chain, thereby being able to perform more in-depth yield analysis, process drift monitoring and quality root cause tracing.

[0017] Optionally, the data interface module is further configured to: provide the electronic data record to a downstream receiving card assembly manufacturing execution system, and the manufacturing execution system groups chips according to the comprehensive performance evaluation result or other key parameter values included in the electronic data record, and uses chips in a specific group for a specified position on a receiving card.

[0018] By adopting the above technical solutions, it is shown how the application realizes lean manufacturing through data driving, and in the case of not increasing the cost of additional chips, the overall performance and reliability of the final product are improved through optimized resource allocation.

[0019] Optionally, the test modules stored in the test module library include at least one of: a gray scale linearity test module for detecting the gray scale display control precision of the chip; a throughput stress test module for verifying the network packet processing capability of the chip under a set load; or a signal integrity test module for evaluating the signal quality of the high-speed output port of the chip.

[0020] By adopting the above technical solutions, it is clearly shown how the application solves the actual technical pain points in this specific field, such as ensuring the delicate and uniform display screen, ensuring the stability of high-bandwidth data transmission, and maintaining the quality of high-speed signals, so that the practicality and pertinence of the application are specifically embodied.

[0021] Optionally, the preset evaluation rule set in the state evaluation unit specifically includes: a first type of evaluation rule defining that when the real-time test data indicates that there is a preset fatal defect, the current test state is determined as the termination state; a second type of evaluation rule defining that when one or more performance parameter values in the real-time test data are in the edge interval of the preset qualified threshold, the current test state is determined as the deep verification state; and a third type of evaluation rule defining that when all performance parameter values in the real-time test data are in the preset excellent interval, the current test state is determined as the standard flow state, and the test flow scheduling unit is allowed to skip part of the redundant diagnostic test module.

[0022] By adopting the above technical solutions, the synergistic effect of the three types of rules ensures that the test system can make a reasonable trade-off between efficiency, quality, and cost. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 The FT test system block diagram of the LED display screen receiving card control chip of the application is shown. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical scheme and advantages of the application more clear, the specific embodiments of the application will be described in detail below. It can be understood that the specific embodiments here are only used to explain the application, but not to limit the application.

[0025] As shown in Figure 1 The FT test system of the LED display screen receiving card control chip proposed by the embodiments of the application includes a test module library, a data acquisition unit, a state evaluation unit, and a test flow scheduling unit. In addition, the FT test system can also optimally integrate a fault feature matching subsystem and a chip full life cycle test data recording subsystem.

[0026] Specifically, the test module library can be a set of software library files or function sets on the ATE host computer, each test module being used for a test program for a certain specific function or performance index of the LED display screen receiving card control chip.

[0027] It can be understood that the test modules stored in the test module library are various, for example, the test modules stored in the test module library can include at least one of a gray scale linearity test module, a throughput stress test module or a signal integrity test module.

[0028] Specifically, the gray scale performance of the LED display screen directly affects the delicacy and level of the picture, and the gray scale linearity test module is used to detect the gray scale linearity of the gray scale display control accuracy of the chip. When executed, the module will control the chip to output all gray scale levels from the lowest gray scale to the highest gray scale, for example, from 0 to 65535, and cooperate with a high-precision optical sensor to detect the actual brightness value corresponding to the output, and then analyze the linear relationship between the output brightness and the input gray scale code value. Any nonlinear deviation can cause the picture to lose details in dark parts or distort colors in bright parts.

[0029] The LED display screen receiving card control chip needs to process a large amount of video data stream, and the throughput stress test module is used to verify the throughput stress of the chip in processing network data packets under a set load; when executed, the ATE will simulate a sending end, inject a high-speed and uninterrupted data packet stream far exceeding the normal application load into the network interface of the chip, and check whether the data returned by the chip after processing appears packet loss, packet error or processing delay exceeds the standard, etc.

[0030] With the improvement of data rate, the signal quality of the high-speed output port of the chip becomes critical, and the signal integrity test module is used to evaluate the signal integrity of the signal quality of the high-speed output port of the chip. The high-speed oscilloscope or special eye diagram test instrument on the ATE will capture the data signal output by the chip, and analyze various parameters of the eye diagram, such as eye height, eye width, jitter, etc., to evaluate the distortion degree of the signal in the transmission process.

[0031] In addition, the test module library can also include a power-on self-test module, a basic input / output function test module, a built-in self-test module, a clock stability test module, a power consumption analysis module, a high-low temperature cycle stress test module, etc., each module can be called by the test flow scheduling unit at any time as needed.

[0032] It can be understood that the data acquisition unit is configured to be connected to the chip under test during the execution of the test module, and to acquire the test data fed back by the chip under test in real time, which characterizes the running state thereof. In the ATE system, the data acquisition unit is a collection of multiple precision measurement units, such as a power supply measurement unit, a digital pin electronic unit, and a synchronous interface with external instruments such as an oscilloscope, a spectrum analyzer, and the like.

[0033] The data acquisition unit of the present application not only acquires traditional DC parameters or final pass / fail results, but also focuses on capturing dynamic data and multi-dimensional characteristics in the test process. For example, when the gray scale linearity test module is running, the data acquisition unit will continuously record the brightness value corresponding to each gray scale, forming a complete response curve, rather than just determining whether the final linearity error is within the specification.

[0034] It can be understood that the state evaluation unit is electrically connected with the data acquisition unit, for receiving real-time test data and analyzing the real-time test data according to a preset evaluation rule set. The evaluation rule set defines the mapping relationship between different test data results and the test state of the chip under test. Based on this mapping relationship, the state evaluation unit can determine the current test state of the chip under test in real time.

[0035] In the present embodiment, the current test state includes at least three basic states of a termination state, a deep verification state, and a standard flow state.

[0036] Specifically, the termination state indicates that the chip has an unrecoverable defect, such as a power-on short circuit or a complete failure of a core functional unit. The deep verification state indicates that the chip has passed the basic functions, but one or more performance parameters thereof are in a critical range of qualification, and there is a potential quality risk, which needs to be verified more deeply. The standard flow state indicates that the performance parameters of the chip perform well and are in a normal qualified range, and the standard test flow can be continued.

[0037] The test flow scheduling unit is connected with the state evaluation unit and the test module library, and is configured to respond to the current test state determined by the state evaluation unit, so as to dynamically select and execute the test module. The determination of the real-time data by the state evaluation unit and the dynamic selection of the test module by the test flow scheduling unit.

[0038] Specifically, the working flow of the test flow scheduling unit includes the following steps.

[0039] When the test flow is started, the test flow scheduling unit will load and execute a preset baseline test module that all chips must pass, such as a power-on self-test and a basic communication handshake test, from the test module library.

[0040] After the execution of the baseline test module or any subsequent test module, the data acquisition unit sends the acquired test data to the state evaluation unit.

[0041] The state evaluation unit makes a decision according to the evaluation rules in it. It can be understood that the preset evaluation rule set in the state evaluation unit can specifically include the first type of evaluation rule, the second type of evaluation rule, and the third type of evaluation rule.

[0042] Specifically, the first type of evaluation rule defines that when the real-time test data indicates the presence of a short circuit, an open circuit, or a complete failure of a core functional unit, etc. the preset fatal defect, the current test state is determined as a termination state; for example, the rule can be: if the current exceeds the threshold of 100 mA at the moment of power-on, it is determined as a short circuit, and the state is "terminated"; the second type of evaluation rule defines that when one or more performance parameter values in the real-time test data are in the edge interval of the preset qualified threshold, the current test state is determined as a deep verification state; for example, the specification requires that the gray scale linearity error be less than 3%, and the qualified threshold is 3%; the rule can define the edge interval from 2% to 3%, and if the measured error is 2.5%, the state is "deep verification"; the third type of evaluation rule defines that when all performance parameter values in the real-time test data are in the preset excellent interval, the current test state is determined as a standard flow state; for example, if the measured gray scale linearity error is less than 1%, it is considered that the performance is excellent.

[0043] After receiving the current test state determined by the state evaluation unit, the test flow scheduling unit performs the following corresponding scheduling operations.

[0044] When the current test state is a termination state, the test flow scheduling unit generates and sends a termination instruction, which will be passed to the ATE system and the handler to immediately stop all subsequent tests on the current chip under test and classify it as a failure.

[0045] When the current test state is a deep verification state, the test flow scheduling unit selects and schedules one or more preset deep test modules for supplementary or enhanced verification from the test module library according to the specific state; for example, when the gray scale linearity is in the edge interval, the scheduling unit can call the "high-low temperature gray scale stability test module" to investigate its performance drift under temperature changes.

[0046] When the current test state is a standard flow state, the test flow scheduling unit selects and schedules the next preset standard test module from the test module library; further, according to the third type of evaluation rule, when the chip performs excellently, the test flow scheduling unit is also allowed to skip part of the redundant diagnostic test modules to further shorten the test time.

[0047] It can be understood that, assuming that the chip to be tested A is a serious defective product, the chip A is placed on the test station by the handler, and the test starts; the test flow scheduling unit calls the "power-on self-test module"; the data acquisition unit detects that there is a very low resistance between the VCC power pin and the GND ground pin of the chip at the moment of power-on, and the current instantaneously rises to 500 mA; the state evaluation unit receives the current data, matches the definition of the fatal defect of "power-on current seriously exceeding the standard" in the first type of evaluation rules, and immediately determines the current test state as "termination state"; the test flow scheduling unit receives the "termination state", and immediately generates a termination instruction, and all subsequent test modules are cancelled; the handler puts the chip A into the "defective product" bin according to the instruction. The whole test process may take less than 100 milliseconds.

[0048] Suppose that the chip to be tested B is a sub-healthy product, the chip B successfully passes the power-on self-test module and the basic IO function test module, and the state evaluation unit determines "standard flow state" for two times in succession; the test flow scheduling unit continues to call the throughput stress test module, in which the chip B passes the test under standard load, but when the ATE increases the data packet injection rate to the limit load, the data acquisition unit captures sporadic CRC check errors in the chip's return data, with an error rate of about one ten-thousandth, which is close to the edge although it is still within the specification limit; the state evaluation unit receives the error rate data, matches the definition of "critical performance parameter in edge interval" in the second type of evaluation rules, and determines the current test state as "deep verification state"; the test flow scheduling unit receives the "deep verification state", and according to the pre-set associated logic, judges that the CRC error may be related to clock stability, so it selects and schedules the clock jitter precision test module and the wide temperature network stress test module from the test module library; in the wide temperature network stress test module, when the ATE raises the test environment temperature to 85 degrees Celsius, the CRC error rate of the chip B rises sharply, far exceeding the specification; finally, the chip B is determined as a "temperature-sensitive functional defective product" and is sorted into the corresponding grade bin.

[0049] Assuming that the to-be-tested chip C is a good product, the chip C executes the "power-on self-test module", the "basic IO function test module" and the "throughput stress test module" in turn; in all tests, the data acquired by the data acquisition unit all show that the performance parameters of the chip C are not only qualified, but also have a great margin, for example, the error rate is zero, and all timing parameters are in the center area of the specification range; the state evaluation unit continuously determines it as the "standard flow state" according to the third type of evaluation rule, and meets the condition of "excellent performance"; when the test flow scheduling unit is preparing to schedule the standard module "signal integrity diagnosis module", it checks its scheduling rule table and finds a rule: "if the throughput stress test result is excellent, the diagnosis module can be skipped", so the scheduling unit skips the execution of the module; the chip C completes all necessary tests in a shorter time than the standard flow, is judged as a "good product", and enters the highest grade warehouse.

[0050] Through the above three cases, the system of the application realizes intelligent and differentiated processing of chips of different qualities, and the technical effects are obvious.

[0051] On the basis of the above system architecture, the application can also include a fault feature matching subsystem, which includes a feature extraction module, a fault feature library and a matching analysis module.

[0052] Specifically, the feature extraction module is used to extract a plurality of dimensional feature parameters from the real-time test data acquired by the data acquisition unit to form a real-time feature vector. These feature parameters are dynamic information that can more profoundly reflect the internal state of the chip. Specifically, the multi-dimensional feature parameters extracted by the feature extraction module can include at least one of the following: a transient power consumption curve feature of the to-be-tested chip when executing a specific instruction or state switching, a voltage drop amplitude and recovery time of the power supply voltage of the to-be-tested chip when the load changes, and a period jitter or phase jitter parameter of the clock output signal of the to-be-tested chip.

[0053] It can be understood that when a complex image rendering instruction is executed, the peak height, rise time and overall shape of the transient power consumption curve feature can all be related to the health status of the internal computing unit of the chip; when the load of the chip suddenly increases, the voltage on the power supply network will instantaneously drop, and a healthy chip should have a voltage drop within a controllable range and a fast recovery, and an excessive drop or slow recovery can indicate defects in the power supply network design or on-chip capacitance; a small clock jitter can cause data sampling errors, and the period jitter or phase jitter parameter of the clock output signal of the to-be-tested chip can be obtained by precise measurement of the clock signal for a long time.

[0054] In data communication test, the distribution mode of error bits in data packet when error check fails is: randomly distributed error bits and error bits concentrated in a specific position, which may point to completely different physical defect reasons, randomly distributed error bits may be caused by noise interference, and error bits concentrated in a specific position may be related to damage of a specific block of the memory.

[0055] The fault feature library is a knowledge database, which stores a plurality of preset fault feature records. Each fault feature record includes a known physical defect mode, such as "slow locking speed of phase-locked loop", "weak short circuit of address line of secondary cache", and the like, and a corresponding historical feature vector. The historical feature vector is a unique combination of a plurality of dimensional feature parameters exhibited by the known defect during testing.

[0056] The matching analysis module is configured to compare and match the real-time feature vector generated by the feature extraction module with each historical feature vector stored in the fault feature library. For example, a cosine similarity algorithm, an Euclidean distance calculation, or a pre-trained lightweight neural network model is used to output one or more most possible matching results and corresponding confidence levels.

[0057] Finally, the state evaluation unit is further configured to receive the matching result and use the matching result as another important basis for determining the current test state. For example, when the state evaluation unit detects that the CRC error rate is in the edge interval and the fault feature matching subsystem reports that the real-time feature vector of the chip has a matching degree of up to ninety percent with the fault feature record of "clock tree signal crosstalk", the state evaluation unit can more confidently determine the state as "deep verification" and suggest the test flow scheduling unit to preferentially call a deep test module related to clock stability.

[0058] In order to ensure the timeliness and completeness of the fault feature library, the fault feature matching subsystem preferably includes a fault feature library updating unit. The fault feature library updating unit provides a variety of ways to enrich and perfect the knowledge base.

[0059] For example, based on the physical fault analysis results of a known failure mode chip, the feature vector generated during the test process is associated to generate a new fault feature record and store it in the fault feature library. Based on the simulation feature vector generated by simulating the virtual defects injected in the chip design stage, a new fault feature record is generated and stored in the fault feature library.

[0060] More importantly, the failure feature library updating unit is also configured to receive an externally input electronic data record of a chip that has failed in the terminal application, and generate or correct a failure feature record corresponding to the field failure mode in combination with a physical analysis result of the failure chip, so that the test system can continuously improve its prediction ability for potential long-term reliability problems.

[0061] In order to effectively manage and utilize the massive high-value data generated in the test process, the application further includes a chip full-life-cycle test data recording subsystem, which comprises a data record generation module, a data storage unit and a data interface module.

[0062] Specifically, the data record generation module is configured to generate an independent electronic data record for each chip under test, and the electronic data record is strictly associated with a unique identification code of the chip, such as an ID engraved on the surface of the chip by laser. In the electronic data record, in addition to the final test conclusion, at least the actual test module sequence executed by the test flow scheduling unit, the key parameter values obtained by the data acquisition unit during the module test process, and the wafer batch information, the position information on the wafer, the packaging batch information of the chip, and the comprehensive performance evaluation result calculated by the system according to all test parameters through a weighting algorithm, such as a health score of 0 to 100, are included.

[0063] The data storage unit is configured to persistently save the generated electronic data records, which can be a local database server of the factory, or a cloud computing-based, elastically expandable data lake.

[0064] The data interface module provides a set of standard application program interfaces for responding to external system requests and providing queries and access to the electronic data records according to the unique identification code.

[0065] Through big data analysis of the massive test passports in the data storage unit, the correlation between process fluctuations and chip performance can be found. For example, an analyst may find that chips from a certain wafer batch or a certain quadrant area have a generally low health score, and the failure features are mostly directed to poor signal integrity. This insight can be quickly fed back to the wafer factory to guide the inspection and calibration of the corresponding photolithography machine or etching process, thereby improving the yield from the root cause, i.e., empowering the upstream.

[0066] The data interface module can be further used to provide the electronic data record to a downstream receiving card assembly manufacturing execution system, and the manufacturing execution system can query the test passport of each control chip to be mounted when assembling an LED receiving card, and according to the comprehensive performance evaluation result or other key parameter value contained in the electronic data record, the chips can be intelligently grouped, and the chips of a specific group are used for a designated position on the receiving card; for example, the system can preferentially use chips with a health score higher than 98 points for the master control position for processing the main data stream, and use chips with slightly lower scores but still qualified for the redundant backup channel, thereby significantly improving the performance redundancy and working reliability of the final card without changing the bill of materials cost, that is, empowering the downstream.

[0067] In summary, the present application provides a complete, advanced and highly practical LED display screen receiving card control chip FT test solution through its fundamental adaptive test control loop and the optional deep diagnosis and full life cycle data management subsystem. It not only solves many pain points of the prior art, but also changes the FT test from a isolated cost center to a data hub driving the quality improvement and efficiency optimization of the entire value chain. The implementation of the present application will bring profound changes to the quality assurance system of high-performance semiconductor chips.

[0068] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above functional modules is taken as an example for illustration, and in actual application, the above functions can be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. The specific working process of the system, device and unit described above can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

[0069] In the several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented by other means. For example, the device embodiments described above are only schematic, for example, the division of the modules or units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the shown or discussed mutual ones can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0070] The units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, i.e. may be located in one place, or may be distributed on multiple network units. Part or all of the units may be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0071] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present alone, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0072] The integrated unit, if realized in the form of a software functional unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the part of the prior art that contributes to the technical solutions or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The foregoing storage medium includes a U disk, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk, and various program code storage media.

[0073] The above are the preferred embodiments of the present application, and are not intended to limit the protection scope of the present application. Any feature disclosed in the specification (including the abstract and the drawings) can be replaced by other equivalent or similar features unless specifically stated. That is, each feature is only an example of a series of equivalent or similar features unless specifically stated.

Claims

1. An FT test system for an LED display receiver card control chip, characterized in that, include: The test module library stores multiple independent and callable test modules, each of which corresponds to a test program for a specific function or performance indicator of the LED display receiver card control chip. The data acquisition unit is used to connect to the chip under test during the execution of the test module and acquire test data characterized by the operating status fed back by the chip under test in real time. A status evaluation unit, electrically connected to the data acquisition unit, is used to receive the real-time test data and analyze the real-time test data according to a preset set of evaluation rules; the set of evaluation rules defines the mapping relationship between different test data results and the test status of the chip under test. Based on this mapping relationship, the status evaluation unit determines the current test status of the chip under test. The current test status includes at least: a termination status indicating an unrecoverable defect in the chip; a deep verification status indicating that the chip's performance parameters are within the acceptable critical range; and a standard process status indicating that the chip's performance parameters are within the normal acceptable range. The test process scheduling unit is connected to both the status evaluation unit and the test module library, and its function is configured as follows: When the test process starts, a preset baseline test module is loaded and executed from the test module library; After any test module has been executed, the current test status determined by the status evaluation unit is received. When the current test state is the termination state, the test process scheduling unit generates and sends a termination command to stop all subsequent tests on the current chip under test and classify it as a defective product. When the current test state is the deep verification state, the test process scheduling unit selects and schedules one or more deep test modules for supplementary or enhanced verification from the test module library according to the specific state. When the current test state is the standard process state, the test process scheduling unit selects and schedules the next preset standard test module from the test module library for execution; The judgment of real-time data by the state evaluation unit and the dynamic selection of test modules by the test process scheduling unit together form a control loop that adjusts the test path based on the real-time feedback of the individual chip under test.

2. The system as described in claim 1, characterized in that, The system further includes a fault feature matching subsystem, which includes: The feature extraction module is used to extract feature parameters of multiple dimensions from the real-time test data obtained by the data acquisition unit to form a real-time feature vector. A fault feature database stores multiple pre-defined fault feature records. Each fault feature record includes a known physical defect pattern and its corresponding historical feature vector; and The matching analysis module is used to compare and match the real-time feature vector with the historical feature vector stored in the fault feature database to output the matching result; The state evaluation unit is further used to receive the matching result and use the matching result as another basis for determining the current test state.

3. The system as described in claim 2, characterized in that, The fault feature matching subsystem further includes a fault feature database update unit, which is used for: Based on the physical fault analysis results of chips with known failure modes, the feature vectors generated during the testing process are correlated to generate new fault feature records and store them in the fault feature library. And / or Based on the simulation feature vector generated by simulating and testing the virtual defects injected during the chip design stage, new fault feature records are generated and stored in the fault feature library.

4. The system as described in claim 3, characterized in that, The fault feature library update unit is also used to: receive electronic data records of chips that have failed in terminal applications, and generate or correct fault feature records corresponding to the field failure mode by combining the physical analysis results of the failed chip, thereby realizing closed-loop update of the fault feature library.

5. The system as described in claim 2, characterized in that, The multi-dimensional feature parameters extracted by the feature extraction module include at least one of the following: Transient power consumption curve characteristics of the chip under test when executing specific instructions or switching states; The voltage drop and recovery time of the supply voltage of the chip under test when the load changes; The period jitter or phase jitter parameters of the clock output signal of the chip under test; or In data communication testing, the distribution pattern of error bits within the data packet when an error check fails.

6. The system as described in claim 1, characterized in that, The system also includes a chip lifecycle test data recording subsystem, which includes: The data record generation module is used to generate an independent electronic data record for each chip under test; the electronic data record is associated with the chip's unique identification code and includes at least: the actual test module sequence executed by the test process scheduling unit, the key parameter values ​​acquired by the data acquisition unit during the testing of each module, and the final test conclusion; Data storage unit, used for persistently storing the electronic data records generated by the data record generation module; and The data interface module is used to respond to external system requests and provide query and access to the electronic data records based on the unique identification code.

7. The system as described in claim 6, characterized in that, The electronic data record also includes: the chip's wafer batch number, its location on the wafer, packaging batch information, and the comprehensive performance evaluation result calculated by the system based on all test parameters.

8. The system as described in claim 6, characterized in that, The data interface module is further configured to: provide the electronic data record to a downstream receiving card assembly manufacturing execution system, wherein the manufacturing execution system groups the chips based on the comprehensive performance evaluation results or other key parameter values ​​contained in the electronic data record, and uses the chips in a specific group at a designated location on the receiving card.

9. The system as described in claim 1, characterized in that, The test modules stored in the test module library include at least one of the following: A grayscale linearity test module used to test the grayscale display control accuracy of a chip; A throughput stress test module used to verify the chip's ability to process network packets under a set load; or A signal integrity test module used to evaluate the signal quality of high-speed output ports of chips.

10. The system as claimed in claim 1, characterized in that, The preset set of evaluation rules in the state evaluation unit specifically includes: The first type of evaluation rule defines that when the real-time test data indicates the existence of a preset fatal flaw, the current test state will be determined as the termination state. The second type of evaluation rule defines the current test state as the deep verification state when one or more performance parameter values ​​in the real-time test data are within the edge range of a preset qualified threshold. The third type of evaluation rule defines that when all performance parameter values ​​in the real-time test data are within a preset good range, the current test state is determined to be the standard process state, and the test process scheduling unit is allowed to skip some redundant diagnostic test modules.

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