Calibration system and calibration method for high-speed digital-to-analog converter
By combining the calibration systems of ADC and DAC, and utilizing a reasonable reference clock frequency and multiple calibration methods, the delay and pulse width error problems of high-speed DACs were solved, achieving high-precision digital-to-analog conversion, improving chip performance and reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- JOYWELL SEMICON (SHANGHAI) CO LTD
- Filing Date
- 2025-08-14
- Publication Date
- 2026-06-16
AI Technical Summary
Existing high-speed digital-to-analog converters (DACs) suffer from various errors, especially delay and pulse width errors, which affect system performance. Furthermore, existing calibration techniques are costly and difficult to implement.
By combining ADC and DAC, utilizing a reasonable reference clock frequency and multiple calibration methods, a calibration system is designed, including a sequentially connected transmitter circuit, digital-to-analog converter, analog-to-digital converter, and calibration circuit. Phase delay calibration and pulse width error calibration modules are used to achieve high-precision digital-to-analog conversion.
It achieves high-precision digital-to-analog conversion, reduces DAC latency and pulse width error, improves the performance of the chip's transmitting circuit, is suitable for high-speed chips, and the front-end calibration does not affect power consumption, requiring only the addition of a low-speed ADC and digital circuitry.
Smart Images
Figure CN121036760B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a calibration system and calibration method for a high-speed digital-to-analog converter. Background Technology
[0002] Digital-to-analog converters (DACs) are widely used in electronic systems. Digital circuit systems process and generate discrete digital signals. If information needs to be transmitted through a channel, the discrete digital signals need to be converted into continuous analog signals, processed by analog circuits, and then sent. The input of a DAC is a discrete digital signal, and it generates a summed voltage signal by using the value (0 or 1) of each digital bit and its weight.
[0003] High-speed DACs are essential components of high-speed serial interface chips and incoherent / coherent optical chips, and their sampling accuracy directly determines the overall performance of the chip. Currently, the demand for chip speed is increasing; however, high-speed DACs suffer from various errors that severely degrade chip performance. Especially with the advent of ultra-high-speed DACs, delay and pulse width errors have begun to significantly impact system performance. Current research in academia and industry focuses on optimizing the DAC itself, using superior materials or optimized processes, but this also brings difficulties in engineering implementation and increases costs. In general, there is currently no effective technology for calibrating the various errors of high-speed DACs. Summary of the Invention
[0004] The purpose of this application is to provide a calibration system and method for a high-speed digital-to-analog converter. By combining ADC and DAC, utilizing a reasonable reference clock frequency and multiple calibration methods, a high-precision digital-to-analog converter circuit is achieved, which has high calibration accuracy and realizes phase delay and pulse width error type calibration.
[0005] In a first aspect, this application provides a calibration system for a high-speed digital-to-analog converter (DAC), comprising: a transmitting circuit, a DAC, an analog-to-digital converter (ADC), and a calibration circuit connected in sequence; the ADC is connected to a reference clock generating circuit, the reference clock generating circuit outputs a reference clock to the ADC; the DAC includes multiple sub-DAC units; and the calibration circuit calculates and outputs an error control word to the DAC based on the output data of the ADC to perform corresponding error calibration.
[0006] The sampling relationship between the outputs of the digital-to-analog converter and the analog-to-digital converter and the data signal is determined according to the following formula based on the period PAT of the data signal output by the transmitting circuit, the number of sub-digital-to-analog converter units PHA, and the period CLK of the reference clock:
[0007] mod(PAT, PHA) = m;
[0008] mod(CLK_d, PAT) = n;
[0009] mod(CLK_d, PHA) = s;
[0010] CLK = CLK_d + 0.5T;
[0011] Where mod() represents modulo operation, T represents the time interval of 1 unit, CLK_d is the period of the reference clock CLK minus 0.5T, m represents the remainder after the data signal is cyclically sampled by each sub-digital-to-analog converter unit of the digital-to-analog converter, n+0.5 represents the interval of the sequence number of the data signal corresponding to the output data of the analog-to-digital converter, and s+0.5 represents the interval of the sequence number of the sub-digital-to-analog converter unit corresponding to the output data of the analog-to-digital converter.
[0012] In a preferred embodiment, m equals 1, or m is coprime to both the period PAT of the data signal and the number PHA of the sub-digital-to-analog converter units.
[0013] In a preferred embodiment, n equals 1, or n is coprime to both the CLK_d and the period PAT of the data signal.
[0014] In a preferred embodiment, s equals 1, or s is coprime to both the CLK_d and the number of sub-digital-to-analog converter units PHA.
[0015] In a preferred embodiment, if the reference clock is a non-return-to-zero coded signal, the number of sub-digital-to-analog converter units PHA is 8, the period of the data signal PAT is 41, and the period of the reference clock CLK is 337.5T, then m is 1, n is 9, and s is 1.
[0016] In a preferred embodiment, if the reference clock is a PRBS3 signal, the number of sub-digital-to-analog converter units PHA is 8, the period of the data signal PAT is 91, and the period of the reference clock CLK is 337.5T, then m is 3, n is 64, and s is 1.
[0017] In a preferred embodiment, the calibration circuit includes: a sequence positioning module for the sub-digital-to-analog converter unit and a phase delay calibration module, wherein the phase delay calibration module outputs a delay control word to the digital-to-analog converter; wherein,
[0018] The phase delay calibration module sets the phase delay control word of one of the plurality of sub-digital-to-analog converter units to 0 and obtains the first output data c1 of the plurality of sub-digital-to-analog converter units;
[0019] The phase delay calibration module sets the phase delay control word to b and obtains the second output data c2 of the plurality of sub-digital-to-analog converter units;
[0020] The phase delay calibration module sets the phase delay control word to -b and obtains the third output data c3 of the plurality of sub-digital-to-analog converter units;
[0021] The sequential positioning module calculates the d value of each sub-digital-to-analog converter unit according to d=(c2-c1)+(c1-c3), and the sub-digital-to-analog converter unit with the largest absolute value of d value is the corresponding sub-digital-to-analog converter unit.
[0022] In another embodiment, the phase delay calibration module sets the phase delay control word of one of the plurality of sub-digital-to-analog converter units to 0 and obtains the first output data c1 of the plurality of sub-digital-to-analog converter units;
[0023] The phase delay calibration module sets the phase delay control word to b and obtains the second output data c2 of the plurality of sub-digital-to-analog converter units;
[0024] The phase delay calibration module sets the phase delay control word to 2b and obtains the second output data c2' of the plurality of sub-digital-to-analog converter units;
[0025] The phase delay calibration module sets the phase delay control word to -b and obtains the third output data c3 of the plurality of sub-digital-to-analog converter units;
[0026] The phase delay calibration module sets the phase delay control word to -2b and obtains the third output data c3' of the plurality of sub-digital-to-analog converter units;
[0027] The sequential positioning module calculates the d' value of each sub-digital-to-analog converter unit according to d=(c2+ c2'-c1)+(c1-c3- c3'), where the sub-digital-to-analog converter unit with the largest absolute value of d' is the corresponding sub-digital-to-analog converter unit.
[0028] In a preferred embodiment, the phase delay calibration module calculates the phase delay control word according to hs(n+1) = hs(n) + g*(ye(n)-Vth), where hs(n+1) and hs(n) are the phase delay control words at time n+1 and time n, respectively, g is the adjustment rate, ye(n) is the value of the rising and falling edges of the input data, and Vth is the offset value of the register configuration.
[0029] In a preferred embodiment, the calibration circuit further includes a pulse width error calibration module, which outputs a pulse width error control word to the digital-to-analog converter; the pulse width error calibration module calculates the pulse width error control word according to hm(n+1) = hm(n) + g * [yf(n-1) * (yf(n) - target)] - k, where hm(n+1) and hm(n) are the pulse width error control words at time n+1 and time n, respectively, g is the adjustment rate, yf(n) is the positive maximum value of the data signal, k is a pre-configured correlation value of yf(n-1) and yf(n), and target is the average value of the positive maximum value of the data signal before calibration.
[0030] In a second aspect, this application provides a calibration method for a high-speed digital-to-analog converter (DAC), applicable to a calibration system for a high-speed DAC including a transmitting circuit, a DAC, an analog-to-digital converter (ADC), and a calibration circuit connected in sequence. The ADC is connected to a reference clock generating circuit, which outputs a reference clock to the ADC. The DAC includes multiple sub-DAC units, and the calibration circuit includes a sequence positioning module and a phase delay calibration module for the sub-DAC units. The method includes the following steps:
[0031] The phase delay calibration module sequentially outputs phase delay control words of 0, b, and -b to one of the plurality of sub-digital-to-analog converter units, and the sequence positioning module determines the sub-digital-to-analog converter unit that outputs the first data based on the data c1, c2, and c3 sequentially output by the digital-to-analog converter.
[0032] The calibration circuit determines the sampling relationship between the output of the analog-to-digital converter and the data signal according to the following formula based on the period PAT of the data signal output by the transmitting circuit, the number of sub-digital-to-analog converter units PHA, and the period CLK of the reference clock:
[0033] mod(PAT, PHA) = m;
[0034] mod(CLK_d, PAT) = n;
[0035] mod(CLK_d, PHA) = s;
[0036] CLK = CLK_d + 0.5T; where mod() represents modulo operation, T represents the time interval of 1 unit, CLK_d is the period of the reference clock CLK minus 0.5T, m represents the remainder after the data signal is cyclically sampled by each sub-digital-to-analog converter unit of the digital-to-analog converter, n+0.5 represents the interval of the sequence number of the data signal corresponding to the output data of the analog-to-digital converter, and s+0.5 represents the interval of the sequence number of the sub-digital-to-analog converter unit corresponding to the output data of the analog-to-digital converter;
[0037] The calibration circuit determines the sequence number of the data signal corresponding to the output data of the analog-to-digital converter and the sequence number of the corresponding sub-digital-to-analog converter unit based on the determined sub-digital-to-analog converter unit of the first output data and the sampling relationship, and calculates and outputs the error control word of each sub-digital-to-analog converter unit.
[0038] In one embodiment, before determining the sub-digital-to-analog converter unit for the first output data, the calibration circuit acquires the output data of the analog-to-digital converter and performs amplitude calibration on the output data.
[0039] The embodiments of this application have the following beneficial effects:
[0040] This invention combines an ADC and a DAC, utilizing a suitable reference clock frequency and multiple calibration methods to achieve a high-precision digital-to-analog converter circuit. It boasts high calibration accuracy, achieving phase delay and pulse width error type calibration, thus realizing a high-precision chip transmission circuit and enabling ultra-high-speed data sampling and conversion, suitable for high-speed chips. Furthermore, the pre-processing calibration (performed before the chip's actual operation) has no impact on power consumption, requiring only the addition of a low-speed ADC and digital circuitry, resulting in minimal area impact. This solution effectively reduces DAC delay and pulse width errors, thereby significantly improving DAC accuracy.
[0041] The specification of this application contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these technical features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which should be considered as described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description
[0042] Figure 1 This is a schematic diagram of the structure of a high-speed digital-to-analog converter calibration system according to one embodiment of this application.
[0043] Figure 2 This is a schematic diagram of the calibration process for a high-speed digital-to-analog converter according to one embodiment of this application.
[0044] Figure 3 This is a flowchart illustrating the sequential positioning of sub-DAC units according to one embodiment of this application.
[0045] Figure 4 The results are simulations of the DAC performance before and after calibration at low and high frequencies, based on one embodiment of this application.
[0046] Figure 5 This is a flowchart illustrating a high-speed digital-to-analog converter calibration method according to one embodiment of this application. Detailed Implementation
[0047] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.
[0048] The following is a brief summary of some of the innovative aspects of the embodiments of this application:
[0049] By designing a reasonable data type for the transmitter circuit output, the number of sub-DAC units, and the reference clock frequency, the sampling relationship between the DAC output and the transmitted data signal, as well as the sampling relationship between the ADC output and the transmitted data signal, can be determined. Furthermore, the ADC can completely sample the transmitted data sequence points and the points within 0.5 UI between sequences. Further, dithering and correlation methods are used to sequentially locate the sub-DAC units and identify the DAC signal. The correspondence between the DAC sampled data, the sub-DAC units, and the input data is confirmed by combining the sampling relationship. Based on this, the DAC is calibrated for phase delay and pulse width error.
[0050] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.
[0051] A digital-to-analog converter (DAC) is responsible for converting discrete digital signals into continuous analog signals, which are then sent to subsequent analog circuits for processing, or directly transmitted to the receiving circuit via a channel. To achieve error calibration of a high-speed DAC, this application designs a calibration system based on a high-speed DAC and a high-speed ADC, the block diagram of which is shown below. Figure 1 As shown, the calibration system includes a transmitter circuit 101, a digital-to-analog converter (DAC) 102, an analog-to-digital converter (ADC) 103, a DAC calibration circuit 104, and a reference clock generation circuit 105. The transmitter circuit 101, DAC 102, ADC 103, and DAC calibration circuit 104 are sequentially coupled. The transmitter circuit 101 outputs a discrete digital signal to the DAC 102. The DAC 102 includes multiple sub-DAC units (not shown in the figure). The reference clock generation circuit 105 is coupled to the ADC 103. The calibration circuit calculates and outputs an error control word to the DAC 102 based on the output data of the ADC 103 to perform corresponding error calibration. A detailed description of the calibration process is provided below.
[0052] The transmitting circuit 101 sends a data signal to the DAC 102 according to the control signal of the calibration circuit 104. There are two data types of data signals. The first is an NRZ signal, which first sends a certain number of positive maximum signals, followed by a certain number of negative maximum signals. In this embodiment, one cycle includes 21 positive maximum signals and 20 negative maximum signals. The second is an extended PRBS signal. In this embodiment, a 3x period PRBS3 is used (PRBS3 is 0010111, and 3x extension is 000 000 111000 111 111 111). The sent data signal is sent to the DAC 102 after passing through a serial-to-parallel conversion circuit. After being converted into an analog signal, it is sent to the ADC 103, then converted into a digital signal and sent to the calibration circuit 104 for calibration. The output data of the ADC 103 is converted into parallel data by a register and sent to the calibration circuit. In this embodiment, the parallelism is 8, but it is not limited to 8. The DAC 102 consists of multiple sub-DAC units. In this embodiment, it is set to 8, but it is not limited to 8; for example, it can also be set to 4 or 16, etc. The sub-DAC unit samples the data signals output by the transmitter in sequence and combines them into the final transmitted data.
[0053] The reference clock generation circuit generates a reference clock, which is sent to ADC 103 and serves as the sampling trigger signal for ADC 103. To ensure that each sub-DAC unit can sample every unit of the clock signal or PRBS signal (each positive and negative maximum, 1UI), as well as the midpoint of adjacent unit signals (0.5UI position), a specially designed reference clock frequency of 337.5T is required. In this embodiment, it is set to 337.5T, but it is not limited to 337.5T. The digital-to-analog converter calibration circuit 104 analyzes the input data to obtain the phase delay error control word and pulse width error control word, which are then sent to DAC 102 for calibration.
[0054] The period of the data signal output by the transmitting circuit 101 is defined as PAT, the number of sub-DAC units is defined as PHA, and the period of the reference clock is defined as CLK. The sampling relationship between the output of DAC 102 and the data signal, and the sampling relationship between the output of ADC 103 and the data signal are determined according to the following formulas (1)-(4):
[0055] mod(PAT, PHA) = m (1)
[0056] mod(CLK_d, PAT) = n (2)
[0057] mod(CLK_d, PHA) = s (3)
[0058] CLK = CLK_d +0.5T (4)
[0059] Where mod() represents the modulo operation, T represents the time of one unit interval (UI), CLK_d is the period of the reference clock CLK minus 0.5T, and CLK_d is an integer. m equals 1, or m is coprime to both the period PAT of the data signal and the number of sub-DAC units PHA. n equals 1, or n is coprime to both CLK_d and the period PAT of the data signal. s equals 1, or s is coprime to both CLK_d and the number of sub-DAC units PHA.
[0060] Understandably, 'm' represents the remainder after the data signal is cyclically sampled by each sub-DAC unit of DAC 102. For example, if the data signal period PAT is 41 and the number of sub-DAC units is 8, the data signal will have 1 data point remaining after being cyclically sampled by the 8 sub-DAC units for 5 rounds. Or, if the data signal period PAT is 91 and the number of sub-DAC units is 8, the data signal will have 3 data points remaining after being cyclically sampled by the 8 sub-DAC units for 11 rounds. 'n+0.5' represents the interval of the data signal sequence number corresponding to the output data of ADC 103, and 's+0.5' represents the interval of the sub-DAC unit sequence number corresponding to the output data of ADC 103. Since the data signal output from the transmitting end has been converted into a continuous analog signal after passing through DAC 102, it can be sampled at intervals of 0.5.
[0061] If the reference clock is a Non-Return-to-Zero (NRZ) coded signal, the number of sub-DAC units (PHA) is 8, the data signal period (PAT) is 41, and the reference clock period (CLK) is 337.5T, then m is 1, n is 9, and s is 1. Therefore, the remainder after the data signal is cyclically sampled by each sub-DAC unit of DAC 102 is 1. The interval between the sequence numbers of the data signals corresponding to the output data of ADC 103 is 9.5, and the interval between the sequence numbers of the sub-DAC units corresponding to the output data of ADC 103 is 1.5. The sampling relationship between ADC and DAC under NRZ signal is shown in Table 1 below.
[0062] Table 1. Sampling relationship between ADC and DAC under clock (NRZ) signal
[0063]
[0064] The input signal sequence number corresponds to which data point in the data signal output by the transmitting circuit 101 is being processed, and the sub-DAC unit sequence number corresponds to the first sub-DAC unit outputting the data. Specifically, in the sampling relationship of DAC 102, input data sequence number 0 indicates that the data is the first data point in the data signal output by the transmitting circuit 101, sub-DAC unit sequence number 0 indicates that the data is the first sub-DAC unit outputting the data, and so on. The input data sequence number increments by 1 until it reaches a maximum value of 40, then restarts the incrementing process from 0. The sub-DAC unit sequence number increments by 1 until it reaches a maximum value of 7, then restarts the incrementing process from 0. In the sampling relationship of ADC 103, input data sequence number 0 indicates that the data is the first data in the data signal output by transmitting circuit 101, sub-DAC unit sequence number 0 indicates that the data is output by the first sub-DAC unit, input data sequence number 9.5 indicates that the data is the 10.5th data in the data signal output by transmitting circuit 101, sub-DAC unit sequence number 1.5 indicates that the data is output by the 2.5th sub-DAC unit, and so on. The input data sequence number is incremented by 9.5. When the accumulated value is greater than 40, 41 is subtracted from the accumulated value (i.e., PAT), and the incrementing starts again from 9.5. For example, input data sequence number 38 incremented by 9.5 equals 47.5, which is greater than 40. After subtracting 41 from 47.5, the incrementing starts again from the calculated result of 6.5. The sub-DAC unit numbers are incremented by 1.5. When the incremented value is greater than 7, 8 (i.e., PHA) is subtracted from the incremented value, and the incrementing starts again from 1.5. For example, if the sub-DAC unit number is 7.5 and then incremented by 1.5, it equals 9. Since the result is greater than 7, 8 is subtracted from 9, and the incrementing starts again from the calculated result of 1.
[0065] If the reference clock is the PRBS3 signal, the number of sub-DAC units (PHA) is 8, the data signal period (PAT) is 91, and the reference clock period (CLK) is 337.5T, then m is 3, n is 64, and s is 1. Therefore, the remainder after the data signal is cyclically sampled by each sub-DAC unit of DAC 102 is 3, the interval between the sequence numbers of the data signals corresponding to the output data of ADC 103 is 64.5, and the interval between the sequence numbers of the sub-DAC units corresponding to the output data of ADC 103 is 1.5. The sampling relationship between ADC and DAC under a 3x extended PRBS signal is shown in Table 2 below.
[0066] Table 2. Sampling relationship between ADC and DAC for 3x extended PRBS signal
[0067]
[0068] The key difference between the sampling relationships of the 3x extended PRBS signal and the NRZ signal lies in the sampling relationship of the ADC103. While the remainder *m* differs in the sampling relationship of the DAC102, the progression of the sequence numbers remains unchanged. Specifically, in the sampling relationship of the DAC102, input data sequence number 0 indicates that the data is the first data in the data signal output by the transmitting circuit 101; sub-DAC unit sequence number 0 indicates that the data is output by the first sub-DAC unit, and so on. The input data sequence number increments by 1 until it reaches a maximum value of 90, then restarts the incrementing from 0. The sub-DAC unit sequence number increments by 1 until it reaches a maximum value of 7, then restarts the incrementing from 0. In contrast, in the sampling relationship of the ADC103, input data sequence number 0 indicates that the data is the first data in the data signal output by the transmitting circuit 101; input data sequence number 64.5 indicates that the data is the 65.5th data in the data signal output by the transmitting circuit 101, and so on. The input data sequence number is incremented by 64.5. When the accumulated value is greater than 90, 91 is subtracted from the accumulated value (i.e., PAT), and the incrementing process restarts at 64.5. For example, if the input data sequence number is 64.5 and the increment is 64.5, the result is 129, which is greater than 90. 41 is subtracted from 129, and the incrementing process restarts at the calculated result of 38. The correspondence between the sub-DAC unit numbers of the ADC 103 under the 3x extended PRBS signal is similar to that of the NRZ signal, and will not be elaborated here.
[0069] By designing a reasonable data type, number of sub-DAC units, and reference clock frequency for the output of the transmitting circuit, the sampling relationship shown in the table above can be achieved. The ADC can completely sample the NRZ sequence points and the points 0.5UI between sequences (or the PRBS sequence points and the points 0.5UI between sequences), which is the basis for the implementation of subsequent calibration methods.
[0070] The calibration circuit 104 includes an ADC amplitude calibration module, a sub-DAC unit sequence positioning module, a phase delay calibration module, and a pulse width error calibration module. The phase delay calibration module outputs a delay control word to DAC 102. The pulse width error calibration module outputs a pulse width error control word to DAC 102. The calibration process of DAC 102 by the calibration circuit 104 is as follows: Figure 2 As shown. First, the ADC amplitude is calibrated to match the ranges of DAC 102 and ADC 103, and to avoid amplitude fluctuations caused by external interference. Because there is a certain delay between DAC 102 and ADC 103, and then to the calibration circuit 104, it is impossible to know which sub-DAC unit the first data received in the calibration circuit 104 originates from. Therefore, the sub-DAC unit sequence needs to be determined. After the sequence determination is completed, the phase delay and pulse width error are calibrated sequentially.
[0071] Under normal transmission sequences, although it can be determined that the sub-DAC units sample in the order of 01234567, due to circuit delays, it is impossible to know which sub-DAC unit the first data received in the calibration circuit 104 originates from. In other words, the starting point of this sequence is unknown. Therefore, sub-DAC unit sequence positioning is required. The sub-DAC unit sequence positioning process is as follows: Figure 3 As shown, this embodiment uses dithering and correlation to locate the order of sub-DAC units. For the phase delay control word, this embodiment sets a dithering sequence of the phase delay control word in the [0 b - b] sequence. First, the phase delay word of sub-DAC unit 1 is set to 0 (no phase compensation), and then the output values c1 of the 8 sub-DAC units at fixed rising edge positions are sampled. Then, the phase delay control word of sub-DAC unit 1 is set to b (positive compensation), and the output values c2 of the 8 sub-DAC units at fixed rising edge positions are sampled again. Finally, the control word of sub-DAC unit 1 is set to the default value -b (reverse compensation), and the DAC output value c3 at the same position is sampled. Throughout the process, the phase delay control words of all sub-DAC units except sub-DAC unit 1 remain unchanged. c1, c2, and c3 each have 8 values, each including the output result of each of the 8 sub-DAC units. Then, using a correlation method, d = (c2 - c1) + (c1 - c3), where d also has 8 values, each corresponding to one sub-DAC unit. The value with the largest absolute value in d corresponds to sub-DAC unit 1 (the first sub-DAC unit). Therefore, the starting point of the sub-DAC unit sampling sequence can be obtained. Combining this with the above sampling relationship, the calibration circuit 104 can determine which sub-DAC unit sampled each of the eight data points sent to the calibration circuit. Simultaneously, since the sampling point is a fixed rising edge, the calibration circuit 104 can also determine which bit in the clock sequence the data sent to the calibration circuit corresponds to. In this example, the phase delay control word jitter sequence is set to [0 b - b]. It can also be set to [0 b 2*b - b 2b], etc., as long as there are delay words in three directions: positive, negative, and 0.
[0072] The phase delay and pulse width error calibration methods include: obtaining the error by sampling the value at a specific position of the input data, sending the error to the update circuit, and using the LMS algorithm to obtain the error control word. Simultaneously, the location of the specific position of the input data is directly obtained using the result of the sequential positioning method of the sub-DAC unit. The phase delay uses the rising and falling edges of the input data, and the pulse width error calibration uses the maximum positive value of the input data. The calculation methods for the two control words are shown in formulas (5) and (6):
[0073] Phase delay: hs(n+1) = hs(n) + g*(ye(n)-Vth) (5)
[0074] Pulse width error: hm(n+1) = hm(n) + g* [yf(n-1)*(yf(n)-target)] - k (6)
[0075] Where hs(n+1) and hs(n) are the phase delay control words at times n+1 and n, respectively, and hm(n+1) and hm(n) are the pulse width error control words at times n+1 and n, respectively. g is the adjustment rate, which can be adaptively adjusted according to the duration. ye(n) are the values of the rising and falling edges of the input data, and Vth is the offset value configured in the register. yf(n) is the maximum positive value of the input data, and k is the pre-configured correlation value of yf(n-1) and yf(n), which is strongly correlated with the bandwidth. target is the average value of the maximum positive values of the input data calculated in advance before calculating the calibration value.
[0076] Using MATLAB simulation, relevant errors and jitter were added to the high-speed DAC. It can be seen that the accuracy of the calibrated DAC is significantly improved, and the phase delay and pulse width error are reduced from about 1 ps to about 50 fs. Figure 4 The performance results of the DAC before and after calibration at low frequency (0.93 GHz) and high frequency (55.84 GHz) are presented (with clock jitter, 8-bit DAC). The DAC results before low-frequency calibration are shown below. Figure 4 As shown in (a), the signal-to-noise ratio (SNDR) and spurious-free dynamic range (SFDR) are 20.8 dB and 25.9 dB, respectively. The DAC results after low-frequency calibration are as follows. Figure 4 As shown in (c), sndr and sfdr are 40.6dB and 51.2dB respectively. The DAC results before high-frequency calibration are as follows. Figure 4 As shown in (b), sndr and sfdr are 10.5dB and 15.5dB respectively. The DAC results after high-frequency calibration are as follows. Figure 4 As shown in (d), sndr and sfdr are 37.1dB and 48.7dB, respectively. It can be seen that the performance has been significantly improved after calibration.
[0077] This application also provides a calibration method for a high-speed DAC 102, applicable to the calibration system for the high-speed DAC described above, the flowchart of which is shown below. Figure 5 As shown, the method includes the following steps:
[0078] Step 201: The phase delay calibration module sequentially outputs phase delay control words of 0, b and -b to one of the multiple sub-DAC units. The sequence positioning module determines the sub-DAC unit that outputs the first data based on the data c1, c2 and c3 sequentially output by DAC 102.
[0079] Specifically, the sub-DAC unit for determining the first output data is implemented using the following steps:
[0080] The phase delay calibration module sets the phase delay control word of one of the multiple sub-DAC units to 0, while keeping the calibration words of the other sub-DAC units unchanged, and obtains the first output data c1 of the multiple sub-DAC units;
[0081] The phase delay calibration module sets the phase delay control word to b, while the calibration words of other sub-DAC units remain unchanged, and obtains the second output data c2 of multiple sub-DAC units;
[0082] The phase delay calibration module sets the phase delay control word to -b, while the calibration words of other sub-DAC units remain unchanged, and obtains the third output data c3 of multiple sub-DAC units;
[0083] The sequential positioning module calculates the d value of each sub-DAC unit according to d=(c2-c1)+(c1-c3), and the sub-DAC unit with the largest absolute value of d value is the corresponding sub-DAC unit.
[0084] In another embodiment, the sub-DAC unit that determines the first output data is implemented using the following steps:
[0085] The phase delay calibration module sets the phase delay control word of one of the multiple sub-DAC units to 0, while keeping the calibration words of the other sub-DAC units unchanged, and obtains the first output data c1 of the multiple sub-DAC units;
[0086] The phase delay calibration module sets the phase delay control word to b, while the calibration words of other sub-DAC units remain unchanged, and obtains the second output data c2 of multiple sub-DAC units;
[0087] The phase delay calibration module sets the phase delay control word to 2b, while the calibration words of other sub-DAC units remain unchanged, and obtains the second output data c2' of multiple sub-DAC units;
[0088] The phase delay calibration module sets the phase delay control word to -b, while the calibration words of other sub-DAC units remain unchanged, and obtains the third output data c3 of multiple sub-DAC units;
[0089] The phase delay calibration module sets the phase delay control word to -2b, while keeping the calibration words of other sub-DAC units unchanged, and obtains the third output data c3' of multiple sub-DAC units;
[0090] The sequential positioning module calculates the d' value of each sub-DAC unit according to d=(c2+ c2'-c1)+(c1-c3- c3'), and the sub-DAC unit with the largest absolute value of d' is the corresponding sub-DAC unit.
[0091] Step 202, the calibration circuit 104 determines the sampling relationship between the output of ADC 103 and the data signal according to the following formula based on the period PAT of the data signal output by the transmitting circuit 101, the number of sub-DAC units PHA, and the period CLK of the reference clock:
[0092] mod(PAT, PHA) = m;
[0093] mod(CLK_d, PAT) = n;
[0094] mod(CLK_d, PHA) = s;
[0095] CLK = CLK_d + 0.5T; where mod() represents modulo operation, T represents the time interval of 1 unit, CLK_d is the period of the reference clock CLK minus 0.5T, m represents the remainder after the data signal is cyclically sampled by each sub-DAC unit of the DAC, n+0.5 represents the interval of the sequence number of the data signal corresponding to the output data of ADC 103, and s+0.5 represents the interval of the sequence number of the sub-DAC unit corresponding to the output data of ADC 103.
[0096] In step 203, the calibration circuit 104 determines the sequence number of the data signal corresponding to the output data of the ADC 103 and the sequence number of the corresponding sub-DAC unit based on the determined sub-DAC unit and sampling relationship of the first output data, and calculates and outputs the error control word of each sub-DAC unit.
[0097] In one embodiment, before determining the sub-DAC unit for the first output data, the calibration circuit 104 acquires the output data of the ADC 103 and performs amplitude calibration on the output data.
[0098] In summary, this application uses a clock signal coprime to the sampling clock frequency and an extended PRBS3 signal as input signals to ensure that each sub-DAC unit can sample every signal point. Furthermore, a sub-DAC unit jitter method is used to identify the DAC signal, confirming the correspondence between the DAC sampled data, the sub-DAC units, and the input data. Further, a fixed-point comparison and correlation method is employed to calibrate phase delay and pulse width errors, and this method has a high tolerance for system clock jitter.
[0099] It should be noted that in this patent application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this patent application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.
[0100] The term “coupled to” and its derivatives may be used in this document. “Coupled” can mean two or more elements in direct physical or electrical contact. However, “coupled” can also mean two or more elements in indirect contact with each other, but still cooperating or interacting with each other, and can mean one or more other elements coupled or connected between elements referred to as being coupled to each other.
[0101] All references to this specification are considered to be incorporated integrally into the disclosure of this application so that they can serve as the basis for modifications if necessary. Furthermore, it should be understood that the above descriptions are merely preferred embodiments of this specification and are not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of one or more embodiments of this specification.
Claims
1. A calibration system for a high-speed digital-to-analog converter, characterized in that, include: The transmitter circuit, digital-to-analog converter, analog-to-digital converter, and calibration circuit are connected in sequence. The analog-to-digital converter is connected to a reference clock generation circuit, which outputs a reference clock to the analog-to-digital converter. The digital-to-analog converter includes multiple sub-digital-to-analog converter units. The calibration circuit calculates and outputs an error control word to the digital-to-analog converter based on the output data of the analog-to-digital converter to perform corresponding error calibration. The sampling relationship between the outputs of the digital-to-analog converter and the analog-to-digital converter and the data signal is determined according to the following formula based on the period PAT of the data signal output by the transmitting circuit, the number of sub-digital-to-analog converter units PHA, and the period CLK of the reference clock: mod(PAT, PHA) = m; mod(CLK_d, PAT) = n; mod(CLK_d, PHA) = s; CLK = CLK_d + 0.5T; Where mod() represents modulo operation, T represents the time interval of 1 unit, CLK_d is the period of the reference clock CLK minus 0.5T, m represents the remainder after the data signal is cyclically sampled by each sub-digital-to-analog converter unit of the digital-to-analog converter, n+0.5 represents the interval of the sequence number of the data signal corresponding to the output data of the analog-to-digital converter, and s+0.5 represents the interval of the sequence number of the sub-digital-to-analog converter unit corresponding to the output data of the analog-to-digital converter; The calibration circuit includes a sequential positioning module for the sub-digital-to-analog converter units and a phase delay calibration module. The phase delay calibration module outputs a delay control word to the digital-to-analog converter. Specifically, the phase delay calibration module sequentially outputs phase delay control words of 0, b, and -b to each of the plurality of sub-digital-to-analog converter units. The sequential positioning module calculates the d value corresponding to each sub-digital-to-analog converter unit using the formula d=(c2-c1)+(c1-c3) based on the data c1, c2, and c3 sequentially output by the plurality of sub-digital-to-analog converters. The sub-digital-to-analog converter unit corresponding to the d value with the largest absolute value is determined as the sub-digital-to-analog converter unit that outputs the first data.
2. The calibration system as described in claim 1, characterized in that, m equals 1, or m is coprime to both the period PAT of the data signal and the number PHA of the sub-digital-to-analog converter units.
3. The calibration system as described in claim 1, characterized in that, n equals 1, or n is coprime to both the CLK_d and the period PAT of the data signal.
4. The calibration system as described in claim 1, characterized in that, s equals 1, or s is coprime to both the CLK_d and the number of sub-digital-to-analog converter units PHA.
5. The calibration system as described in claim 1, characterized in that, If the reference clock is a non-return-to-zero coded signal, the number of sub-digital-to-analog converter units PHA is 8, the period of the data signal PAT is 41, and the period of the reference clock CLK is 337.5T, then m is 1, n is 9, and s is 1.
6. The calibration system as described in claim 1, characterized in that, If the reference clock is a PRBS3 signal with a 3x extension, the number of sub-digital-to-analog converter units PHA is 8, the period of the data signal PAT is 91, and the period of the reference clock CLK is 337.5T, then m is 3, n is 64, and s is 1.
7. The calibration system as described in claim 1, characterized in that, The calibration circuit includes: a sequence positioning module and a phase delay calibration module for the sub-digital-to-analog converter unit; the phase delay calibration module outputs a delay control word to the digital-to-analog converter. The phase delay calibration module sets the phase delay control word of one of the plurality of sub-digital-to-analog converter units to 0 and obtains the first output data c1 of the plurality of sub-digital-to-analog converter units; The phase delay calibration module sets the phase delay control word to b and obtains the second output data c2 of the plurality of sub-digital-to-analog converter units; The phase delay calibration module sets the phase delay control word to -b and obtains the third output data c3 of the plurality of sub-digital-to-analog converter units; The sequential positioning module calculates the d value of each sub-digital-to-analog converter unit according to d=(c2-c1)+(c1-c3), and the sub-digital-to-analog converter unit with the largest absolute value of d value is the corresponding sub-digital-to-analog converter unit.
8. The calibration system as described in claim 7, characterized in that, The phase delay calibration module calculates the phase delay control word according to hs(n+1) = hs(n) + g*(ye(n)-Vth), where hs(n+1) and hs(n) are the phase delay control words at time n+1 and time n, respectively, g is the adjustment rate, ye(n) is the value of the rising and falling edges of the input data, and Vth is the offset value configured in the register.
9. A calibration method for a high-speed digital-to-analog converter, characterized in that, A calibration system is applicable to a high-speed digital-to-analog converter (DAC) comprising a sequentially connected transmitting circuit, a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), and a calibration circuit. The ADC is connected to a reference clock generation circuit, which outputs a reference clock to the ADC. The DAC includes multiple sub-DAC units, and the calibration circuit includes a sequential positioning module and a phase delay calibration module for the sub-DAC units. The method includes the following steps: The phase delay calibration module sequentially outputs phase delay control words of 0, b, and -b to each of the plurality of sub-digital-to-analog converter units. The sequence positioning module calculates the d value corresponding to each sub-digital-to-analog converter unit according to the data c1, c2, and c3 sequentially output by the plurality of sub-digital-to-analog converters using the formula d=(c2-c1)+(c1-c3). The sub-digital-to-analog converter unit corresponding to the d value with the largest absolute value is determined as the sub-digital-to-analog converter unit that outputs the first data. The calibration circuit determines the sampling relationship between the output of the analog-to-digital converter and the data signal according to the following formula based on the period PAT of the data signal output by the transmitting circuit, the number of sub-digital-to-analog converter units PHA, and the period CLK of the reference clock: mod(PAT, PHA) = m; mod(CLK_d, PAT) = n; mod(CLK_d, PHA) = s; CLK = CLK_d + 0.5T; where mod() represents modulo operation, T represents the time interval of 1 unit, CLK_d is the period of the reference clock CLK minus 0.5T, m represents the remainder after the data signal is cyclically sampled by each sub-digital-to-analog converter unit of the digital-to-analog converter, n+0.5 represents the interval of the sequence number of the data signal corresponding to the output data of the analog-to-digital converter, and s+0.5 represents the interval of the sequence number of the sub-digital-to-analog converter unit corresponding to the output data of the analog-to-digital converter; The calibration circuit determines the sequence number of the data signal corresponding to the output data of the analog-to-digital converter and the sequence number of the corresponding sub-digital-to-analog converter unit based on the determined sub-digital-to-analog converter unit of the first output data and the sampling relationship, and calculates and outputs the error control word of each sub-digital-to-analog converter unit.
10. The calibration method as described in claim 9, characterized in that, Before determining the first output data of the sub-digital-to-analog converter unit, the calibration circuit acquires the output data of the analog-to-digital converter and performs amplitude calibration on the output data.