A miniature LED display chip

Abstract

This application discloses a micro LED display chip including a light-emitting mesa array. The light-emitting mesa array includes multiple light-emitting mesa units, each of which includes: a micro-light-emitting mesa, which, from bottom to top, includes a first semiconductor layer, an active layer, and a second semiconductor layer; a material layer covering the sidewalls of the micro-light-emitting mesa; and a conductive layer covering the top of the micro-light-emitting mesa and the surface of the material layer. This micro LED display chip can improve the electroluminescent efficiency of the light-emitting mesa units and increase the yield.

Description

Technical Field

[0001] This application relates to the field of micro LEDs, and further to micro LED display chips. Background Technology

[0002] Micro LED (Micro Light Emitting Diode), also known as micro light-emitting diode, micro LED, or μ-LED, is a display chip that consists of an array of micro LEDs containing multiple pixel elements. The distance between the LED pixels in the array is on the order of 100 nanometers to 100 micrometers, and each micro LED pixel is self-emissive.

[0003] Micro-LEDs are becoming increasingly important due to their potential applications, including self-emitting microdisplays, visible light communication, and optogenetics. They offer superior output performance compared to conventional LEDs due to their better strain relaxation, light extraction efficiency, and uniform current spread. Micro-LEDs also exhibit several advantages over conventional LEDs, such as improved thermal performance, faster response times, a wider operating temperature range, higher resolution, a wider color gamut, higher contrast, lower power consumption, and operability at higher current densities.

[0004] Micro-LED displays, based on micro-LEDs, are much smaller than traditional LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode) displays, and are therefore used in automotive displays, wearable products, smartwatches, VR / AR, and other fields. Typically, micro-LED arrays are fabricated by etching III-V epitaxial layers to form multiple mesa.

[0005] However, existing micro LED display chips have complex structures and high production costs, and there is an urgent need for a micro LED display chip with optimized structure and lower cost. Summary of the Invention

[0006] To address one or more of the aforementioned technical problems, this application provides a micro LED display chip comprising a pixel array, wherein the pixel array includes multiple light-emitting mesa units, each light-emitting mesa unit comprising: a micro-light-emitting mesa, wherein the micro-light-emitting mesa sequentially comprises, from bottom to top, a first semiconductor layer, an active layer, and a second semiconductor layer; a material layer covering the sidewalls of the micro-light-emitting mesa; and a conductive layer covering the top of the micro-light-emitting mesa and the surface of the material layer. This micro LED display chip can improve the electroluminescent efficiency of the light-emitting mesa units and can improve the yield rate.

[0007] In some embodiments, the light-emitting mesa unit further includes: an electrode layer disposed on top of the micro-light-emitting mesa; the conductive layer further includes a first conductive layer covering the surface of the electrode layer and at least a portion of the top of the micro-light-emitting mesa not covered by the electrode layer; and a second conductive layer covering the surface of the first conductive layer and the surface of the material layer.

[0008] In some embodiments, the light-emitting mesa unit further includes a top material layer located above the top edge region of the micro-light-emitting mesa, the material layer covering the outer sidewall of the top material layer, a second conductive layer covering the inner sidewall of the top material layer, and an electrode layer located above the middle region of the top surface of the micro-light-emitting mesa.

[0009] In some embodiments, the light-emitting mesa unit is a first light-emitting mesa unit, and the light-emitting mesa array further includes a plurality of second light-emitting mesa units located on the periphery of the light-emitting mesa array. The second light-emitting mesa units are not electrically conductive, thereby protecting the light-emitting mesa array from being etched or cut and damaged.

[0010] In some embodiments, the active layer is doped with one or more doping elements, which are doped in the active layer by a combination of uniform doping and gradient doping.

[0011] In some embodiments, the active layer includes a plurality of quantum well layers and a plurality of quantum barrier layers spaced apart from each other. The active layer is doped with one or more doping elements, which are doped in the active layer through spaced doping. The active layer of this application can effectively control stress and / or wavelength. Attached Figure Description

[0012] The above and other objects, features and advantages of this disclosure will become more apparent from the more detailed description of exemplary embodiments thereof taken in conjunction with the accompanying drawings, wherein like reference numerals generally denote like parts.

[0013] Figure 1 This is a top view of a micro LED display chip according to some embodiments of this application;

[0014] Figure 2 A top view schematic diagram of a light-emitting mesa array according to some embodiments of the present disclosure is shown;

[0015] Figure 3 This is a cross-sectional structural diagram of two adjacent light-emitting platform units arranged side by side according to some embodiments of this application;

[0016] Figure 4A top view schematic diagram of the bottom metal layer and the micro-light-emitting platform according to some embodiments of the present disclosure is shown;

[0017] Figures 5A to 5E Schematic diagrams showing the cross-sectional distance relationship between the metal structure and the micro-luminescent mesa in different embodiments are shown respectively;

[0018] Figure 6A A schematic diagram of the metal structure and light-emitting platform unit according to an embodiment of this application is shown in a top view.

[0019] Figure 6B A schematic diagram of the metal structure and light-emitting mesa unit in a light-emitting mesa array according to an embodiment of this application is shown in a top view.

[0020] Figure 7A This is a cross-sectional structural diagram of two adjacent light-emitting platform units arranged side by side according to some embodiments of this application;

[0021] Figure 7B This is a cross-sectional structural diagram of two adjacent light-emitting platform units arranged side by side according to some embodiments of this application;

[0022] Figure 8A and Figure 8B Top views of the micro-light-emitting platform in different embodiments are shown respectively;

[0023] Figure 9 This is a cross-sectional schematic diagram of a micro-light-emitting mesa and a light-emitting mesa unit according to some embodiments of this application;

[0024] Figure 10 This is a top view schematic diagram of a micro-light-emitting mesa and a light-emitting mesa unit according to some embodiments of this application;

[0025] Figure 11 This is a schematic diagram of the structure of a micro-light-emitting mesa according to some embodiments of this application;

[0026] Figure 12 This is a cross-sectional structural diagram of three adjacent light-emitting platform units arranged side by side according to some embodiments of this application;

[0027] Figure 13 A schematic diagram of the horizontal outline of the microlens 1201 and the light-emitting platform 310 is shown;

[0028] Figure 14 This is a top view of a micro LED display chip 1400 according to some embodiments of this application;

[0029] Figures 15A to 15C A schematic diagram of the structure of a second light-emitting platform unit according to different embodiments of the present application is shown;

[0030] Figure 16 This is a schematic diagram of the structure of a micro-light-emitting mesa according to some embodiments of this application;

[0031] Figures 17A to 17C The diagram illustrates the relationship between doping concentration and active layer growth height in different embodiments combining uniform doping and gradient doping according to some embodiments of this application.

[0032] Figure 18A and Figure 18B A schematic diagram showing the relationship between doping concentration and active layer growth height in different embodiments of spacer doping according to some embodiments of this application is illustrated. Detailed Implementation

[0033] Preferred embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0034] Some embodiments of this application provide a micro LED display chip that can effectively improve the luminous efficiency and yield of the light-emitting platform.

[0035] Figure 1 This is a top view schematic diagram of a micro LED display chip 100 according to some embodiments of this application. (Refer to...) Figure 1 The micro LED display chip 100 includes a mesa array 110 and an IC (integrated circuit) backplane 120. The mesa array 110 is located on the IC backplane 120 to form the image display area of ​​the micro LED display chip 100. The remaining area of ​​the IC backplane 120 not covered by the mesa array 110 is formed as a non-functional area. The IC backplane 120 is formed on the back side of the mesa array 110 and extends partially beyond the mesa array 110, i.e., partially not covered by the mesa array 110. The mesa array 110 includes a plurality of mesa units 130 disposed in the array. The IC backplane 120 is configured to control the plurality of mesa units 130.

[0036] Figure 2 A top view schematic diagram of a light-emitting mesa array 200 according to some embodiments of the present disclosure is shown. (Refer to...) Figure 2The light-emitting mesa array 200 includes multiple light-emitting mesa units 210, each of which includes at least one micro LED 211. The light-emitting mesa array 200 includes multiple light-emitting mesa units arranged laterally along the X-axis (also referred to as rows) and multiple light-emitting mesa units arranged longitudinally along the Y-axis (also referred to as columns). It is understood that the X-axis and Y-axis here are only for ease of describing relative relationships and do not define the absolute positions of the light-emitting mesa units. The number of light-emitting mesa units in each row and the number of light-emitting mesa units in each column can be the same or different.

[0037] Figure 3 This is a cross-sectional structural diagram of two adjacent light-emitting platform units arranged side by side according to some embodiments of this application. Figure 3 As shown, each light-emitting mesa unit 300 includes a micro-light-emitting mesa 310, which, from bottom to top, includes a first semiconductor layer 311, an active layer 312, and a second semiconductor layer 313. In some embodiments, the first semiconductor layer 311 is an N-type semiconductor layer, the second semiconductor layer 313 is a P-type semiconductor layer, and the active layer 312 is a light-emitting layer. In some embodiments, the active layer 312 is a multiple quantum well (MQW) layer. The active layer 312 can emit blue, green, or red light.

[0038] The light-emitting mesa unit 300 further includes a material layer 320 covering the sidewalls of the micro-light-emitting mesa 310, i.e., the material layer 320 surrounds and encloses the micro-light-emitting mesa 310, and a conductive layer 340 covering the top of the micro-light-emitting mesa 310 and the surface of the material layer 320. In some embodiments, the light-emitting mesa unit 300 further includes an electrode layer 330 disposed on the top of the micro-light-emitting mesa 310, i.e., on the top of the second semiconductor layer 313. In some embodiments, the electrode layer 330 is centrally disposed on the top surface of the second semiconductor layer 313. In some embodiments, the ratio of the maximum width of the electrode layer 330 in the horizontal direction to the maximum width of the top of the micro-light-emitting mesa 310 in the horizontal direction ranges from 35% to 67%, such as 45%, 50%, 60%, etc. This horizontal direction is parallel to the light-emitting surface of the micro-light-emitting mesa, i.e., parallel to the top surface of the micro-light-emitting mesa 310. In some embodiments, the ratio of the area of ​​the electrode layer 330 to the area of ​​the top surface of the micro-light-emitting mesa 310 is 12% to 45%, such as 13%, 15%, 20%, 25%, 28%, 30%, 33%, 35%, 40%, 45%, etc., preferably 30%. The electrode layer configuration in the embodiments of this application ensures that the voltage of the electrode layer is not too high and reduces the impact of the electrode layer on light shading, thus ensuring the light extraction efficiency of the micro-light-emitting mesa. In some embodiments, the maximum width of the electrode layer 330 in the horizontal direction ranges from 0.6 micrometers to 1 micrometer, such as 0.6 micrometers, 0.7 micrometers, 0.9 micrometers, 1 micrometer, etc., and the maximum width of the top of the micro-light-emitting mesa 310 in the horizontal direction ranges from 1.5 micrometers to 1.7 micrometers, such as 1.5 micrometers, 1.6 micrometers, 1.7 micrometers, etc. In some embodiments, the micro-light-emitting mesa 310 is a truncated cone, and the top surface of the micro-light-emitting mesa 310 is circular, with its maximum width in the horizontal direction being the diameter of the top surface. In some embodiments, the electrode layer 330 is also circular, and its maximum width in the horizontal direction is the diameter of the electrode layer 330, that is, the diameter of the electrode layer 330 ranges from 0.6 micrometers to 1 micrometer.

[0039] In some embodiments, the electrode layer 330 is made of one or more of gold-germanium alloy (AuGe alloy), gold-germanium-nickel alloy (AuGeNi alloy), and indium tin oxide (ITO). The shape of the electrode layer 330 is circular, annular, polygonal (e.g., square), star-shaped, or irregular.

[0040] See also Figure 3In some embodiments, the conductive layer 340 covers the top of the micro-light-emitting mesa 310 and covers the electrode layer 330, as well as the surface of the material layer 320. In some embodiments, the conductive layer 340 includes a first conductive layer 341 and a second conductive layer 342. The first conductive layer 341 covers the surface of the electrode layer 330 and at least a portion of the top of the micro-light-emitting mesa 310 not covered by the electrode layer 330. In some embodiments, the edge of the first conductive layer 341 is aligned with the top edge of the micro-light-emitting mesa 310, i.e., the first conductive layer 341 completely covers the top surface of the micro-light-emitting mesa 310. In some examples, the edge of the first conductive layer 341 may be some distance from the top edge of the micro-light-emitting mesa 310, i.e., the first conductive layer 341 completely covers the electrode layer 330 but not completely covers the top surface of the micro-light-emitting mesa 310. The second conductive layer 342 covers the surface of the first conductive layer 341 and the surface of the material layer 320. Figure 3 As shown, in some embodiments, the second conductive layers 342 of adjacent light-emitting mesa units are interconnected. For example, the second conductive layers 342 form a continuous conductive layer on top of the light-emitting mesa array. This double-layer conductive layer design can protect the electrode layer and the micro-light-emitting mesa during etching, and can also enhance current diffusion between adjacent micro-light-emitting mesas, thereby improving conductivity. During etching, the first conductive layer 341 covering the top of the electrode layer 330 and the micro-light-emitting mesa 310 can protect the top of the micro-light-emitting mesa 310 and the electrode layer 330 from being etched and can further improve the lateral current conduction. The second conductive layer 342 covers the entire micro-light-emitting mesa 310, increasing the current diffusion area. The continuous second conductive layer 342 further improves the current diffusion efficiency of the entire light-emitting mesa array. In some embodiments, the materials of the first conductive layer 341 and the second conductive layer 342 may be selected from one or more combinations of ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), FTO (Fluorine-doped Tin Oxide), and AZO (Aluminum-doped Zinc Oxide). In some embodiments, the process parameters for preparing the first conductive layer 341 and the second conductive layer 342 are different.

[0041] In some embodiments, the light-emitting mesa unit 300 further includes a bottom metal layer 340 disposed at the bottom of the micro-light-emitting mesa 310, i.e., at the bottom of the first semiconductor layer 311. The micro-light-emitting mesa 310 is located on the bottom metal layer 340. The edge of the bottom metal layer 340 extends beyond the bottom surface of the micro-light-emitting mesa 310 to form a redundant ring. Figure 4This diagram illustrates a top view of the bottom metal layer and the micro-light-emitting platform according to some embodiments of the present disclosure. In this embodiment, the micro-light-emitting platform 310 is illustrated as a truncated cone, with a circular bottom surface and a circular bottom metal layer 340. It is understood that in other embodiments, the micro-light-emitting platform 310 can be other platform shapes, such as a truncated pyramid. Figure 4 As shown, in some embodiments, the distance D3 from the outer edge of the bottom metal layer 340 to the bottom edge of the micro-emitting mesa 310 along the horizontal direction is 3% to 17% of the diameter D1 of the bottom surface of the micro-emitting mesa 310. This horizontal direction is parallel to the light-emitting surface of the micro-emitting mesa 310, that is, parallel to the top surface of the micro-emitting mesa 310. In some embodiments, the distance D3 from the outer edge of the bottom metal layer 340 to the bottom edge of the micro-emitting mesa 310 ranges from 0.1 micrometers to 0.4 micrometers, such as 0.2 micrometers, 0.3 micrometers, etc., and the width D1 of the bottom of the micro-emitting mesa 310 along the horizontal direction (i.e., the diameter of the bottom surface of the micro-emitting mesa 310) ranges from 2.35 micrometers to 2.65 micrometers, preferably 2.5 micrometers. The structure of the bottom metal layer 340 extending beyond the bottom edge of the micro-emitting mesa 310 can protect the micro-emitting mesa from being etched during the etching process to form the light-emitting mesa unit, while simultaneously ensuring the conductivity of the light-emitting mesa unit. In some embodiments, the material of the bottom metal layer 340 includes one or more of platinum (Pt), gold (Au), tin (Sn), chromium (Cr), titanium (Ti), and silver (Ag).

[0042] See also Figure 3 In some embodiments, the material layer 320 of the light-emitting mesa unit 300 further includes a first material layer 321 and a second material layer 322. The first material layer 321 covers the sidewall of the micro-light-emitting mesa 310. The second material layer 322 covers the sidewall of the bottom metal layer 340. In some embodiments, the first material layer 321 and the second material layer 322 are integrally connected. In some embodiments, the first material layer 321 includes a first sub-material layer 321a and a second sub-material layer 321b, the first sub-material layer 321a covering the sidewall of the micro-light-emitting mesa 310, and the second sub-material layer 321b covering the outside of the first sub-material layer 321a. In some embodiments, the material layers between adjacent micro-light-emitting mesas are interconnected. In some embodiments, the thickness of the first material layer 321 ranges from 280 nanometers to 320 nanometers, and the thickness of the second material layer 322 ranges from 190 nanometers to 210 nanometers. In some embodiments, the thickness of the first material layer 321 is greater than the thickness of the second material layer 322. In some embodiments, the thickness of the first material layer 321 is less than the thickness of the second material layer 322. In some embodiments, the thickness of the first material layer 321 is equal to the thickness of the second material layer 322.

[0043] In some embodiments, the materials of the first material layer 321 and the second material layer 322 include one or more combinations of SiO2, SiON, Al2O3, and SiN. The materials of the first material layer 321 and the second material layer 322 are different. For example, the first material layer 321 is SiN, and the second material layer 322 is SiO2. In some embodiments, the materials of the first material layer 321 and the second material layer 322 are the same.

[0044] See you again Figure 3 In some embodiments, the light-emitting mesa unit 300 further includes a bottom conductive layer 350. The bottom conductive layer 350 is disposed between the bottom metal layer 340 and the bottom surface of the micro-light-emitting mesa 310, improving the electrical connection between the micro-light-emitting mesa 310 and the bottom metal layer 340. The second material layer 322 further covers the sidewalls of the bottom conductive layer 350. In some embodiments, the bottom conductive layer 350 is a transparent conductive layer. In some embodiments, the bottom conductive layer 350 is one or more of a combination of TCO (transparent conductive oxide) film, ITO (Indium Tin Oxide) film, AZO (Antimony doped Zinc Oxide) film, ATO (Antimony doped Tin Oxide) film, and FTO (Fluorine doped Tin Oxide) film.

[0045] In some embodiments, a trench is formed between two adjacent micro-emitting mesa surfaces. The micro-LED display chip also includes a metal structure (N-PAD) 410, which covers a portion of the surface of at least one sidewall of the trench. In some embodiments, the bottom of the trench, i.e., the lowest point A of the trench, is lower than the bottom of the bottom metal layer 340, thereby ensuring that each emitting mesa surface can be sufficiently separated and thus independently controlled. The shortest horizontal distance from the bottom edge of the micro-emitting mesa surface 310 to the metal structure 410 is greater than or equal to 0.2 micrometers. In some embodiments, the metal structure 410 is a ring-shaped three-dimensional structure that surrounds each micro-emitting mesa surface 310. The cross-sectional structure of the metal structure 410 can be triangular, quadrilateral, V-shaped, or other arbitrary shapes. Figures 5A to 5E Schematic diagrams showing the cross-sectional distance relationships between the metal structure and the micro-luminescent mesa in different embodiments are provided. Figures 5A-5C As shown, in these embodiments, the cross-sectional structure of the metal structure 410 is an equilateral triangle, and the bottom of the metal structure 410 has the shortest horizontal distance to the bottom of the micro-light-emitting platform 310. This shortest distance D4 is greater than or equal to 0.2 micrometers. Figure 5DAs shown, in this embodiment, the cross-sectional structure of the metal structure 410 is rectangular, and the horizontal distance from the sidewalls of the metal structure 410 to the bottom of the micro-light-emitting platform 310 is equal. Figure 5E As shown, in this embodiment, the cross-sectional structure of the metal structure 410 is an inverted trapezoid, and the horizontal distance between the top of the metal structure 410 and the bottom of the micro-light-emitting mesa 310 is the shortest. It can be understood that the space between the metal structure 410 and the micro-light-emitting mesa 310 can be filled with... Figure 3 The material layer or conductive layer shown.

[0046] In some embodiments, the material of the metal structure 410 includes one or more of Al, Au, Rh, Ag, Cr, Ti, Pt, Sn, Cu, AuSn, TiW, etc.

[0047] Figure 6A A schematic diagram of the metal structure and light-emitting platform unit according to an embodiment of this application is shown in a top view. Figure 6B A top view schematic diagram of the metal structure and light-emitting mesa units in an embodiment of the present application is shown. Figure 6A and Figure 6B As shown, in some embodiments, within each light-emitting mesa unit 300, the ratio of the total width of the metal structure 410 in any longitudinal section (e.g., a longitudinal section along the AA direction, a longitudinal section along the BB direction, or a longitudinal section along the CC direction) to the width of the light-emitting mesa unit 300 in that longitudinal section along the horizontal direction ranges from 12.5% ​​to 47%, for example, 15%, 20%, 25%, 30%, 35%, 40%, 45%, etc. This design of the metal structure 410 can maximize the light-emitting area and improve the light-emitting efficiency while ensuring the lateral electrical conduction efficiency of the micro-LED display chip. The longitudinal section is perpendicular to the light-emitting surface of the micro-light-emitting mesa, and the horizontal direction is parallel to the light-emitting surface of the micro-light-emitting mesa. In some embodiments, the longitudinal section includes a first sub-longitudinal section (e.g., a longitudinal section along the AA direction or a longitudinal section along the BB direction), which is parallel to the lateral or longitudinal array in the light-emitting mesa array. Within each light-emitting mesa unit 300, the ratio of the total horizontal width of the metal structure 410 in the first sub-longitudinal section, i.e., W2+W3, to the horizontal width W1 of the light-emitting mesa unit 300 in the first sub-longitudinal section ranges from 12.5% ​​to 25%, such as 15%, 18%, 20%, 23%, etc. In some embodiments, the horizontal width W1 of the light-emitting mesa unit 300 in the first sub-longitudinal section is 4 micrometers, and the total horizontal width W2+W3 of the metal structure 410 in the first sub-longitudinal section is 0.5 micrometers to 1 micrometer, such as 0.8 micrometers.

[0048] In some embodiments, the longitudinal section includes a second sub-longitudinal section (e.g., a longitudinal section along the CC direction), which forms a 45° angle with the transverse or longitudinal array in the light-emitting mesa array. Within each light-emitting mesa unit 300, the ratio of the total width of the metal structure 410 along the second sub-longitudinal section, i.e., W5+W6, to the width W4 of the light-emitting mesa unit 300 along the second sub-longitudinal section ranges from 12.5% ​​to 47%, such as 15%, 18%, 22%, 25%, 30%, 35%, 42%, 45%, etc. In some embodiments, the width W4 of the light-emitting mesa unit 300 along the horizontal direction in the second sub-longitudinal section is 4 micrometers, and the total width W5+W6 of the metal structure 410 along the horizontal direction in the second sub-longitudinal section is 2 micrometers to 2.5 micrometers, such as 2.1 micrometers.

[0049] In some embodiments, within a light-emitting platform unit, the ratio of the area of ​​the metal structure 410 to the area of ​​the light-emitting platform unit 300 is not greater than 80%, for example, 35% to 60%, preferably 39.8% to 49.7%, for example, 45%.

[0050] A metal structure 410 is set between adjacent light-emitting mesa units. On the one hand, it can reflect the light emitted from the sidewall of the light-emitting mesa unit, thereby improving the luminous efficiency; on the other hand, it can improve the surface conductivity of the light-emitting mesa array.

[0051] Figure 7A This is a cross-sectional structural diagram of two adjacent light-emitting platform units arranged side by side according to some embodiments of this application. Figure 7A As shown, in this embodiment, the light-emitting mesa unit 700 further includes a top material layer 790. The top material layer 790 is located above the top edge region of the micro-light-emitting mesa 710. Material layer 720 covers the outer sidewall of the top material layer 790, a second conductive layer 742 covers the inner sidewall of the top material layer 790, and electrode layer 730 is located above the middle region of the top surface of the micro-light-emitting mesa 710. In some embodiments, the angle α between the bottom of the top material layer 790 and the inner sidewall of the top material layer ranges from 30° to 60°, for example, 35°. In some embodiments, the thickness T1 of the top material layer 790 ranges from 90 nanometers to 290 nanometers, that is, the distance from the bottom of the top material layer 790 to the highest point of the top material layer 790, for example, 100 nanometers, 220 nanometers, 260 nanometers, etc. Figure 8A and Figure 8B Top views of different embodiments of the micro-luminescent mesa are shown. Figure 8A As shown, combined with Figure 7A In some embodiments, the top material layer 790 covers at least a portion of the first conductive layer 741. For example... Figure 8BAs shown in some embodiments, the top material layer 790 is not in contact with the first conductive layer 741, that is, there is a certain distance between the outer edge of the first conductive layer 741 and the inner edge of the top material layer 790. See also Figure 7A In some embodiments, the maximum width D5 of the central opening of the material layer 720 (i.e., the maximum opening width of the lower edge of the opening of the material layer 720) ranges from 1 micrometer to 1.6 micrometers, such as 1.1 micrometers, 1.2 micrometers, 1.5 micrometers, etc. In some embodiments, the outer edge of the top material layer 790 is aligned with the top edge of the micro-light-emitting mesa 710. The top material layer 790 can further protect the micro-light-emitting mesa 710 during the etching process, avoiding compatibility issues in subsequent processes (such as resist removal) while ensuring sufficient etching.

[0052] Please see Figure 7A The light-emitting mesa unit 700 includes a material layer 720 covering the sidewalls of the micro-light-emitting mesa 710. In some embodiments, the material layer 720 further covers the sidewalls of the bottom conductive layer 750 and the bottom metal layer 740, wherein the width of the portion of the material layer 720 located on the sidewall of the micro-light-emitting mesa 710 is greater than the width of the portion of the material layer 720 located on the sidewall of the bottom metal layer 740. As shown in FIG. 7, in some embodiments, the material layers 720 between adjacent micro-light-emitting mesas are interconnected. In some embodiments, the material layer 720 includes a third material layer 723 and a fourth material layer 724. The third material layer 723 covers the sidewalls of the micro-light-emitting mesa 710, and the fourth material layer 724 covers the surface of the third material layer 723. In some embodiments, the fourth material layer 724 further covers the sidewalls of the bottom conductive layer 750 and the bottom metal layer 740. In some embodiments, the thickness of the third material layer 723 ranges from 50 nanometers to 150 nanometers, and the thickness of the fourth material layer 724 ranges from 150 nanometers to 250 nanometers. In some embodiments, the third material layers 723 of adjacent micro-light-emitting mesa are not connected to each other, while the fourth material layers 724 of adjacent micro-light-emitting mesa are connected to each other. In some embodiments, the materials of the third material layer 723 and the fourth material layer 724 include one or more combinations of SiO2, SiON, Al2O3, and SiN. The materials of the third material layer 723 and the fourth material layer 724 are different. For example, the third material layer 723 is SiN, and the fourth material layer 724 is SiO2.

[0053] In some embodiments, the third material layer 723 and the fourth material layer 724 are made of the same material. Thus, the third material layer and the fourth material layer are a single, integral structure. Figure 7B As shown, this is the overall material layer 720.

[0054] Other structures of the light-emitting mesa unit 700 can be referenced from [the relevant source]. Figure 3 The description of the light-emitting mesa unit 300 will not be repeated here.

[0055] Figure 9 This is a cross-sectional schematic diagram of a micro-light-emitting mesa and a light-emitting mesa unit according to some embodiments of this application. For example... Figure 9 As shown, the bottom width of the micro-luminescent mesa 310 along the horizontal direction is... The width of the top of the micro-luminescent platform 310 along the horizontal direction The height of the micro-luminescent platform 310 along the vertical direction and the angle between the sidewall and the bottom of the microluminescent platform 310. It satisfies the following formula: In some embodiments, the height of the micro-light-emitting mesa 310 along the light-emitting direction is... The range is from 0.7 micrometers to 2.0 micrometers, and the angle between the sidewall and the bottom of the micro-luminescent mesa 310 is... The range is 50° to 80°. In some embodiments, when the ratio of the sidewall length S of the micro-light-emitting mesa 310 to the width D of the light-emitting mesa unit ranges from 0.1 to 1.12, the angle between the sidewall and the bottom of the micro-light-emitting mesa 310 is... The range is from 45° to 90°. In some embodiments, the bottom width of the micro-light-emitting platform 310 in the horizontal direction is... The height of the micro-luminescent platform 310 along the vertical direction The ratio ranges from 1.9 to 2.8. In some embodiments, the top of the micro-light-emitting mesa 310 has a horizontal width... Height of the micro-luminescent platform in the vertical direction The ratio ranges from 1.25 to 1.7. In some embodiments, the top of the micro-light-emitting mesa 310 has a horizontal width... Width along the horizontal direction of the bottom of the micro-luminescent platform 310 The ratio ranges from 0.56 to 0.63, for example, from 0.58 to 0.62, for example, 0.6.

[0056] In some embodiments, the top of the micro-light-emitting mesa 310 has a horizontal width The ratio of the width D of the corresponding light-emitting mesa unit 300 along the horizontal direction ranges from 20% to 40%, for example, 25%, 30%, 35%. The bottom width of the micro-light-emitting mesa 310 along the horizontal direction... The ratio of the width D of the corresponding light-emitting mesa unit 300 along the horizontal direction ranges from 50% to 95%, such as 50%, 65%, 70%, 75%, 80%, 90%, etc., preferably 50%. In some embodiments, the width of the top of the micro-light-emitting mesa 310 along the horizontal direction... The range is 1.5 micrometers to 1.7 micrometers, and the width of the bottom of the micro-luminescent mesa 310 in the horizontal direction is... The range is 2.3 micrometers to 2.7 micrometers, and the height h of the micro-luminescent mesa 310 along the vertical direction ranges from 1 micrometer to 1.2 micrometers.

[0057] Figure 10 This is a top view schematic diagram of a micro-emitting mesa and an emitting mesa unit according to some embodiments of this application. In some embodiments, the active layer 312 includes a quantum well layer. Within each emitting mesa unit, the ratio of the width of the quantum well layer 312 in any longitudinal section (e.g., a longitudinal section along the AA direction, a longitudinal section along the BB direction, or a longitudinal section along the CC direction) in the horizontal direction to the width of the emitting mesa unit 300 in the horizontal direction of that longitudinal section ranges from 37.5% to 70%, such as 38%, 40%, 45%, 50%, 55%, 60%, 65%, etc. This longitudinal section is perpendicular to the light-emitting surface of the micro-emitting mesa 310 and parallel to the light-emitting surface of the micro-emitting mesa 310 in the horizontal direction. In some embodiments, this longitudinal section includes a third sub-longitudinal section (e.g., a longitudinal section along the AA direction or a longitudinal section along the BB direction), which is parallel to the transverse or longitudinal array in the emitting mesa array. The ratio of the width W7 of the quantum well layer 312 in the horizontal direction on the third sub-section to the width W8 of the light-emitting mesa unit 300 in the horizontal direction on the third sub-section ranges from 37.5% to 70%, such as 38%, 40%, 45%, 50%, 55%, 60%, 65%, etc. The width W7 of the quantum well layer 312 in the horizontal direction on the third sub-section can range from 1 micrometer to 3.5 micrometers, for example, in the case where the micro-light-emitting mesa emits red light. In some embodiments, the ratio of the width W7 of the quantum well layer 312 in the horizontal direction on the third sub-section to the width W8 of the light-emitting mesa unit 300 in the horizontal direction on the third sub-section ranges from 37.5% to 70%, such as 38%, 40%, 45%, 50%, 55%, 60%, 65%, etc. The width W7 of the quantum well layer 312 in the horizontal direction on the third sub-section ranges from 1.5 micrometers to 2.8 micrometers, for example, in the case where the micro-light-emitting mesa emits green or blue light.

[0058] In some embodiments, the longitudinal section further includes a fourth sub-longitudinal section (e.g., a longitudinal section along the CC direction), which forms a 45° angle with the transverse or longitudinal array in the luminescent mesa array. The ratio of the width W9 of the quantum well layer 312 in the horizontal direction (e.g., the CC direction) of the fourth sub-longitudinal section to the width W10 of the luminescent mesa unit 300 in the same horizontal direction on the fourth sub-longitudinal section ranges from 37.5% to 70%, such as 38%, 40%, 45%, 50%, 55%, 60%, 65%, etc. The width W9 of the quantum well layer 312 in the horizontal direction on the fourth sub-longitudinal section can range from 1 micrometer to 3.5 micrometers, for example, in the case of a microluminescent mesa emitting red light. In some embodiments, the ratio of the width W9 of the quantum well layer 312 in the horizontal direction on the fourth sub-section to the width W10 of the light-emitting mesa unit 300 in the horizontal direction on the fourth sub-section ranges from 37.5% to 70%, and the width W9 of the quantum well layer 312 in the horizontal direction on the fourth sub-section ranges from 1.5 micrometers to 2.8 micrometers, such as when the micro-light-emitting mesa emits green or blue light.

[0059] Figure 11 This is a schematic diagram of the structure of a micro-light-emitting mesa according to some embodiments of this application. For example... Figure 11As shown, in some embodiments, the ratio of the thickness T2 of the active layer 312 in the vertical direction to the thickness T of the micro-emitting mesa 310 in the vertical direction ranges from 3% to 50%, for example, 22% to 28%. In some embodiments, the ratio of the thickness T2 of the active layer 312 in the vertical direction to the thickness T of the micro-emitting mesa 310 in the vertical direction ranges from greater than or equal to 3% to less than 32%. In some embodiments, the ratio of the thickness T2 of the active layer 312 in the vertical direction to the thickness T of the micro-emitting mesa 310 in the vertical direction ranges from greater than 32% to less than or equal to 50%. In some embodiments, the ratio of the thickness T3 of the second semiconductor layer 313 in the vertical direction to the thickness T1 of the first semiconductor layer 311 in the vertical direction ranges from 60% to 150%, for example, 71% to 80%, preferably 72% to 78%. In some embodiments, the thickness T1 of the first semiconductor layer 311 in the vertical direction ranges from 200 nanometers to 400 nanometers. In some embodiments, the thickness T1 of the first semiconductor layer 311 in the vertical direction ranges from 500 nm to 800 nm, for example, 500 nm to 550 nm. In some embodiments, the thickness T3 of the second semiconductor layer in the vertical direction ranges from 200 nm to 350 nm. In some embodiments, the thickness T3 of the second semiconductor layer in the vertical direction ranges from 350 nm to 800 nm, for example, 360 nm to 400 nm. In some embodiments, the total thickness (T1+T2+T3) of the first semiconductor layer 311, the active layer 312, and the second semiconductor layer 313 in the vertical direction (i.e., the thickness T of the micro-light-emitting mesa 310) ranges from 500 nm to 14000 nm. In some embodiments, the total thickness (T1+T2+T3) of the first semiconductor layer 311, the active layer 312, and the second semiconductor layer 313 in the vertical direction (i.e., the thickness T of the micro-light-emitting mesa 310) ranges from 500 nm to 1000 nm. In some embodiments, the total thickness (T1+T2+T3) of the first semiconductor layer 311, the active layer 312, and the second semiconductor layer 313 along the vertical direction (i.e., the thickness T of the micro-emitting mesa 310) ranges from 1000 nm to 14000 nm. In some embodiments, the total thickness (T1+T2+T3) of the first semiconductor layer 311, the active layer 312, and the second semiconductor layer 313 along the vertical direction (i.e., the thickness T of the micro-emitting mesa 310) ranges from 1100 nm to 1250 nm. In some embodiments, the total thickness (T1+T2+T3) of the first semiconductor layer 311, the active layer 312, and the second semiconductor layer 313 along the vertical direction (i.e., the thickness T of the micro-emitting mesa 310) ranges from 1250 nm to 2000 nm. The micro-emitting mesa provided in this application can effectively increase the number of electrons and holes injected into the active layer in a balanced manner and improve the internal quantum efficiency.

[0060] Figure 12 This is a cross-sectional structural diagram of three adjacent light-emitting platform units arranged side by side according to some embodiments of this application. Figure 12 As shown, the micro LED display chip also includes a microlens array located on the light-emitting mesa array. The microlens array includes multiple microlenses 1201, with one microlens 1201 corresponding to one micro-light-emitting mesa 310. The microlenses 1201 are disposed on the micro-light-emitting mesa 310. Figure 13 A schematic diagram of the horizontal profile of the microlens 1201 and the light-emitting platform 310 is shown. Figure 13 As shown, the horizontal profile of the microlens 1201 is larger than the maximum horizontal profile of the micro-light-emitting mesa. In some embodiments, the micro-LED display chip further includes a spacer layer 1202 located between the micro-light-emitting mesa 310 and the microlens 1201. The ratio of the vertical height H of the spacer layer 1202 to the horizontal width W11 of the microlens 1201 ranges from 0.25 to 1.5, for example, 0.4, 0.5, 0.7, 0.9, 1.2, 1.3, 1.4, etc. In some embodiments, the vertical height H of the spacer layer 1202 is no higher than 5 micrometers, and the maximum horizontal width W11 of the microlens 1201 ranges from 1 micrometer to 3 micrometers. Smaller microlens sizes can be adapted to the design requirements of products with smaller light-emitting mesa spacing, thereby improving the pixel resolution of the micro-LED display chip or reducing the size of the micro-LED display chip. In some embodiments, the vertical height H of the spacer layer 1202 is 2.294 micrometers, and the maximum horizontal width W11 of the microlens 1201 is 3.874 micrometers. In some embodiments, the vertical height H of the spacer layer 1202 is 2.198 micrometers, and the maximum horizontal width W11 of the microlens 1201 is 3.907 micrometers. In some embodiments, the vertical height H of the spacer layer 1202 is 2.273 micrometers, and the maximum horizontal width W11 of the microlens 1201 is 3.858 micrometers. In some embodiments, the vertical height H of the spacer layer 1202 is 2.342 micrometers, and the maximum horizontal width W11 of the microlens 1201 is 3.874 micrometers. In some embodiments, the vertical height H of the spacer layer 1202 is 2.362 micrometers, and the maximum horizontal width W11 of the microlens 1201 is 3.907 micrometers.

[0061] In some embodiments, there is a gap between two adjacent microlenses and two adjacent spacer layers are connected.

[0062] Figure 14 This is a top view schematic diagram of a micro LED display chip 1400 according to some embodiments of this application. (Refer to...) Figure 14The micro LED display chip 1400 includes a mesa array 1410 and an IC (integrated circuit) backplane 1420. The mesa array 1410 is located on the IC backplane 1420 to form the image display area of ​​the micro LED display chip 100. The remaining area of ​​the IC backplane 1420 not covered by the mesa array 1410 is formed as a non-functional area. The IC backplane 1420 is formed on the back of the mesa array 1410 and extends partially beyond the mesa array 1410, i.e., partially not covered by the mesa array 1410. The mesa array 1410 includes a plurality of mesa units disposed in the array, each mesa unit including a first micro-mesa 1430. The IC backplane 120 is configured to control the plurality of mesa units, i.e., the first mesa units 1430. In this embodiment, the micro LED display chip 1400 further includes a plurality of second light-emitting mesa units 1440. The second light-emitting mesa units 1440 are located around the light-emitting mesa array 1410 and are not electrically connected. In some embodiments, the second light-emitting mesa units 1440 surround the array of first light-emitting mesa units 1430; for example, only one column or row of second light-emitting mesa units 1440 is arranged outside the array of first light-emitting mesa units 1430. This protects the light-emitting mesa array 1410 from etching or cutting damage.

[0063] Figures 15A to 15C A schematic diagram of the structure of a second light-emitting mesa unit according to different embodiments of this application is shown. See also Figure 15A In this embodiment, compared to the first light-emitting mesa unit 1430, the second light-emitting mesa unit 1440 does not have a bottom electrode 1438 electrically connected to the driving circuit at its bottom. Therefore, the second light-emitting mesa unit 1440 cannot be driven. See also... Figure 15B In this embodiment, compared to the first light-emitting mesa unit 1430, the material layer 1444 of the second light-emitting mesa unit covers not only the sidewalls of the micro-light-emitting mesa 1441 but also its top. Therefore, the second light-emitting mesa unit 1440 cannot be electrically connected. See also Figure 15C In this embodiment, the bottom of the second light-emitting platform unit 1440 is not provided with a bottom electrode 1438 that is electrically connected to the driving circuit, and the material layer 1444 of the second light-emitting platform unit not only covers the side wall of the micro-light-emitting platform 1441 but also covers the top of the micro-light-emitting platform 1441.

[0064] Some embodiments of this application also provide an active layer structure. Figure 16 This is a schematic diagram of the structure of a micro-light-emitting mesa according to some embodiments of this application. For example... Figure 16As shown, the micro-light-emitting mesa 1600 comprises, from bottom to top, a first semiconductor layer 1610, an active layer 1620, and a second semiconductor layer 1630. In some embodiments, the first semiconductor layer 1610 is an N-type semiconductor layer, the second semiconductor layer 1630 is a P-type semiconductor layer, and the active layer 1620 is a multiple quantum well (MQW) structure, formed by overlapping multiple quantum barrier layers and quantum well layers. The active layer 1620 is doped with one or more doping elements, such as Mg, As, Sb, Fe, Zn, Si, Te, Bi, etc. In some embodiments, the active layer 1620 can be an AlGaInP system or an InGaN system.

[0065] In some embodiments, one or more doping elements are doped in the active layer 1620 by a combination of uniform doping and gradient doping.

[0066] Figures 17A to 17C The diagram illustrates the relationship between doping concentration and active layer growth height in different embodiments combining uniform doping and gradient doping according to some embodiments of this application. Figures 17A to 17C The schematic diagram of the micro-luminescent mesa 1600 shown can be regarded as... Figure 16 The micro-luminescent mesa in the middle is rotated 90 degrees clockwise. See also Figure 17A In some embodiments, the active layer 1620 includes a uniformly doped region 1621A and a gradient-doped region 1622A. Within the uniformly doped region 1621A, the doping concentration of the dopant element (e.g., dopant element A or dopant element B) is a first concentration, and this first concentration varies by no more than 20% within the uniformly doped region 1621A, i.e., it is relatively fixed. Within the gradient-doped region 1622A, the doping concentration of the dopant element (e.g., dopant element A or dopant element B) is a second concentration, and this second concentration varies with the height of the active layer 1620, i.e., it varies with the growth height of the active layer 1620. The uniformly doped region 1621A is located near the first semiconductor layer 1610, and the gradient-doped region 1622A is located near the second semiconductor layer 1630. The initial concentration of the second concentration is the same as the first concentration. That is, the dopant element is doped at the first concentration in the uniformly doped region 1621A of the active layer. When doping reaches point P, the concentration increases or decreases with the growth height of the active layer, starting from the first concentration, within the gradient doped region 1622A. In this embodiment, the region from the starting point of the active layer 1620 to point P is the uniformly doped region, and the region from point P to the end of the active layer 1620 is the gradient doped region. In some embodiments, point P can be any position within the active layer 1620. In some embodiments, point P is the middle position of the active layer.

[0067] In some embodiments, such as for dopant element A, the second concentration increases with increasing height of the active layer in the gradient doping region 1622A. In this embodiment, the first concentration ranges from 2E16 cm⁻¹. -3 Up to 5E17 cm -3 The final concentration range for the second concentration is 5E17 cm⁻¹. -3 Up to 2E18 cm -3 In some embodiments, the ratio of the final concentration of the second concentration to the initial concentration of the second concentration (i.e., the first concentration) is greater than 1.5.

[0068] In some embodiments, such as for dopant element B, the second concentration decreases with increasing height of the active layer in the gradient doping region 1622A. In this embodiment, the first concentration ranges from 5E17 cm⁻¹. -3 Up to 2E18 cm -3 The final concentration range for the second concentration is 1E17 cm⁻¹. -3 Up to 5E17 cm -3 In some embodiments, the ratio of the initial concentration of the second concentration (i.e., the first concentration) to the final concentration of the second concentration is greater than 1.5.

[0069] In some embodiments, the dopant element further dops the second semiconductor layer to a final concentration of the second concentration. In some embodiments, doping is stopped after the active layer growth is complete.

[0070] See Figure 17BIn some embodiments, the active layer 1620 includes a gradient-doped region 1621B and a uniformly doped region 1622B. Within the gradient-doped region 1621B, the doping concentration of the dopant element (e.g., dopant element A or dopant element B) is a first concentration, which varies with the height of the active layer 1620, i.e., it varies with the growth height of the active layer 1620. Within the uniformly doped region 1622B, the doping concentration of the dopant element (e.g., dopant element A or dopant element B) is a second concentration, and the variation amplitude of this second concentration in the uniformly doped region 1622B does not exceed 20%, i.e., it is relatively fixed. The gradient-doped region 1621B is located near the first semiconductor layer 1610, and the uniformly doped region 1622B is located near the second semiconductor layer 1630. The final concentration of the first concentration is the second concentration. That is, the dopant element is doped at the first concentration in the gradient doping region 1621B of the active layer. The doping concentration increases or decreases with the height of the active layer. When doping reaches point Q, the concentration at point Q is used as the second concentration in the uniform doping region 1622B. The variation amplitude of this second concentration in the uniform doping region 1622B does not exceed 20%, i.e., it is relatively fixed. In this embodiment, the region from the starting point of the active layer 1620 to point Q is the gradient doping region, and the region from point Q to the end of the active layer 1620 is the uniform doping region. In some embodiments, the position of point Q can be any position in the active layer 1620. In some embodiments, the position of point Q is the middle position of the active layer.

[0071] In some embodiments, such as for dopant element A, the first concentration in the gradient doping region 1621B increases with the height of the active layer. In this embodiment, the first concentration ranges from 2E16 cm⁻¹. -3 Up to 5E17 cm -3 The final concentration range of the first concentration is 5E17 cm⁻¹. -3 Up to 2E18 cm -3 In some embodiments, the ratio of the final concentration of the first concentration (i.e., the second concentration) to the initial concentration of the first concentration is greater than 1.5.

[0072] In some embodiments, such as for dopant element B, the first concentration decreases with increasing height of the active layer in the gradient doping region 1621B. In this embodiment, the first concentration ranges from 5E17 cm⁻¹. -3 Up to 2E18 cm -3 The final concentration range of the first concentration is 1E17 cm⁻¹. -3 Up to 5E17 cm -3 In some embodiments, the ratio of the initial concentration of the first concentration to the final concentration of the first concentration (i.e., the second concentration) is greater than 1.5.

[0073] In some embodiments, the dopant element further dops the second semiconductor layer at a second concentration. In some embodiments, the doping of the dopant element is stopped after the active layer growth is completed.

[0074] See Figure 17C In some embodiments, the active layer 1620 includes a first uniformly doped region 1621C, a gradient doped region 1622C, and a second uniformly doped region 1623C. Within the first uniformly doped region 1621C, the doping concentration of the doping element (e.g., doping element A or doping element B) is a first concentration, and the variation range of this first concentration within the first uniformly doped region 1621C does not exceed 20%, i.e., it is relatively fixed. Within the gradient doped region 1622C, the doping concentration of the doping element (e.g., doping element A or doping element B) is a second concentration, and this second concentration varies with the height of the active layer 1620, i.e., it varies with the growth height of the active layer 1620. Within the second uniformly doped region 1623C, the doping concentration of the doping element (e.g., doping element A or doping element B) is a third concentration, and the variation range of this third concentration within the second uniformly doped region 1623C does not exceed 20%, i.e., it is relatively fixed. The first uniformly doped region 1621C is located near the first semiconductor layer 1610, the second uniformly doped region 1623C is located near the second semiconductor layer 1630, and the gradient doped region 1622C is located between the first uniformly doped region 1621C and the second uniformly doped region 1623C. The initial concentration of the second concentration is the concentration of the first concentration, that is, the dopant element is doped at the first concentration in the first region 1621C with the active layer. When doping reaches point P, the concentration increases or decreases with the growth height of the active layer 1620, starting from the first concentration. The final concentration of the second concentration is the third concentration, that is, the dopant element is doped at the second concentration in the gradient doped region 1622C of the active layer. The doping concentration increases or decreases with the height of the active layer. When doping reaches point Q, the concentration at point Q is used as the third concentration in the second uniformly doped region 1623C. The variation amplitude of the third concentration in the second uniformly doped region 1623C does not exceed 20%, that is, it is relatively fixed. In this embodiment, the region from the starting point of the active layer 1620 to point P is the first uniformly doped region, the region growing from point P to point Q is the gradient doped region, and the region continuing to grow from point Q to the termination position of the active layer 1620 is the second uniformly doped region. In some embodiments, point P can be any position within the active layer 1620, and point Q can be any position after point P. In some embodiments, the heights of the first and second uniformly doped regions are equal, that is, the distance from the starting position of the active layer to point P and the distance from point Q to the termination position of the active layer are equal.

[0075] In some embodiments, such as for dopant element A, the second concentration increases with increasing height of the active layer in the gradient doping region 1622C. In this embodiment, the first concentration ranges from 2E16 cm⁻¹. -3 Up to 5E17 cm -3 The third concentration range is 5E17 cm⁻¹ -3 Up to 2E18 cm -3 In some embodiments, the ratio of the third concentration to the first concentration is greater than 1.5.

[0076] In some embodiments, such as for dopant element B, the second concentration decreases with increasing height of the active layer in the gradient doping region 1622C. In this embodiment, the first concentration ranges from 5E17 cm⁻¹. -3 Up to 2E18 cm -3 The third concentration range is 1E17 cm⁻¹ -3 Up to 5E17 cm -3 In some embodiments, the ratio of the first concentration to the third concentration is greater than 1.5.

[0077] In some embodiments, the dopant element further dops the second semiconductor layer at a third concentration. In some embodiments, doping is stopped after the active layer growth is complete.

[0078] By combining uniform doping and gradient doping to dope the active layer, the internal quantum efficiency and light extraction efficiency of the active layer can be improved, thereby improving the external quantum efficiency and brightness uniformity of the micro LED display chip.

[0079] In some embodiments, one or more doping elements are doped into the active layer 1620 by spacer doping.

[0080] Figure 18A and Figure 18B A schematic diagram showing the relationship between doping concentration and active layer growth height in different embodiments of spacer doping according to some embodiments of this application is illustrated. Figure 18A and Figure 18B The schematic diagram of the micro-luminescent mesa 1600 shown can be regarded as... Figure 16 The micro-luminescent mesa in the middle is rotated 90 degrees clockwise. See also Figure 18A and Figure 18BThe active layer 1620 includes a plurality of quantum well layers W and a plurality of quantum barrier layers B arranged at intervals between each other. In some embodiments, the number of quantum well layers is N, and the number of quantum barrier layers is N+1, where N is a positive integer, meaning there is one more quantum barrier layer than quantum well layer. The layers closest to the first semiconductor layer 1610 and the second semiconductor layer 1620 are all quantum barrier layers B. In some embodiments, the total number of quantum barrier layers and quantum well layers does not exceed 50. The doping concentration of the one or more doping elements in the quantum well layers is different from the doping concentration of the doping element in the quantum barrier layers.

[0081] See Figure 18A The doping concentration of the dopant element in the quantum well layer W is a fourth concentration C1, and the doping concentration of the dopant element in the quantum barrier layer B is a fifth concentration C2. As shown in the figure, the dopant element is doped at the fourth concentration C1 at the starting position of growth in the quantum well layer W, and at the fifth concentration C2 near the starting position of growth in the quantum barrier layer B. In this embodiment, the fourth concentration C1 is greater than the fifth concentration C2, that is, for this dopant element, a higher concentration is used in the quantum well layer W, and a lower concentration is used in the quantum barrier layer B, so as to achieve spaced doping in the active layer 1620. In some embodiments, the range of the fourth concentration C1 is 1E17 cm⁻¹. -3 Up to 1E18 cm -3 The fifth concentration of C2 ranges from 5E16 cm⁻¹. -3 Up to 2E17cm -3 The ratio of the fourth concentration C1 to the fifth concentration C2 (i.e., C1 / C2) is greater than 1.5.

[0082] In some embodiments, the quantum well layer W further includes a buffer region, wherein the doping concentration of the dopant element in the buffer region of the quantum well layer W is a fifth concentration C2, which is the same as the doping concentration in the quantum barrier layer B. See also Figure 18A Taking quantum well layer 1601 as an example, quantum well layer 1601 grows from position a to position b, ending at which point the growth of the next quantum barrier layer B begins. Starting from position a, a dopant element is added to quantum well layer 1601 at a fourth concentration C1 until quantum well layer 1601 grows to position c. From position c, the dopant element is then added to quantum well layer 1601 at a fifth concentration C2, and this fifth concentration C2 is continued for quantum barrier layer B. The region where quantum well layer 1601 grows from position c to position b is the buffer region. In some embodiments, the thickness of the buffer region is one-third to four-fifths of the thickness of its corresponding quantum well layer; that is, the distance from point c to point b is one-third to four-fifths of the distance from point a to point b.

[0083] See Figure 18BThe doping concentration of the dopant element in the quantum well layer W is a fourth concentration C1, and the doping concentration of the dopant element in the quantum barrier layer B is a fifth concentration C2. As shown in the figure, the dopant element is doped at the fifth concentration C2 at the starting position of the growth of the quantum barrier layer B, and at the fourth concentration C1 near the starting position of the growth of the quantum well layer W. In this embodiment, the fifth concentration C2 is greater than the fourth concentration C1, that is, for this dopant element, it is doped at a higher concentration in the quantum barrier layer B and at a lower concentration in the quantum well layer W, thereby achieving spaced doping in the active layer 1620. In some embodiments, the fourth concentration C1 ranges from 5E16 cm⁻¹. -3 Up to 2E17 cm -3 The fifth concentration of C2 ranges from 1E17 cm⁻¹. -3 Up to 2E18cm -3 The ratio of the fifth concentration C2 to the fourth concentration C1 (i.e., C2 / C1) is greater than 1.5.

[0084] In some embodiments, the quantum barrier layer B further includes a buffer region, wherein the doping concentration of the dopant element in the buffer region of the quantum barrier layer B is a fourth concentration C1, which is the same as the doping concentration in the quantum well layer W. See also Figure 18B Taking quantum barrier layer 1602 as an example, quantum barrier layer 1602 grows from position a to position b, ending at which point the growth of the next quantum well layer W begins. Starting from position a, a dopant element is added to quantum barrier layer 1602 at a fifth concentration of C2 until quantum barrier layer 1602 grows to position c. From position c, the dopant element is then added to quantum barrier layer 1602 at a fourth concentration of C1, and this fourth concentration of C1 is continued to be used to dope quantum well layer W. The region where quantum barrier layer 1602 grows from position c to position b is the buffer region. In some embodiments, the thickness of the buffer region is one-third to four-fifths of the thickness of the corresponding quantum barrier layer, that is, the distance from point c to point b is one-third to four-fifths of the distance from point a to point b. By doping the active layer in a spaced-out manner, stress or wavelength can be controlled.

[0085] The micro LED display chip provided in this application can effectively improve luminous efficiency and increase the yield during the etching process.

[0086] It should be noted that relational terms in this document, such as “first” and “second”, are used only to distinguish an entity or operation from another entity or operation, without requiring or implying any actual relationship or order between these entities or operations. Furthermore, the words “including,” “having,” and “containing,” as well as other similar forms, are intended to be equivalent in meaning and are open-ended; one or more items following any of these words do not imply an exhaustive list of such items or that the list is limited to only one or more items.

[0087] As used herein, unless expressly stated otherwise, the term "or" covers all possible combinations unless impractical. For example, if a component is stated to include A or B, then unless expressly stated otherwise or impractical, the component may include A, or B, or A and B. As a second example, if a component is stated to include A, B, or C, then unless expressly stated otherwise or impractical, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0088] In the foregoing description, numerous specific details have been described, which may vary depending on the implementation. Certain modifications and alterations may be made to the described embodiments. Other embodiments will be apparent to those skilled in the art in light of the specification and practice of this application disclosed herein. The specification and examples are intended to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims. The sequence of steps shown in the accompanying drawings is also intended for illustrative purposes only and is not intended to limit one to any particular order of steps. Therefore, those skilled in the art will understand that these steps may be performed in different orders while achieving the same method.

[0089] Exemplary embodiments have been disclosed in the accompanying drawings and description. However, many variations and modifications can be made to these embodiments. Therefore, although specific terminology has been used, it is used in a general and descriptive sense only and not for limiting purposes.

Claims

1. A micro LED display chip comprising an array of light emitting mesas, the array of light emitting mesas comprising a plurality of light emitting mesa units, characterized in that, Each of the light emitting mesa units comprises: a micro light emitting mesa comprising, from bottom to top, a first semiconductor layer, an active layer, and a second semiconductor layer; a material layer covering sidewalls of the micro light emitting mesa; a conductive layer covering a top of the micro light emitting mesa and a surface of the material layer; and an electrode layer disposed on the top of the micro light emitting mesa, the conductive layer covering a surface of the electrode layer and at least part of the top of the micro light emitting mesa not covered by the electrode layer, the conductive layer further comprises: a first conductive layer covering a surface of the electrode layer and at least part of the top of the micro light emitting mesa not covered by the electrode layer; and a second conductive layer covering a surface of the first conductive layer and a surface of the material layer, an edge of the first conductive layer is aligned with an edge of the top of the micro light emitting mesa.

2. The micro-LED display chip of claim 1, wherein, The second conductive layers of adjacent light emitting mesa units are connected to each other.

3. The micro-LED display chip of claim 1, wherein, An opening of the material layer has a maximum width ranging from 1 micrometer to 1.6 micrometers.

4. The micro-LED display chip of claim 1, wherein, The light emitting mesa unit further comprises a top material layer disposed above a top edge region of the micro light emitting mesa, an outer sidewall of the top material layer is covered by the material layer, an inner sidewall of the top material layer is covered by the second conductive layer, and the electrode layer is disposed above a middle region of a top surface of the micro light emitting mesa.

5. The micro-LED display chip of claim 4, wherein, The top material layer covers at least part of the first conductive layer.

6. The micro-LED display chip of claim 4, wherein, An outer edge of the top material layer is aligned with an edge of the top of the micro light emitting mesa.

7. The micro LED display chip of claim 4, wherein, An angle between a bottom of the top material layer and the inner sidewall of the top material layer ranges from 30° to 60°. 8.The micro-LED display chip of claim 4, wherein, A thickness of the top material layer ranges from 90 nanometers to 290 nanometers.

9. The micro-LED display chip of claim 1, wherein, The light emitting mesa unit is a first light emitting mesa unit, the light emitting mesa array further comprises a plurality of second light emitting mesa units, the second light emitting mesa units are disposed at a periphery of the light emitting mesa array, and the second light emitting mesa units are not to be turned on.

10. The micro-LED display chip of claim 9, wherein, The second light emitting mesa units do not comprise a bottom electrode.

11. The micro-LED display chip of claim 9, wherein, The material layer covers sidewalls and a top of a micro light emitting mesa of the second light emitting mesa units.

12. The micro-LED display chip of claim 9, wherein, The second light emitting mesa units surround the array of the first light emitting mesa units.

13. The micro-LED display chip of claim 12, wherein, An outer side of the array of the first light emitting mesa units comprises only one column or one row of the second light emitting mesa units.

14. The micro-LED display chip of claim 1, wherein, The light emitting mesa unit further comprises a bottom metal layer disposed at a bottom of the micro light emitting mesa.

15. The micro-LED display chip of claim 14, wherein, A distance from an outer edge of the bottom metal layer to an edge of the bottom of the micro light emitting mesa along a horizontal direction parallel to a light emitting surface of the micro light emitting mesa ranges from 3% to 17% of a diameter of a bottom surface of the micro light emitting mesa.

16. The micro-LED display chip of claim 15, wherein, The distance from the outer edge of the bottom metal layer to the edge of the bottom of the micro light emitting mesa along the horizontal direction ranges from 0.1 micrometer to 0.4 micrometer, and a width of the bottom of the micro light emitting mesa along the horizontal direction ranges from 2.35 micrometers to 2.65 micrometers.

17. The micro LED display chip of claim 1, wherein the material layer between adjacent micro light emitting mesas is connected to each other.

18. The micro-LED display chip of claim 14, wherein the material layer further covers sidewalls of the bottom metal layer, and the material layer comprises: a first material layer covering sidewalls of the micro light emitting mesa; and a second material layer covering sidewalls of the bottom metal layer, wherein a thickness of the first material layer is greater than a thickness of the second material layer. The material layer comprises:

19. The micro-LED display chip of claim 14, wherein, a third material layer covering sidewalls of the micro light emitting mesa; and a fourth material layer covering a surface of the third material layer and sidewalls of the bottom metal layer.

20. The micro-LED display chip of claim 19, wherein the third material layer and the fourth material layer are different material layers. The third material layer has a thickness ranging from 50 nm to 150 nm, and the fourth material layer has a thickness ranging from 150 nm to 250 nm.

21. The micro-LED display chip of claim 19, wherein, The micro-LED display chip further comprises a microlens array disposed on the micro light emitting mesa array, wherein the microlens array comprises a plurality of microlenses, one microlens corresponding to one micro light emitting mesa, the microlens is disposed on the micro light emitting mesa, and a horizontal profile of the microlens is greater than a maximum horizontal profile of the micro light emitting mesa.

22. The micro-LED display chip of claim 1, wherein, The micro-LED display chip further comprises a spacer layer disposed between the micro light emitting mesa and the microlens, wherein a ratio of a vertical height of the spacer layer to a horizontal width of the microlens ranges from 0.25 to 1.5, the horizontal direction is parallel to a light emitting surface of the micro light emitting mesa, and the vertical direction is perpendicular to the light emitting surface of the micro light emitting mesa.

23. The micro-LED display chip of claim 22, wherein, The vertical height of the spacer layer is not higher than 5 microns, and the maximum horizontal width of the microlens ranges from 1 micron to 3 microns.

24. The micro-LED display chip of claim 23, wherein, Adjacent two microlenses have a gap therebetween, and adjacent two spacer layers are connected.

25. The micro-LED display chip of claim 23, wherein, Adjacent two micro light emitting mesas form a groove therebetween, and the micro-LED display chip further comprises a metal structure covering at least part of a surface of a sidewall of the groove.

26. The micro-LED display chip of claim 14, wherein, A shortest horizontal distance from an edge of a bottom of the micro light emitting mesa to the metal structure is greater than or equal to 0.2 microns.

27. The micro-LED display chip of claim 26, wherein, A cross-sectional shape of the metal structure is triangular or quadrangular or irregular.

28. The micro-LED display chip of claim 26, wherein, A bottom of the groove is lower than a bottom of the bottom metal layer.

29. The micro-LED display chip of claim 26, wherein, In each light emitting mesa unit, a ratio of a total width of the metal structure along a first horizontal direction on a first longitudinal section to a width of the light emitting mesa unit along the first horizontal direction on the first longitudinal section ranges from 12.5% to 47%, the first longitudinal section is perpendicular to a light emitting surface of the micro light emitting mesa, and the first horizontal direction is parallel to the light emitting surface of the micro light emitting mesa.

30. The micro-LED display chip of claim 26, wherein, The first longitudinal section comprises a first sub-longitudinal section, and in each light emitting mesa unit, a ratio of a total width of the metal structure along the first horizontal direction on the first sub-longitudinal section to a width of the light emitting mesa unit along the first horizontal direction on the first sub-longitudinal section ranges from 12.5% to 25%, the first sub-longitudinal section is parallel to a transverse array or a longitudinal array in the micro light emitting mesa array.

31. The micro-LED display chip of claim 30, wherein, ​ 32. The micro-LED display chip of claim 30, wherein, The first longitudinal section includes a second sub-longitudinal section, and within each light emitting mesa unit, a ratio of a total width of the metal structure along the second sub-longitudinal section to a width of the light emitting mesa unit along the second sub-longitudinal section ranges from 12.5% to 47%, the second sub-longitudinal section forms a 45° angle with a transverse array or a longitudinal array in the light emitting mesa array.

33. The micro-LED display chip of claim 1, wherein, A ratio of a maximum width of the electrode layer along a horizontal direction to a maximum width of the micro light emitting mesa top along the horizontal direction ranges from 35% to 67%, the horizontal direction being parallel to a light emitting surface of the micro light emitting mesa.

34. The micro-LED display chip of claim 33, wherein, A maximum width of the electrode layer along the horizontal direction ranges from 0.6 micrometers to 1 micrometer, and a maximum width of the micro light emitting mesa top along the horizontal direction ranges from 1.5 micrometers to 1.7 micrometers.

35. The micro-LED display chip of claim 33, wherein, The electrode layer is circular, and a diameter of the circular shape ranges from 0.6 micrometers to 1 micrometer.

36. The micro-LED display chip of claim 1, wherein, A width of the micro light emitting mesa bottom along a horizontal direction, a width of the micro light emitting mesa top along the horizontal direction, a height of the micro light emitting mesa along a vertical direction, and an angle between the micro light emitting mesa sidewall and the bottom satisfy: wherein is a width of a bottom of the micro light emitting mesa along the horizontal direction, is a width of a top of the micro light emitting mesa along the horizontal direction, h is a height of the micro light emitting mesa along the light emitting direction, and θ is an angle between a sidewall of the micro light emitting mesa and the bottom, the horizontal direction is parallel to a light emitting surface of the micro light emitting mesa, and the vertical direction is perpendicular to the light emitting surface of the micro light emitting mesa.

37. The micro-LED display chip of claim 36, wherein, A height of the micro light emitting mesa along a light emitting direction ranges from 0.7 micrometers to 2.0 micrometers, and an angle between the micro light emitting mesa sidewall and the bottom ranges from 50° to 80°.

38. The micro-LED display chip of claim 36, wherein, A ratio of a width of the micro light emitting mesa bottom along the horizontal direction to a height of the micro light emitting mesa along the vertical direction ranges from 1.9 to 2.

8.

39. The micro-LED display chip of claim 36, wherein, A ratio of a width of the micro light emitting mesa top along the horizontal direction to a height of the micro light emitting mesa along the vertical direction ranges from 1.25 to 1.

7.

40. The micro-LED display chip of claim 36, wherein, A ratio of a width of the micro light emitting mesa top along the horizontal direction to a width of the micro light emitting mesa bottom along the horizontal direction ranges from 0.56 to 0.

63.

41. The micro-LED display chip of claim 36, wherein, A ratio of a width of the micro light emitting mesa top along the horizontal direction to a width of a corresponding light emitting mesa unit along the horizontal direction ranges from 20% to 40%, and a ratio of a width of the micro light emitting mesa bottom along the horizontal direction to a width of the corresponding light emitting mesa unit along the horizontal direction ranges from 62.5% to 80%.

42. The micro-LED display chip of claim 1, wherein, The active layer includes a quantum well layer, and within each light emitting mesa unit, a ratio of a width of the quantum well layer along a second horizontal direction on a second longitudinal section to a width of the light emitting mesa unit along the second horizontal direction on the second longitudinal section ranges from 37.5% to 70%, the second longitudinal section being perpendicular to a light emitting surface of the micro light emitting mesa, and the second horizontal direction being parallel to the light emitting surface of the micro light emitting mesa.

43. The micro-LED display chip of claim 42, wherein, The second longitudinal section includes a third sub-longitudinal section, and within each light emitting mesa unit, a ratio of a width of the quantum well layer along the second horizontal direction on the third sub-longitudinal section to a width of the light emitting mesa unit along the second horizontal direction on the third sub-longitudinal section ranges from 37.5% to 70%, the third sub-longitudinal section being parallel to a transverse array in the light emitting mesa array.

44. The micro-LED display chip of claim 43, wherein, The second longitudinal section further comprises a fourth sub-longitudinal section, a ratio of a width of the quantum well layer along the second horizontal direction on the fourth sub-longitudinal section to a width of the light-emitting mesa unit along the second horizontal direction on the fourth sub-longitudinal section ranges from 37.7% to 70%, and the fourth sub-longitudinal section forms a 45° angle with a transverse array in the light-emitting mesa array.

45. The micro-LED display chip of claim 1, wherein, A ratio of a thickness of the active layer along a vertical direction to a thickness of the micro light-emitting mesa along the vertical direction ranges from 3% to 50%, and the vertical direction is perpendicular to a light-emitting surface of the micro light-emitting mesa.

46. The micro-LED display chip of claim 45, wherein, A ratio of a thickness of the second semiconductor layer along the vertical direction to a thickness of the first semiconductor layer along the vertical direction ranges from 60% to 150%.

47. The micro-LED display chip of claim 45, wherein, The thickness of the first semiconductor layer along the vertical direction ranges from 200 nanometers to 800 nanometers, and the vertical direction is perpendicular to the light-emitting surface of the micro light-emitting mesa.

48. The micro-LED display chip of claim 45, wherein, The thickness of the second semiconductor layer along the vertical direction ranges from 200 nanometers to 800 nanometers, and the vertical direction is perpendicular to the light-emitting surface of the micro light-emitting mesa.

49. The micro-LED display chip of claim 45, wherein, A total thickness of the first semiconductor layer, the active layer and the second semiconductor layer along the vertical direction ranges from 500 nanometers to 2000 nanometers, and the vertical direction is perpendicular to the light-emitting surface of the micro light-emitting mesa.

50. The micro-LED display chip of claim 14, wherein, The material of the bottom metal layer comprises one or more of platinum, gold, tin, chromium, titanium and silver.

51. The micro-LED display chip of claim 14, wherein, The material of the electrode layer is one or more of gold germanium alloy, gold germanium nickel alloy and indium tin oxide, and the shape of the electrode layer is one of a circle, a ring, a polygon and a special shape.

52. The micro-LED display chip of claim 1, wherein, The active layer is doped with one or more doping elements, and the one or more doping elements are doped in the active layer in a combination of uniform doping and gradient doping.

53. The micro-LED display chip of claim 52, wherein, The active layer comprises a first region and a second region, in the first region, the one or more doping elements are doped in the active layer in a form of uniform doping, and in the second region, the one or more doping elements are doped in the active layer in a form of gradient doping.

54. The micro-LED display chip of claim 53, wherein, In the first region, a doping concentration of the doping element is a first concentration and a variation amplitude is not more than 20%, and in the second region, a doping concentration of the doping element is a second concentration, and the second concentration varies with a height of the active layer.

55. The micro-LED display chip of claim 54, wherein, The first region is close to the first semiconductor layer, the second region is close to the second semiconductor layer, and a starting concentration of the second concentration is the first concentration.

56. The micro-LED display chip of claim 55, wherein, The second concentration increases with an increase of the height of the active layer.

57. The micro-LED display chip of claim 55, wherein, The second concentration decreases with an increase of the height of the active layer.

58. The micro-LED display chip of claim 54, wherein, The first region is close to the second semiconductor layer, the second region is close to the first semiconductor layer, and a final concentration of the second concentration is the first concentration.

59. The micro-LED display chip of claim 58, wherein, The second concentration increases with an increase of the height of the active layer.

60. The micro-LED display chip of claim 58, wherein, The second concentration decreases with an increase of the height of the active layer.

61. The micro-LED display chip of claim 53, wherein, The active layer further comprises a third region, the second region is located between the first region and the third region, in the third region, the one or more doping elements are doped in the active layer in a uniform doping form.

62. The micro-LED display chip of claim 61, wherein, In the third region, the doping concentration of the doping elements is a third concentration and the variation amplitude is not more than 20%.

63. The micro-LED display chip of claim 1, wherein, The active layer comprises a plurality of quantum well layers and a plurality of quantum barrier layers arranged at intervals, the active layer is doped with one or more doping elements, the one or more doping elements are doped in the active layer in an interval doping form.

64. The micro-LED display chip of claim 63, wherein, The doping concentration of the doping elements in the quantum well layer is a third concentration, the doping concentration of the doping elements in the quantum barrier layer is a fourth concentration, the third concentration and the fourth concentration are different.

65. The micro-LED display chip of claim 64, wherein, The third concentration is greater than the fourth concentration, the ratio of the third concentration to the fourth concentration is greater than 1.

5.

66. The micro-LED display chip of claim 64, wherein, The third concentration is less than the fourth concentration, the ratio of the fourth concentration to the third concentration is greater than 1.

5.

67. The micro-LED display chip of claim 64, wherein, The quantum well layer or the quantum barrier layer comprises a buffer region, the doping concentration of the doping elements in the buffer region of the quantum well layer is the fourth concentration, and the doping concentration of the doping elements in the buffer region of the quantum barrier layer is the third concentration.

68. The micro-LED display chip of claim 67, wherein, The ratio of the thickness of the buffer region to the quantum well layer or the quantum barrier layer ranges from two-thirds to four-fifths.

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