An FPGA data uploading method, an uploading device and a medium

Abstract

The application discloses an FPGA data uploading method and device and a medium, relates to the technical field of data transmission, and comprises the following steps: collecting current sensor data of an array sensor; determining current effective data in the current sensor data; assigning the current effective data according to current row and column coordinates of a sensor corresponding to the current effective data in the array; determining a total data amount of the current effective data and the current row and column coordinates; determining a data packet number according to the total data amount, and uploading the current effective data and the current row and column coordinates to an upper computer in packets based on the data packet number; and each current effective data and the current row and column coordinates corresponding to each current effective data are in the same data packet. Only effective data and row and column coordinates are uploaded, a large amount of invalid data is removed, the data uploading amount is greatly reduced on the premise of not losing key information (effective data), the cost of the upper computer is saved, a 10-gigabit network card or a multi-core server does not need to be upgraded, and the cost of the whole machine is reduced.

Description

Technical Field

[0001] This application relates to the field of data transmission technology, and in particular to a method, device and medium for uploading FPGA data. Background Technology

[0002] Today, from high-density sensor arrays in smart factories to plantar pressure platforms for medical rehabilitation, Field-Programmable Gate Arrays (FPGAs) and host computers are the mainstream architecture for any application involving high-speed parallel sampling. However, as array sizes upgrade from 32×32 to 128×128 and even higher, a single frame of raw data easily exceeds 10KB, and cascading multiple devices instantly saturates 100Mbps and 1Gbps links. Existing solutions generally adopt a "full upload" approach: the FPGA collects data, packages it, and sends it, forcing the host computer to receive a large number of zero or invalid points. This leads to a surge in CPU usage, cache overflow, and interface lag, forcing users to upgrade to 10Gbps network cards or increase memory, thus increasing the overall cost of the system, but still failing to completely eliminate bandwidth waste and frame drop risks.

[0003] Therefore, how to save on the overhead of the host computer and reduce the overall cost of the system without losing critical information is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this application is to provide a method, device, and medium for uploading FPGA data, addressing the issues of high overhead and overall cost associated with the "full upload" approach.

[0005] To address the aforementioned technical problems, this application provides a method for uploading FPGA data, comprising:

[0006] Acquire current sensor data from the array sensor;

[0007] Determine the currently valid data in the current sensor data;

[0008] The current valid data is assigned a value based on the current row and column coordinates of the sensor corresponding to the current valid data in the array;

[0009] Determine the total amount of data, including the currently valid data and the current row and column coordinates;

[0010] The number of data packets is determined based on the total data volume, and the current valid data and the current row and column coordinates are divided into packets and uploaded to the host computer based on the number of data packets; wherein, each current valid data and the current row and column coordinates corresponding to each current valid data are in the same data packet.

[0011] In one feasible embodiment, before determining the total amount of data for the currently valid data and the current row and column coordinates, the method further includes:

[0012] Determine whether the current sensor data is the first frame of data in this data acquisition task;

[0013] If so, store the current valid data and the current row and column coordinates corresponding to the current valid data into a random access memory;

[0014] If not, retrieve the historical valid data in the random access memory and the historical row and column coordinates corresponding to the historical valid data;

[0015] Determine the row and column coordinates in the current row and column coordinates that are the same as the historical row and column coordinates, and denot them as the target row and column coordinates;

[0016] The historical valid data and the corresponding historical row and column coordinates in the random access memory are transferred to FIFO for packet uploading to the host computer, and the current row and column coordinates and the current valid data are stored in the random access memory.

[0017] If the target's current valid data corresponding to the target's current row and column coordinates is the same as the target's historical valid data corresponding to the target's current row and column coordinates, then the current row and column coordinates and the current valid data after deleting the target's current valid data are transferred to a FIFO for later packet uploading to the host computer.

[0018] In one feasible embodiment, before uploading the currently valid data and the current row and column coordinates to the host computer in packets based on the number of data packets, the method further includes:

[0019] A frame protocol is added before each data packet; wherein the frame protocol is used to mark the total amount of data, the amount of duplicate data, the number of data packets, and the current data packet sequence number.

[0020] In one feasible embodiment, acquiring current sensor data from the array sensor includes:

[0021] Data acquisition begins with the sensor located in the first row and first column of the array, keeping the column index unchanged, and is collected row by row in ascending order of row index until the sensor in the last row is reached;

[0022] Increment the column index by one and reset the row index to the first row. Collect data row by row in ascending order of row index until both the row index and column index reach the last position, thus completing the data collection of one frame.

[0023] In one feasible embodiment, determining the currently valid data in the current sensor data includes:

[0024] Identify invalid data in the current sensor data;

[0025] The invalid data is discarded to determine the currently valid data in the current sensor data.

[0026] In one feasible embodiment, determining invalid data in the current sensor data includes:

[0027] Data in the current sensor data that is less than a first set value or greater than a second set value is determined to be invalid data.

[0028] The second setting value is greater than the first setting value.

[0029] In one feasible embodiment, it further includes:

[0030] The sensor corresponding to the data in the current sensor data that is greater than the second set value is identified as a faulty sensor;

[0031] Generate a fault detection report containing the faulty sensor; wherein the fault detection report is used to indicate the repair of the faulty sensor.

[0032] This application also provides an FPGA data uploading device, including:

[0033] The data acquisition module is used to acquire the current sensor data of the array sensor;

[0034] The first determining module is used to determine the currently valid data in the current sensor data;

[0035] The assignment module is used to assign a value to the current valid data according to the current row and column coordinates of the sensor corresponding to the current valid data in the array;

[0036] The second determining module is used to determine the total amount of data, including the currently valid data and the current row and column coordinates.

[0037] The packet upload module is used to determine the number of data packets based on the total data volume, and to upload the currently valid data and the current row and column coordinates to the host computer based on the number of data packets; wherein each currently valid data and the current row and column coordinates corresponding to each currently valid data are in the same data packet.

[0038] This application also provides an FPGA data uploading device, including a memory for storing computer programs;

[0039] A processor is used to implement the steps of the FPGA data uploading method when executing the computer program.

[0040] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the FPGA data uploading method.

[0041] This application provides a method for uploading FPGA data, comprising: acquiring current sensor data from an array of sensors; determining currently valid data within the current sensor data; assigning values ​​to the currently valid data based on the current row and column coordinates of the sensor in the array corresponding to the currently valid data; determining the total amount of data including the currently valid data and the current row and column coordinates; determining the number of data packets based on the total amount of data, and uploading the currently valid data and the current row and column coordinates to a host computer based on the number of data packets; wherein each currently valid data and its corresponding current row and column coordinates are within the same data packet. By uploading only valid data and row and column coordinates, a large amount of invalid data is eliminated, significantly reducing the amount of data uploaded without losing key information (valid data), thereby saving on host computer overhead and eliminating the need to upgrade to a 10 Gigabit network card or multi-core server, thus reducing the overall system cost.

[0042] Furthermore, each valid value is accompanied by row and column coordinates, which solves the problem of data order disorder after compression. Even if packet loss occurs, the missing area can be quickly located by row and column coordinates, so as to facilitate subsequent interpolation or retransmission. The fault tolerance granularity is finer and the system robustness is higher. The number of packets is dynamically calculated based on the total data volume to avoid packet loss or retransmission due to sending too many packets at once. Data collection and assignment and packet sending can be carried out simultaneously, which can save upload time. Packet segmentation also divides the assigned valid data into several data packets in real time, so that the expanded data volume can be released in segments and avoid overall accumulation.

[0043] The beneficial effects and methods of the FPGA data uploading device and medium provided in this application are as described above. Attached Figure Description

[0044] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 A flowchart illustrating an FPGA data uploading method provided in this application embodiment;

[0046] Figure 2 This application provides a structural diagram of an FPGA data uploading system according to an embodiment of the present application.

[0047] Figure 3This is a partial schematic diagram of an array sensor provided in an embodiment of this application;

[0048] Figure 4 A force diagram of an array sensor provided in an embodiment of this application;

[0049] Figure 5 A structural diagram of an FPGA data uploading device provided in an embodiment of this application;

[0050] Figure 6 This is a structural diagram of another FPGA data uploading device provided in an embodiment of this application. Detailed Implementation

[0051] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0052] The core of this application is to provide a method, device, and medium for uploading FPGA data, which can save the overhead of the host computer and reduce the overall cost without losing critical information.

[0053] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0054] Figure 1 A flowchart illustrating an FPGA data uploading method provided in this application embodiment is shown below. Figure 1 As shown, a method for uploading FPGA data includes:

[0055] S10: Acquire current sensor data from the array sensor.

[0056] S11: Determine the currently valid data in the current sensor data.

[0057] S12: Assign values ​​to the current valid data based on the current row and column coordinates of the sensor corresponding to the current valid data in the array.

[0058] S13: Determine the current valid data and the total amount of data in the current row and column coordinates.

[0059] S14: Determine the number of data packets based on the total data volume, and upload the current valid data and the current row and column coordinates to the host computer based on the number of data packets; wherein, each current valid data and the current row and column coordinates corresponding to each current valid data are in the same data packet.

[0060] To facilitate understanding, the hardware scenarios corresponding to the FPGA data uploading method are described below. Figure 2 This application provides a structural diagram of an FPGA data uploading system, as shown in the embodiments below. Figure 2 As shown, the system includes FPGA devices, dot matrix sensors, switches, and a host computer. The dot matrix sensors are connected to the FPGA devices, which in turn are connected to the host computer via the switches. There are four FPGA devices and four sets of dot matrix sensors, each set containing 80 sensors in each row and column, for a total of 6400 dot matrix sensors. Each sensor data is converted into 2 bytes of data. Due to project requirements, the FPGAs need to send the sensor data to the host computer via Ethernet. Therefore, each device needs to send 6400 * 2 = 12800 bytes per transmission. Given the high acquisition speed of the FPGAs, the large number of devices, and the large amount of data transmitted, the host computer may not be able to keep up, potentially causing system crashes or significant data loss.

[0061] In step S10, the acquisition of current sensor data of the array sensor specifically includes: starting from the sensor located in the first row and first column of the array, keeping the column index unchanged, and acquiring data row by row in ascending order of row index to the sensor in the last row; incrementing the column index by one and resetting the row index to the first row, acquiring data row by row in ascending order of row index until both the row index and column index reach the last position, thus completing one frame of data acquisition.

[0062] To facilitate understanding, an example is given below. Data acquisition begins with the sensor in row 1, column 1, using a row-first, column-later pattern. That is, data is acquired from row 1, column 1; row 2, column 1; ... row N, column 1. Then, the column number is incremented by 1, and data is acquired from row 1, column 2; row 2, column 2; ... row N, column 2. This process continues until data is acquired from row N, column N, marking the completion of one frame of data acquisition. Alternatively, a column-first, row-later pattern can also be used.

[0063] In step S11, determining the currently valid data in the current sensor data specifically includes: determining invalid data in the current sensor data; discarding invalid data to determine the currently valid data in the current sensor data. Discarding invalid data and retaining the remaining data as the currently valid data can immediately reduce the amount of redundant information and reduce subsequent storage.

[0064] Determining invalid data in the current sensor data specifically includes: classifying data that is less than a first set value or greater than a second set value as invalid data; wherein the second set value is greater than the first set value. If no force is applied to the sensor and the acquired sensor value is zero, it is judged as invalid data. Due to the inherent characteristics and sensitivity of the sensor, the sensor may still exhibit data value fluctuations even without force. After processing, these values ​​can be controlled within 5. When judging valid data, if the value is less than 5, it is judged as invalid data; if the value is greater than 5, it is valid data. However, if the obtained data is the extreme value of 255 (8-bit acquisition chip) or 4096 (12-bit acquisition chip), it can be judged as a sensor malfunction, and these extreme values ​​greater than the second set value can also be judged as invalid data.

[0065] Furthermore, sensors corresponding to data exceeding a second set value in the current sensor data are identified as faulty sensors; a fault detection report containing the faulty sensors is generated; this report is used to instruct on the repair of the faulty sensors. Alternatively, sensor fault detection can be performed by having people of different weights stand at the same sensor location on a foot pressure plate; if the data remains unchanged, the sensor is considered faulty.

[0066] In step S12, the assignment of values ​​to the current valid data based on the current row and column coordinates of the sensor corresponding to the current valid data in the array is illustrated below for ease of understanding. Figure 3 This is a partial schematic diagram of an array sensor provided in an embodiment of this application, as shown below. Figure 3 As shown, the row and column coordinates of sensor C are (A1, B1), and the row and column coordinates of sensor D are (A3, B4). Assigning row and column coordinates to the current valid data avoids data corruption after uploading to the host computer.

[0067] If all data from the array sensors were to be uploaded to the host computer, the more sensors there are, the more data would need to be uploaded (for example, the project uses an array of 80×80=6400 sensors; each sensor collects 2 bytes of data, so the total data to be uploaded would be 6400×2 bytes=12800 bytes). This application only needs to upload the sensor data for the footprint, along with its row and column coordinates. Figure 4 This is a force diagram of an array sensor provided in an embodiment of this application, as shown below. Figure 4 As shown, there are approximately 900 sensors in the two boxes. Excluding the unloaded sensors, there are about 600 effective sensors. The required data upload is 600 × 2 bytes × 2 bytes (1 byte for row coordinates, 1 byte for column coordinates) = 2400 bytes. 2400 bytes is also much smaller than 12800 bytes.

[0068] In step S13, after frame acquisition is completed, the FPGA accumulates the total number of bytes occupied by all valid data and their corresponding row and column coordinates within the current frame to obtain the total amount of data to be transmitted. Alternatively, it can accumulate the total number of valid data and their corresponding row and column coordinates, and use this total number as the total amount of data.

[0069] In step S14, before uploading the current valid data and current row and column coordinates to the host computer in packets based on the number of data packets, the method further includes: adding a frame protocol before each data packet; wherein, the frame protocol is used to mark the total amount of data, the amount of duplicate data, the number of data packets, and the current data packet sequence number.

[0070] After frame acquisition, the FPGA accumulates the total number of bytes occupied by all valid data and their corresponding row and column coordinates within the current frame, obtaining the total amount of data to be transmitted. It synchronously compares the data with the historical data of the previous frame; the total number of data points whose detection values ​​from the same sensor have not changed is recorded as duplicate data, used by the host computer to quickly locate sensor positions that do not require updating. Using the maximum payload per packet as the boundary, the data to be transmitted, after removing duplicate values, is divided into several data packets according to the rounding-up principle; valid data and row and column coordinates from the same sensor are always allocated within the same packet to avoid cross-packet splitting. A frame protocol header is uniformly appended to the front of each data packet, sequentially writing: total data amount, duplicate data amount, number of data packets, and current data packet sequence number. This protocol allows the host computer to grasp the complete frame structure at the beginning of reception, enabling packet retransmission, on-demand parsing, and memory pre-allocation. The encapsulated data packets are queued sequentially in a First-In, First-Out (FIFO) manner and continuously uploaded by Media Access Control (MAC) according to standard Ethernet frames, ensuring a seamless pipeline connection between acquisition and transmission.

[0071] This application provides a method for uploading FPGA data, comprising: acquiring current sensor data from an array of sensors; determining currently valid data within the current sensor data; assigning values ​​to the currently valid data based on the current row and column coordinates of the sensor corresponding to the current valid data in the array; determining the total amount of data including the currently valid data and the current row and column coordinates; determining the number of data packets based on the total amount of data, and uploading the currently valid data and the current row and column coordinates to a host computer based on the number of data packets; wherein each currently valid data and its corresponding current row and column coordinates are within the same data packet. By uploading only valid data and row and column coordinates, a large amount of invalid data is eliminated, significantly reducing the amount of data uploaded without losing key information (valid data), thereby saving on host computer overhead and eliminating the need to upgrade to a 10 Gigabit network card or multi-core server, thus reducing the overall cost of the system.

[0072] Furthermore, each valid value is accompanied by row and column coordinates, which solves the problem of data order disorder after compression. Even if packet loss occurs, the missing area can be quickly located by row and column coordinates, so as to facilitate subsequent interpolation or retransmission. The fault tolerance granularity is finer and the system robustness is higher. The number of packets is dynamically calculated based on the total data volume to avoid packet loss or retransmission due to sending too many packets at once. Data collection and assignment and packet sending can be carried out simultaneously, which can save upload time. Packet segmentation also divides the assigned valid data into several data packets in real time, so that the expanded data volume can be released in segments and avoid overall accumulation.

[0073] Based on the above embodiments, before determining the total amount of current valid data and current row and column coordinates, this application embodiment further includes: determining whether the current sensor data is the first frame data in this data acquisition task; if so, storing the current valid data and the current row and column coordinates corresponding to the current valid data in a random access memory; if not, calling the historical valid data and the historical row and column coordinates corresponding to the historical valid data in the random access memory; determining the row and column coordinates in the current row and column coordinates that are the same as the historical row and column coordinates, and recording them as the target row and column coordinates; transferring the historical valid data and the historical row and column coordinates corresponding to the historical valid data in the random access memory to a FIFO for packet uploading to the host computer, and storing the current row and column coordinates and the current valid data in the random access memory; if the target current valid data corresponding to the target row and column coordinates in the current row and column coordinates is the same as the target historical valid data corresponding to the target row and column coordinates in the historical row and column coordinates, then transferring the current row and column coordinates and the current valid data after deleting the target current valid data to a FIFO for packet uploading to the host computer.

[0074] Each time the FPGA starts up, it first checks the frame sequence register. If the register is 0, it assumes that the current sample is the first frame. At this point, no comparison is performed; all currently valid data and their corresponding current row and column coordinates are directly written into Random Access Memory (RAM) as the benchmark for subsequent comparisons, and the register is changed to 1. Starting from the second frame, the historical valid data and their corresponding historical row and column coordinates from the previous frame are moved from RAM into the comparison buffer for comparison. The row and column coordinates that are the same as the historical row and column coordinates in the current row and column coordinates are identified and recorded as the target row and column coordinates. For example, (A1, B1) and (A3, B4) in the current row and column coordinates are the same as (A1, B1) and (A3, B4) in the historical row and column coordinates, and (A1, B1) and (A3, B4) are recorded as the target row and column coordinates. Using a move-then-write strategy, the historical valid data and historical row and column coordinates in RAM are transferred to the transmit FIFO at once, forming the packet to be uploaded. The current valid data and current row and column coordinates are written to RAM to become the new baseline. If the target's current valid data corresponding to the target's row and column coordinates (A1, B1) in the current row and column coordinates is the same as the target's historical valid data corresponding to the target's row and column coordinates (A1, B1) in the historical row and column coordinates, the target's current valid data is deleted from the current valid data, but the target's row and column coordinates (A1, B1) corresponding to the target's current valid data are retained. After uploading the historical valid data and the historical row and column coordinates corresponding to the historical valid data from the FIFO to the host computer, the target's current valid data is deleted from the current valid data and transferred to the FIFO for later packet uploading to the host computer. This reduces the amount of data uploaded, and significantly reduces network bandwidth and the host computer's parsing pressure.

[0075] The above embodiments have described the method for uploading FPGA data in detail. This application also provides embodiments corresponding to the FPGA data uploading device. It should be noted that this application describes the embodiments of the device part from two perspectives: one is based on the functional module, and the other is based on the hardware.

[0076] Figure 5 This is a structural diagram of an FPGA data uploading device provided in an embodiment of this application, as shown below. Figure 5 As shown, the FPGA data uploading device includes:

[0077] The acquisition module 10 is used to acquire the current sensor data of the array sensor;

[0078] The first determining module 11 is used to determine the currently valid data in the current sensor data;

[0079] The assignment module 12 is used to assign values ​​to the current valid data according to the current row and column coordinates of the sensor corresponding to the current valid data in the array;

[0080] The second determining module 13 is used to determine the current valid data and the total amount of data at the current row and column coordinates;

[0081] The packet upload module 14 is used to determine the number of data packets based on the total data volume, and to upload the current valid data and the current row and column coordinates to the host computer based on the number of data packets; wherein, each current valid data and the current row and column coordinates corresponding to each current valid data are in the same data packet.

[0082] Based on the above embodiments, in one feasible embodiment, it further includes:

[0083] The judgment module is used to determine whether the current sensor data is the first frame of data in this data acquisition task;

[0084] The storage module is used to store the current valid data and the current row and column coordinates corresponding to the current valid data into the random access memory if the current sensor data is the first frame of data in this data acquisition task.

[0085] The calling module is used to call historical valid data and the corresponding historical row and column coordinates in the random access memory if the current sensor data is not the first frame of data in this data acquisition task.

[0086] The third determination module is used to determine the row and column coordinates that are the same as the historical row and column coordinates in the current row and column coordinates, and denoted as the target row and column coordinates;

[0087] The first transfer module is used to transfer the historical valid data and the historical row and column coordinates corresponding to the historical valid data in the random access memory to the FIFO for packet uploading to the host computer, and to store the current row and column coordinates and the current valid data in the random access memory;

[0088] The second transfer module is used to transfer the current row and column coordinates and the current valid data after deleting the current valid data of the target to the FIFO if the target's current valid data in the current row and column coordinates is the same as the target's historical valid data in the historical row and column coordinates. This is to wait for the data to be packetized and uploaded to the host computer.

[0089] Based on the above embodiments, in one feasible embodiment, it further includes:

[0090] An add module is used to add a frame protocol before each data packet; the frame protocol is used to mark the total amount of data, the amount of duplicate data, the number of data packets, and the current data packet sequence number.

[0091] Based on the above embodiments, in one feasible embodiment, the acquisition module includes:

[0092] The first acquisition unit is used to acquire data starting from the sensor located in the first row and first column of the array, keeping the column index unchanged, and acquiring data row by row in ascending order of row index to the sensor in the last row;

[0093] The second acquisition unit is used to increment the column index by one and reset the row index to the first row. It acquires data row by row in ascending order of row index until both the row index and column index reach the last position, thus completing the acquisition of one frame of data.

[0094] Based on the above embodiments, in one feasible embodiment, the first determining module includes:

[0095] The determination unit is used to determine invalid data in the current sensor data;

[0096] The discard unit is used to discard invalid data to determine the currently valid data in the current sensor data.

[0097] Based on the above embodiments, in one feasible embodiment, the determining unit includes:

[0098] The first determining subunit is used to determine data in the current sensor data that is less than a first set value or greater than a second set value as invalid data; wherein the second set value is greater than the first set value.

[0099] Based on the above embodiments, in one feasible embodiment, it further includes:

[0100] The second determining subunit is used to determine the sensor corresponding to the data in the current sensor data that is greater than the second set value as the faulty sensor;

[0101] A generation subunit is used to generate a fault detection report containing information about the faulty sensor; the fault detection report is used to indicate the repair of the faulty sensor.

[0102] Since the embodiments of the apparatus and the embodiments of the method correspond to each other, please refer to the description of the embodiments of the method for the embodiments of the apparatus, which will not be repeated here.

[0103] Figure 6 A structural diagram of another FPGA data uploading device provided in the embodiments of this application is shown below. Figure 6 As shown, the FPGA data uploading device includes: a memory 20 for storing computer programs;

[0104] The processor 21 is used to implement the steps of the FPGA data uploading method as described in the above embodiment when executing a computer program.

[0105] The processor 21 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 21 may be implemented using at least one of the following hardware forms: Digital Signal Processor (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 21 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 21 may also include an Artificial Intelligence (AI) processor, which handles computational operations related to machine learning.

[0106] The memory 20 may include one or more computer-readable storage media, which may be non-transitory. The memory 20 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 20 is used to store at least the following computer program 201, which, after being loaded and executed by the processor 21, is capable of implementing the relevant steps of the FPGA data uploading method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202 and data 203, and the storage method may be temporary or permanent storage. The operating system 202 may include Windows, Unix, Linux, etc. The data 203 may include, but is not limited to, current sensor data.

[0107] In some embodiments, the FPGA data uploading device may further include a display screen 22, an input / output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.

[0108] Those skilled in the art will understand that Figure 6 The structure shown does not constitute a limitation on the FPGA data uploading device and may include more or fewer components than shown.

[0109] The FPGA data uploading device provided in this application includes a memory and a processor. When the processor executes the program stored in the memory, it can implement the following method: acquiring the current sensor data of the array sensor; determining invalid data in the current sensor data, discarding invalid data to obtain the current valid data of the current sensor data; assigning values ​​to the current valid data according to the current row and column coordinates of the sensor corresponding to the current valid data in the array, and uploading the current valid data and the current row and column coordinates corresponding to the current valid data to the host computer.

[0110] Finally, this application also provides an embodiment corresponding to a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps described in the FPGA data uploading method of the above-described method embodiment.

[0111] It is understood that if the methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0112] The foregoing has provided a detailed description of an FPGA data uploading method, uploading device, and medium provided in this application. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0113] It should also be noted that, in this specification, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A method for uploading FPGA data, characterized in that, include: Acquire current sensor data from the array sensor; Determine the currently valid data in the current sensor data; The current valid data is assigned a value based on the current row and column coordinates of the sensor corresponding to the current valid data in the array; Determine the total amount of data, including the currently valid data and the current row and column coordinates; The number of data packets is determined based on the total data volume, and the current valid data and the current row and column coordinates are divided into packets and uploaded to the host computer based on the number of data packets; wherein, each current valid data and the current row and column coordinates corresponding to each current valid data are in the same data packet; Before determining the total amount of data for the current valid data and the current row and column coordinates, the following steps are also included: Determine whether the current sensor data is the first frame of data in this data acquisition task; If so, store the current valid data and the current row and column coordinates corresponding to the current valid data into a random access memory; If not, retrieve the historical valid data in the random access memory and the historical row and column coordinates corresponding to the historical valid data; Determine the row and column coordinates in the current row and column coordinates that are the same as the historical row and column coordinates, and denot them as the target row and column coordinates; The historical valid data and the corresponding historical row and column coordinates in the random access memory are transferred to FIFO for packet uploading to the host computer, and the current row and column coordinates and the current valid data are stored in the random access memory. If the target's current valid data corresponding to the target's current row and column coordinates is the same as the target's historical valid data corresponding to the target's current row and column coordinates, then the current row and column coordinates and the current valid data after deleting the target's current valid data are transferred to a FIFO for later packet uploading to the host computer.

2. The FPGA data uploading method according to claim 1, characterized in that, Before uploading the currently valid data and the current row and column coordinates to the host computer in packets based on the number of data packets, the process also includes: A frame protocol is added before each data packet; wherein the frame protocol is used to mark the total amount of data, the amount of duplicate data, the number of data packets, and the current data packet sequence number.

3. The FPGA data uploading method according to claim 1, characterized in that, Acquire current sensor data from the array sensor, including: Data acquisition begins with the sensor located in the first row and first column of the array, keeping the column index unchanged, and is collected row by row in ascending order of row index until the sensor in the last row is reached; Increment the column index by one and reset the row index to the first row. Collect data row by row in ascending order of row index until both the row index and column index reach the last position, thus completing the data collection of one frame.

4. The FPGA data uploading method according to claim 1, characterized in that, Determining the currently valid data in the current sensor data includes: Identify invalid data in the current sensor data; The invalid data is discarded to determine the currently valid data in the current sensor data.

5. The FPGA data uploading method according to claim 4, characterized in that, Determining invalid data in the current sensor data includes: Data in the current sensor data that is less than a first set value or greater than a second set value is determined to be invalid data. The second setting value is greater than the first setting value.

6. The FPGA data uploading method according to claim 5, characterized in that, Also includes: The sensor corresponding to the data in the current sensor data that is greater than the second set value is identified as a faulty sensor; Generate a fault detection report containing the faulty sensor; wherein the fault detection report is used to indicate the repair of the faulty sensor.

7. An FPGA data uploading device, characterized in that, include: The data acquisition module is used to acquire the current sensor data of the array sensor; The first determining module is used to determine the currently valid data in the current sensor data; The assignment module is used to assign a value to the current valid data according to the current row and column coordinates of the sensor corresponding to the current valid data in the array; The second determining module is used to determine the total amount of data, including the currently valid data and the current row and column coordinates. The packet upload module is used to determine the number of data packets based on the total data volume, and to upload the currently valid data and the current row and column coordinates to the host computer based on the number of data packets; wherein, each currently valid data and the current row and column coordinates corresponding to each currently valid data are in the same data packet; Also includes: The judgment module is used to determine whether the current sensor data is the first frame of data in this data acquisition task; The storage module is used to store the current valid data and the current row and column coordinates corresponding to the current valid data into the random access memory if the current sensor data is the first frame of data in this data acquisition task. The calling module is used to call historical valid data and the corresponding historical row and column coordinates in the random access memory if the current sensor data is not the first frame of data in this data acquisition task. The third determination module is used to determine the row and column coordinates that are the same as the historical row and column coordinates in the current row and column coordinates, and denoted as the target row and column coordinates; The first transfer module is used to transfer the historical valid data and the historical row and column coordinates corresponding to the historical valid data in the random access memory to the FIFO for packet uploading to the host computer, and to store the current row and column coordinates and the current valid data in the random access memory; The second transfer module is used to transfer the current row and column coordinates and the current valid data after deleting the current valid data of the target to the FIFO if the target's current valid data in the current row and column coordinates is the same as the target's historical valid data in the historical row and column coordinates. This is to wait for the data to be packetized and uploaded to the host computer.

8. An FPGA data uploading device, characterized in that, Includes memory used to store computer programs; A processor, configured to implement the steps of the FPGA data uploading method as described in any one of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the FPGA data uploading method as described in any one of claims 1 to 6.

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